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DHigh-Performance Fixed-Point Digital
Signal Processor (DSP) − TMS320C62x
− 4-, 3.33-ns Instruction Cycle Time
− 250-, 300-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 2000, 2400 MIPS
DC6203B and C6202 GLS Ball Grid Array
(BGA) Packages are Pin-Compatible With
the C6204 GLW BGA Package†
DC6203B and C6202B GNZ, GNY and ZNY
Packages are Pin-Compatible
DVelociTI Advanced Very-Long-Instruction-
Word (VLIW) C62x DSP Core
− Eight Highly Independent Functional
Units:
− Six ALUs (32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Result)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D7M-Bit On-Chip SRAM
− 3M-Bit Internal Program/Cache
(96K 32-Bit Instructions)
− 4M-Bit Dual-Access Internal Data
(512K Bytes)
− Organized as Two 256K-Byte Blocks
for Improved Concurrency
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− 52M-Byte Addressable External Memory
Space
DFour-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
DFlexible Phase-Locked-Loop (PLL) Clock
Generator
D32-Bit Expansion Bus (XBus)
− Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
− Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
− Master/Slave Functionality
− Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
DThree Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral Interface (SPI)
Compatible (Motorola)
DTwo 32-Bit General-Purpose Timers
DIEEE-1149.1 (JTAG‡)
Boundary-Scan-Compatible
D352-Pin BGA Package (GNZ)
D384-Pin BGA Package (GLS)
D384-Pin BGA Packages (GNY and ZNY)
D0.15-µm/5-Level Metal Process
− CMOS Technology
D3.3-V I/Os, 1.5-V Internal
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
†For more details, see the GLS BGA package bottom view.
‡IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2006, Texas Instruments Incorporated
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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Table of Contents
parameter measurement information 46. . . . . . . . . . . . . . .
signal transition levels 46. . . . . . . . . . . . . . . . . . . . . . . . . .
timing parameters and board routing analysis 47. . . . . .
input and output clocks 49. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 52. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 55. . . . . . . . . . . . . . . . .
synchronous DRAM timing 59. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 66. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 69. . . . . . . . . . . . . . . . . . . . . . . . . .
expansion bus synchronous FIFO timing 70. . . . . . . . . . . .
expansion bus asynchronous peripheral timing 72. . . . . .
expansion bus synchronous host-port timing 75. . . . . . . .
expansion bus asynchronous host-port timing 81. . . . . . .
XHOLD/XHOLDA timing 83. . . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 85. . . . . . . . . . . . .
DMAC, timer, power-down timing 97. . . . . . . . . . . . . . . . . .
JTAG test-port timing 99. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
revision history 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GNZ, GLS, GNY and ZNY BGA packages (bottom view) 4
description 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C62x device compatibility 8. . . . . . . . . . . . . . . . . . . . . . . . . . .
functional and CPU (DSP core) block diagram 9. . . . . . . . .
CPU (DSP core) description 10. . . . . . . . . . . . . . . . . . . . . . .
memory map summary 12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
peripheral register descriptions 13. . . . . . . . . . . . . . . . . . . . .
DMA synchronization events 17. . . . . . . . . . . . . . . . . . . . . . .
interrupt sources and interrupt selector 18. . . . . . . . . . . . . .
signal groups description 19. . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions 22
development support 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support 36. . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-down mode logic 39. . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing 43. . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 JTAG compatibility statement 44. . . . . . . . . . .
absolute maximum ratings over operating case
temperature ranges 45. . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 45. . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges
of supply voltage and operating case temperature 45. .
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REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS086M device-specific data
sheet to make it an SPRS086N revision.
Scope: Applicable updates to the C62x device family, specifically relating to the C6203/B devices, have been
incorporated.
PAGE(S)
NO. ADDITIONS/CHANGES/DELETIONS
Global:
Added ZNY packaging information
3Revision History:
Moved Revision History to the front of the document.
34 Device and Development-Support Tool Nomenclature section:
Deleted the “TMS320C203B Device Part Numbers (P/Ns) and Ordering Information” table and associated paragraph
Updated the “To designate the stages in the product development cycle...” paragraph.
Updated the “TI device nomenclature also includes ...” paragraph.
Added “The ZNY package, like the GNY package, is ...” paragraph.
35 TMS320C6000 DSP Platform Device Nomenclature (Including TMS320C6203B):
Updated figure to include ZNY packaging information.
101 Mechanical Data for C6203B:
Deleted package drawings and updated Thermal table titles.
Added thermal resistance characteristics (S-PBGA package) for ZNY table.
Added Packaging Information section and lead−in sentence.
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GNZ, GLS, GNY and ZNY BGA packages (bottom view)
GNZ 352-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
AF
AD
AB
AA
AC
W
Y
U
V
AE
R
N
P
L
H
J
K
M
F
G
D
E
B
A
C
T
25262223
20
19 2117151612
1314 1810
9
8
75 64
3
2
111 24
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GNZ, GLS, GNY and ZNY BGA packages (bottom view) (continued)
22
1920
17
16 18
1314
11
10 12 15
AA
U
W
N
R
8
7
5
46
J
L
E
G
2
1
A
C
3 9 21
B
D
F
H
K
M
P
T
V
Y
AB
GLS 384-PIN BGA PACKAGE (BOTTOM VIEW)
The C6203B and C6202 GLS BGA packages are pin-compatible with the C6204 GLW
package except that the inner row of balls (which are additional power and ground pins)
are removed for the C6204 GLW package.
These balls are NOT applicable for the C6204 devices 340-pin GLW BGA package.
GNY and ZNY 384-PIN BGA PACKAGE (BOTTOM VIEW)
22
1920
17
16 18
1314
11
10 12 15
AA
U
W
N
R
8
7
5
46
J
L
E
G
2
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3 9 21
B
D
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Y
AB
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description
The TMS320C6203B device is part of the TMS320C62x fixed-point DSP generation in the TMS320C6000
DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an
excellent choice for multichannel and multifunction applications.
The TMS320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges.
The TMS320C6203B has a performance capability of up to 2400 MIPS at a clock rate of 300 MHz. The C6203B
DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly
independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high
degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203B can produce two
multiply-accumulates (MACs) per cycle for a total of 600 million MACs per second (MMACS). The C6203B DSP
also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6203B device program memory consists of two blocks, with a 256K-byte block configured as
memory-mapped program space, and the other 128K-byte block user-configurable as cache or
memory-mapped program space. Data memory for the C6203B consists of two 256K-byte blocks of RAM.
The C6203B device has a powerful and diverse set of peripherals. The peripheral set includes three
multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XBus) that
offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless
32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous
peripherals.
The C62x devices have a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
device characteristics
Table 1 provides an overview of the TMS320C6203B, TMS320C6202, TMS320C6202B, and TMS320C6204
DSPs. The table shows significant features of each device, including the capacity of on-chip RAM, the
peripherals, the execution time, and the package type with pin count, etc. This data sheet primarily focuses on
the functionality of the TMS320C6203B device although it also identifies to the user the pin-compatibility of the
C6203B and C 6 2 02 G L S , a nd t h e C 6 20 4 G LW BGA packages. This data sheet identifies the pin-compatibility
of the C6203B and the C6202B GNZ, GNY and ZNY packages. For the functionality information on the
TMS320C6202/02B devices, see the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors
Data Sheet (literature number SPRS104). For the functionality information on the TMS320C6204 device, see
the TMS320C6204 Fixed-Point Digital Signal Processor Data Sheet (literature number SPRS152). And for
more details on the C6000 DSP part numbering, see Figure 4.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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device characteristics (continued)
Table 1. Characteristics of the Pin-Compatible DSPs
HARDWARE FEATURES C6203B C6202 C6202B C6204
EMIF √ √ √ √
Peripherals
DMA 4-Channel With
Throughput
Enhancements 4-Channel 4-Channel With
Throughput
Enhancements
4-Channel With
Throughput
Enhancements
Peripherals
Expansion Bus √ √ √ √
McBSPs 3 3 3 2
32-Bit Timers 2 2 2 2
Size (Bytes) 384K 256K 256K 64K
Internal
Program
Memory Organization
Block 0:
256K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped Program
Block 0:
128K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
Block 0:
128K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
1 Block:
64K-Byte
Cache/Mapped
Program
Size (Bytes) 512K 128K 128K 64K
Internal Data
Memory Organization
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
2 Blocks:
Four 16-Bit Banks per
Block
50/50 Split
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
CPU ID +
CPU Rev ID Control Status
Register (CSR.[31:16]) 0x0003 0x0002 0x0003 0x0003
Frequency MHz 250, 300 200, 250 250, 300 200
Cycle Time ns 3.33 ns (6203B-300)
4 ns (6203B-250)
4 ns (03BGNZA-250)
4 ns (6202−250)
5 ns (6202−200)
3.33 ns (6202B-300)
4 ns (6202B-250)
4 ns (02BGNZA-250) 5 ns (6204-200)
Core (V)
1.5
1.8
1.5
1.5
Voltage Core (V) 1.7 1.8 1.5 1.5
Voltage
I/O (V) 3.3 3.3 3.3 3.3
PLL Options
CLKIN frequency
multiplier [Bypass (x1),
x4, x6, x7, x8, x9, x10,
and x11]
All PLL Options
(GLS/GNY/ZNY Pkgs)
x1, x4, x8, x10
(GNZ Pkg)
x1, x4
(Both Pkgs)
All PLL Options
(GNY/ZNY Pkgs)
x1, x4, x8, x10
(GNZ Pkg)
x1, x4
(Both Pkgs)
27 x 27 mm 352-pin GNZ 352-pin GJL 352-pin GNZ —
BGA
18 x 18 mm 384-pin GLS 384-pin GLS —340-pin GLW
BGA
Packages 18 x 18 mm 384-pin GNY and ZNY
(2.x, 3.x only) —384-pin GNY and ZNY −
16 x 16 mm — — — 288-pin GHK
Process
Technology µm0.15 µm0.18 µm0.15 µm0.15 µm
Product
Status†
Product Preview (PP)
Advance Information
(AI)
Production Data (PD)
PD PD PD PD
†PRODUCTION D ATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
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C62x device compatibility
The TMS320C6202, C6202B, C6203B, and C6204 devices are pin-compatible; thus, making new system
designs easier and providing faster time to market. The following list summarizes the C62x DSP device
characteristic differences:
DCore Supply Voltage (1.8 V versus 1.7 V versus 1.5 V)
The C6202 device core supply voltage is 1.8 V while the C6202B, C6203B, C6204 devices have core supply
voltages of 1.5 V. The C6203B device (GLS, GNZ, GNY and ZNY packages) also has a 1.7-V core supply
voltage.
DDevice Clock Speeds
The C6202B and C6203B devices run at −250 and −300 MHz clock speeds (with a C620xBGNZA extended
temperature device that also runs at −250 MHz), while the C6202 device runs at −200 and −250 MHz, and
the C6204 device runs at −200 MHz clock speed.
DPLL Options Availability
Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4, etc.] for each of the
C62x DSP devices. For additional details on the PLL clock module and specific options for the C6203B
device, see the Clock PLL section of this data sheet.
For additional details on the PLL clock module and specific options for the C6202/02B devices, see the
Clock PLL section of the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors Data
Sheet (literature number SPRS104).
And for additional details on the PLL clock module and specific options for the C6204 device, see the Clock
PLL section of the TMS320C6204 Fixed-Point Digital Signal Processor Data Sheet (literature number
SPRS152).
DOn-Chip Memory Size
The C6202/02B, C6203B, and C6204 devices have different on-chip program memory and data memory
sizes (see Table 1).
DMcBSPs
The C6202, C6202B, and C6203B devices have three McBSPs while the C6204 device has two McBSPs
on-chip.
For a more detailed discussion on migration concerns, and similarities/differences between the C6202,
C6202B, C6203B, and C6204 devices, see the How to Begin Development Today and Migrate Across the
TMS320C6202/02B/03B/04 DSPs Application Report (literature number SPRA603).
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functional and CPU (DSP core) block diagram
32
Multichannel
Buffered Serial
Port 1
32
Direct Memory
Access Controller
(DMA)
(See Table 1)
Test
C62x CPU (DSP Core)
Data Path B
B Register File
Program
Access/Cache
Controller
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
PLL
(x1, x4, x6, x7, x8,
x9, x10, x11)†
Data
Access
Controller
Power-
Down
Logic
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
SDRAM or
SBSRAM
ROM/FLASH
SRAM
I/O Devices
Synchronous
FIFOs
I/O Devices
Timer 0
Timer 1
External Memory
Interface (EMIF)
Multichannel
Buffered Serial
Port 0
Multichannel
Buffered Serial
Port 2
Expansion
Bus (XBus)
32-Bit
Internal Program Memory:
1 Block Program (256K Bytes)
1 Block Program/Cache
(128K Bytes)
Control
Registers
Control
Logic
Internal Data
Memory
(512K Bytes)
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
C6203B Digital Signal Processor
Peripheral Control Bus
DMA
Bus
Boot Configuration
Interrupt
Selector
†For additional details on the PLL clock module and specific options for the C6203B device, see Table 1 and the Clock PLL section of this data
sheet.
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CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram
and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally, each side features a single data bus connected to all the registers on the other side, by
which the two sets of functional units can access data from the register files on the opposite side. While register
access by functional units on the same side of the CPU as the register file can service all the units in a single
clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- o r 15-bit of fsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
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CPU (DSP core) description (continued)
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1X
.L2
.S2
.M2
.D2
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.D1
.M1
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.S1
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.L1
long src
dst
src2
src1
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁ
Á
Á
Á
Á
Á
src1
src1
src1
src1
src1
src1
src1
8
8
8
8
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
ÁÁ
DA1
DA2
ST1
LD1
LD2
ST2
32
32
Register
File A
(A0−A15)
long src
long dst
long dst
long src
Data Path B
Data Path A
Register
File B
(B0−B15)
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
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12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory map summary
Table 2 shows the memory map address ranges of the C6203B device. The C6203B device has the capability
of a MAP 0 or MAP 1 memory block configuration. These memory block configurations are set up at reset by
the boot configuration pins (generically called BOOTMODE[4:0]). For the C6203B device, the BOOTMODE
configuration is handled, at reset, by the expansion bus module (specifically XD[4:0] pins). For more detailed
information on the C6203B device settings, which include the device boot mode configuration at reset and other
device-specific configurations, see TMS320C620x/C670x DSP Boot Modes and Configuration (SPRU642).
Table 2. TMS320C6203B Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
MAP 0 MAP 1
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
External Memory Interface (EMIF) CE0 Internal Program RAM 384K 0000_0000–0005_FFFF
EMIF CE0 Reserved 4M–384K 0006_0000–003F_FFFF
EMIF CE0 EMIF CE0 12M 0040_0000–00FF_FFFF
EMIF CE1 EMIF CE0 4M 0100_0000–013F_FFFF
Internal Program RAM EMIF CE1 384K 0140_0000–0145_FFFF
Reserved EMIF CE1 4M–384K 0146_0000–017F_FFFF
EMIF Registers 256K 0180_0000–0183_FFFF
DMA Controller Registers 256K 0184_0000–0187_FFFF
Expansion Bus (XBus) Registers 256K 0188_0000–018B_FFFF
McBSP 0 Registers 256K 018C_0000–018F_FFFF
McBSP 1 Registers 256K 0190_0000–0193_FFFF
Timer 0 Registers 256K 0194_0000–0197_FFFF
Timer 1 Registers 256K 0198_0000–019B_FFFF
Interrupt Selector Registers 512 019C_0000–019C_01FF
Power-Down Registers 256K–512 019C_0200–019F_FFFF
Reserved 256K 01A0_0000–01A3_FFFF
McBSP 2 Registers 256K 01A4_0000–01A7_FFFF
Reserved 5.5M 01A8_0000–01FF_FFFF
EMIF CE2 16M 0200_0000–02FF_FFFF
EMIF CE3 16M 0300_0000–03FF_FFFF
Reserved 1G–64M 0400_0000–3FFF_FFFF
XBus XCE0 256M 4000_0000–4FFF_FFFF
XBus XCE1 256M 5000_0000–5FFF_FFFF
XBus XCE2 256M 6000_0000–6FFF_FFFF
XBus XCE3 256M 7000_0000–7FFF_FFFF
Internal Data RAM 512K 8000_0000–8007_FFFF
Reserved 2G–512K 8008_0000–FFFF_FFFF
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peripheral register descriptions
Table 3 through Table 12 identify the peripheral registers for the C6203B device by their register names,
acronyms, and hex address or hex address range. For more detailed information on the register contents, bit
names, and their descriptions, see the peripheral reference guide referenced in TMS320C6000 DSP
Peripherals Overview Reference Guide (literature number SPRU190).
Table 3. EMIF Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0180 0000 GBLCTL EMIF global control
0180 0004 CECTL1 EMIF CE1 space control External or internal; dependent on MAP0 or MAP1
configuration (selected by the MAP bit in the EMIF
GBLCTL register)
0180 0008 CECTL0 EMIF CE0 space control External or internal; dependent on MAP0 or MAP1
configuration (selected by the MAP bit in the EMIF
GBLCTL register)
0180 000C − Reserved
0180 0010 CECTL2 EMIF CE2 space control Corresponds to EMIF CE2 memory space:
[0200 0000 − 02FF FFFF]
0180 0014 CECTL3 EMIF CE3 space control Corresponds to EMIF CE3 memory space:
[0300 0000 − 03FF FFFF]
0180 0018 SDCTL EMIF SDRAM control
0180 001C SDTIM EMIF SDRAM refresh control
0180 0020 − 0180 0054 − Reserved
0180 0058 − 0183 FFFF – Reserved
Table 4. DMA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 0000 PRICTL0 DMA channel 0 primary control
0184 0004 PRICTL2 DMA channel 2 primary control
0184 0008 SECCTL0 DMA channel 0 secondary control
0184 000C SECCTL2 DMA channel 2 secondary control
0184 0010 SRC0 DMA channel 0 source address
0184 0014 SRC2 DMA channel 2 source address
0184 0018 DST0 DMA channel 0 destination address
0184 001C DST2 DMA channel 2 destination address
0184 0020 XFRCNT0 DMA channel 0 transfer counter
0184 0024 XFRCNT2 DMA channel 2 transfer counter
0184 0028 GBLCNTA DMA global count reload register A
0184 002C GBLCNTB DMA global count reload register B
0184 0030 GBLIDXA DMA global index register A
0184 0034 GBLIDXB DMA global index register B
0184 0038 GBLADDRA DMA global address register A
0184 003C GBLADDRB DMA global address register B
0184 0040 PRICTL1 DMA channel 1 primary control
0184 0044 PRICTL3 DMA channel 3 primary control
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14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 4. DMA Registers (Continued)
HEX ADDRESS RANGE REGISTER NAMEACRONYM
0184 0048 SECCTL1 DMA channel 1 secondary control
0184 004C SECCTL3 DMA channel 3 secondary control
0184 0050 SRC1 DMA channel 1 source address
0184 0054 SRC3 DMA channel 3 source address
0184 0058 DST1 DMA channel 1 destination address
0184 005C DST3 DMA channel 3 destination address
0184 0060 XFRCNT1 DMA channel 1 transfer counter
0184 0064 XFRCNT3 DMA channel 3 transfer counter
0184 0068 GBLADDRC DMA global address register C
0184 006C GBLADDRD DMA global address register D
0184 0070 AUXCTL DMA auxiliary control register
0184 0074−0187 FFFF — Reserved
Table 5. Expansion Bus (XBUS) Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0188 0000 XBGC Expansion bus global control register
0188 0004 XCECTL1 XCE1 space control register Corresponds to XBus XCE0 memory
space:
[4000 0000−4FFF FFFF]
0188 0008 XCECTL0 XCE0 space control register Corresponds to XBus XCE1 memory
space:
[5000 0000−5FFF FFFF]
0188 000C XBHC Expansion bus host port interface control register DSP read/write access only
0188 0010 XCECTL2 XCE2 space control register Corresponds to XBus XCE2 memory
space:
[6000 0000−6FFF FFFF]
0188 0014 XCECTL3 XCE3 space control register Corresponds to XBus XCE3 memory
space:
[7000 0000−7FFF FFFF]
0188 0018 — Reserved
0188 001C — Reserved
0188 0020 XBIMA Expansion bus internal master address register DSP read/write access only
0188 0024 XBEA Expansion bus external address register DSP read/write access only
0188 0028−018B FFFF — Reserved
— XBISA Expansion bus internal slave address
— XBD Expansion bus data
peripheral register descriptions (continued)
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peripheral register descriptions (continued)
Table 6. Interrupt Selector Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts
10−15 (INT10−INT15)
019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4−9
(INT04−INT09)
019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)
019C 000C−019C 01FF — Reserved
019C 0200 PDCTL Peripheral power-down control register
019C 0204−019F FFFF — Reserved
Table 7. Peripheral Power-Down Control Register
HEX ADDRESS RANGE ACRONYM REGISTER NAME
019C 0200 PDCTL Peripheral power-down control register
Table 8. McBSP 0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
018C 0000 DRR0 McBSP0 data receive register The CPU and DMA controller can only read
this register; they cannot write to it.
018C 0004 DXR0 McBSP0 data transmit register
018C 0008 SPCR0 McBSP0 serial port control register
018C 000C RCR0 McBSP0 receive control register
018C 0010 XCR0 McBSP0 transmit control register
018C 0014 SRGR0 McBSP0 sample rate generator register
018C 0018 MCR0 McBSP0 multichannel control register
018C 001C RCER0 McBSP0 receive channel enable register
018C 0020 XCER0 McBSP0 transmit channel enable register
018C 0024 PCR0 McBSP0 pin control register
018C 0028−018F FFFF — Reserved
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peripheral register descriptions (continued)
Table 9. McBSP 1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0190 0000 DRR1 Data receive register The CPU and DMA controller can only read
this register; they cannot write to it.
0190 0004 DXR1 McBSP1 data transmit register
0190 0008 SPCR1 McBSP1 serial port control register
0190 000C RCR1 McBSP1 receive control register
0190 0010 XCR1 McBSP1 transmit control register
0190 0014 SRGR1 McBSP1 sample rate generator register
0190 0018 MCR1 McBSP1 multichannel control register
0190 001C RCER1 McBSP1 receive channel enable register
0190 0020 XCER1 McBSP1 transmit channel enable register
0190 0024 PCR1 McBSP1 pin control register
0190 0028−0193 FFFF — Reserved
Table 10. McBSP 2 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01A4 0000 DRR2 McBSP2 data receive register The CPU and DMA controller can only read
this register; they cannot write to it.
01A4 0004 DXR2 McBSP2 data transmit register
01A4 0008 SPCR2 McBSP2 serial port control register
01A4 000C RCR2 McBSP2 receive control register
01A4 0010 XCR2 McBSP2 transmit control register
01A4 0014 SRGR2 McBSP2 sample rate generator register
01A4 0018 MCR2 McBSP2 multichannel control register
01A4 001C RCER2 McBSP2 receive channel enable register
01A4 0020 XCER2 McBSP2 transmit channel enable register
01A4 0024 PCR2 McBSP2 pin control register
01A4 0028−01A7 FFFF — Reserved
Table 11. Timer 0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0194 0000 CTL0 Timer 0 control register Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter.
0194 000C−0197 FFFF — Reserved
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Table 12. Timer 1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter.
0198 000C−019B FFFF — Reserved
DMA synchronization events
The C6203B DMA supports up to four independent programmable DMA channels. The four main DMA channels
can be read/write synchronized based on the events shown in Table 13. Selection of these events is done via
the RSYNC and WSYNC fields in the Primary Control registers of the specific DMA channel. For more detailed
information on the DMA module, associated channels, and event-synchronization, see TMS320C620x/C670x
DSP Program and Data Memory Controller / Direct Memory Access (DMA) Controller Reference Guide
(literature number SPRU577).
Table 13. TMS320C6203B DMA Synchronization Events
DMA EVENT
NUMBER
(BINARY) EVENT NAME EVENT DESCRIPTION
00000 Reserved Reserved
00001 TINT0 Timer 0 interrupt
00010 TINT1 Timer 1 interrupt
00011 SD_INT EMIF SDRAM timer interrupt
00100 EXT_INT4 External interrupt pin 4
00101 EXT_INT5 External interrupt pin 5
00110 EXT_INT6 External interrupt pin 6
00111 EXT_INT7 External interrupt pin 7
01000 DMA_INT0 DMA channel 0 interrupt
01001 DMA_INT1 DMA channel 1 interrupt
01010 DMA_INT2 DMA channel 2 interrupt
01011 DMA_INT3 DMA channel 3 interrupt
01100 XEVT0 McBSP0 transmit event
01101 REVT0 McBSP0 receive event
01110 XEVT1 McBSP1 transmit event
01111 REVT1 McBSP1 receive event
10000 DSP_INT Host processor-to-DSP interrupt
10001 XEVT2 McBSP2 transmit event
10010 REVT2 McBSP2 receive event
10011 −11111 Reserved Reserved. Not used.
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18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
interrupt sources and interrupt selector
The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 14. The highest-priority interrupt
is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default t o the interrupt source specified in Table 14. The interrupt source for interrupts 4−15 can be programmed
by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control
registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 14. C6203B DSP Interrupts
CPU
INTERRUPT
NUMBER
INTERRUPT
SELECTOR
CONTROL
REGISTER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT INTERRUPT SOURCE
INT_00†— — RESET
INT_01†— — NMI
INT_02†— — Reserved Reserved. Do not use.
INT_03†— — Reserved Reserved. Do not use.
INT_04‡MUXL[4:0] 00100 EXT_INT4 External interrupt pin 4
INT_05‡MUXL[9:5] 00101 EXT_INT5 External interrupt pin 5
INT_06‡MUXL[14:10] 00110 EXT_INT6 External interrupt pin 6
INT_07‡MUXL[20:16] 00111 EXT_INT7 External interrupt pin 7
INT_08‡MUXL[25:21] 01000 DMA_INT0 DMA channel 0 interrupt
INT_09‡MUXL[30:26] 01001 DMA_INT1 DMA channel 1 interrupt
INT_10‡MUXH[4:0] 00011 SD_INT EMIF SDRAM timer interrupt
INT_11‡MUXH[9:5] 01010 DMA_INT2 DMA channel 2 interrupt
INT_12‡MUXH[14:10] 01011 DMA_INT3 DMA channel 3 interrupt
INT_13‡MUXH[20:16] 00000 DSP_INT Host-processor-to-DSP interrupt
INT_14‡MUXH[25:21] 00001 TINT0 Timer 0 interrupt
INT_15‡MUXH[30:26] 00010 TINT1 Timer 1 interrupt
— — 01100 XINT0 McBSP0 transmit interrupt
— — 01101 RINT0 McBSP0 receive interrupt
— — 01110 XINT1 McBSP1 transmit interrupt
— — 01111 RINT1 McBSP1 receive interrupt
— — 10000 Reserved Reserved. Not used.
— — 10001 XINT2 McBSP2 transmit interrupt
— — 10010 RINT2 McBSP2 receive interrupt
— — 10011 −11111 Reserved Reserved. Do not use.
†Interrupts INT_00 through INT_03 are non-maskable and fixed.
‡Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 14 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
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signal groups description
TRST
EXT_INT7
Clock/PLL
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and
Interrupts
DMA Status
Power-Down
Status
Control/Status
TDI
TDO
TMS
TCK
CLKIN
CLKOUT1
CLKMODE0
PLLV
PLLG
PLLF
EMU1
EMU0
RSV2
RSV1
RSV0
NMI
IACK
INUM3
INUM2
INUM1
INUM0
DMAC3
DMAC2
DMAC1
DMAC0
PD
RSV4
EXT_INT6
EXT_INT5
EXT_INT4
RESET
CLKOUT2
CLKMODE1
CLKMODE2†
†CLKMODE2 is NOT available on the GNZ package for the C6203B device.
RSV3
Figure 2. CPU (DSP Core) Signals
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20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
signal groups description (continued)
CE3
ARE
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE
AWE
ARDY
SDA10
SDRAS/SSOE
SDCAS/SSADS
SDWE/SSWE
TOUT0
CLKX2
FSX2
DX2
CLKR2
FSR2
DR2
CLKS2
Data
Memory Map
Space Select
Word Address
Byte Enables
HOLD/
HOLDA
32
20
Asynchronous
Memory
Control
Synchronous
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Transmit
Transmit
Timer 0
Timers
McBSP1
McBSP2
Receive
Receive
Clock
Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Transmit
McBSP0
Receive
Clock
Figure 3. Peripheral Signals
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signal groups description (continued)
XD[31:0]
XBE2/XA4
XBE1/XA3
XBE0/XA2
XRDY
XHOLD
XHOLDA
XFCLK
XCLKIN
XOE
XRE
Data
Byte-Enable
Control/
Address
Control
Arbitration
32 Clocks
I/O Port
Control
Expansion Bus
XWE/XWAIT
XCE3
XCE2
XCE1
XCE0
XCS
XAS
Host
Interface
Control
XCNTL
XW/R
XBLAST
XBOFF
XBE3/XA5
Figure 3. Peripheral Signals (Continued)
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22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
CLOCK/PLL
CLKIN C12 B10 I Clock input
CLKOUT1 AD20 Y18 O Clock output at full device speed
CLKOUT2 AC19 AB19 O Clock output at half (1/2) of device speed
-Used for synchronous memory interface
CLKMODE0 B15 B12 I Clock mode selects
CLKMODE1 C11 A9 I -Selects what multiply factors of the input clock frequency the CPU frequency equals. Fo
r
more details on the GNZ, GLS, GNY and ZNY CLKMODE pins and the PLL multiply factors
CLKMODE2 − A14 I
more details on the GNZ, GLS, GNY and ZNY CLKMODE pins and the PLL multiply factors
for the C6203B device, see the Clock PLL section of this data sheet.
PLLV‡D13 C11 A§PLL analog VCC connection for the low-pass filter
PLLG‡D14 C12 A§PLL analog GND connection for the low-pass filter
PLLF‡C13 A11 A§PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS AD7 Y5 I JTAG test-port mode select (features an internal pullup)
TDO AE6 AA4 O/Z JTAG test-port data out
TDI AF5 Y4 I JTAG test-port data in (features an internal pullup)
TCK AE5 AB2 I JTAG test-port clock
TRST AC7 AA3 I JTAG test-port reset (features an internal pulldown)
EMU1 AF6 AA5 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶
EMU0 AC8 AB4 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶
RESET AND INTERRUPTS
RESET K2 J3 I Device reset
NMI L2 K2 I Nonmaskable interrupt
-Edge-driven (rising edge)
EXT_INT7 V4 U2
External interrupts
EXT_INT6 Y2 U3
I
External interrupts
-Edge-driven
EXT_INT5 AA1 W1 I
-Edge-driven
-Polarity independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0])
EXT_INT4 W4 V2
-Polarity independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0])
IACK Y1 V1 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 V2 R3
Active interrupt identification number
INUM2 U4 T1
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
INUM1 V3 T2 O-Valid during IACK for all active interrupts (not just external)
-Encoding order follows the interrupt-service fetch-packet ordering
INUM0 W2 T3 -
Encoding order follows the interrupt-service fetch-packet ordering
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§A = Analog Signal (PLL Filter)
¶For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor . For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
POWER-DOWN STATUS
PD AB2 Y2 O Power-down modes 2 or 3 (active if high)
EXPANSION BUS
XCLKIN A9 C8 I Expansion bus synchronous host interface clock input
XFCLK B9 A8 O Expansion bus FIFO interface clock output
XD31 D15 C13
XD30 B16 A13
XD29 A17 C14
XD28 B17 B14
XD27 D16 B15
XD26 A18 C15
XD25 B18 A15
XD24 D17 B16
XD23 C18 C16
XD22 A20 A17
Expansion bus data
XD21 D18 B17
Expansion bus data
-Used for transfer of data, address, and control
XD20 C19 C17 -
Used for transfer of data, address, and control
-Also controls initialization of DSP modes and expansion bus at reset
XD19 A21 B18
-Also controls initialization of DSP modes and expansion bus at reset
[Note: For more information on pin control and boot configuration fields, see the Boo
t
Modes and Configuration chapter of the TMS320C6000 DSP Peripherals Overview
XD18 D19 A19
[Note: For more information on pin control and boot configuration fields, see the Boot
Modes and Configuration chapter of the TMS320C6000 DSP Peripherals Overview
Reference Guide (literature number SPRU190)]
XD17 C20 C18
Reference Guide (literature number SPRU190)]
XD16 B21 B19
I/O/Z
XD[30:16]− XCE[3:0] memory type
XD13 − XBLAST polarity
XD15 A22 C19 I/O/Z
XD[30:16]− XCE[3:0] memory type
XD13 − XBLAST polarity
XD12 − XW/R polarity
XD14 D20 B20
XD12 − XW/R polarity
XD11 − Asynchronous or synchronous host operation
XD13 B22 A21
XD11 − Asynchronous or synchronous host operation
XD10 − Arbitration mode (internal or external)
XD9 − FIFO mode
XD12 E25 C21
XD10 − Arbitration mode (internal or external)
XD9 − FIFO mode
XD8 − Little endian/big endian
XD11 F24 D20
XD8 − Little endian/big endian
XD[4:0] − Boot mode
XD10 E26 B22
XD[4:0] − Boot mode
All other expansion bus data pins not listed should be pulled down.
XD9 F25 D21 All other expansion bus data pins not listed should be pulled down.
XD8 G24 E20
XD7 H23 E21
XD6 F26 D22
XD5 G25 F20
XD4 J23 F21
XD3 G26 E22
XD2 H25 G20
XD1 J24 G21
XD0 K23 G22
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
EXPANSION BUS (CONTINUED)
XCE3 F2 D2
Expansion bus I/O port memory space enables
XCE2 E1 B1
O/Z
Expansion bus I/O port memory space enables
Enabled by bits 28, 29, and 30 of the word address
XCE1 F3 D3 O/Z -Enabled by bits 28, 29, and 30 of the word address
-Only one asserted during any I/O port data access
XCE0 E2 C2 -
Only one asserted during any I/O port data access
XBE3/XA5 C7 C5
Expansion bus multiplexed byte-enable control/address signals
XBE2/XA4 D8 A4
I/O/Z
Expansion bus multiplexed byte-enable control/address signals
Act as byte-enable for host-port operation
XBE1/XA3 A6 B5 I/O/Z -Act as byte-enable for host-port operation
-Act as address for I/O port operation
XBE0/XA2 C8 C6 -
Act as address for I/O port operation
XOE A7 A6 O/Z Expansion bus I/O port output-enable
XRE C9 C7 O/Z Expansion bus I/O port read-enable
XWE/XWAIT D10 B7 O/Z Expansion bus I/O port write-enable and host-port wait signals
XCS A10 C9 I Expansion bus host-port chip-select input
XAS D9 B6 I/O/Z Expansion bus host-port address strobe
XCNTL B10 B9 I Expansion bus host control. XCNTL selects between expansion bus address or data register.
XW/R D11 B8 I/O/Z Expansion bus host-port write/read-enable. XW/R polarity is selected at reset.
XRDY A5 C4 I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high)
XBLAST B6 B4 I/O/Z Expansion bus host-port burst last-polarity selected at reset
XBOFF B11 A10 I Expansion bus back off
XHOLD B5 A2 I/O/Z Expansion bus hold request
XHOLDA D7 B3 I/O/Z Expansion bus hold acknowledge
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 AB25 Y21
Memory space enables
CE2 AA24 W20
O/Z
Memory space enables
Enabled by bits 24 and 25 of the word address
CE1 AB26 AA22 O/Z -Enabled by bits 24 and 25 of the word address
-Only one asserted during any external data access
CE0 AA25 W21 -
Only one asserted during any external data access
BE3 Y24 V20
Byte-enable control
BE2 W23 V21
O/Z
Byte-enable control
-Decoded from the two lowest bits of the internal address
BE1 AA26 W22 O/Z
-Decoded from the two lowest bits of the internal address
-Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BE0 Y25 U20
-Byte-write enables for most types of memory
-Can be directly connected to SDRAM read and write mask signal (SDQM)
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
EMIF − ADDRESS
EA21 J25 H20
EA20 J26 H21
EA19 L23 H22
EA18 K25 J20
EA17 L24 J21
EA16 L25 K21
EA15 M23 K20
EA14 M24 K22
EA13 M25 L21
EA12 N23 L20
O/Z
External address (word address)
EA11 P24 L22 O/Z External address (word address)
EA10 P23 M20
EA9 R25 M21
EA8 R24 N22
EA7 R23 N20
EA6 T25 N21
EA5 T24 P21
EA4 U25 P20
EA3 T23 R22
EA2 V26 R21
EMIF − DATA
ED31 AD8 Y6
ED30 AC9 AA6
ED29 AF7 AB6
ED28 AD9 Y7
ED27 AC10 AA7
ED26 AE9 AB8
ED25 AF9 Y8
ED24 AC11 AA8
ED23 AE10 AA9
I/O/Z
External data
ED22 AD11 Y9 I/O/Z External data
ED21 AE11 AB10
ED20 AC12 Y10
ED19 AD12 AA10
ED18 AE12 AA11
ED17 AC13 Y11
ED16 AD14 AB12
ED15 AC14 Y12
ED14 AE15 AA12
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
EMIF − DATA (CONTINUED)
ED13 AD15 AA13
ED12 AC15 Y13
ED11 AE16 AB13
ED10 AD16 Y14
ED9 AE17 AA14
ED8 AC16 AA15
ED7 AF18 Y15
I/O/Z
External data
ED6 AE18 AB15 I/O/Z External data
ED5 AC17 AA16
ED4 AD18 Y16
ED3 AF20 AB17
ED2 AC18 AA17
ED1 AD19 Y17
ED0 AF21 AA18
EMIF − ASYNCHRONOUS MEMORY CONTROL
ARE V24 T21 O/Z Asynchronous memory read-enable
AOE V25 R20 O/Z Asynchronous memory output-enable
AWE U23 T22 O/Z Asynchronous memory write-enable
ARDY W25 T20 I Asynchronous memory ready input
EMIF − SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10 AE21 AA19 O/Z SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS AE22 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE AF22 Y19 O/Z SDRAM row-address strobe/SBSRAM output-enable
SDWE/SSWE AC20 AA20 O/Z SDRAM write-enable/SBSRAM write-enable
EMIF − BUS ARBITRATION
HOLD Y26 V22 I Hold request from the host
HOLDA V23 U21 O Hold-request-acknowledge to the host
TIMER 0
TOUT0 F1 D1 O Timer 0 or general-purpose output
TINP0 H4 E2 I Timer 0 or general-purpose input
TIMER 1
TOUT1 J4 F2 O Timer 1 or general-purpose output
TINP1 G2 F3 I Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3 Y3 V3
DMAC2 AA2 W2
O
DMA action complete
DMAC1 AB1 AA1 ODMA action complete
DMAC0 AA3 W3
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 M4 K3 I External clock source (as opposed to internal)
CLKR0 M2 L2 I/O/Z Receive clock
CLKX0 M3 K1 I/O/Z Transmit clock
DR0 R2 M2 I Receive data
DX0 P4 M3 O/Z Transmit data
FSR0 N3 M1 I/O/Z Receive frame sync
FSX0 N4 L3 I/O/Z Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 G1 E1 I External clock source (as opposed to internal)
CLKR1 J3 G2 I/O/Z Receive clock
CLKX1 H2 G3 I/O/Z Transmit clock
DR1 L4 H1 I Receive data
DX1 J1 H2 O/Z Transmit data
FSR1 J2 H3 I/O/Z Receive frame sync
FSX1 K4 G1 I/O/Z Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
CLKS2 R3 N1 I External clock source (as opposed to internal)
CLKR2 T2 N2 I/O/Z Receive clock
CLKX2 R4 N3 I/O/Z Transmit clock
DR2 V1 R2 I Receive data
DX2 T4 R1 O/Z Transmit data
FSR2 U2 P3 I/O/Z Receive frame sync
FSX2 T3 P2 I/O/Z Transmit frame sync
RESERVED FOR TEST
RSV0 L3 J2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1 G3 E3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2 A12 B11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3 C15 B13 O Reserved (leave unconnected, do not connect to power or ground)
RSV4 D12 C10 O Reserved (leave unconnected, do not connect to power or ground)
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS
A11 A3
A16 A7
B7 A16
B8 A20
B19 D4
B20 D6
C6 D7
C10 D9
C14 D10
C17 D13
C21 D14
G4 D16
G23 D17
H3 D19
H24 F1
K3 F4
K24 F19
L1 F22
L26 G4
DV
DD
N24 G19 S3.3-V supply voltage (I/O)
DVDD
P3 J4
S
3.3-V supply voltage (I/O)
T1 J19
T26 K4
U3 K19
U24 L1
W3 M22
W24 N4
Y4 N19
Y23 P4
AD6 P19
AD10 T4
AD13 T19
AD17 U1
AD21 U4
AE7 U19
AE8 U22
AE19 W4
AE20 W6
AF11 W7
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
AF16 W9
— W10
— W13
— W14
— W16
DV
DD
— W17 S3.3-V supply voltage (I/O)
DVDD
— W19
S
3.3-V supply voltage (I/O)
— AB5
— AB9
— AB14
— AB18
A1 E7
A2 E8
A3 E10
A24 E11
A25 E12
A26 E13
B1 E15
B2 E16
B3 F7
B24 F8
B25 F9
B26 F11
C1 F12
C2 F14
1.5-V supply voltage (core)
CV
DD
C3 F15 S
1.5-V supply voltage (core)
1.7-V supply voltage (core) (C6203BGLS, C6203BGNY, C6203BZNY and C6203BGNZ
1.7-V parts only)
CVDD
C4 F16
S
1.7-V supply voltage (core) (C6203BGLS, C6203BGNY, C6203BZNY and C6203BGNZ
1.7-V parts only)
C23 G5
C24 G6
C25 G17
C26 G18
D3 H5
D4 H6
D5 H17
D22 H18
D23 J6
D24 J17
E4 K5
E23 K18
AB4 L5
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
AB23 L6
AC3 L17
AC4 L18
AC5 M5
AC22 M6
AC23 M17
AC24 M18
AD1 N5
AD2 N18
AD3 P6
AD4 P17
AD23 R5
AD24 R6
AD25 R17
AD26 R18
AE1 T5
AE2 T6
1.5-V supply voltage (core)
CV
DD
AE3 T17 S
1.5-V supply voltage (core)
1.7-V supply voltage (core) (C6203BGLS, C6203BGNY, C6203BZNY and C6203BGNZ
1.7-V parts only)
CVDD
AE24 T18
S
1.7-V supply voltage (core) (C6203BGLS, C6203BGNY, C6203BZNY and C6203BGNZ
1.7-V parts only)
AE25 U7
AE26 U8
AF1 U9
AF2 U11
AF3 U12
AF24 U14
AF25 U15
AF26 U16
− V7
− V8
− V10
− V11
− V12
− V13
− V15
− V16
GROUND PINS
A4 A1
VSS
A8 A5
GND
Ground pins
VSS A13 A12 GND Ground pins
A14 A18
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
A15 A22
A19 B2
A23 B21
B4 C1
B12 C3
B13 C20
B14 C22
B23 D5
C5 D8
C16 D11
C22 D12
D1 D15
D2 D18
D6 E4
D21 E5
D25 E6
D26 E9
VSS
E3 E14
GND
Ground pins
VSS E24 E17 GND Ground pins
F4 E18
F23 E19
H1 F5
H26 F6
K1 F10
K26 F13
M1 F17
M26 F18
N1 H4
N2 H19
N25 J1
N26 J5
P1 J18
P2 J22
P25 K6
P26 K17
R1 L4
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
R26 L19
U1 M4
U26 M19
W1 N6
W26 N17
AA4 P1
AA23 P5
AB3 P18
AB24 P22
AC1 R4
AC2 R19
AC6 U5
AC21 U6
AC25 U10
AC26 U13
AD5 U17
AD22 U18
AE4 V4
V
SS
AE13 V5 GND Ground pins
VSS
AE14 V6
GND
Ground pins
AE23 V9
AF4 V14
AF8 V17
AF10 V18
AF12 V19
AF13 W5
AF14 W8
AF15 W11
AF17 W12
AF19 W15
AF23 W18
− Y1
− Y3
− Y20
− Y22
− AA2
− AA21
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
PIN NO.
SIGNAL
NAME GNZ GLS/
GNY/
ZNY
TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
— AB1
— AB3
— AB7
V
SS
— AB11 GND Ground pins
VSS
— AB16
GND
Ground pins
— AB20
— AB22
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
development support
TI o ffers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate
the performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP,
or TMS (e.g., TMS320C6203BGLS300). Texas Instruments recommends two of three possible prefix
designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools
(TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GLS), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -300 is 300 MHz).
The ZNY package, like the GNY package, is a 384-ball plastic BGA only with Pb-free balls. For device part
numbers and further ordering information for TMS320C6203B in the GNZ, GLS, GNY and ZNY package types,
see the TI website (http://www.ti.com) or contact your TI sales representative.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PREFIX DEVICE SPEED RANGE
TMS 320 C 6203B GLS 300
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
DEVICE FAMILY
320 = TMS320t DSP family
TECHNOLOGY
PACKAGE TYPE†‡
GFN = 256-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GNY = 384-pin plastic BGA
GNZ = 352-pin plastic BGA
GLZ = 532-pin plastic BGA
GHK = 288-pin plastic MicroStar BGAt
ZNY = 384-pin plastic BGA, with Pb-free soldered balls
C = CMOS
DEVICE§
C6000 DSP:
6201 6205 6415 6711C
6202 6211 6416 6712
6202B 6211B 6701 6712C
6203B 6411 6711 6713
6204 6414 6711B
†BGA = Ball Grid Array
‡The ZNY mechanical package designator represents the version of the GNY with Pb−Free soldered balls.
§For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this
document or the TI website (www.ti.com).
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
( )
Blank = 0°C to 90°C, commercial temperature
A = −40°C to 105°C, extended temperature
100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
500 MHz
600 MHz
Figure 4. TMS320C6000 DSP Platform Device Nomenclature (Including TMS320C6203B)
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
documentation support
Extensive documentation supports all TMS320 DSP family devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices and tools; technical briefs;
development-support tools; on-line help; and hardware and software applications. The following is a brief,
descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) briefly
describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the
64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buf fered
serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller,
expansion bus (XBus), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and
power-down modes.
The How to Begin Development Today and Migrate Across the TMS320C6202/02B/03B/04 DSPs Application
Report (literature number SPRA603) describes the migration concerns and identifies the similarities and
differences between the C6202, C6202B, C6203B, and C6204 C6000 DSP devices.
The TMS320C6203, TMS320C6203B Digital Signal Processors Silicon Errata (literature number SPRZ174)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320C6203 and TMS320C6203B devices.
The Using IBIS Models for Timing Analysis Application Report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio IDE. For a
complete listing of the latest C6000 DSP documentation, visit the Texas Instruments web site on the Worldwide
Web at http://www.ti.com uniform resource locator (URL).
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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clock PLL
Most of the internal C6203B clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
and Table 15 through Table 17 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply
modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6203B device and the external
clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section.
CLKMODE0
CLKMODE1 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to C6203B
CPU
CLOCK
C1 R1
3.3 V
10 mF0.1 mF
PLLF
C3 C4
1
0
CLKMODE2†
(For the PLL Options
and CLKMODE pins setup,
see Table 15 through Table 17)
EMI Filter
†The CLKMODE2 pin is not available for the C6203B GNZ package.
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved with
the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
clock PLL (continued)
PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
Internal to C6203B
CPU
CLOCK
PLLF
1
0
3.3V
CLKMODE0
CLKMODE1
CLKMODE2†
† The CLKMODE2 pin is not available for the C6203B GNZ package.
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
Table 15. TMS320C6203B GLS and C6203B GNY and ZNY Packages PLL Multiply and Bypass (x1)
Options†
GLS PACKAGE − 18 X 18 MM BGA
GNY AND ZNY PACKAGES − 18 X 18 MM BGA
BIT
CLKMODE2
CLKMODE1
CLKMODE0
DEVICES AND PLL CLOCK OPTIONS
BIT
(PIN NO.)
CLKMODE2
(A14)
CLKMODE1
(A9)
CLKMODE0
(B12) GLS GNY AND ZNY
0 0 0 Bypass (x1) Bypass (x1)
0 0 1 x4 x4
0 1 0 x8 x8
Value
0 1 1 x10 x10
Value 1 0 0 x6 x6
1 0 1 x9 x9
1 1 0 x7 x7
1 1 1 x11 x11
†f(CPU Clock) = f(CLKIN) x (PLL mode)
Table 16. TMS320C6203B GNZ Package PLL Multiply and Bypass (x1) Options†
GNZ PACKAGE 27 X 27 MM BGA
BIT
(PIN NO.) CLKMODE2
(N/A)‡CLKMODE1
(C11) CLKMODE0
(B15) DEVICES AND PLL CLOCK OPTIONS
0 0 Bypass (x1)
Value
N/A
0 1 x4
Value
N/A
1 0 x8
1 1 x10
†f(CPU Clock) = f(CLKIN) x (PLL mode)
‡The CLKMODE2 pin is not available (N/A) for the C6203B GNZ package.
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clock PLL (continued)
Table 17. TMS320C6203B PLL Component Selection Table†
CLKMODE‡CLKIN
RANGE
(MHZ)
CPU CLOCK
FREQUENCY
RANGE (MHZ)
CLKOUT2
RANGE
(MHZ)
R1 [±1%]
(REVISION
NO.)
C1 [±10%]
(REVISION
NO.)
C2 [±10%]
(REVISION
NO.)
TYPICAL
LOCK TIME
(ΜS)
x4 32.5−75
x6 21.7−50
x7 18.6−42.9
60.4 (1.X)
27 NF (1.X)
560 PF (1.X)
x8 16.3−37.5 130−300 65−150
60.4 (1.X)
45.3 (2.X,
3.X)
27 NF (1.X)
47 NF (2.X,
3.X)
560 PF (1.X)
10 PF (2.X,
3.X)
75
x9 14.4−33.3
130−300
65−150
45.3
(2.X,
3.X)
47 NF (2.X,
3.X)
10 PF (2.X,
3.X)
75
x10 13−30
x11 11.8−27.3
†Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
‡CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS/GNY/ZNY devices. The GNZ device is restricted to x1, x4, x8, and x10 multiply
factors.
power-down mode logic
Figure 7 shows the power-down logic on for the 6203B.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Internal
Peripheral
Clock
PLL
CLKIN RESET
CLKOUT1
TMS320C6203B
PD
(pin)
PD3
Internal
Peripheral
Figure 7. Power-Down Mode Logic
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triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 10−15)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 18.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
31 16
15 14 13 12 11 10 9 8
Reserved Enable or
non-enabled
interrupt wake
Enabled
interrupt wake PD3 PD2 PD1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 8. PWRD Field of the CSR Register
Power-down mode P D1 t akes e f fect e ight t o n ine c lock c ycles a fter t he i nstruction t hat s ets t he P WRD b its i n t he
CSR.
If P D1 m ode i s t erminated b y a n on-enabled i nterrupt, t he p rogram e x ecution r eturns t o t he i nstruction w here P D 1
took e f fect . I f P D1 m ode i s t erminated b y a n e nabled i nterrupt, t he i nterrupt s ervice r outine w ill b e e xecuted f irst,
then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE
bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute;
otherwise, execution r eturns t o t he i nstruction w here P D1 t ook e f fect u pon P D1 mode termination b y a n e nabled
interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 18 summarizes all the power-down modes.
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Table 18. Characteristics of the Power-Down Modes
PRWD
BITS 15−10 POWER-DOWN
MODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION
000000 No power-down —
001001 PD1 Wake by an enabled interrupt CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
010001 PD1 Wake by an enabled or
non-enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary o f the CPU, preventing most of its logic from switching
.
During PD1, DMA transactions can proceed between peripheral
s
and internal memory.
011010 PD2†Wake by a device reset Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. Signal terminal PD is driven high. All register and internal
RAM contents are preserved. All functional I/O “freeze” in the last
state when the PLL clock is turned off.‡
011100 PD3†Wake by a device reset Input clock to the PLL stops generating clocks. Signal terminal P D
is d riven h igh. A ll r egister a nd i nternal R AM c ontents a re p reserved.
All functional I/O “freeze” in the last state when the PLL clock is
turned of f.† F ollowing reset, the P LL needs time to re-lock, just as
it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked.
other Reserved —
†On the C6203B, both the PD2 and PD3 signals assert the PD pin for external recognition of these two power-down modes.
‡When entering PD2 and PD3, all functional I/O will remain in the previous state. However, for peripherals which are asynchronous in nature
(HPI) or peripherals with an external clock source (McBSP, XBUS, timers), output signals may transition in response to stimulus on the inputs.
Peripheral operation may not perform as intended under these conditions.
peripheral power-down mode for TMS320C6203B
The C6203B has the ability to turn of f clocks to individual peripherals on the device. This feature allows the user
to selectively turn off peripherals which are not being used for a specific application and not pay the extra price
in power consumption for unused peripherals.
The Figure 9 title displays the peripheral power down register address location and Figure 9 itself shows the
register fields.
31 16
Reserved
R-0
15 8
Reserved
R-0
7 543210
Reserved MCBSP2 MCBSP1 MCBSP0 EMIF DMA
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W−x = Read/write reset value
Figure 9. Peripheral Power-Down Control Register (PDCTL) for TMS320C6203B (019C 0200h)
triggering, wake-up, and effects (continued)
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peripheral power-down mode for TMS320C6203B (continued)
Table 19 lists and describes the fields in the peripheral power-down control register (PDCTL).
Table 19. Power-Down Control Register (PDCTL) Field Desccriptions
BIT FIELD VALUE DESCRIPTION
31−5 Reserved Reserved. The reserved bit location is always read as zero. A value written to this field has no
effect.
4 MCBSP2 Internal McBSP2 clock enable bit.
0Internal McBSP2 clock is enabled.
1Internal McBSP2 clock is disabled. McBSP2 is not functional.
3 MCBSP1 Internal McBSP1 clock enable bit.
0Internal McBSP1 clock is enabled.
1Internal McBSP1 clock is disabled. McBSP1 is not functional.
2 MCBSP0 Internal McBSP0 clock enable bit.
0Internal McBSP0 clock is enabled.
1Internal McBSP0 clock is disabled. McBSP1 is not functional.
1 EMIF Internal EMIF clock enable bit.
0Internal EMIF clock is enabled.
1Internal EMIF clock is disabled. EMIF is not functional.
0DMA Internal DMA clock enable bit.
0Internal DMA clock is enabled.
1Internal DMA clock is disabled. DMA is not functional.
The user must be careful to not disable a portion of the device which is being used, since the peripheral becomes
non-operational once disabled. A clock-off mode can be entered and exited depending on the needs of the
application. For example, if an application does not need the serial ports, the ports can be disabled and then
re-enabled when needed. While a peripheral is in power-down mode, no writes to the peripheral’ s registers will
occur; and reads from the peripheral will produce invalid data.
When re-enabling any of the peripheral power-down bits, the CPU should wait at least 5 additional clock cycles
before attempting to access that peripheral.
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power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, therefore, preventing bus contention with other chips on the board.
power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 10).
DVDD
CVDD
VSS
C6000
DSP
Schottky
Diode
I/O Supply
Core Supply
GND
Figure 10. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core,
I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
On systems using C62x and C67x DSPs, the core may consume in excess of 2 A per DSP until the I/O supply
powers on. This extra current results from uninitialized logic within the DSP(s). A normal current state returns
once the I/O power supply turns on and the CPU sees a clock pulse. Decreasing the amount of time between
the core supply power-up and the I/O supply power-up reduces the effects of the current draw. If the external
supply to the DSP core cannot supply the excess current, the minimum core voltage may not be achieved until
after normal current returns. This voltage starvation of the core supply during power up does not af fect run-time
operation. Voltage starvation can affect power supply systems that gate the I/O supply via the core supply,
causing the I/O supply to never turn on. During the transition from excess to normal current, a voltage spike may
be seen on the core supply. Care must be taken when designing overvoltage protection circuitry on the core
supply to not restart the power sequence due to this spike. Otherwise, the supply may cycle indefinitely.
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IEEE 1149.1 JTAG compatibility statement
For compatibility with IEEE 1149.1 JTAG programmers, the TRST pin may need to be externally pulled up via
a 1-kΩ resistor. For these C62x devices, this pin is internally pulled down, holding the JTAG port in reset by
default. This is typically only a problem in systems where the DSP shares a scan chain with some other device.
Some JTAG programmers for these other devices do not actively drive TRST high, leaving the scan chain
inoperable while the C62x JTAG port is held in reset. TI emulators do drive TRST high, so the external pullup
resistor is not needed in systems where TI emulators are the only devices that control JTAG scan chains on
which the DSP(s) reside. If the system has other devices in the same scan chain as the DSP, and the
programmer for these devices does not drive TRST high, then an external 1-kΩ pullup resistor is required.
With this external 1-kΩ pullup resistor installed, care must be taken to keep the DSP in a usable state under
all circumstances. When TRST is pulled up, the JTAG driver must maintain the TMS signal high for 5 TCLK
cycles, forcing the DSP(s) into the test logic reset (TLR) state. From the TLR state, the DSP’s data scan path
can be put in bypass (scan all 1s into the IR) to scan the other devices. The TLR state also allows normal
operation of the DSP. If operation without anything driving the JTAG port is desired, the pullup resistor should
be jumpered so that it may be engaged for programming the other devices and disconneted for running without
a JTAG programmer or emulator.
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absolute maximum ratings over operating case temperature ranges (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) − 0.3 V to 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, DVDD (see Note 1) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature ranges, TC:(default) 0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(A version): C6203BGNZA-250 −40_C to105_C. . . . . . . . . . . . . . .
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature cycle range, (1000-cycle performance) −40_C to 125_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
CVDD
Supply voltage, Core 1.43 1.5 1.57 V
CVDD Supply voltage, Core‡1.65 1.7 1.75 V
DVDD Supply voltage, I/O 3.14 3.3 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −8 mA
IOL Low-level output current 8 mA
TC
Operating case temperature
Default 0 90 _C
T
C
Operating case temperature
A version: C6203BGNZA-250 −40 105 _C
‡Supply voltage, Core for the C6203B 1.7 V devices which are identified in the orderable part number with a “17” following the device number
and the package type identifiers.
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.6 V
IIInput current§VI = VSS to DVDD ±10 uA
IOZ Off-state output current VO = DVDD or 0 V ±10 uA
IDD2V Supply current, CPU + CPU memory
access¶C6203B, CVDD = NOM, CPU clock = 300 MHz 510 mA
IDD2V Supply current, peripherals¶C6203B, CVDD = NOM, CPU clock = 300 MHz 352 mA
IDD3V Supply current, I/O pins¶C6203B, CVDD = NOM, CPU clock = 300 MHz 67 mA
CiInput capacitance 10 pF
CoOutput capacitance 10 pF
§TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
¶Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C62x/C67x
Power Consumption Summary application report (literature number SPRA486).
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PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
Vcomm
IOL
CT
IOH
Output
Under
Test
50 Ω
Where: IOL = 2 mA
IOH = 2 mA
Vcomm = 1.5 V
CT= 15-pF typical load-circuit capacitance
Figure 11. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 12. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and
VOL MAX and VOH MIN for output clocks.
Vref = VIL MAX (or VOL MAX)
Vref = VIH MIN (or VOH MIN)
Figure 13. Rise and Fall Transition Time Voltage Reference Levels
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 20 and Figure 14).
Figure 14 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 20. Board-Level Timings Examples (see Figure 14)
NO. DESCRIPTION
1Clock route delay
2Minimum DSP hold time
3Minimum DSP setup time
4External device hold time requirement
5External device setup time requirement
6Control signal route delay
7External device hold time
8External device access time
9DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
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1
2
3
4
5
6
7
8
10
11
CLKOUT2
(Output from DSP)
CLKOUT2
(Input to External Device)
Control Signals†
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals‡
(Output from External Device)
Data Signals‡
(Input to DSP)
9
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 14. Board-Level Input/Output Timings
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INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN (PLL used)†‡§ (see Figure 15)
NO.
-250 -300
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 4 * M 3.33 * M ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11) for C6203B GLS, GNY and ZNY only.
M = the PLL multiplier factor (x4, x8, or x10) for C6203B GNZ only.
For more details on both devices, see the Clock PLL section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN [PLL bypassed (x1)]†¶ (see Figure 15)
NO.
-250 -300
UNIT
NO.
MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 4 3.33 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 0.6 0.6 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
¶C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. The maximum CLKIN cycle time in PLL bypass
mode (x1) is 200 MHz.
CLKIN
1
2
3
4
4
Figure 15. CLKIN Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for XCLKIN† (see Figure 16)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
1 tc(XCLKIN) Cycle time, XCLKIN 4P ns
2 tw(XCLKINH) Pulse duration, XCLKIN high 1.8P ns
3 tw(XCLKINL) Pulse duration, XCLKIN low 1.8P ns
†P = 1/CPU clock frequency in nanoseconds (ns).
XCLKIN
1
2
3
Figure 16. XCLKIN Timings
switching characteristics over recommended operating conditions for CLKOUT2ठ(see Figure 17)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 tw(CKO2H) Pulse duration, CLKOUT2 high P − 0.7 P + 0.7 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low P − 0.7 P + 0.7 ns
‡P = 1/CPU clock frequency in ns.
§The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
CLKOUT2
1
3
2
Figure 17. CLKOUT2 Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for XFCLK†‡ (see Figure 18)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tc(XFCK) Cycle time, XFCLK D * P − 0.7 D * P + 0.7 ns
2 tw(XFCKH) Pulse duration, XFCLK high (D/2) * P − 0.7 (D/2) * P + 0.7 ns
3 tw(XFCKL) Pulse duration, XFCLK low (D/2) * P − 0.7 (D/2) * P + 0.7 ns
†P = 1/CPU clock frequency in ns.
‡D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable
XFCLK
1
2
3
Figure 18. XFCLK Timings
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ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§¶ (see Figure 19 − Figure 22)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 1 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 4.9 ns
6 tsu(ARDYH-AREL) Setup time, ARDY high before ARE low −[(RST − 3) * P − 6] ns
7 th(AREL-ARDYH) Hold time, ARDY high after ARE low (RST − 3) * P + 2 ns
9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low −[(RST − 3) * P − 6] ns
10 th(AREL-ARDYL) Hold time, ARDY low after ARE low (RST − 3) * P + 2 ns
11 tw(ARDYH) Pulse width, ARDY high 2P ns
15 tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low −[(WST − 3) * P − 6] ns
16 th(AWEL-ARDYH) Hold time, ARDY high after AWE low (WST − 3) * P + 2 ns
18 tsu(ARDYL-AWEL) Setup time, ARDY low before AWE low −[(WST − 3) * P − 6] ns
19 th(AWEL-ARDYL) Hold time, ARDY low after AWE low (WST − 3) * P + 2 ns
†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous memory
cycles‡§¶# (see Figure 19 − Figure 22)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN TYP MAX
UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * P − 2 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * P − 2 ns
5 tw(AREL) Pulse width, ARE low RST * P ns
8 td(ARDYH-AREH) Delay time, ARDY high to ARE high 3P 4P + 5 ns
12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * P − 3 ns
13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * P − 2 ns
14 tw(AWEL) Pulse width, AWE low WST * P ns
17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high 3P 4P + 5 ns
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
#Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
5
2
1
4
3
21
21
7
6
CLKOUT1
CEx†
BE[3:0]
ED[31:0]
AOE
ARE
AWE
ARDY
21
EA[21:2]
†CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read
HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.
Figure 19. Asynchronous Memory Read Timing (ARDY Not Used)
Setup = 2 Strobe = 3 Not Ready Hold = 2
8
21
4
3
21
21
21
11
10
9
CLKOUT1
CEx†
BE[3:0]
ED[31:0]
AOE
ARE
AWE
ARDY
EA[21:2]
†CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read
HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.
Figure 20. Asynchronous Memory Read Timing (ARDY Used)
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
14
1312
1312
1312
1312
16
15
CEx†
BE[3:0]
ED[31:0]
AOE
ARE
AWE
ARDY
EA[21:2]
CLKOUT1
†If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value
of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely
reflects the EMIF’s overhead.
Figure 21. Asynchronous Memory Write Timing (ARDY Not Used)
Setup = 2 Strobe = 3 Not Ready Hold = 2
17
1312
1312
1312
1312
11
19
18
CEx†
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
CLKOUT1
†If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value
of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely
reflects the EMIF’s overhead.
Figure 22. Asynchronous Memory Write Timing (ARDY Used)
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles for C6203B Rev. 2 (see Figure 23)
NO.
-250 -300
UNIT
NO.
MIN MAX MIN MAX
UNIT
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.0 1.7 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.0 1.5 ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles for C6203B Rev. 2†‡ (see Figure 23 and Figure 24)
NO.
PARAMETER
-250 -300
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P − 0.8 P + 0.1 ns
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high P − 3 P − 2.3 ns
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P − 0.8 P + 0.1 ns
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high P − 3 P − 2.3 ns
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P − 0.8 P + 0.1 ns
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high P − 3 P − 2.3 ns
9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2
high P − 0.8 P + 0.1 ns
10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2
high P − 3 P − 2.3 ns
11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2
high P − 0.8 P + 0.1 ns
12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high P − 3 P − 2.3 ns
13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§P − 1.2 P + 0.1 ns
14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high P − 3 P − 2.3 ns
15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2
high P − 0.8 P + 0.1 ns
16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high P − 3 P − 2.3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles for C6203B Rev. 3 (see Figure 23)
NO.
C6203BGNY173-250
C6203BZNY173-250
C6203BGNZ173-250
C6203BGNZA-250
C6203BGNY173-300
C6203BZNY173-300
C6203BGNY300-300
C6203BZNY300-300
C6203BGNZ173-300
C6203BGNZ300-300
C6203BGNY3
E-300
C6203BZNY3
E-300 UNIT
MIN MAX MIN MAX MIN MAX
7 tsu(EDV-CKO2H) Setup time, read EDx valid
before CLKOUT2 high 2.9 1.6 1.6 ns
8 th(CKO2H-EDV) Hold time, read EDx valid
after CLKOUT2 high 2.1 2.3 2.3 ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles for C6203B Rev. 3†‡ (see Figure 23 and Figure 24)
NO. PARAMETER
C6203BGNY173-250
C6203BZNY173-250C
6203BGNZ173-250
C6203BGNZA-250
C6203BGNY173-300
C6203BZNY173-300
C6203BGNY300-300
C6203BZNY300-300
C6203BGNZ173-300
C6203BGNZ300-300
C6203BGNY3E-300
C6203BZNY3E-300 UNIT
MIN MAX MIN MAX MIN MAX
1 tosu(CEV-CKO2H) Output setup time,
CEx valid before
CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
2 toh(CKO2H-CEV) Output hold time, CEx
valid after CLKOUT2
high P − 3.4 P − 2.7 P − 2.7 ns
3 tosu(BEV-CKO2H) Output setup time,
BEx valid before
CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
4 toh(CKO2H-BEIV) Output hold time, BEx
invalid after CLKOUT2
high P − 3.4 P − 2.7 P − 2.7 ns
5 tosu(EAV-CKO2H) Output setup time,
EAx valid before
CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
6 toh(CKO2H-EAIV) Output hold time, EAx
invalid after CLKOUT2
high P − 3.4 P − 2.7 P − 2.7 ns
9 tosu(ADSV-CKO2H) Output setup time,
SDCAS/SSADS valid
before CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
10 toh(CKO2H-ADSV) Output hold time,
SDCAS/SSADS valid
after CLKOUT2 high P − 3.4 P − 2.7 P − 2.7 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles for C6203B Rev. 3†‡ (see Figure 23 and Figure 24) (continued)
NO
.
PARAMETER
C6203BGNY173-250
C6203BZNY173-250
C6203BGNZ173-250
C6203BGNZA-250
C6203BGNY173-300
C6203BZNY173-300
C6203BGNY300-300
C6203BZNY300-300
C6203BGNZ173-300
C6203BGNZ300-300
C6203BGNY3E-300
C6203BZNY3E-300 UNIT
MIN MAX MIN MAX MIN MAX
11 tosu(OEV-CKO2H)
Output setup time,
SDRAS/SSOE valid
before CLKOUT2
high
P − 1.7 P − 1 P − 1.5 ns
12 toh(CKO2H-OEV) Output hold time,
SDRAS/SSOE valid
after CLKOUT2 high P − 3.4 P − 2.7 P − 2.7 ns
13 tosu(EDV-CKO2H) Output setup time,
EDx valid before
CLKOUT2 high§P − 2.3 P − 1.6 P − 1.6 ns
14 toh(CKO2H-EDIV) Output hold time,
EDx invalid after
CLKOUT2 high P − 3.2 P − 2.5 P − 2.5 ns
15 tosu(WEV-CKO2H)
Output setup time,
SDWE/SSWE valid
before CLKOUT2
high
P − 1.7 P − 1 P − 1.5 ns
16 toh(CKO2H-WEV) Output hold time,
SDWE/SSWE valid
after CLKOUT2 high P − 3.4 P − 2.7 P − 2.7 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SDCAS/SSADS†
SDRAS/SSOE†
SDWE/SSWE†
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
65
43
21
8
7
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 23. SBSRAM Read Timing
CLKOUT2
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SDRAS/SSOE†
SDWE/SSWE†
SDCAS/SSADS†
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1615
109
1413
65
43
21
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 24. SBSRAM Write Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles for C6203B Rev. 2 (see Figure 25)
NO.
-250 -300
UNIT
NO.
MIN MAX MIN MAX
UNIT
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 1.2 0.5 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.7 2 ns
switching characteristics over recommended operating conditions for synchronous DRAM cycles
for C6203B Rev. 2†‡ (see Figure 25−Figure 30)
NO.
PARAMETER
-250 -300
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P − 0.9 P + 0.6 ns
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high P − 2.9 P − 1.8 ns
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P − 0.9 P + 0.6 ns
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high P − 2.9 P − 1.8 ns
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P − 0.9 P + 0.6 ns
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high P − 2.9 P − 1.8 ns
9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2
high P − 0.9 P + 0.6 ns
10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high P − 2.9 P − 1.8 ns
11 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§P − 1.5 P + 0.6 ns
12 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high P − 2.8 P − 1.8 ns
13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high P − 0.9 P + 0.6 ns
14 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high P − 2.9 P − 1.8 ns
15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high P − 0.9 P + 0.6 ns
16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high P − 2.9 P − 1.8 ns
17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2
high P − 0.9 P + 0.6 ns
18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high P − 2.9 P − 1.8 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
timing requirements for synchronous DRAM cycles for C6203B Rev. 3 (see Figure 25)
NO. PARAMETER
C6203BGNY173-250
C6203BZNY173-250
C6203BGNZ173-250
C6203BGNZA-250
C6203BGNY173-300
C6203BZNY173-300
C6203BGNY300-300
C6203BZNY300-300
C6203BGNZ173-300
C6203BGNZ300-300
C6203BGNY3E-300
C6203BZNY3E-300 UNIT
MIN MAX MIN MAX MIN MAX
7 tsu(EDV-CKO2H) Setup time, read EDx valid
before CLKOUT2 high 1.3 0 0 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after
CLKOUT2 high 2.3 2.3 2.7 ns
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous DRAM cycles
for C6203B Rev. 3†‡ (see Figure 25−Figure 30)
NO
.
PARAMETER
C6203BGNY173-250
C6203BZNY173-250
C6203BGNZ173-250
C6203BGNZA-250
C6203BGNY173-300
C6203BZNY173-300
C6203BGNY300-300
C6203BZNY300-300
C6203BGNZ173-300
C6203BGNZ300-300
C6203BGNY3E-300
C6203BZNY3E-300 UNIT
MIN MAX MIN MAX MIN MAX UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx
valid before CLKOUT2
high P − 1.7 P − 1 P − 1.5 ns
2 toh(CKO2H-CEV) Output hold time, CEx
valid after CLKOUT2 high P − 3 P − 2.3 P − 2.3 ns
3 tosu(BEV-CKO2H) Output setup time, BEx
valid before CLKOUT2
high P − 1.7 P − 1 P − 1.5 ns
4 toh(CKO2H-BEIV) Output hold time, BEx
invalid after CLKOUT2
high P − 3 P − 2.3 P − 2.3 ns
5 tosu(EAV-CKO2H) Output setup time, EAx
valid before CLKOUT2
high P − 1.7 P − 1 P − 1.5 ns
6 toh(CKO2H-EAIV) Output hold time, EAx
invalid after CLKOUT2
high P − 3 P − 2.3 P − 2.3 ns
9 tosu(CASV-CKO2H) Output setup time,
SDCAS/SSADS valid
before CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
10 toh(CKO2H-CASV) Output hold time,
SDCAS/SSADS valid
after CLKOUT2 high P − 3 P − 2.3 P − 2.3 ns
11 tosu(EDV-CKO2H) Output setup time, EDx
valid before CLKOUT2
high§P − 2.3 P − 1.6 P − 1.5 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous DRAM cycles
for C6203B Rev. 3†‡ (see Figure 25−Figure 30) (continued)
NO
.
PARAMETER
C6203BGNY173-250
C6203BZNY173-250
C6203BGNZ173-250
C6203BGNZA-250
C6203BGNY173-300
C6203BZNY173-300
C6203BGNY300-300
C6203BZNY300-300
C6203BGNZ173-300
C6203BGNZ300-300
C6203BGNY3E-300
C6203BZNY3E-300 UNIT
MIN MAX MIN MAX MIN MAX UNIT
12 toh(CKO2H-EDIV) Output hold time, EDx
invalid after CLKOUT2
high P − 2.7 P − 2 P − 2 ns
13 tosu(WEV-CKO2H) Output setup time,
SDWE/SSWE valid
before CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
14 toh(CKO2H-WEV) Output hold time,
SDWE/SSWE valid
after CLKOUT2 high P − 3 P − 2.3 P − 2.3 ns
15 tosu(SDA10V-CKO2H) Output setup time,
SDA10 valid before
CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
16 toh(CKO2H-SDA10IV) Output hold time,
SDA10 invalid after
CLKOUT2 high P − 3 P − 2.3 P − 2.3 ns
17 tosu(RASV-CKO2H) Output setup time,
SDRAS/SSOE valid
before CLKOUT2 high P − 1.7 P − 1 P − 1.5 ns
18 toh(CKO2H-RASV) Output hold time,
SDRAS/SSOE valid
after CLKOUT2 high P − 3 P − 2.3 P − 2.3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
109
1615
6
5
4
3
21
8
7
READ
READ
READ
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 25. Three SDRAM READ Commands
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
1413
109
1615
12
11
6
5
4
3
2
1
WRITE
WRITE
WRITE
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 26. Three SDRAM WRT Commands
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
Bank Activate/Row Address
Row Address
18
17
15
5
2
1
ACTV
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 27. SDRAM ACTV Command
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†14
18
16
2
15
1
17
13
DCAB
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 28. SDRAM DCAB Command
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
10
9
18
17
2
1
REFR
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 29. SDRAM REFR Command
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
MRS Value
14
10
18
6
2
1
5
17
9
13
MRS
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 30. SDRAM MRS Command
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 31)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 31)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 3P §ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2P ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 3P 7P ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus External Requestor
Owns Bus DSP Owns Bus
C6203B C6203B
1
3
25
4
†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 31. HOLD/HOLDA Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING
timing requirements for reset† (see Figure 32)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
1
tw(RST)
Width of the RESET pulse (PLL stable)‡10P ns
1 tw(RST) Width of the RESET pulse (PLL needs to sync up)§250 µs
10 tsu(XD) Setup time, XD configuration bits valid before RESET high¶5P ns
11 th(XD) Hold time, XD configuration bits valid after RESET high¶5P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL
are stable for C6203B GLS, GNY and ZNY devices. And applies to CLKMODE x4, x6, x8, and x10 when CLKIN and PLL are stable for C6203B
GNZ devices.
§This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only (it does not apply to CLKMODE x1) for C6203B GLS, GNY and ZNY
devices. This parameter applies to CLKMODE x4, x6, x8, and x10 only (it does not apply to CLKMODE x1) for C6203B GNZ devices. The RESET
signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or
after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the Clock PLL
section for PLL lock times.
¶XD[31:0] are the boot configuration pins during device reset.
switching characteristics over recommended operating conditions during reset†# (see Figure 32)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid P ns
3 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 4P ns
4 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid P ns
5 td(RSTH-HIGHV) Delay time, RESET high to high group valid 4P ns
6 td(RSTL-LOWIV) Delay time, RESET low to low group invalid P ns
7 td(RSTH-LOWV) Delay time, RESET high to low group valid 4P ns
8 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance P ns
9 td(RSTH-ZV) Delay time, RESET high to Z group valid 4P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
#High group consists of: XFCLK, HOLDA
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING (CONTINUED)
CLKOUT1
9
8
76
54
32
11
10
RESET
CLKOUT2
HIGH GROUP†
LOW GROUP†
Z GROUP†
XD[31:0]‡
1
Boot Configuration
†High group consists of: XFCLK, HOLDA
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA.
‡XD[31:0] are the boot configuration pins during device reset.
Figure 32. Reset Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles† (see Figure 33)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
2 tw(ILOW) Width of the interrupt pulse low 2P ns
3 tw(IHIGH) Width of the interrupt pulse high 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
switching characteristics over recommended operating conditions during interrupt response
cycles†‡ (see Figure 33)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tR(EINTH−IACKH) Response time, EXT_INTx high to IACK high 9P ns
4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid −1.5 10 ns
5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid −2.0 10 ns
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid −2.0 10 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
‡When CLKOUT2 is in half (1/2) mode (see CLKOUT2 in Signal Descriptions table), timings are based on falling edges .
1
23
5
4 4
6
CLKOUT2 (1/2)
EXT_INTx, NMI
Intr Flag
IACK
INUMx Interrupt Number
Figure 33. Interrupt Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS FIFO TIMING
timing requirements for synchronous FIFO interface (see Figure 34, Figure 35, and Figure 36)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
5 tsu(XDV-XFCKH) Setup time, read XDx valid before XFCLK high 3 ns
6 th(XFCKH-XDV) Hold time, read XDx valid after XFCLK high 2.5 ns
switching characteristics over recommended operating conditions for synchronous FIFO
interface (see Figure 34, Figure 35, and Figure 36)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(XFCKH-XCEV) Delay time, XFCLK high to XCEx valid 1.5 5.5 ns
2 td(XFCKH-XAV) Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid†1.5 5.5 ns
3 td(XFCKH-XOEV) Delay time, XFCLK high to XOE valid 1.5 5.5 ns
4 td(XFCKH-XREV) Delay time, XFCLK high to XRE valid 1.5 5.5 ns
7 td(XFCKH-XWEV) Delay time, XFCLK high to XWE/XWAIT‡ valid 1.5 5.5 ns
8 td(XFCKH-XDV) Delay time, XFCLK high to XDx valid 6 ns
9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid 1.5 ns
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
44
33
22
11
XFCLK
XCE3†
XBE[3:0]/XA[5:2]‡
XOE
XRE
XWE/XWAIT§
XD[31:0]
†FIFO read (glueless) mode only available in XCE3.
‡XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
§XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 34. FIFO Read Timing (Glueless Read Mode)
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
44
33
22
11
XFCLK
XCEx
XBE[3:0]/XA[5:2]†
XOE
XRE
XWE/XWAIT‡
XD[31:0]
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 35. FIFO Read Timing
XA1 XA2 XA3 XA4
D1 D2 D3 D4
9
8
77
22
11
XFCLK
XCEx
XBE[3:0]/XA[5:2]†
XOE
XRE
XD[31:0]
XWE/XWAIT‡
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 36. FIFO Write Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
timing requirements for asynchronous peripheral cycles†‡§¶ (see Figure 37−Figure 40)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
3 tsu(XDV-XREH) Setup time, XDx valid before XRE high 4.5 ns
4 th(XREH-XDV) Hold time, XDx valid after XRE high 2.5 ns
6 tsu(XRDYH-XREL) Setup time, XRDY high before XRE low −[(RST − 3) * P − 6] ns
7 th(XREL-XRDYH) Hold time, XRDY high after XRE low (RST − 3) * P + 2 ns
9 tsu(XRDYL-XREL) Setup time, XRDY low before XRE low −[(RST − 3) * P − 6] ns
10 th(XREL-XRDYL) Hold time, XRDY low after XRE low (RST − 3) * P + 2 ns
11 tw(XRDYH) Pulse width, XRDY high 2P ns
15 tsu(XRDYH-XWEL) Setup time, XRDY high before XWE low −[(WST − 3) * P − 6] ns
16 th(XWEL-XRDYH) Hold time, XRDY high after XWE low (WST − 3) * P + 2 ns
18 tsu(XRDYL-XWEL) Setup time, XRDY low before XWE low −[(WST − 3) * P − 6] ns
19 th(XWEL-XRDYL) Hold time, XRDY low after XWE low (WST − 3) * P + 2 ns
†To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Therefore, XRDY can be an asynchronous input.
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous peripheral
cycles‡§¶# (see Figure 37−Figure 40)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN TYP MAX
UNIT
1 tosu(SELV-XREL) Output setup time, select signals valid to XRE low RS * P − 2 ns
2 toh(XREH-SELIV) Output hold time, XRE low to select signals invalid RH * P − 2 ns
5 tw(XREL) Pulse width, XRE low RST * P ns
8 td(XRDYH-XREH) Delay time, XRDY high to XRE high 3P 4P + 5 ns
12 tosu(SELV-XWEL) Output setup time, select signals valid to XWE low WS * P − 3 ns
13 toh(XWEH-SELIV) Output hold time, XWE low to select signals invalid WH * P − 2 ns
14 tw(XWEL) Pulse width, XWE low WST * P ns
17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high 3P 4P + 5 ns
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
#Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an
additional 7P ns following the end of the cycle.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
5
2
1
4
3
21
21
7
6
CLKOUT1
XCEx
XBE[3:0]/
XA[5:2]†
XD[31:0]
XOE
XRE
XWE/XWAIT‡
XRDY§
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 37. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)
Setup = 2 Strobe = 3 Not Ready Hold = 2
8
21
4
3
21
21
11
10
9
CLKOUT1
XCEx
XD[31:0]
XOE
XRE
XBE[3:0]/
XA[5:2]†
XWE/XWAIT‡
XRDY§
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 38. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
14
1312
1312
1312
16
15
CLKOUT1
XCEx
XD[31:0]
XRE
XBE[3:0]/
XA[5:2]†
XWE/XWAIT‡
XRDY§
XOE
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 39. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)
XOE
Setup = 2 Strobe = 3 Not Ready Hold = 2
17
1312
1312
1312
11
19
18
CLKOUT1
XCEx
XD[31:0]
XRE
XBE[3:0]/
XA[5:2]†
XWE/XWAIT‡
XRDY§
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 40. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as bus master (see Figure 41 and Figure 42)
REV. 2 REV. 3
NO. -250
-300 -250
-300 UNIT
MIN MAX MIN MAX
1 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high 3.5 3.5 ns
2 th(XCKIH-XCS) Hold time, XCS valid after XCLKIN high 2.8 2.8 ns
3 tsu(XAS-XCKIH) Setup time, XAS valid before XCLKIN high 3.5 3.5 ns
4 th(XCKIH-XAS) Hold time, XAS valid after XCLKIN high 2.8 2.8 ns
5 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high 3.5 3.5 ns
6 th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high 2.8 2.8 ns
7 tsu(XWR-XCKIH) Setup time, XW/R valid before XCLKIN high†3.5 3.5 ns
8 th(XCKIH-XWR) Hold time, XW/R valid after XCLKIN high†2.8 2.8 ns
9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high‡3.5 3.5 ns
10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN high‡2.8 2.8 ns
16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§3.5 3.5 ns
17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§2.8 2.8 ns
18 tsu(XD-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 3.5 ns
19 th(XCKIH-XD) Hold time, XDx valid after XCLKIN high 2.8 2.8 ns
†XW/R input/output polarity selected at boot.
‡XBLAST input polarity selected at boot
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as bus
master¶ (see Figure 41 and Figure 42)
REV. 2 REV. 3
NO. PARAMETER -250
-300 -250
-300 UNIT
MIN MAX MIN MAX
11 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance 0 0 ns
12 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 16.5 4P − 0.5 ns
13 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid 5 3 ns
14 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance 4P 4P ns
15 td(XCKIH-XRY) Delay time, XCLKIN high to XRDY invalid#5 16.5 3 4P − 0.5 ns
20 td(XCKIH-XRYLZ) Delay time, XCLKIN high to XRDY low impedance 5 16.5 3 4P − 0.5 ns
21 td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance#2P + 5 3P + 16.5 2P + 3 7P − 0.5 ns
¶P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
#XRDY operates as active-low ready input/output during host-port accesses.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
D1 D2 D3 D4
15
13
12
11
10
9
10
9
8
7
8
7
6
5
4
3
2
1
XCLKIN
XCS
XAS
XCNTL
XW/R†
XW/R†
XBE[3:0]/XA[5:2]‡
XBLAST§
XBLAST§
XD[31:0]
XRDY¶15
14
20 21
†XW/R input/output polarity selected at boot
‡XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
§XBLAST input polarity selected at boot
¶XRDY operates as active-low ready input/output during host-port accesses.
Figure 41. External Host as Bus Master—Read
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XBE1 XBE2 XBE3 XBE4
D1 D2 D3 D4
19
18
10
9
10
9
17
16
6
5
4
3
2
1
XCLKIN
XCS
XAS
XCNTL
XW/R†
XW/R†
XBLAST§
XBLAST§
XD[31:0]
8
7
8
7
XBE[3:0]/XA[5:2]‡
15
XRDY¶15
20 21
†XW/R input/output polarity selected at boot
‡XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
§XBLAST input polarity selected at boot
¶XRDY operates as active-low ready input/output during host-port accesses.
Figure 42. External Host as Bus Master—Write
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
timing requirements with C62x as bus master (see Figure 43, Figure 44, and Figure 45)
REV. 2 REV. 3
NO. -250
-300 -250
-300 UNIT
MIN MAX MIN MAX
9 tsu(XDV-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 3.5 ns
10 th(XCKIH-XDV) Hold time, XDx valid after XCLKIN high 2.8 2.8 ns
11 tsu(XRY-XCKIH) Setup time, XRDY valid before XCLKIN high†3.5 3.5 ns
12 th(XCKIH-XRY) Hold time, XRDY valid after XCLKIN high†2.8 2.8 ns
14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high 3.5 3.5 ns
15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high 2.8 2.8 ns
†XRDY operates as active-low ready input/output during host-port accesses.
switching characteristics over recommended operating conditions with C62x as bus master‡
(see Figure 43, Figure 44, and Figure 45)
REV. 2 REV. 3
NO. PARAMETER -250
-300 -250
-300 UNIT
MIN MAX MIN MAX
1 td(XCKIH-XASV) Delay time, XCLKIN high to XAS valid 5 16.5 3 4P − 0.5 ns
2 td(XCKIH-XWRV) Delay time, XCLKIN high to XW/R valid§5 16.5 3 4P − 0.5 ns
3 td(XCKIH-XBLTV) Delay time, XCLKIN high to XBLAST valid¶5 16.5 3 4P − 0.5 ns
4 td(XCKIH-XBEV) Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid#5 16.5 3 4P − 0.5 ns
5 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance 0 0 ns
6 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 16.5 4P − 0.5 ns
7 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid 5 3 ns
8 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance 4P 4P ns
13 td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid|| 5 16.5 3 4P − 0.5 ns
‡P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§XW/R input/output polarity selected at boot.
¶XBLAST output polarity is always active low.
#XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
|| XWE/XWAIT operates as XWAIT output signal during host-port accesses.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
BE
AD D1 D2 D3 D4
13
13
1211
10
9
8
7
6
5
44
3
3
22
1
1
XCLKIN
XAS
XW/R†
XW/R†
XBLAST‡
XBE[3:0]/XA[5:2]§
XD[31:0]
XRDY
XWE/XWAIT¶
†XW/R input/output polarity selected at boot
‡XBLAST output polarity is always active low.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
¶XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 43. C62x as Bus Master—Read
Addr D1 D2 D3 D4
13
13
1211
8
7
6
5
44
3
3
22
1
1
XCLKIN
XAS
XW/R†
XW/R†
XBLAST‡
XBE[3:0]/XA[5:2]§
XD[31:0]
XRDY
XWE/XWAIT¶
†XW/R input/output polarity selected at boot
‡XBLAST output polarity is always active low.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
¶XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 44. C62x as Bus Master—Write
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
Addr D1 D2
15
14
12
11
87
6
5
44
22
11
XCLKIN
XAS
XW/R†
XW/R†
XBLAST‡
XD[31:0]
XRDY
XBOFF
XHOLD¶
XHOLDA¶
XHOLD#
XHOLDA#
XBE[3:0]/XA[5:2]§
†XW/R input/output polarity selected at boot
‡XBLAST output polarity is always active low.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
¶Internal arbiter enabled
#Internal arbiter disabled
|| This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 48 and Figure 49.
Figure 45. C62x as Bus Master—XBOFF Operation||
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as asynchronous bus master† (see Figure 46 and
Figure 47)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
1 tw(XCSL) Pulse duration, XCS low 4P ns
2 tw(XCSH) Pulse duration, XCS high 4P ns
3 tsu(XSEL-XCSL) Setup time, expansion bus select signals‡ valid before XCS low 1 ns
4 th(XCSL-XSEL) Hold time, expansion bus select signals‡ valid after XCS low 3.4 ns
10 th(XRYL-XCSL) Hold time, XCS low after XRDY low P + 1.5 ns
11 tsu(XBEV-XCSH) Setup time, XBE[3:0]/XA[5:2] valid before XCS high§1 ns
12 th(XCSH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCS high§3 ns
13 tsu(XDV-XCSH) Setup time, XDx valid before XCS high 1 ns
14 th(XCSH-XDV) Hold time, XDx valid after XCS high 3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡Expansion bus select signals include XCNTL and XR/W.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as
asynchronous bus master† (see Figure 46 and Figure 47)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
5 td(XCSL-XDLZ) Delay time, XCS low to XDx low impedance 0 ns
6 td(XCSH-XDIV) Delay time, XCS high to XDx invalid 0 12 ns
7 td(XCSH-XDHZ) Delay time, XCS high to XDx high impedance 4P ns
8 td(XRYL-XDV) Delay time, XRDY low to XDx valid −4 1.8 ns
9 td(XCSH-XRYH) Delay time, XCS high to XRDY high −1 12 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED)
Word
99
7
685
7
685
4
3
4
3
4
3
4
3
4
3
4
3
XCS
XCNTL
XBE[3:0]/XA[5:2]†
XR/W‡
XR/W‡
XD[31:0]
XRDY
10
12110
†XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
‡XW/R input/output polarity selected at boot
Figure 46. External Device as Asynchronous Master—Read
word
99
14
13
14
13
4
3
4
3
4
3
4
3
12
11
12
11
4
3
4
3
10
10
XCS
XCNTL
XBE[3:0]/XA[5:2]†
XR/W‡
XR/W‡
XD[31:0]
XRDY
121
Word
†XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
‡XW/R input/output polarity selected at boot
Figure 47. External Device as Asynchronous Master—Write
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
XHOLD/XHOLDA TIMING
timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 48)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for expansion bus arbitration
(internal arbiter enabled)†‡ (see Figure 48)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(XHDH-XBHZ) Delay time, XHOLD high to XBus high impedance 3P §ns
2 td(XBHZ-XHDAH) Delay time, XBus high impedance to XHOLDA high 0 2P ns
4 td(XHDL-XHDAL) Delay time, XHOLD low to XHOLDA low 3P ns
5 td(XHDAL-XBLZ) Delay time, XHOLDA low to XBus low impedance 0 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
§All pending XBus transactions are allowed to complete before XHOLDA is asserted.
2
DSP Owns Bus External Requestor DSP Owns Bus
C6203B C6203B
51
4
3
XHOLD (input)
XHOLDA (output)
Owns Bus
XBus†
†XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 48. Expansion Bus Arbitration—Internal Arbiter Enabled
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
XHOLD/XHOLDA TIMING (CONTINUED)
switching characteristics over recommended operating conditions for expansion bus arbitration
(internal arbiter disabled)† (see Figure 49)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(XHDAH-XBLZ) Delay time, XHOLDA high to XBus low impedance‡2P 2P + 10 ns
2 td(XBHZ-XHDL) Delay time, XBus high impedance to XHOLD low‡0 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
C6203B
1
2
XHOLD (output)
XHOLDA (input)
XBus†
†XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 49. Expansion Bus Arbitration—Internal Arbiter Disabled
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 50)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P−1¶ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 9
ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 8
ns
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0.5 ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4.5 ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 9
ns
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 4ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§The maximum bit rate for the C6203B device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz
(P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶The minimum CLKR/X pulse duration is either (P−1) or 4 ns, whichever is larger. For example, when running parts at 300 MHz (P = 3.3 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P−1) = 9 ns as the minimum CLKR/X pulse
duration.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 50)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input 4 16 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int −2 3
ns
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 2 9 ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int −1 5
ns
12 tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high CLKX ext 2 9 ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −0.5 4
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 211 ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid ONLY applies when in data
FSX int −1 5
ns
14 td(FXH-DXV)
Delay time, FSX high to DX valid ONLY applies when in data
delay 0 (XDATDLY = 00b) mode. FSX ext 0 10 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The maximum bit rate for the C6203B device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz
(P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
#C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
87
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
Figure 50. McBSP Timings
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 51)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 51. FSR Timing When GSYNC = 1
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 52)
NO.
-250
-300
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 52)
NO.
PARAMETER
-250
-300
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T − 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L − 2 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −3 4 3P + 4 5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low L − 2 L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high P + 3 3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 52. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
91
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53)
NO.
-250
-300
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 53)
NO.
PARAMETER
-250
-300
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L − 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T − 2 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −2 4 3P + 4 5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low −2 4 3P + 3 5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 4 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
92 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
93
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 54)
NO.
-250
-300
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 54)
NO.
PARAMETER
-250
-300
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T − 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H − 2 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −3 4 3P + 4 5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high H − 2 H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high P + 3 3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
95
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)
NO.
-250
-300
UNIT
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)
NO.
PARAMETER
-250
-300
UNIT
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H − 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T − 2 T + 2 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −3 4 3P + 4 5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high −2 4 3P + 3 5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 5 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics over recommended operating conditions for DMAC outputs†
(see Figure 56)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tw(DMACH) Pulse duration, DMAC high 2P−3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
DMAC[3:0] 1
Figure 56. DMAC Timing
timing requirements for timer inputs† (see Figure 57)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
1 tw(TINPH) Pulse duration, TINP high 2P ns
2 tw(TINPL) Pulse duration, TINP low 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for timer outputs†
(see Figure 57)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
3 tw(TOUTH) Pulse duration, TOUT high 2P−3 ns
4 tw(TOUTL) Pulse duration, TOUT low 2P−3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
TINPx
TOUTx
4
3
2
1
Figure 57. Timer Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics over recommended operating conditions for power-down outputs†
(see Figure 58)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tw(PDH) Pulse duration, PD high 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
PD 1
Figure 58. Power-Down Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 59)
NO.
-250
-300
UNIT
NO.
MIN MAX
UNIT
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 11 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 59)
NO.
PARAMETER
-250
-300
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid −4.5 13.5 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 59. JTAG Test-Port Timing
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MECHANICAL DATA FOR C6203B
package thermal resistance characteristics
The following tables show the thermal resistance characteristics for the GNZ, GLS, GNY and ZNY mechanical
packages.
thermal resistance characteristics (S-PBGA package) for GNZ
NO °C/W AIR FLOW M/S†
1 RΘJC Junction-to-case 6.35 N/A
2 RΘJA Junction-to-free air 20.0 0.00
3 RΘJA Junction-to-free air 17.0 0.50
4 RΘJA Junction-to-free air 16.3 1.00
5 RΘJA Junction-to-free air 15.2 2.00
†m/s = meters per second
thermal resistance characteristics (S-PBGA package) for GLS
NO °C/W Air Flow m/s†
1 RΘJC Junction-to-case 0.85 N/A
2 RΘJA Junction-to-free air 21.6 0.0
3 RΘJA Junction-to-free air 18.0 0.5
4 RΘJA Junction-to-free air 15.5 1.0
5 RΘJA Junction-to-free air 12.8 2.0
†m/s = meters per second
thermal resistance characteristics (S-PBGA package) for GNY
NO
C6203B
Air Flow m/s†
NO
C6203B
(°C/W)
Air Flow m/s†
1 RΘJC Junction-to-case 6.27 N/A
2 RΘJA Junction-to-free air 17.6 0.0
3 RΘJA Junction-to-free air 13.9 0.5
4 RΘJA Junction-to-free air 13.1 1.0
5 RΘJA Junction-to-free air 11.9 2.0
†m/s = meters per second
thermal resistance characteristics (S-PBGA package) for ZNY
NO
C6203B
Air Flow m/s†
NO
C6203B
(°C/W)
Air Flow m/s†
1 RΘJC Junction-to-case 6.27 N/A
2 RΘJA Junction-to-free air 17.6 0.0
3 RΘJA Junction-to-free air 13.9 0.5
4 RΘJA Junction-to-free air 13.1 1.0
5 RΘJA Junction-to-free air 11.9 2.0
†m/s = meters per second
SPRS086N − JANUAR Y 1999 − REVISED JULY 2006
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
packaging information
The following packaging information and addendum reflect the most current released data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TMS320C6203BGLS-3H OBSOLETE FCBGA GLS 384 TBD Call TI Call TI
TMS320C6203BGLSH OBSOLETE FCBGA GLS 384 TBD Call TI Call TI
TMS320C6203BGNY173 ACTIVE FC/CSP GNY 384 90 TBD SNPB Level-4-220C-72 HR
TMS320C6203BGNY17C ACTIVE FC/CSP GNY 384 90 TBD SNPB Level-4-220C-72 HR
TMS320C6203BGNY300 ACTIVE FC/CSP GNY 384 90 TBD SNPB Level-4-220C-72 HR
TMS320C6203BGNY30C ACTIVE FC/CSP GNY 384 90 TBD SNPB Level-4-220C-72 HR
TMS320C6203BGNY3E OBSOLETE FC/CSP GNY 384 TBD Call TI Call TI
TMS320C6203BGNZ173 ACTIVE FCBGA GNZ 352 40 TBD SNPB Level-4-220C-72 HR
TMS320C6203BGNZ300 ACTIVE FCBGA GNZ 352 40 TBD SNPB Level-4-220C-72 HR
TMS320C6203BZNY173 ACTIVE FC/CSP ZNY 384 90 TBD Call TI Call TI
TMS320C6203BZNY300 ACTIVE FC/CSP ZNY 384 90 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320C6203BZNZ300 ACTIVE FCBGA ZNZ 352 40 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS32C6203BGLS173A OBSOLETE FCBGA GLS 384 TBD Call TI Call TI
TMS32C6203BGLS173H OBSOLETE FCBGA GLS 384 TBD Call TI Call TI
TMS32C6203BGNZA250 ACTIVE FCBGA GNZ 352 40 TBD SNPB Level-4-220C-72 HR
TMS32C6203BZNZA250 ACTIVE FCBGA ZNZ 352 40 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2009
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2009
Addendum-Page 2
MPBG181D – MARCH 2001 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GNZ (S–PBGA–N352) PLASTIC BALL GRID ARRAY
4202595-2/E 12/02
2,80 MAX
0,60
0,40
27,20
26,80 SQ
24,80
25,20 SQ
Seating Plane
A
2
1
0,50
25,00 TYP
0,50
0,70
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
34567891011121314151617181920212223242526
0,50 NOM
M
0,10
1,00
0,15
1,00
0,50
Bottom View
A1 Corner
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only.
D. Substrate color may vary.
MECHANICAL DATA
MPBG139B – JUNE 2000 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GNY (S-PBGA-N384) PLASTIC BALL GRID ARRAY
M
∅0,10
0,80
0,12
0,80
4201137/C 11/01
Seating Plane
0,55
0,45
A
1
0,40
16,80 TYP
0,35
0,45
17,90
18,10 SQ
2
B
2,35 MAX
3 5 7 9 11 13 15 17 19 21
4 6 8 10 12 14 16 18 20 22
C
E
G
J
L
N
R
U
W
AA
D
F
H
K
M
P
T
V
Y
AB
0,40
Bottom View
A1 Corner
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only
D. Substrate color may vary
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