54ACQ573,54ACTQ573
54ACQ573 54ACTQ573 Quiet Series Octal Latch with TRI-STATE Outputs
Literature Number: SNOS063
54ACQ573 •54ACTQ573
Quiet Series Octal Latch with TRI-STATE®Outputs
General Description
The ’ACQ/’ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common Out-
put Enable (OE) inputs. The ’ACQ/’ACTQ573 is functionally
identical to the ’ACQ/’ACTQ373 but with inputs and outputs
on opposite sides of the package. The ’ACQ/’ACTQ utilizes
NSC Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Series™features GTO™output control and un-
dershoot corrector in addition to a split ground bus for supe-
rior performance.
Features
nI
CC
and I
OZ
reduced by 50%
nGuaranteed simultaneous switching noise level and
dynamic threshold performance
nImproved latch-up immunity
nInputs and outputs on opposite sides of package allow
easy interface with microprocessors
nOutputs source/sink 24 mA
nFaster prop delays than standard ’ACT573
n4 kV minimum ESD immunity
nStandard Microcircuit Drawing (SMD)
—’ACTQ573: 5962-92194
—’ACQ573: 5962-92180
Logic Symbols
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE TRI-STATE Output Enable Input
O
0
–O
7
TRI-STATE Latch Outputs
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT®is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series™is a trademark of Fairchild Semiconductor Corporation.
DS100242-1
IEEE/IEC
DS100242-2
August 1998
54ACQ573
•
54ACTQ573 Quiet Series Octal Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100242 www.national.com
Connection Diagrams Functional Description
The ’ACQ/’ACTQ573 contains eight D-type latches with
TRI-STATE output buffers. When the Latch Enable (LE) in-
put is HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high im-
pedance mode but this does not interfere with entering new
data into the latches.
Truth Table
Inputs Outputs
OE LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
H
=
HIGH Voltage
L=LOW Voltage
Z=High Impedance
X=Immaterial
O0=Previous O0before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Pin Assignment for DIP
and Flatpak
DS100242-3
Pin Assignment for LCC
DS100242-4
DS100242-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com 2
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=−0.5V −20 mA
V
I
=V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=−0.5V −20 mA
V
O
=V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)±50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latchup Source
or Sink Current ±300 mA
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACQ 2.0V to 6.0V
’ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (V
O
) 0VtoV
CC
Operating Temperature (T
A
)
54ACQ/ACTQ −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACQ Devices
V
IN
from 30%to 70%of V
CC
V
CC
@3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V 125 mV/ns
Note 1: All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from −40˚C to +125˚C.
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT®circuits outside databook specifications.
DC Characteristics for ’ACQ Family Devices
54ACQ
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
V
IH
Minimum High Level 3.0 2.1 V
OUT
=0.1V
Input Voltage 4.5 3.15 V or V
CC
− 0.1V
5.5 3.85
V
IL
Maximum Low Level 3.0 0.9 V
OUT
=0.1V
Input Voltage 4.5 1.35 V or V
CC
− 0.1V
5.5 1.65
V
OH
Minimum High Level 3.0 2.9 I
OUT
=−50 µA
Output Voltage 4.5 4.4 V
5.5 5.4 (Note 3)
V
IN
=V
IL
or V
IH
3.0 2.4 I
OH
=−12 mA
4.5 3.7 V I
OH
=−24 mA
5.5 4.7 I
OH
=−24 mA
V
OL
Maximum Low Level 3.0 0.1 I
OUT
=50 µA
Output Voltage 4.5 0.1 V
5.5 0.1 (Note 3)
V
IN
=V
IL
or V
IH
3.0 0.50 I
OL
=12 mA
4.5 0.50 V I
OL
=24 mA
5.5 0.50 I
OL
=24 mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current (Note 5)
www.national.com3
DC Characteristics for ’ACQ Family Devices (Continued)
54ACQ
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
I
OLD
(Note 4)
Minimum Dynamic
Output Current
5.5 50 mA V
OLD
=1.65 V
Max
I
OHD
5.5 −50 mA V
OHD
=3.85 V
Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=V
CC
Supply Current or GND (Note 5)
I
OZ
Maximum TRI-STATE V
I
(OE) =V
IL
,V
IH
Leakage Current 5.5 ±5.0 µA V
I
=V
CC
, GND
V
O
=V
CC
, GND
V
OLP
Quiet Output 5.0 1.75 V
Maximum Dynamic V
OL
(Notes 6, 7)
V
OLV
Quiet Output 5.0 −1.2 V
Minimum Dynamic V
OL
(Notes 6, 7)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.
ICC for 54ACQ @25˚C is identical to 74ACQ @25˚C.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @GND.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
V
IH
Minimum High Level 4.5 2.0 V V
OUT
=0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 4.5 0.8 V V
OUT
=0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=−50 µA
Output Voltage 5.5 5.4 (Note 8)
V
IN
=V
IL
or V
IH
4.5 3.70 V I
OH
=−24 mA
5.5 4.70 I
OH
=−24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=50 µA
Output Voltage 5.5 0.1 (Note 8)
V
IN
=V
IL
or V
IH
4.5 0.50 V I
OL
=24 mA
5.5 0.50 I
OL
=24 mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
OZ
Maximum TRI-STATE 5.5 ±5.0 µA V
I
=V
IL
,V
IH
Leakage Current V
O
=V
CC
, GND
I
CCT
Maximum 5.5 1.6 mA V
I
=V
CC
− 2.1V
I
CC
/Input
www.national.com 4
DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
I
OLD
(Note 9)
Minimum Dynamic
Output Current
5.5 50 mA V
OLD
=1.65V Max
I
OHD
5.5 −50 mA V
OHD
=3.85V Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=V
CC
Supply Current or GND (Note 10)
V
OLP
Quiet Output 5.0 1.5 V (Notes 11, 12)
Maximum Dynamic V
OL
V
OLV
Quiet Output 5.0 −1.2 V (Notes 11, 12)
Minimum Dynamic V
OL
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: ICC for 54ACTQ @25˚C is identical to 74ACTQ @25˚C.
Note 11: Plastic DIP package.
Note 12: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @GND.
AC Electrical Characteristics
54ACQ
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 13) C
L
=50 pF
Min Max
t
PHL
, Propagation Delay 3.3 1.5 16.0 ns
t
PLH
D
n
to O
n
5.0 1.5 11.0
t
PLH
, Propagation Delay 3.3 1.5 15.0 ns
t
PHL
LE to O
n
5.0 1.5 11.0
t
PZL
, Output Enable Time 3.3 1.5 13.5 ns
t
PZH
5.0 1.5 10.0
t
PHZ
, Output Disable Time 3.3 1.5 13.0 ns
t
PLZ
5.0 1.0 10.5
Note 13: Voltage Range 5.0 is 5.0V ±0.5V
Voltage Range 3.3 is 3.3V ±0.3V
AC Operating Requirements
54ACQ
V
CC
T
A
=−55˚C
Symbol Parameter (V) to +125˚C Units
(Note 14) C
L
=50 pF
Guaranteed
Minimum
t
S
Setup Time, HIGH or LOW 3.3 4.0 ns
D
n
to LE 5.0 4.0
t
H
Hold Time, HIGH or LOW 3.3 2.0 ns
D
n
to LE 5.0 2.0
t
W
LE Pulse Width, HIGH 3.3 5.0 ns
5.0 5.0
Note 14: Voltage Range 5.0 is 5.0V ±0.5V
Voltage Range 3.3 is 3.3V ±0.3V
www.national.com5
AC Electrical Characteristics
54ACTQ
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 15) C
L
=50 pF
Min Max
t
PHL
, Propagation Delay 5.0 1.5 10.0 ns
t
PLH
D
n
to O
n
t
PLH
, Propagation Delay 5.0 1.5 11.0 ns
t
PHL
LE to O
n
t
PZL
,t
PZH
Output Enable Time 5.0 1.5 11.0 ns
t
PHZ
,t
PLZ
Output Disable Time 5.0 1.5 11.0 ns
Note 15: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
54ACTQ
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 16) C
L
=50 pF
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW 5.0 3.5 ns
D
n
to LE
t
H
Hold Time, HIGH or LOW 5.0 1.5 ns
D
n
to LE
t
W
LE Pulse Width, HIGH 5.0 5.0 ns
Note 16: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=OPEN
C
PD
Power Dissipation 42.0 pF V
CC
=5.0V
Capacitance
www.national.com 6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
www.national.com7
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
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the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
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Tel: 1-800-272-9959
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20-Lead Ceramic Flatpak (F)
NS Package Number W20A
54ACQ573
•
54ACTQ573 Quiet Series Octal Latch with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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