1
JANUARY 2002
DSC-2689/11
©2002 Integrated Device Technology, Inc.
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
9L
A
0L
2689 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/W
L
INT
L
BUSY
R
I/O
0R
-I/O
7R
A
9R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2)
(1,2)
(2)
R/W
R
CE
R
OE
R
10
10
R/W
R
,
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
IDT7130SA/LA
IDT7140SA/LA
Features
◆◆
◆◆
◆High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT7130/IDT7140SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
– IDT7130/IDT7140LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
◆◆
◆◆
◆MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
Functional Block Diag ram
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
◆◆
◆◆
◆On-chip port arbitration logic (IDT7130 Only)
◆◆
◆◆
◆BUSY output flag on IDT7130; BUSY input on IDT7140
◆◆
◆◆
◆INT flag for port-to-port communication
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆Battery backup operation–2V data retention (LA only)
◆◆
◆◆
◆TTL-compatible, single 5V ±10% power supply
◆◆
◆◆
◆Military product compliant to MIL-PRF-38535 QML
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆◆
◆◆
◆Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2
Description
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-
more-bit memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate con-
trol, address, and I/O pins that permit independent asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on chip circuitry
of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance tech-nology,
these devices typically operate on only 550mW of power. Low-
power (LA) versions offer battery backup data retention capability,
with each Dual-Port typically consuming 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze
or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP
and STQFP. Military grade products are manufactured in compli-
ance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
148
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IDT7130/40
PorC
P48-1
(4)
&
C48-2
(4)
48-Pin
DIP
Top View
(5)
2689 drw 02
GND
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
I/O
7L
I/O
6L
I/O
5L
I/O
4L
CE
R
CE
L
OE
L
A
0L
INT
L
BUSY
L
R/W
L
R/W
R
BUSY
R
INT
R
V
CC
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
,
01
/
08
/
02
IN
01/
3
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
INDEX
IDT7130/40TF or PF
PP64-1 & PN64-1
(4)
64-Pin STQFP
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33 I/O6R
N/C
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
OER
N/C
N/C
I/O2L
A0L
OEL
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
N/C
N/C
2689 drw 05
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
GND
N/C
R/W
R
CE
R
V
CC
V
CC
BUSY
L
INT
L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
R/W
L
CE
L
BUSY
R
INT
R
,
01/08/02
IDT7130/40J
J52-1
(4)
52-Pin PLCC
Top View
(5)
INDEX
N/C
GND
N/C
N/C
CE
R
CE
L
OE
L
A
0L
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
234567
33323130292827262524232221
2689 drw 04
INT
L
BUSY
L
R/W
L
R/W
R
BUSY
R
INT
R
I/O
6R
V
CC
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
I/O
7L
I/O
6L
I/O
5L
I/O
4L
,
01/08/02
Pin Configurations(1,2,3) (con't.)
NOTES:
1. All V CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
4
Absolute Maximum Ratings(1) Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Capacitance (TA = +25°C, f = 1.0MHz)
STQFP and TQFP Packages Only
NOTE:
1. At Vcc < 2.0V leakages are undefined.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Symbol Rating Commercial
& Industrial Military Unit
V
TERM
(2)
Te rm inal Vo ltage
wi th Re s pe c t
to GND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Under Bias -55 to +125 -65 to + 135
o
C
T
STG
Storage
Temperature -65 to +150 -65 to +150
o
C
I
OUT
DC Outp ut
Current 50 50 mA
2689 tbl 01
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup p l y Vo l tag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Inp ut Hig h Vo l tag e 2. 2
____
6.0
(2)
V
V
IL
Inp ut Lo w Vo ltag e -0.5
(1)
____
0.8 V
2689 tbl 02
Grade Ambient
Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5.0V
+
10%
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to + 85
O
C0V 5.0V
+
10%
2689 tbl 03
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Outp ut Cap ac itanc e V
OUT
= 3dV 10 pF
2689 tbl 05
Symbol Parameter Test Conditi ons
7130SA
7140SA 7130LA
7140LA
UnitMin. Max. Min. Max.
|I
LI
| In put L e ak ag e Curre nt
(1)
V
CC
= 5. 5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
|Output Leakage Current
(1)
V
CC
- 5. 5V,
CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Outp ut Low Vol tag e (I/O
0
-I/O
7
)I
OL
= 4mA
___
0.4
___
0.4 V
V
OL
Op en Drain Outp ut
Low Voltage (BUSY, INT)I
OL
= 16mA
___
0.5
___
0.5 V
V
OH
Outp ut Hig h Voltag e I
OH
= -4mA 2.4
___
2.4
___
V
2689 t bl 04
5
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC , TQFP and STQFP packages only.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7130X20
(2)
7140X20
(2)
Com'l Only
7130X25
7140X25
Com ' l, I n d
& Mi litary
7130X35
7140X35
Com'l
& Military
Symb ol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating
Current
(Bo th Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
COM'L SA
LA 110
110 250
200 110
110 220
170 110
110 165
120 mA
MIL &
IND SA
LA
____
____
____
____
110
110 280
220 110
110 230
170
I
SB1
Standby Current
(Bo th Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(3)
COM'L SA
LA 30
30 65
45 30
30 65
45 25
25 65
45 mA
MIL &
IND SA
LA
____
____
____
____
30
30 80
60 25
25 80
60
I
SB2
Standby Current
(One Po rt - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(6)
Active Port OutputsDisabled,
f=f
MAX
(3)
COM'L SA
LA 65
65 165
125 65
65 150
115 50
50 125
90 mA
MIL &
IND SA
LA
____
____
____
____
65
65 160
125 50
50 150
115
I
SB3
Full Stand b y Current
(Bo th Ports -
CM OS Le v e l Inp uts )
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
COM'L SA
LA 1.0
0.2 15
51.0
0.2 15
51.0
0.2 30
10 mA
MIL &
IND SA
LA
____
____
____
____
1.0
0.2 30
10
____
____
____
____
I
SB4
Full Stand b y Current
(One Port -
CM OS Le v e l Inp uts )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(6)
V
IN
> V
CC
- 0.2V o r V
IN
< 0. 2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L SA
LA 60
60 155
115 60
60 145
105 45
45 110
85 mA
MIL &
IND SA
LA
____
____
____
____
60
60 155
115 45
45 145
105
2689 tb l 06a
7130X55
7140X55
Com ' l, I n d
& Mi litary
7130X100
7140X100
Com'l, Ind
& Military
Symb ol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating
Current
(Bo th Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
COM'L SA
LA 110
110 155
110 110
110 155
110 mA
MIL &
IND SA
LA 110
110 190
140 110
110 190
140
I
SB1
Standby Current
(Bo th Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(3)
COM'L SA
LA 20
20 65
35 20
20 55
35 mA
MIL &
IND SA
LA 20
20 65
45 20
20 65
45
I
SB2
Standby Current
(One Po rt - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(6)
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L SA
LA 40
40 110
75 40
40 110
75 mA
MIL &
IND SA
LA 40
40 125
90 40
40 125
90
I
SB3
Full Stand b y Current
(Bo th Ports -
CM OS Le v e l Inp uts )
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
COM'L SA
LA 1.0
0.2 15
41.0
0.2 15
4mA
MIL &
IND SA
LA 1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Stand b y Current
(One Port -
CM OS Le v e l Inp uts )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(6)
V
IN
> V
CC
- 0.2V o r V
IN
< 0. 2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L SA
LA 40
40 100
70 40
40 95
70 mA
MIL &
IND SA
LA 40
40 110
85 40
40 110
80
2689 t b l 06b
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
6
Data Retention Waveform
V
CC
CE
4.5V 4.5V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
2692 drw 06
≥
,
Data Retention Characteristics (LA Version Only)
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
7130LA/7140LA
Symbol Parameter Test Condi tion Mi n. Typ.
(1)
Max. Unit
V
DR
V
CC
fo r Data Re tenti o n 2. 0
___ ___
V
I
CCDR
Data Rete nti o n Curre nt
V
CC
= 2.0V, CE > V
CC
-0.2V
MIL. & IND.
___
100 4000 µA
COM'L.
___
100 1500
t
CDR
(3)
Chi p De s e le c t to Data Rete ntio n Time V
IN
> V
CC
-0.2V or V
IN
< 0.2V 0
___ ___
ns
t
R
(3)
Op eratio n Reco v ery Time t
RC
(2)
___ ___
ns
2689 t bl 07
7
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
5V
1250Ω
*100pF for 55 and 100ns versions
30pF*
775Ω
DATA
OUT
5V
1250Ω
775Ω5pF*
DATA
OUT
2689 drw 07
5V
270Ω
30pF*
BUSY or INT
*100pF for 55 and 100ns versions
AC Test Conditions
Figure 3. BUSY and INT
AC Output Test Load
Figure 1. Output Test Load Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* including scope and jig
Input Pulse Levels
Inp ut Rise / Fall Time s
Inp ut Timing Refe renc e Lev el s
Outp ut Re fe re nc e Lev e ls
Outp ut Lo ad
GND to 3.0V
5ns
1.5V
1.5V
Fig u re s 1,2 and 3
2689 tbl 08
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. PLCC, TQFP and STQFP packages only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
.
7130X20
(2)
7140X20
(2)
Com'l Onl y
7130X25
7140X25
Com'l, I nd
& Mi l itary
7130X35
7140X35
Com'l
& Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Re ad Cy c le Time 20
____
25
____
35
____
ns
t
AA
Add ress Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Acc ess Time
____
20
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
11
____
12
____
20 ns
t
OH
Outp ut Hold fro m Ad d re ss Chang e 3
____
3
____
3
____
ns
t
LZ
Outp ut Low-Z Time
(1,4)
0
____
0
____
0
____
ns
t
HZ
Output Hig h-Z Time
(1,4)
____
10
____
10
____
15 ns
t
PU
Chip Enable to Po wer Up Time
(4)
0
____
0
____
0
____
ns
t
PD
Chi p Disab le to P owe r Down Ti me
(4)
____
20
____
25
____
35 ns
2 689 tb l 09a
7130X55
7140X55
Com'l, I nd
& Mi l itary
7130X100
7140X100
Com 'l, I nd
& Mi l itary
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
tRC Read Cy c le Time 55
____
100
____
ns
tAA Ad dre ss Acce ss Time
____
55
____
100 ns
tACE Chip Enable Access Time
____
55
____
100 ns
tAOE Outp ut E nabl e Ac ce ss Time
____
25
____
40 ns
tOH Outp ut Ho ld from Ad d res s Chang e 3
____
10
____
ns
tLZ Outp ut Lo w-Z Time
(1,4)
5
____
5
____
ns
tHZ Outp ut Hig h-Z Ti me
(1,4)
____
25
____
40 ns
tPU Ch ip E nab l e to P o we r Up Tim e
(4)
0
____
0
____
ns
tPD Chi p Disable to P ower Down Time
(4)
____
50
____
50 ns
2689 tbl 09b
9
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Wav e form of Read Cycle No. 2, Either Side(3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Wav e form of Read Cycle No. 1, Either Side(1)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2689 drw 08
t
BDDH
(2,3)
BUSY
OUT
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t AOE, t ACE, tAA, and tBDD.
CE
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2689 drw 09
(4)
(1)
(1) (2)
(2)
(4)
t
LZ
t
HZ
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but
is not production tested.
2. PLCC, TQFP and STQFP packages only.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data
to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
Symbol Parameter
7130X20
(2)
7140X20
(2)
Co m'l On ly
7130X25
7140X25
Com'l, I nd
& Mi li tary
7130X35
7140X35
Com'l
& Mi li tary
UnitMin. Max. Min. Max. Min. Max.
WR IT E C Y CLE
t
WC
Write Cycle Time
(3)
20
____
25
____
35
____
ns
t
EW
Chip Enab le to End -o f-Write 15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width
(4)
15
____
15
____
25
____
ns
t
WR
Write Recove ry Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
12
____
15
____
ns
t
HZ
Outpu t Hi gh-Z Ti me
(1)
____
10
____
10
____
15 ns
t
DH
Data Hold Time 0
____
0
____
0
____
ns
t
WZ
Write Enable to Output i n Hig h-Z
(1)
____
10
____
10
____
15 ns
t
OW
Output A c ti ve from E nd -o f-W rite
(1)
0
____
0
____
0
____
ns
2 689 tb l 10 a
Symbol Parameter
7130X55
7140X55
Com'l, I nd
& Mi li tary
7130X100
7140X100
Com 'l, I nd
& Mi li tary
UnitMin. Max. Min. Max.
WR IT E C Y CLE
t
WC
Write Cycle Time
(3)
55
____
100
____
ns
t
EW
Chip Enab le to End -o f-Write 40
____
90
____
ns
t
AW
Address Valid to End-of-Write 40
____
90
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(4)
30
____
55
____
ns
t
WR
Write Recove ry Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 20
____
40
____
ns
t
HZ
Outpu t Hi gh-Z Ti me
(1)
____
25
____
40 ns
t
DH
Data Hold Time 0
____
0
____
ns
t
WZ
Write Enable to Output i n Hig h-Z
(1)
____
25
____
40 ns
t
OW
Output A c ti ve from E nd -o f-W rite
(1)
0
____
0
____
ns
2689 tbl 10b
11
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Wav ef orm of Write Cy cle No. 2, (CE Controlled Timing)(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
Timing Wav eform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
t
WC
ADDRESS
OE
CE
R/W
DATA
OUT
DATA
IN
t
AS
(6)
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(7)
(4) (4)
t
WZ
(7)
t
HZ
(7)
2689 drw 10
t
WR
(3)
t
WC
ADDRESS
CE
R/W
DATA
IN
t
AS
(6)
t
EW
(2)
t
WR
(3)
t
DW
t
DH
t
AW
2689 drw 11
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7)
NOTES:
1. PLCC, TQFP and STQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – t WP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. 'X' in part numbers indicates power rating (S or L).
7130X20
(1)
7140X20
(1)
Com'l Only
7130X25
7140X25
Com'l, Ind
& Military
7130X35
7140X35
Com'l
& Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER IDT 7130)
t
BAA
BUSY Access Time from Address
____
20
____
20
____
20 ns
t
BDA
BUSY Disab le Time from Address
____
20
____
20
____
20 ns
t
BAC
BUSY A ccess Time from Chip Enable
____
20
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
20 ns
t
WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pu lse to Data De lay
(2)
____
40
____
50
____
60 ns
t
DDD
Write Data Vali d to Re ad Data De lay
(2)
____
30
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(4)
____
25
____
35
____
35 ns
BUSY I N PUT TIM ING (For SLAVE I DT 7 140)
t
WB
Write to BUSY In p ut
(5)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pu lse to Data De lay
(2)
____
40
____
50
____
60 ns
t
DDD
Write Data Vali d to Re ad Data De lay
(2)
____
30
____
35
____
35 ns
26 89 tb l 11 a
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Mi li tar y
Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (For MASTER IDT 7130)
t
BAA
BUSY Access Time from Address]
____
30
____
50 ns
t
BDA
BUSY Disable Time from Address
____
30
____
50 ns
t
BAC
BUSY Ac cess Time from Chip Enab le
____
30
____
50 ns
t
BDC
BUSY Disable Time from Chip Enable
____
30
____
50 ns
t
WH
Write Hold After BUSY
(6)
20
____
20
____
ns
t
WDD
Write Pulse to Data De lay
(2)
____
80
____
120 ns
t
DDD
Write Data Vali d to Re ad Data De lay
(2)
____
55
____
100 ns
t
APS
A rb i trati o n P ri o ri ty S e t-up Ti me
(3)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(4)
____
55
____
65 ns
BUSY I NPUT TIMING (For SLAVE I DT 7140)
t
WB
Wri te to BUSY Inp ut
(5)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(6)
20
____
20
____
ns
t
WDD
Write Pulse to Data De lay
(2)
____
80
____
120 ns
t
DDD
Write Data Vali d to Re ad Data De lay
(2)
____
55
____
100 ns
2 689 tbl 11b
13
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Wa veform of Write with Po rt-to-Port Read and BUSY(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Wa veform of Write with BUSY(3)
NOTES:
1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
BUSY
"B"
2689 drw 13
R/W
"A"
t
WP
t
WH
t
WB
R/W
"B" (2)
(1)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/W
"A"
BUSY
"B"
t
APS
(1)
2689 drw 12
t
BAA
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
14
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(2)
NOTES:
1. PLCC, TQFP and STQFP package only.
2. 'X' in part numbers indicates power rating (SA or LA).
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
Timing Waveform by BUSY Arbitration Controlled
by Address Match Timing(1)
t
APS
ADDR
'A'
AND
'B'
ADDRESSES MATCH
t
BAC
t
BDC
CE
'B'
CE
'A'
BUSY
'A'
2689 drw 14
(2)
BUSY
'B'
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
ADDR
'A'
ADDR
'B'
2689 drw 15
(2)
t
BAA
t
BDA
t
RC
OR t
WC
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
7130X20
(1)
7140X20
(1)
Co m'l On ly
7130X25
7140X25
Com'l, I nd
& Mi li tary
7130X35
7140X35
Com'l
& Mi li tary
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recove ry Time 0
____
0
____
0
____
ns
t
INS
In te rrup t S e t Tim e
____
20
____
25
____
25 ns
t
INR
Inte r rup t Re s e t Ti me
____
20
____
25
____
25 ns
2 689 tb l 12 a
15
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
t
INS
ADDR
'A'
INT
'B'
INTERRUPT ADDRESS
t
WC
t
AS
R/W
'A'
t
WR
2689 drw 16
(3)
(3)
(2)
(4)
INT Set:
Timing Waveform of Interrupt Mode(1)
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal ( CE or R/W) is de-asserted first.
INT Clear:
AC Electrical characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
7130X55
7140X55
Com'l, I nd
& Mi l itary
7130X100
7140X100
Com'l, Ind
& Mil itary
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUPT TI MING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Wri te Rec ov ery Time 0
____
0
____
ns
t
INS
Inte rrup t Se t Time
____
45
____
60 ns
t
INR
In te rrupt Re s et Ti me
____
45
____
60 ns
2689 tbl 12b
t
RC
INTERRUPT CLEAR ADDRESS
ADDR
'B'
OE
'B'
t
INR
INT
'A'
2689 drw 17
t
AS
(3)
(3)
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
16
Truth Table I — Non-Contention Read/Write Control(4)
Truth Tables
Truth Table II — Interrupt Flag(1,4)
Truth Table III — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for
IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
NOTES:
1. A0L – A10L • A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Inputs
(1)
FunctionR/WCE OE D
0-7
X H X Z Po rt Dis ab le d and in Po wer-Down Mo de , I
SB2
or I
SB4
XHX Z
CE
R
= CE
L
= V
IH
, P o we r-Do wn Mo d e , I
SB1
or I
SB3
LLXDATA
IN
D ata on P o rt Wri tte n in to Me m o ry
(2)
HLLDATA
OUT
Data in Memory Output on Port
(3)
H L H Z High Impedance Outputs
2689 tbl 13
L eft Port Rig ht P ort
FunctionR/W
L
CE
L
OE
L
A
9L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
9R
-A
0R
INT
R
L LX3FFXXXX X L
(2)
Set Right INT
R
Flag
XXX X XXLL 3FF H
(3)
Re s e t Ri g ht INT
R
Flag
XXX X L
(3)
L L X 3 FE X S e t Le ft INT
L
Flag
XL L3FE H
(2)
XXXXXReset Left INT
L
Flag
2689 tbl 14
Inputs Outputs
Function
CE
L
CE
R
A
0L
-A
9L
A
0R
-A
9R
BUSY
L
(1)
BUSY
R
(1)
X X NO MATCH H H No rmal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhib it
(3)
2 6 89 tb l 15
17
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Functional Description
The IDT7130/IDT7140 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7130/IDT7140 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FE (HEX), where a write is defined as the CER = R/WR = VIL per Truth
Table II. The left port clears the interrupt by access address location
3FE access when CEL = OEL = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
right port must access the memory location 3FF. The message (8 bits)
at 3FE or 3FF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations 3FE and
3FF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table II for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. In slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT7130 RAM (Master) are open drain
type outputs and require open drain resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an RAM array in width while using busy logic, one
master part is used to decide which side of the RAM array will receive
a busy indication, and to output that indication. Any number of slaves
to be addressed in the same address range as the master, use the
busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140
RAMs the BUSY pin is an output if the part is Master (IDT7130), and
the BUSY pin is an input if the part is a Slave (IDT7140) as shown in
Figure 3.
If two or more master parts were used when expanding in width,
a split decision could result with one master indicating busy on one side
of the array and another master indicating busy on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs.
2689 drw 18
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
DECODER
5V 5V
270Ω
270Ω
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
18
Ordering Information
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
XXXXIDT
Device Type
A999 A A
Power Speed Package Process/
Temperature
Range
7130
7140
Speed in nanoseconds
8K (1K x 8-Bit) MASTER Dual-Port RAM
8K (1K x 8-Bit) SLAVE Dual-Port RAM
Commercial PLCC, TQFP and STQFP Only
Commercial, Industrial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
2689 drw 19
BLANK
I
(1)
B
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°Cto+125°C)
Compliant to MIL-PRF-38535 QML
P
C
J
L48
F
PF
TF
20
25
35
55
100
LA
SA Low Power
Standard Power
Datasheet Document History
3/15/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
6/8/99: Changed drawing format
8/2/99: Page 2 Corrected package number in note 3
9/29/99: Page 2 Fixed pin 1 in DIP pin configuration
11/10/99: Page 1 & 18 Replaced IDT logo
6/23/00: Page 4 Increased storage temperature parameters
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Page 10 Changed ±500mV to 0mV in notes
01/08/02: Page 1 Added Ceramic Flatpack to 48-pin package offerings
Page 2 & 3 Added date revision to pin configurations
Page 4, 5, 8, 10, 12, 14 & 15 Removed industrial temp option footnote from all tables
Continued on page 19
19
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History (cont'd)
01/08/02: Page 5, 8, 10, 12, & 14 Added industrial temp for 25ns to DC & AC Electrical Characteristics
Page 5, 8, 10, 12, & 14 Removed industrial temp for 35ns to DC & AC Electrical Characteristics
Page 18 Added industrial temp for 25ns and removed industrial temp for 35ns in ordering information
Updated industrial temp option footnote
Page 1 & 19 Replaced IDT TM logo with IDT ® logo
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
