PD97511 IR3837MPbF SupIRBuck TM HIGHLY INTEGRATED 14A SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR Features Description * * * * * * * * * * * * * * * * * * * * * * The IR3837 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3837 a space-efficient solution, providing accurate power delivery for low output voltage applications. Greater than 96% Maximum Efficiency Single 16V Application Single 5V Application Wide Output Voltage Range: 0.6V to 0.9*Vin Continuous 14A Load Capability Programmable Switching Frequency up to 1.5MHz Internal Digital Soft-Start Enable Input with Voltage Monitoring Capability Hiccup Mode Over Current Protection Internal LDO External Synchronization Enhanced PreBias Start up External Reference for Margining Purposes Input for Tracking Applications Integrated MOSFET Drivers and Bootstrap Diode Operating Junction Temp: -40oC <Tj<125oC Thermal Shut Down Power Good Output with Tracking Capability Over Voltage Detection Feature Pin Compatible with 6A and 10A Versions Small Size 5mmx6mm PQFN, 0.9 mm Height Lead-free, Halogen-free and RoHS Compliant Applications * * * Netcom and Telecom Applications Data Center Applications Distributed Point of Load Power Architectures IR3837 is a versatile regulator which offers programmability of switching frequency and current limit while operates in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. IR3837 offers margining capability through Vref pin. During the margining operation, PGood tracks Vref via feedback to ensure correct status of the output voltage. The internal LDO enables the device to operate from a single supply. This internal LDO can be bypassed when an external bias voltage is available. Fig. 1. Typical application diagram Rev 1.31 1 IR3837MPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified) * PVin, Vin ...................................................... -0.3V to 25V * Vcc/LDO_out ................................................... -0.3V to 8V (Note2) * Boot ........................................................... -0.3V to 33V * SW ........................................................... -0.3V to 25V (DC), -4V to 25V (AC, 100ns) * Boot to SW * OCset * Input / output Pins * PGnd to Gnd ................................................... -0.3V to +0.3V * Storage Temperature Range .................................... -55C To 150C * Junction Temperature Range ................................... -40C To 150C (Note2) * ESD Classification ................................. ......... JEDEC(2KV) * Moisture sensitivity level..................................... JEDEC Level 2 @260 C (Note 5) ......................................... ......... -0.3V to Vcc+0.3V (Note1) ........................................................ -0.3V to 30V ....................................... ... -0.3V to Vcc+0.3V (Note1) Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Package Information 5mm x 6mm Power QFN (Top View) 11 13 12 PVin SW PGnd JA = 35 o C / W J -PCB = 2 o C / W Boot 14 Enable 15 Vp 16 1 10 17 Gnd 2 3 4 Fb Vref Comp Gnd 5 6 Vcc/LDO_out 9 Vin 8 Sync 7 Rt OCset PGood ORDERING INFORMATION Rev 1.31 PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR3837MTRPbF 17 4000 M IR3837MTR1PbF 17 750 2 IR3837MPbF Block Diagram Fig. 2. Simplified block diagram of the IR3837 Rev 1.31 3 IR3837MPbF Pin Description Pin Name Description 1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier 2 Vref 3 Comp 4 Gnd 5 Rt 6 OCset 7 8 PGood Sync External reference voltage, can be used for margining operation. A 100nF capacitor should be connected between this pin and Gnd. Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb to provide loop compensation Signal ground for internal reference and control circuitry Use an external resistor from this pin to Gnd to set the switching frequency Current limit set point. A resistor from this pin to SW pin will set the current limit threshold Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to Vcc External Synchronization, this pin is used to synchronize the device's switching with an external clock. It is recommended that the external Sync clock be set to 20% above the free-running frequency. If not used, this pin can be left floating. Vin Input voltage for Internal LDO. A 1.0F capacitor should be connected between this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be left floating. 10 VCC /LDO_out Input Bias Voltage, output of internal LDO. Place a minimum 2.2F cap from this pin to PGnd 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system's power ground plane. 12 SW Switch node. This pin is connected to the output inductor 13 PVin Input voltage for power stage 14 Boot Supply voltage for high side driver, a 100nF capacitor should be connected between this pin and SW pin. 15 Enable 16 Vp 17 Gnd 9 Rev 1.31 Enable pin to turn on and off the device, if this pin is connected to PVin pin through a resistor divider, input voltage UVLO can be implemented. Input to error amplifier for tracking purposes Signal ground for internal reference and control circuitry 4 IR3837MPbF Recommended Operating Conditions Symbol PVin Vin Vcc/LDO_out Boot to SW Vo Io Fs Tj Definition Input Voltage for power stage Input Voltage for internal LDO * Supply Voltage * Supply Voltage Output Voltage Output Current Switching Frequency Junction Temperature Min Max 1.5 7.0 4.5 4.5 0.6 0 225 -40 16 16 6.5 7.5 0.9*Vin 14 1650 125 Units V A kHz o C * Vcc/LDO_out can be connected to an external regulated supply ( 5V). If so, the Vin input should be left unconnected. Electrical Specifications Unless otherwise specified, these specification apply over, 7.0V<Vin=PVin<16V, Vref=0.6V in 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. PARAMETER POWER STAGE Power Losses SYMBOL Ploss Top Switch Rds(on)_Top Bottom Switch Rds(on)_Bot Bootstrap Diode Forward Voltage SW leakage Current SUPPLY CURRENT Vin Supply Current (Standby) Vin Supply Current (Dyn) TEST CONDITION Vin=12V, Vo=1.8V, Io=14A, Fs=600kHz, L=0.51uH, Note4 VBoot -Vsw =5.0V, ID=14A,Tj=25C Iin(Standby) Iin(Dyn) TYP MAX 3 Vcc=5.0V, ID=14A I(Boot)= 30mA Isw MIN 180 W 12 16 5.3 7 260 470 SW=0V, Enable=0V 6 SW=0V, Enable=high, Vp=0V 14 Enable low , No Switching, 400 Enable high, Fs=500kHz, Vin=12V UNIT 17 m mV A A mA INTERNAL REGULATOR (LDO) Output Voltage IntVcc IntVcc Dropout IntVcc_drop Short Circuit Current Ishort Vin(min)=7.0V, Io=0-50mA, Cload=2.2uF Io=50mA, Cload=2.2uF 4.7 5.2 5.7 V 50 150 mV 70 mA INTERNAL DIGITAL SOFT START Soft Start Clock Frequency Soft Start Ramp Rate Rev 1.31 Clk(SS) Ramp(SS) Note4 168 200 0.2 254 kHz mV/us 5 IR3837MPbF Electrical Specifications (continued) Unless otherwise specified, these specification apply over, 7.0V<Vin=PVin<16V, Vref=0.6V in 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. PARAMETER SYMBOL TEST CONDITION MIN TYP MAX Vos_Vp Vfb-Vp, Vp=0.6V, Vref >2.0V -1 +1 Vos_Vref Vfb-Vref, Vref=0.6V, Vp>2.0V -1 1 UNIT ERROR AMPLIFIER Input Offset Voltage % Input Bias Current IFb(E/A) -1 +1 A Input Bias Current IVp(E/A) -1 +1 A Sink Current Isink(E/A) 0.40 0.85 1.2 mA Isource(E/A) 8 10 13 mA Source Current Slew Rate Gain-Bandwidth Product DC Gain SR Note4 7 12 20 V/s GBWP Note4 20 30 40 MHz Gain Note4 100 110 120 dB 3.4 3.5 3.75 V 150 220 mV 1.2 V V Maximum Voltage Vmax(E/A) Minimum Voltage Vmin(E/A) Common Mode Voltage 0 OSCILLATOR Rt Voltage Frequency Range FS 0.665 0.7 0.735 Rt=59K 225 250 275 Rt=28.7K 450 500 550 Rt=9.53K, Note4 1350 1500 1650 kHz Vramp Note4 1.8 Vp-p Ramp Offset Ramp(os) Note4 0.6 V Min Pulse Width Dmin(ctrl) Note4 Ramp Amplitude Max Duty Cycle Dmax 70 Fs=250kHz 91 Fixed Off Time Note4 Sync Frequency Range 20% above free running frequency Sync Pulse Duration Sync Level Threshold Sync High % 225 100 VFB ns 1650 kHz ns 2 0.6 Vref pin floating, Vp=Vcc o Accuracy 300 200 Sync Low REFERENCE VOLTAGE Feedback Voltage ns o 0 C<Tj<125 C o o -40 C<Tj<125 C, Note3 0.6 V V -1.0 +1.0 -2.0 +2.0 0.54 1.2 V % Vref margining voltage Vref_marg Sink Current Isink_Vref Vref=0.7V 19 25 A Source Current Isource_Vref Vref=0.5V 19 25 A Tracker Comparator Threshold Tracker Comparator Hysteresis Rev 1.31 Tracker(upper) Vref pulled up externally 1.35 1.5 1.6 Tracker(lower) Vref pulled up externally 1.05 1.2 1.3 Tracker_Hys Vref pulled up externally 220 300 420 V mV 6 IR3837MPbF Electrical Specifications (continued) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX Fs=250kHz 10.4 11.8 13.2 Fs=500kHz 21.5 24.4 27.3 Fs=1500kHz 68 77 86 Note4 -6 0 +6 UNIT FAULT PROTECTION OCSET Current OC comp Offset Voltage SS off time IOCSET VOFFSET SS_Hiccup 4096 Thermal Shutdown Note4 140 Thermal Hysteresis Note4 20 C Vcc Rising Trip Level 4.06 4.26 4.46 VCC-Stop-Threshold VCC_UVLO_Stop Vcc Falling Trip Level 3.76 3.96 4.16 Enable-Start-Threshold Enable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable-Stop-Threshold Enable_UVLO_Stop Supply ramping down 0.75 0.85 0.95 PGOOD Power Good upper Threshold Upper Threshold Delay Power Good lower Threshold Lower Threshold Delay Soft Start Delay Time PGood Voltage Low Tracker Comparator Upper Threshold Tracker Comparator Lower Threshold Tracker Comparator Delay Ien VPG(upper) VPG(upper)_Dly VPG(lower) VPG(lower)_Dly Tdelay(Delay) PG(voltage) Enable=3.3V mV Cycles UNDER VOLTAGE LOCKOUT VCC-Start-Threshold VCC_UVLO_Start Enable leakage current A 10 V V A Fb Rising, Vref < 1.2V 115 %Vref Fb Rising, Vref > 1.5V 115 %Vp 256/Fs s Fb Rising, Vref < 1.2V 85 %Vref Fb Rising, Vref > 1.5V 85 %Vp 256/Fs s Fb Falling Fb Rising Note4 10 IPgood=-5mA ms 0.5 VPG(tracker_upper) Vp Rising, Vref > 1.5V 0.5 VPG(tracker_lower) Vp Falling, Vref > 1.5V 0.3 Tdelay(tracker) Vp Rising, Vref > 1.5V 256/Fs V V s Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by design but not tested in production Note5: Upgrade to industrial/MSL2 level applies from date codes 1141 (marking explained on application note AN1132 page 2). Products with prior date code of 1141 are qualified with MSL3 for Consumer market. Rev 1.31 7 IR3837MPbF Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V (external), Io=1A-14A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vo [V] 1.0 1.2 1.5 1.8 2.5 3.3 5.0 L [H] 0.4 0.51 0.51 0.51 0.68 1.0 1.0 MFR Vitec Vitec Vitec Vitec Wurth Elek. Wurth Elek. Wurth Elek. P/N DCR [m] 59PR9875N 0.29 59PR9876N 0.29 59PR9876N 0.29 59PR9876N 0.29 744 332 0068 0.72 744 332 0100 1.17 744 332 0100 1.17 97 95 Efficiency (%) 93 91 89 87 85 83 81 79 77 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Load Current (A) 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V 4.7 4.2 Power Loss (W) 3.7 3.2 2.7 2.2 1.7 1.2 0.7 0.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Load Current (A) 1.0V Rev 1.31 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V 8 IR3837MPbF Typical Efficiency and Power Loss Curves Vin=12V, Vcc/LDO_out=5.2V, Io=1A-14A, Fs=600kHz, Room Temperature, No Air Flow The same inductors as listed on the previous page have been used. 97 95 93 Efficiency (%) 91 89 87 85 83 81 79 77 75 73 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Load Current (A) 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V 4.7 4.2 Power Loss (W) 3.7 3.2 2.7 2.2 1.7 1.2 0.7 0.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Load Current (A) 1.0V Rev 1.31 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V 9 IR3837MPbF TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC), Fs=500 kHz Iin(Dyn) Iin(Standby) 400 17.0 380 360 16.8 340 320 16.6 [mA] [A] 300 280 260 240 16.4 16.2 220 200 16.0 180 160 15.8 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 Temp [C] 40 60 80 100 120 140 80 100 120 80 100 120 140 80 100 120 140 Temp [C] FREQUENCY IOCSET(500kHz) 27.5 550 540 26.5 530 520 25.5 [A] [kHz] 510 500 24.5 490 23.5 480 470 22.5 460 21.5 450 -40 -20 0 20 40 60 80 100 120 -40 140 -20 0 20 60 140 Vcc(UVLO) Stop 4.46 4.16 4.41 4.11 4.36 4.06 4.31 4.01 [V] [V] Vcc(UVLO) Start 4.26 3.96 3.91 4.21 3.86 4.16 3.81 4.11 3.76 4.06 -40 -20 0 20 40 60 80 100 120 -40 140 -20 0 20 40 60 Temp [C] Temp [C] Enable(UVLO) Stop Enable(UVLO) Start 1.36 0.95 1.34 0.93 1.32 0.91 1.30 0.89 1.28 0.87 1.26 [V] [V] 40 Temp [C] Temp [C] 1.24 0.85 0.83 1.22 0.81 1.20 0.79 1.18 0.77 1.16 0.75 1.14 -40 -20 0 20 40 60 80 100 120 -40 140 -20 0 20 40 60 Temp [C] Temp [C] Vcc_LDO Vfb 5.7 0.612 5.6 0.608 5.5 5.4 0.604 [V] [V] 5.3 5.2 0.600 5.1 0.596 5.0 4.9 0.592 4.8 4.7 0.588 -40 -20 0 20 40 60 Temp [C] Rev 1.31 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Temp [C] 10 IR3837MPbF Rdson of MOSFETs Over Temperature at Vcc=5V 18 16 Resistance [m] 14 12 10 8 6 4 -40 -20 0 20 40 60 80 100 120 140 6.25 6.5 Temperature [C] Sync-FET Ctrl-FET Rdson of Sync-FET versus Vcc at different Temperatures 9 RDS_ON_Sync [m] 8 7 6 5 4 3 4.5 4.75 5 -40C Rev 1.31 5.25 0C 5.5 Vcc [V] 25C 65C 5.75 6 100C 125C 11 IR3837MPbF Thermal De-rating Curves Test Conditions: Vin=12V, Vout=1.8V, Vcc/LDO_out=5.2V, Fs=600kHz, 0- 400LFM L=0.51uH (59P9876N) 15 Maximum Load Current [A] 14 13 12 11 10 9 8 7 25 30 35 40 45 50 55 60 65 70 75 80 85 Ambient Temperature [C] 0 LFM Rev 1.31 100LFM 200LFM 300LFM 400LFM 12 IR3837MPbF Circuit Description THEORY OF OPERATION Introduction The IR3837 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3837 provides precisely regulated output voltage programmed via two external resistors from 0.6V to 0.9*Vin. The IR3837 operates with an internal bias supply voltage of 5.2V (LDO) which is connected to the Vcc/LDO_out pin. This allows operation with single supply. The IC can also be operated with an external supply from 4.5V to 6.5V, allowing an extended operating input voltage (PVin) range from 1.5V to 16V. For using the internal supply, the Vin pin should be connected to PVin pin. If an external supply is used, it should be connected to Vcc/LDO_out pin and the Vin pin should be left floating. The device utilizes the on-resistance of the low side MOSFET (sync FET) as current sense element. This method enhances the converter's efficiency and reduces cost by eliminating the need for external current sense resistor. IR3837 includes two low Rds(on) MOSFETs using IR's HEXFET technology. These are specifically designed for high efficiency applications. Under-Voltage Lockout and POR The under-voltage lockout circuit monitors the voltage of Vcc/Ldo pin and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc/LDO and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). Rev 1.31 Enable The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3837 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3837 does not turn on until the bus voltage reaches the desired level (Fig. 3). Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the IR3837. Therefore, in addition to being a logic input pin to enable the IR3837, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we might want the IR3837 to be disabled at least until PVin exceeds the desired output voltage level. Pvin (12V) 10. 2 V Vcc (5.2V) Enable Threshold= 1.2V Enable SS Fig. 3. Normal Start up, device turns on when the bus voltage reaches 10.2V Figure 4a. shows the recommended start-up sequence for the normal (non-tracking, nonsequencing) operation of IR3837, when Enable is used as a logic input. In this operating mode Vref is left floating. Figure 4b. shows the recommended startup sequence for sequenced operation of IR3837 with Enable used as logic input. For this mode of operation, Vref is left floating. Figure 4c shows the recommended startup sequence for tracking operation of IR3837 with Enable used as logic input. For this mode of operation, Vref is connected to a voltage greater than 1.5V. 13 IR3837MPbF Vref This pin reflects the internal reference voltage which is used by the error amplifier to set the output voltage. In most operating conditions this pin is only connected to an external bypass capacitor and it is left floating. In tracking mode this pin should be connected to an external voltage greater than 1.5V and less than 7V. For margining applications, an external voltage source is connected to Vref pin and overrides the internal reference voltage. The external voltage source should have a low internal resistance (<100) and be able to source and sink more than 25A. Fig. 4a. Recommended startup for Normal operation Pvin (12V) Vcc (5.2V) Enable > 1. 2 V SS Vp Pre-Bias Startup IR3837 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET (sync FET) off until the first gate signal for control MOSFET (control FET) is generated. Figure 5a shows a typical Pre-Bias condition at start up. The sync FET always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. The number of these startup pulses for the sync FET is internally programmed. Figure 5b shows a series of 32, 16, 8 startup pulses. Fig. 4b. Recommended startup for sequencing operation (ratiometric or simultaneous) Pvin (12V) Fig. 5a. Pre-Bias startup Vcc (5.2V) Vcc > Vref > 1.5V Enable > 1. 2 V SS Vp Fig. 4c. Recommended startup for memory tracking operation (Vtt-DDR) Rev 1.31 Fig. 5b. Pre-Bias startup pulses 14 IR3837MPbF Soft-Start The IR3837 has a digital internal soft-start to control the output voltage rise and to limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal SS signal linearly rises with the rate of 0.2mV / s from 0V to 2V. Figure 6 shows the waveforms during soft start (also refer to figure 11). The normal start up time is fixed, and is equal to: Tstart 1.3V - 0.7V 3ms 0.2mV/s - - - - - - - - - - - - - - (1) During the soft start the OCP is enabled to protect the device for any short circuit and over current condition. Table 1. Switching Frequency and IOCSet vs. External Resistor (Rt) Rt (k) 47.5 35.7 28.7 23.7 20.5 17.8 15.8 14.3 12.7 11.5 10.7 9.76 9.31 F s (kHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 I ocset (A) 14.7 19.6 24.35 29.54 34.1 39.3 44.3 48.95 55.1 60.85 65.4 71.7 75.15 Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of the sync FET. This method enhances the converter's efficiency and reduces cost by eliminating a current sense resistor. As shown in figure 7, an external resistor (ROCSet) is connected between OCSet pin and the switch node (SW) which sets the current limit set point. An internal current source sources current (IOCSet ) out of the OCSet pin. This current is a function of Rt and hence, of the free-running switching frequency. I OCSet ( A) Fig. 6. Theoretical operation waveforms during soft-start (non tracking / non sequencing) Operating Frequency The switching frequency can be programmed between 250kHz - 1500kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. Shutdown The IR3837 can be shutdown by pulling the Enable pin below its 0.85 V threshold. This will tri-state both, the high side driver as well as the low side driver. Rev 1.31 700 .......... .......... .......... .....(2) Rt (k) Table 1. shows IOCSet at different switching frequencies. The internal current source develops a voltage across ROCSet. When the sync FET is turned on, the inductor current flows through Q2 and results in a voltage at OCSet which is given by: VOCSet ( IOCSet ROCSet ) ( RDS (on) I L ) ...........(3) An over current is detected if the OCSet pin goes below ground. However, to avoid false tripping , due to the noise generated when the sync FET is turned on, the OCP comparator is enabled about 200ns after sync-FET is turned on. 15 IR3837MPbF External Synchronization The IR3837 incorporates an internal circuit which enables synchronization of the internal oscillator (using rising edge) to an external clock. An external resistor from Rt pin to Gnd is still required to set the free-running frequency close to the Sync input frequency. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple POL (point of load) regulators are used. Applying the external signal to the Sync input changes the effective value of the ramp signal (Vramp/Vosc). Vosc1 1.8 f Free_ Run f Sync ........................(5) Fig. 7. Connection of over current sensing resistor As mentioned earlier, an over current is detected if the OCSet pin goes below ground. Hence, at the current limit threshold, VOCset=0. Then, for a current limit setting ILimit, ROCSet is calculated as follows: ROCSet R DS (on) * I Limit IOCSet ........................ (4) An over-current detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by making the internal SS signal equal to zero and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. The OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. An optional 10pF-22pF filter capacitor can be connected from OCSet pin to PGnd. It is recommended to use this capacitor for very narrow duty cycle applications (pulse-width <150ns). Thermal Shutdown Temperature sensing is provided inside IR3837. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. Rev 1.31 Equation (5) shows that the effective amplitude of the ramp is reduced after the external Sync signal is applied. More difference between the frequency of the Sync and the free-running frequency results in more change in the effective amplitude of the ramp signal. Therefore, since the ramp amplitude takes part in calculating the loop-gain and bandwidth of the regulator, it is recommended to not use a Sync frequency which is much higher than the free-running frequency (or vice versa). In addition, the effective value of the ramp signal, given by equation (5), should be used when the compensator is designed for the regulator. The pulse width of the external clock, which is applied to the sync, should be greater than 100ns and its high level should be greater than 2V, while its lower level is less than 0.6V. For more information refer to the Oscillator section in page6. If this pin is left floating, the IC will run with the free running frequency set by the resistor Rt. Output Voltage Tracking and Sequencing The IR3837 can accommodate user programmable tracking and/or sequencing options using Vp, Vref, Enable, and Power Good pins. In the block diagram presented on page 3, the error-amplifier (E/A) has been depicted with three positive inputs. Ideally, the input with the lower voltage is used for regulating the output voltage and the other two inputs are ignored. In practice the voltage of the other two inputs should be about 200mV greater than the lowvoltage input so that their effects can completely be ignored. For normal operation, Vp is tied to Vcc (1.5V < Vp < Vcc) and Vref is left floating (with a bypass capacitor). 16 IR3837MPbF Therefore, in normal operating condition, after Enable goes high the SS ramps up the output voltage until Vfb (voltage of feedback/Fb pin) reaches about 0.6V. Then Vref takes over and the output voltage is regulated (refer to Fig. 11). Tracking-mode operation is achieved by connecting Vref to Vcc (1.5V<Vref<Vcc). Then, while Vp=0, Enable is taken above its threshold so that the soft start circuit generates internal SS signal. After the internal SS signal reaches the final value (refer to Fig. 4c) ramping up the Vp input will ramp up the output voltage. In tracking mode, Vfb always follows Vp which means Vout is always proportional to Vp voltage (typical for DDR/Vtt rail applications) In sequencing mode of operation (simultaneous or ratiometric), Vref is left floating and Vp is kept to ground level until after SS signal reaches the final value. Then Vp is ramped up and Vfb follows Vp. When Vp>0.6V the error-amplifier switches to Vref and the output voltage is regulated with Vref. Tracking and sequencing operations can be implemented to be simultaneous or ratiometric (refer to figures 9 and 10). Figure 8 shows typical circuit configuration for sequencing operation. With this power-up configuration, the voltage at the Vp pin of the slave reaches 0.6V before the Fb pin of the master. If RE/RF =RC/RD, simultaneous startup is achieved. That is, the output voltage of the slave follows that of the master until the voltage at the Vp pin of the slave reaches 0.6 V. After the voltage at the Vp pin of the slave exceeds 0.6V, the internal 0.6V reference of the slave dictates its output voltage. In reality the regulation gradually shifts from Vp to internal Vref. The circuit shown in Fig. 8 can also be used for simultaneous or ratiometric tracking operation if Vref of the slave is connected to Vcc. Table 2 on page 18 summarizes the required conditions to achieve simultaneous / ratiometric tracking or sequencing operations. Fig. 9 Typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric Fig. 8. Application Circuit for Simultaneous and ratiometric Sequencing Rev 1.31 Fig. 10 Typical waveforms in tracking mode of operation: (a) simultaneous, (b) ratiometric 17 IR3837MPbF Power Good Output The IC continually monitors the output voltage via Feedback (Fb pin). The feedback voltage is compared to a threshold. The threshold is set differently at different operating modes and the results of the comparison sets the PGood signal. Figures 11, 12, and 13 show the timing diagram of the PGood signal at different operating modes. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Table 2. The required conditions to achieve simultaneous / ratiometric tracking and sequencing operations with the circuit configuration of Fig. 8 Operating Mode Vref (slave) Vp Required Condition Normal (Non-Sequencing, Non-Tracking) 0.6V (Float) > 1.5V - Simultaneous Sequencing 0.6V Ramp up from 0V RA/RB > RE/RF =RC/RD Ratiometric Sequencing 0.6V Ramp up from 0V RA/RB >RE/RF > RC/RD Simultaneous Tracking > 1.5V Ramp up from 0V RE/RF =RC/RD Ratiometric Tracking > 1.5V Ramp up from 0V RE/RF >RC/RD TIMING DIAGRAM OF PGOOD FUNCTIONS Vref 0.6V 0 2.0V 1.3V 0.7V SSOK Internal SS 0 1.15*Vref Fb 0.85*Vref 0 PGood 0 256/Fs 256/Fs Fig.11 Non-sequence Startup and Vref Margin (Vp =Vcc) Rev 1.31 18 IR3837MPbF TIMING DIAGRAM OF PGOOD FUNCTIONS Fig.12 Vp Tracking (Vref >1.5V, SS=H) Fig.13 Vp Sequence and Vref Margin Rev 1.31 19 IR3837MPbF Minimum on time Considerations Maximum Duty Ratio Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3837, the typical minimum on-time is specified as 70 ns. Any design or application using the IR3837 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 150 ns. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. A fixed off-time of 300 ns maximum is specified for the IR3837. This provides an upper limit on the operating duty ratio at any given switching frequency. Thus, the higher the switching frequency, the lower is the maximum duty ratio at which the IR3837 can operate. To allow some margin, the maximum operating duty ratio in any application using the IR3837 should still accommodate about 500 ns off-time. Fig 14. shows a plot of the maximum duty ratio v/s the switching frequency, with 300 ns off-time. Vout D Fs Vin Fs In any application that uses the IR3837, the following condition must be satisfied: t on(min) t on t on(min) Vout Vin Fs Vin Fs Vout t on(min) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.6 V. Therefore, for Vout(min) = 0.6 V, Vin Fs 95 90 Max Duty Cycle (%) t on 85 80 75 70 65 60 55 50 250 450 650 850 1050 1250 1450 1650 Switching Frequency (kHz) Fig. 14. Maximum duty cycle v/s switching frequency. Vout (min) Vin Fs t on(min) 0.6 V 4 10 6 V/s 150 ns Therefore, at the maximum recommended input voltage 16V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 250 kHz. Conversely, for operation at the maximum recommended operating frequency (1.65 MHz) and minimum output voltage (0.6V), The input voltage (PVin) should not exceed 2.42V, otherwise pulse skipping will happen. At low output voltages (below 1V) specially at Vo=0.6V, it is recommended to design the compensator so that the bandwidth of the loop does not exceed 1/10 of the switching frequency. Rev 1.31 20 IR3837MPbF Application Information Design Example: The following example is a typical application for IR3837. The application circuit is shown on page 27. Vin = 12 V ( 13.2V max) Vo = 1.8 V I o = 14 A Vo 2% Vo for 30% load transient) Fs = 600 kHz R Vo Vref 1 8 ...................................(8) R9 When an external resistor divider is connected to the output as shown in figure 16. Equation (8) can be rewritten as: Vref R9 R8 V oVref .................................. (9) For the calculated values of R8 feedback compensation section. and R9 see VOUT Enabling the IR3837 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage as shown in figure 15. IR3837 IR3624 R8 Fb R9 V in IR3837 Enable R1 R2 Fig. 15. Using Enable pin for UVLO implementation For a typical Enable threshold of VEN = 1.2 V Vin(min) * R2 VEN 1.2 .......... (6) R1 R2 R2 R1 VEN .......... (7) Vin( min ) VEN For a Vin (min)=10.2V, R1=49.9K and R2=6.8k ohm is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 23.7 k, using Table 1. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. The divider ratio is set to provide 0.6V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: Rev 1.31 Fig. 16. Typical application of the IR3837 for programming the output voltage Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET . This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C6). The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode (figure 17), which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C6 is approximately given as Vc Vcc VD .......................... (10) When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C6 is appropriately chosen, the voltage Vc across C6 remains approximately unchanged and the voltage at the Boot pin becomes: VBoot Vin Vcc VD ........................................ (11) 21 IR3837MPbF Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (i ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: Fig. 17. Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the control FET should be provided by the input capacitor. The RMS value of this ripple is expressed by: 1 i ; t D t Fs ............................... (14) Vo L Vin Vo Vin i * Fs Vin Vo L Where: Vin Maximum input voltage Vo Output Voltage i Inductor ripple current F s Switching frequency t Turn on time D Duty cycle I RMS Io D(1 D ) ........................(12) D Vo ................................ (13) Vin Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=14A and D = 0.15, the IRMS = 5.0A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 4x10uF, 16V ceramic capacitors, ECJ-3YX1C106K from Panasonic. In addition to these, although not mandatory, a 1x330uF, 25V SMD capacitor EEV-FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. If i 35%(Io), then the output inductor is calculated to be 0.52H. Select L=0.51H, 59PR9876N, from VITEC which provides a compact, low profile inductor suitable for this application. Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as Vo Vo( ESR ) Vo( ESL ) Vo( C ) Vo( ESR ) I L * ESR V Vo Vo( ESL ) in * ESL L Vo( C ) Rev 1.31 I L 8* C o * Fs ......................... (15) 22 IR3837MPbF Where: Vo = output voltage ripple IL = Inductor ripple current Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3837 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Seven of Taiyo Yuden's JMK212BJ476MG-T (47uF, 6.3V, 3m) capacitors is a good choice. It is also recommended to use a 0.1F ceramic capacitor at the output for high frequency filtering. Feedback Compensation The IR3837 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45o). The output LC filter introduces a double pole, -40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 18). The resonant frequency of the LC filter is expressed as follows: FLC 1 2 Lo Co Fig. 18. Gain and Phase of LC filter The IR3837 uses a voltage-type error amplifier with high-gain (110dB) and high-bandwidth (30MHz). The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Local feedback with Type II compensation is shown in Fig. 19. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. If the output capacitor's ESR generates a zero at 5kHz to 50kHz, the zero generates acceptable phase margin and the Type II compensator can be used. The ESR zero of the output capacitor is expressed as follows: FESR 1 ........................... (17) 2 *ESR*Co ................................ (16) Figure 18 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. Fig. 19. Type II compensation network and its asymptotic gain plot Rev 1.31 23 IR3837MPbF The transfer function (Ve/Vout) is given by: Zf 1 sR3C4 Ve .....(18) H( s ) Vout ZIN sR8C4 The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: R Hs 3 ......................................(19) R8 Fz 1 ............................(20) 2* R3 * C4 First select the desired zero-crossover frequency (Fo): Fo FESR and Fo 1/5~ 1/10* Fs .......(21) Use the following equation to calculate R3: R3 The additional pole is given by: FP 1 .................................(24) C *C 2* R3 * 4 POLE C4 CPOLE The pole sets to one half of the switching frequency which results in the capacitor CPOLE: CPOLE 1 *R3*Fs For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a type III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 20. VOUT ZIN Vosc * Fo * FESR* R8 ...........................(22) 2 Vin * FLC C7 To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz 75% FLC Fz 0.75* 1 2 Lo * Co .....................................(23) Use equations (20), (21) and (22) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. Rev 1.31 C3 R3 R8 R10 Where: Vin = Maximum Input Voltage Vosc = Amplitude of the oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor 1 C4 1 ...................... (25) *R3*Fs C4 Zf Fb R9 E/A Ve Comp VREF Gain (dB) |H(s)| dB FZ1 FZ 2 FP2 FP3 Frequency Fig.20. Type III Compensation network and its asymptotic gain plot 24 IR3837MPbF Again, the transfer function is given by: Zf Ve H( s ) Vout Z IN By replacing Zin and Zf according to figure 20, the transfer function can be expressed as: H( s ) ( 1 sR3C4 )1 sC7 R8 R10 C * C sR8 ( C4 C3 )1 sR3 4 3 ( 1 sR10C7 ) C4 C3 .... (26) The compensation network has three poles and two zeros and they are expressed as follows: FP1 0 ..................................................................(27) FP2 1 ...............................................(28) 2 * R10 * C7 1 1 ...............(29) C4 * C3 2 * R3 * C3 2 * R3 C4 C3 1 FZ1 .............................................(30) 2 * R3 * C4 FP3 FZ 2 1 1 ..........(31) 2 * C7 * ( R8 R10 ) 2 * C7 * R8 Cross over frequency is expressed as: Fo R3 * C7 * Vin 1 * ................................ (32) Vosc 2* Lo * Co Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. Table 3 shows the compensation types for relative locations of the crossover frequency. Rev 1.31 Table 3. Different types of compensators Compensator Type Type II Type III F ESR vs F 0 F LC < F ESR < F 0 < F S /2 F LC < F 0 < F ESR Typical Output Capacitor Electrolytic SP-Cap, Ceramic The higher the crossover frequency is, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency (Fo) is selected such that Fo 1/5 ~ 1/10 * Fs The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin=12V Vo=1.8V Vosc=1.8V Vref=0.6V Lo=0.51uH Co=7x47uF, ESR3m each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 47uF capacitor used in this design is 26uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer's datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co. These result to: FLC=16.5 kHz FESR=2.04 MHz Fs/2=300 kHz 25 IR3837MPbF Select crossover frequency F0=100 kHz Since FLC<F0<Fs/2<FESR, Type III is selected to place the pole and zeros. Detailed calculation of compensation Type III : Desired Phase Margin 70o FZ 2 Fo 1 sin 17.63kHz 1 sin 1 sin FP2 Fo 567.1kHz 1 sin Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (ROCSet) from the SW pin to the OCSet pin. The resistor can be calculated by using equation (4). This resistor (ROCSet) must be placed close to the IC. The RDS(on) has a positive temperature coefficient and it should be considered for the worst case operation (40% increase due to temperature has been considered in below). I SET I L( critical) ROCSet IOCSet .......................(33) RDS( on) RDS ( on ) 5.3 m *1.4 7.42 m Select: FZ1 0.5* FZ 2 8.82 kHz and FP3 0.5* Fs 300 kHz Select: C7 2.2nF Calculate R3 , C3 and C4 : R3 2* Fo * Lo * Co *Vosc ; R3 3.98 k C7 *Vin Select: R3 4.02 k C4 1 ; C4 4.49 nF, Select: C4 4.7 nF 2 * FZ1 * R 3 C3 1 ; C3 132 pF, Select: C3 120 pF 2* FP3 * R3 Calculate R10 , R8 and R9 : R10 R8 1 ; R10 127.5, Select: R10 127 2* C7 * FP2 1 - R10; R8 3.98 k, 2* C7 * FZ 2 Select: R8 4.02 k R9 Vref Vo -Vref I SET I o( LIM ) 14 A *1.5 21 A (50% over nominal output current ) I OCSet 29.54 A (at Fs 600 kHz) R OCSet 5.28 k Select R OCSet 5.23 k The optional filter capacitor from OCSet pin to PGnd has not been used for this design. Setting the Power Good Threshold In this design IR3837 is used in normal (nontracking, non-sequencing) mode, therefore the PGood thresholds are internally set at 85% and 115% of Vref. At startup as soon as the internal soft start signal reaches 2V (Figure 11), and assuming Fb voltage follows Vref, the PGood is asserted. As long as the voltage at the Fb pin is between the thresholds (mentioned above), Enable is high, and no fault happens, the PGood remains high. The PGood is an open drain output. Hence, it is necessary to use a pull up resistor, RPG, from PGood pin to Vcc. The value of the pull-up resistor must be chosen such as to limit the current flowing into the PGood pin to less than 5mA when the output voltage is not in regulation. A typical value used is 10k. Vref Bypass Capacitor A bypass capacitor of about 0.1uF is required to be placed between Vref and Gnd pins. This capacitor should be placed as close as possible to Vref pin. * R8 ; R9 2.01 k Select: R9 2 k Rev 1.31 26 IR3837MPbF Application Diagram: Fig. 21. Application circuit diagram for a 12V to 1.8 V, 14 A Point Of Load Converter Suggested Bill of Materials for the application circuit: Part Reference Cin Quantity Value 1 330uF Description Manufacturer Part Number SMD Elecrolytic, Fsize, 25V, 20% Panasonic EEV-FK1E331P ECJ-3YX1C106K 4 10uF 1206, 16V, X7R, 20% Panasonic - ECG Lo 1 0.51uH 11x7.2x7.5mm, 20%, 0.29m Vitec 59PR9876N Co 7 47uF Ceramic, 6.3V, 0805, X5R,20% Taiyo Yuden JMK212BJ476MG-T R1 1 49.9K Thick Film, 0603,1/10 W,1% Rohm MCR03EZPFX4992 R2 1 6.8K Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX6801 MCR03EZPFX2372 Rt 1 23.7k Thick Film, 0603,1/10W,1% Rohm ROCSet 1 5.23k Thick Film, 0603,1/10 W,1% Rohm MCR03EZPFX5231 RPG 1 10K Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX1002 Cref 1 0.1uF 0603, 25V, X7R, 10% Panasonic - ECG ECJ-1VB1E104K R3 1 4.02k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX4021 C3 1 120pF 50V, 0603, NPO, 5% Panasonic- ECG ECJ-1VC1H121J C4 1 4.7nF 0603, 50V, X7R, 10% Panasonic - ECG ECJ-1VB1H472K C6 1 0.1uF 0603, 25V, X7R, 10% Panasonic - ECG ECJ-1VB1E104K R8 1 4.02K Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX4021 R9 1 2.0K Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2001 R10 1 127 Thick Film, 0603,1/10W,1% Panasonic - ECG ERJ-3EKF1270V C7 1 2200pF 0603, 50V, X7R, 10% Panasonic - ECG ECJ-1VB1H222K CVcc 1 2.2uF 0603, 10V, X5R, 10% Panasonic - ECG ECJ-1VB1A225K U1 1 IR3837 SupIRBuck, 14A, PQFN 5x6mm International Rectifier IR3837MPbF Rev 1.31 27 IR3837MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO_out=5.2V, Vo=1.8V, Io=0-14A, Room Temperature, No Air Flow Fig. 22: Start up at 14A Load (Note 6) Ch1:Vout Ch2:PGood Ch3:EN Ch4: Vin Fig. 23: Start up at 14A Load (Note 6) Ch1:Vout Ch2:PGood Ch3:Vcc Ch4: Vin Fig. 24: Start up with 1.62V Prebias, 0A Load, Ch1:Vout Ch2: PGood Ch3: EN Fig. 25: Output Voltage Ripple, 14A load Ch1: Vout Fig. 26: Inductor node at 14A load Ch3:SW Rev 1.31 Fig. 27: Short (Hiccup) Recovery Ch1:Vout, Ch2:PGood , Ch4:Iout 28 IR3837MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO_out=5.2V, Vo=1.8V, Room Temperature, No Air Flow Fig. 28: Transient Response 1.4A(10%)-5.6A(40%) load (0.5A/us) Ch1:Vout, Ch4:Io Note6: Enable (EN) is tied to Vin via a resistor divider and triggered when Vin is exceeding above 10.2V. Rev 1.31 29 IR3837MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO_out=5.2V, Vo=1.8V, Io=0-14A, Room Temperature, No Air Flow Fig.29: Bode Plot at 10A load shows a bandwidth of 93kHz and phase margin of 49 degrees Rev 1.31 30 IR3837MPbF Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3837 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3837. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vin, Vcc, Vref and Vp should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. The connection between the OCSet resistor and the SW pin should not share any trace with the connection between the bootstrap capacitor and the SW pin. Instead, it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap Vin capacitor at the SW pin. PGnd Also, place the OCset resistor close to the device. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high AGnd current path to a separateVout loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane in top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 30 illustrates the implementation of the layout guidelines outlined above, on the IRDC3837 4 layer demoboard. Vin PGnd Vout AGnd Enough copper & minimum length ground path between Input and Output AGnd PGnd Vin Compensation parts should be placed as close as possible to the Comp pin. Resistors Rt and ROCSet should be placed as close as possible to their pins. All bypass caps should be placed as close as possible to their connecting pins. Vout PGnd Fig. 30a. IRDC3837 Demoboard layout considerations - Top Layer Rev 1.31 31 IR3837MPbF Boot cap uses separate trace from ROCSet to be connected to SW node PGnd Fig. 30b. IRDC3837 demoboard layout considerations - Bottom Layer Power Ground plane Analog Ground plane Feedback trace should be kept away form noise sources Single point connection between AGND & PGND, should be close to the SupIRBuck, kept away from noise sources. Fig. 30c. IRDC3837 demoboard layout considerations - Mid Layer 1 The trace which connects ROCSet to SW node is separated from the trace which connect Boot Cap to SW node Fig. 30d. IRDC3837 demoboard layout considerations - Mid Layer 2 Rev 1.31 32 IR3837MPbF PCB Metal and Components Placement Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to "SupIRBuckTM Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note." (AN-1132) PCB metal pad sizing (all dimensions in mm) PCB metal pad spacing (all dimensions in mm) Rev 1.31 33 IR3837MPbF Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Rev 1.31 34 IR3837MPbF Stencil Design Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Stencil pad sizing (all dimensions in mm) Stencil pad spacing (all dimensions in mm) Rev 1.31 35 IR3837MPbF DIM A A1 b b1 c D E e e1 e2 MILIMITERS MIN MAX 0.800 1.000 0.000 0.050 0.375 0.475 0.250 0.350 0.203 REF. 5.000 BASIC 6.000 BASIC 1.033 BASIC 0.650 BASIC 0.852 BASIC INCHES MIN MAX 0.0315 0.0394 0.0000 0.0020 0.1477 0.1871 0.0098 0.1379 0.008 REF. 1.969 BASIC 2.362 BASIC 0.0407 BASIC 0.0256 BASIC 0.0335 BASIC DIM L M N O P Q R S t1, t2, t3 t4 t5 MILIMITERS MIN MAX 0.350 0.450 2.441 2.541 0.703 0.803 2.079 2.179 3.242 3.342 1.265 1.365 2.644 2.744 1.500 1.600 0.401 BASIC 1.153 BASIC 0.727 BASIC INCHES MIN MAX 0.0138 0.0177 0.0961 0.1000 0.0277 0.0316 0.0819 0.0858 0.1276 0.1316 0.0498 0.0537 0.1041 0.1080 0.0591 0.0630 0.016 BACIS 0.045 BASIC 0.0286 BASIC IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market (Note5) Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 09/11 Rev 1.31 36