TOSHIBA THLY644031BFG-80,-80L,-10,-10L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 4,194,304-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THLY644031BFG is a 4,194,304-word by 64-bit synchronous dynamic RAM module consisting of four TC59S6416BFT/BFTL DRAMs on a printed circuit board, FEATURES @ 4,194,304-word by 64-bit organization @ Single power supply of 3.3V t 0.3V Pipeline architecture -80 -10 @ Auto-refresh and Self-refresh capability tex Clock Cycle Time (CL = 2) 10ns 12 ns @ All inputs and outputs LVTTL-compatible tras Active-to-Precharge Command 48ns 60n @ 4096 refresh cycles per 64 ms Period (min) s @ Package: 144-pin small-outline DIMM tac Access Time from CLK (CL = 2) | 6ns 8ns (gold contacts) tac Ref/Active-to-Ref/Active Command Period (min) 68 ns 84 ns PIN ASSIGNMENT PIN NAMES FRONT 2 Ail 01 59, 61 1430 LZ | LOTT BACK TTT OT 02 60 62 1440 LN a 1 1 1 10 1 61 1 14 111 11 65 11 11 67 115 11 69 11 118 71 119 120 73 121 122 75 123 124 77 125 126 79 127 128 81 129 130 83 131 132 85 17 133 134 87 135 136 19 137 138 1 91 139 140 93 20 141 142 12 95 21 143 144 961001 EBAI @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified Operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is resented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATIO infri i property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-02-16 1/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L Serial Presence Detect (Rev.1.2A) Byte Function Described * * Number Entry Value Entry Entry Value Entry 0 awe # bytes Written into Serial Memory at Module 128bytes 80h 128bytes 80h 1 Total # bytes of SPO Memory Device 256bytes 08h 2S6bytes 08h 2 (PPM EDOSSDRAM, Pree appendix A SDRAM 04h SORAM 04h 3 # Row Addresses on this Assembly RAO-RA11 0Ch RAQ-RA11 OCh 4 # Column Addresses on this Assembly CA0-CA7 08h CA0-CA7 08h 5 # Module Banks on this Assembly 1Bank Oth 1Bank O1h 6 Data Width of this Assembly... x64 40h x64 40h 7 ..Data Width Continuation x64 00h x64 00h 8 Voltage interface Standard of this Assembly LVTTL Oth LVTTL Oth 9 epRAM Cycle Time at Max. Supported CAS Latency (CL), CL = 3, B.0ns 80h CL = 3, 10ns Ah 10 SDRAM Access from Clock @ CL = X CL = 3, 6.0ns 60h CL = 3, 7.0ns 70h W DIMM Configuration Type (Non-parity, Parity, ECC) Non-Parity 00h Non-Parity 00h 12 Refresh Rate/Type 15.625 ys/self 80h 15.625 ss/self 80h 13 SDRAM Width, Primary DRAM x16 10h x16 10h 14 Error Checking SORAM Data Width N/A 00h N/A 00h 15 minum Clock Delay, Back to Back Random Column CLK Oth CLK Oth 16 Burst Lengths Supported 1,2,4,8 Full page 8Fh 1,2,4,8 Full page 8Fh 17 # Banks on each SDRAM Device 4Bank 04h 4Bank 04h 18 CAS # Latencies Supported 23 O6h 2,3 06h 19 CS # Latency Oth Oth 20 WE # Latency 01h Oth 21 SDRAM Module Attributes 00h 00h 22 SORAM Device Attributes: General OEh OEh 23 Minimum Clock Cycle Time at CL- X-1 CL = 2, 10ns AOh CL = 2, 12 ns COh 24 Maximum Data Access Time from Clock @ CL X-1 CL = 2, 6.0ns 60h CL = 2,8.0ns_ 80h 25 Minimum Clock Cycle Time at Cl X-2 00h 00h 26 Maximum Data Access Time from Clock @ CL X-2 00h 00h 27 Minimum Row Precharge Time 20ns 14h 24ns 18h 28 Minimum Row Active to Row Active Delay 20 ns 14h 20 ns 14h 29 Minimum RAS to CAS Delay 20ns 14h 24ns 18h 30 Minimum RAS Pulse Width 48 ns 30h 60 ns 3Ch 31 Module/Bank Density 32MB 08h 32MB 08h 32 Command & Address signal Input Set-up Time 2ns 20h 2.5 ns 25h 33 Command & Address signal Input Hold Time ins 10h tins 10h 34 Data signal Input Set-up Time 2ns 20h 2.505 25h 35 Data signal Input Hold Time Ins 10h Ins 10h 36-61 Superset Information (may be used in future) FFh FFh 62 SPD Revision Rev.1.2A t2h Rev.1.24 12h 63 Checksum for bytes 0-62 1EC8h C8h 1F56h 56h Option Manufacturers JEDEC ID Code per JEP-106E Manuf Location Manufacturer's Part Number Revision Code Man Date Assembly Serial Number Manufacturer Data Reserved Reserved Intel Specification intel Specification Intel Specification Intel Specification 1998-02-16 2/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L BLOCK DIAGRAM CH oo ra LOQM f DQMB0 RAS RAS vor ? BQO CAS CAS vos - oi Q7 CKE . CKE M1 UDQM -o DQmMal WE WE vga - 098 CLK : : : AO to 11, BS0,1 W016 0015 1s LDQM FO DQMB2 \W4 RAE vor f= pat6 CAS M2 v08 - 0a23 CKE UDQM J--o DQmB3 WE uaa F 024 CLK i i : AO to 11,B50,1 gig Lig o'oay | = cs LDQM fo DQMB4 CLKO o Ras vo1 -- 0932 CAS M3 108 - paag CKE upqgm } Dames WE vQ9 [ naao CLK : : : AO to 11,B80,1 gig bio pay i ra LOQM FO DQMBE WI Lt RAS vol F? 048 CAS M4 vos Fo oss CKE uogm |-o 0QmB7 WE Qo >? nase CLK : : : AO to 11, BS0,1 O16 D063 AO to 11, BAO,1 yoo 1 to 45 8 =c9 12 Mito Vpo = 643 EPROM to to to Vss o $< + 4 > uitoa VS o + > E2PROM 102 10 pF CLK1 o_~\y_ SCL o~] SCL E2PROM SDA }o SDA AO Al A2 WC Cf yf 777 1998-02-16 3/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L ABSOLUTE MAXIMUM RATINGS SYMBOL ITEM RATING UNIT NOTES Vin Input Voltage -0.3 to Vee + 0.3 Vv 1 Vout Output Voltage -0.3 to Vcc + 0.3 Vv 1 Voo Power Supply Voltage -0.3 to 4.6 Vv 1 Topr Operating Temperature 0 to 70 C 1 TstG Storage Temperature -55 to 125 c 1 Pp Power Dissipation 1.2 WwW 1 lout Short Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES Vop Supply Voltage 3.0 3.3 3.6 Vv 2 Vin LVTTL Input High Voltage 2.0 - Vop + 0.3 | Vv 2 Vir LVTTL Input Low Voltage -0.3 - 0.8 Vv 2 CAPACITANCE (Vcc = 3.3 V,f = 1 MHz, Ta = 0 to 70C) SYMBOL PARAMETER * MIN MAX UNIT Cy Input Capacitance (AO to A1}) - T.B.D. pF Ci Input Capacitance (RAS, CAS, WE) - T.B.D. pF Ci3 Input Capacitance (CLKO) ~ T.B.D. pF Cia Input Capacitance ($0} - T.B.D. pF Cis Input Capacitance (DQMBO to 7) ~ T.B.D. pF Cog VO Capacitance (DQO to 0Q63) - T.B.D. pF 1998-02-16 4/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L DC CHARACTERISTICS (Vcc = 3.3V + 0.3V, Ta = 0 to 70C) -80 +10 SYMBOL ITEM UNIT | NOTES MIN MAX MIN MAX lees OPERATING CURRENT Active-Precharge Command vo Cycling without Burst Operation | '"Bank Operation - 360 - 280 mA 3 lcc1B | (tex = tac min) STANDBY CURRENT lez | (tee = min, TS = Vn, CKE = Vin - | 20] - | 100 Vine = Vin (min) / Vi, (max) CKE = Vii mA 3 lccze__| Bank: Inactive State) (Power-down Mode) - 4 - 4 STANDBY CURRENT Icc2s (CLK = Vit, = Vin. CKE = Vy - 32 ~- 32 Vint = Vin (min) / Vi, (max) CKE = Vip mA lccaes_| Bank: Inactive State) (Power-down Mode) ~ 1 - \ Icc3 NO OPERATING CURRENT CKE = Vin - 260 - 200 (te, = min, CS = Vix (min) CKEaV mA 3 Iec3p_~| Bank: Active State (2 Banks)) (Power-down Mode) - 32 - 32 I BURST OPERATING CURRENT 560 440 A 3.4 cca (tem = min, CS = Viz (min) Read/Write Command Cycling) ~ ~ m , AUTO-REFRESH CURRENT 600 520 A C5 | (tee = min, Auto-Refresh Command Cycling) ~ ~ m 3 SELF-REFRESH CURRENT THLY 64403 1BFG-80,-10 - 4 - 4 ala Cc6 . m (Self Refresh Mode, CKE=0.2V) | ri veqgosiarc-soL,-10L| - | 18 | - | 18 INPUT LEAKAGE CURRENT 5 5 5 '() | (OVS Vin S Vop, All Other Pins Not under Test = 0V) ~ ~ 5 vA ,; OUTPUT LEAKAGE CURRENT 5 5 5 5 ow) (Dour Is Disabled, OVS Vout = Vpp) ~ HA Vv OUTPUT LEVEL 24 24 V OH | LVTTL Output H Level Voltage (Ionut = -2mA) , ~ - Vv OUTPUT LEVEL 0.4 04 ot LVTTL Output L Level Voltage (Igyr = 2 mA) ~ , ~ , V 1998-02-16 5/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Vcc = 3.3V 4 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL PARAMETER MIN MAX MIN MAX UNIT | NOTES tre Ref/Active-Ref/Active Command Period 68 84 tras Active- Precharge Command Period 48 100000 60 100000 ns trep Active-Read/Write Command Delay Time 20 24 9 t Read/Write(a) -Read/Write(b) 1 ' ad Command Period cycle trp Precharge-Active Command Period 20 24 trap Active(a)-Active(b) Command Period 20 20 twr Write Recovery Time cL* = 2 10 12 cL* = 3 8 10 tex CLK Cycle Time CL* = 2 10 1000 12 1000 CL* = 3 8 1000 10 1000 tcH CLK High Level Width 3 3 10 ter CLK Low Level Width 3 3 tac Access Time from CLK CL* = 2 6 CL* = 3 6 7 tou Output Data Hold Time 3 3 ns tuz Output Data High Impedance Time 3 8 3 10 8 tiz Output Data Low Impedance Time 0 0 tsp Power-down Mode Entry Time 0 8 0 10 tr Transition Time of CLK (Rise and Fall) 0.5 40 0.5 10 tos Data-in Set-up Time 2 2.5 ton Data-in Hold Time 1 1 tas Address Set-up Time 2 2.5 tay Address Hold Time 1 1 teks CKE Set-up Time 2 2.5 tekH CKE Hold Time 1 1 tems Command Set-up Time 2 2.5 temH Command Hold Time 1 1 trer Refresh Time 64 64 ms trsc Mode Register Set Cycle Time 16 20 ns 9 * CL is CAS latency. 1998-02-16 6/13TOSHIBA THLY644031BFG-80,-80L,-10,-101 NOTES: 1. Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and their values are measured at the minimum cycle rate values tck andtrc. Input signals are changed once during tcx. 4, These parameters depend on the output loading. The specified values are obtained with the output open. 5. The power-up sequence is described in Note 11. 6. AC TEST CONDITIONS Reference Level i 1.4V/1.4V Load See the di for AC Test Load (B) below l Si Levels 2.4V/0.4V Transition Time (Rise and Fall) of Si 2ns | 4 3.3V 1.4V 1.2kQ q 2 Output Output tr pF 8700 T 50 pF AC TEST LOAD (A) AC TEST LOAD (B) 7. Transition times are measured between the Vi and Vin levels. Transition (rise and fall) of input signals has a fixed slope. 8. tuz defines the time at which the outputs go open circuit and are not reference levels. 9. These parameters depend on the number of clock cycles and depend on the operating frequency of the clock as follows: Number of clock cycles = Specified value of timing/Clock period (Round up fractions to a whole number. ) 1998-02-16 7/13TOSHIBA THLY644031BFG-80,-80L,-10,-101 10. 11. a ene tcH is the pulse width of CLK measured from the positive edge to the negative edge and referenced to Viy (min). tor is the pulse width of CLK measured from the negative edge to the positive edge and referenced to Vir, (max). Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Vcc and VecQ (simultaneously) with all input signals held in the NOP state. The CLK signal must be started at the same time as power is applied. 2) After power-up a pause of at least 200 # seconds is required. Then, DQM and CKE must be held High (at the Voc level) to ensure that the DQ output is high-impedance. 3) Both banks must be precharged. 4) The Mode Register Set command must be asserted to initialize the Mode register. 5) An Auto-Refresh operation must consist of at least eight Auto-Refresh cycles. The order in which 4) and 5) are performed is interchangeable. 1998-02-16 8/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L Mode Register Set Cycle trsc ck f VSP NP NIT ">. tems} tewH ry Vs <2 | WZZ7jzuc. -w m= tems} te <tyo> al -__ UII... NTL. tas oS Data VM 000) MAL KZ. AO > N Al Burst Length A2 A3 | Addressing Mode A4 0 0 0 0 1 1 1 1 a}=[olof=|=|ol of> AS CAS Latency A6 A7 | 0 | (Test Mode) A&B | 0 Reserved > a =lol> Cc > a !|w{2 3 a |2 O15 hs ole 6|a/< a AS Ag Write Mode 0 0 0 0 A110] 0 0 1 BAO] 0 | Reserve d Qo. 1 0 BAI] 0 : : AQ Single-Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write 1998-02-16 9/13TOSHIBA THLY644031BFG-80,-80L,-10,-10L TIMING DIAGRAMS Read Timing IVIL LY SY | WHUMUMEEDEEO 7 CLM soa UK XU MMI, _ tac _ tac _, tyz ' toa tiz ton yay i D VALID Q YAN _DATA-OUT Read Comman id Burst tou SN ength 1998-02-16 10/13TOSHIBA THLY644031BFG-80,-80L,-10,-101 Command Input Timin ttl, tH, aK tA FAR, f hf t tr ~ - ah ra Wa : WII _ n a ADA WMI (UIT MMMM 5 jx CK foxs! tcky . 1 tckH <7 de y} 1998-02-16 11/13TOSHIBA Control Timing for Input Data (Word Mask) clk f \ VEN ITN pO tomy tems] temH toms ; oc MED to 7 TT tos! tox tos | tou tos | - | = ton tos VALID VAUD DATA-IN DATA-IN teKH teks Lh (Clock Mask) CLK } CKE tos tos] tou ton DQO to 63 Uy Control Timing for Output Data (Output Enable) CLK _f \_f VENI temx tems| tomy tems ry ry | DQMBO to 7 ff} L_] tac | tac tuz tac tac }- nat > na |_.__ Ou tou tou tz ton VALID VALID - } VALID DQO to 63 DATA-OUT DATA-OUT OPEN Y DATA-OUT (Clock Mask) cx "717 tekH teks | teKH itcKs cke an tac tac tac Fr ton tou ton VALIO VALID DQO to 63 DATA-OUT VALID DATA-OUT DATA-OUT THLY644031BFG-80,-80L,-1 0,-10L 1998-02-16 12/13TOSHIBA TH LY644031BFG-80,-80L,-10,-101. epee PACKAGE DIMENSIONS (THLY644031BFG) Unit: mm FRONT Le 67.60 + 0.13 > 3.80 MAX It 3.20MIN 4.00MIN 25 .4040.13 20.00 4.00+0.10 , at < wo 4 fom 6) 143 (fom ae : 3.30 + 0.13 23.20 4.60 32.80 2.00 + 0.13 ~ . 63.60 REF | | 1.00 + 0.10 BACK 3.70 + 0.13 | | 2.10 | TTT WUT oO? 60 62 14a FRONT i) ' i } x 2 i = i 3 in ! wn | i - ___] i ' 0.60 + 0.05|_ | [iy aol '" Ws0 #010 | ~<___--_____,.! 2.50 ' < 4.60 >| Contacts: gold Weight: g (typ) 1998-02-16 13/13