STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
1
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
General Description
The AA4002 is a monolithic stereo audio power
amplifier including DC volume control, a selectable
gain/bass boost, and stereo bridged audio power ampli-
fiers, with the capabilit y of produci ng 2W into 4Ω with
THD+N less than 1%. The AA4002 is specially
designed for Notebook PC, LCD monitor and portable
media player.
The AA4002 features low power co nsumption in shut-
down mode, power amplifier and headphone mute for
maximum system flexibility and performance. It also
provides therma l shutdown protection.
The AA4002 is availabl e in TSSOP-28 with Exposed-
DAP package.
Features
·DC Volume Control Interface, 0dB to -78dB, 31
Steps
·System Beep Detect
·Very Low Power Consumption in Shutdown
Mode, ISD=0.7µA
·Stereo Power Output for Speakers/Headphones
with BTL Mode/SE Mode
·Selectable Internal/External Gain
·Bass Boost
·Pop Noise Suppression Circuit
·Thermal Shutd own Protection
Applications
·Notebook PC
·LCD monitor
·Portable DVD Player
·Portable Media Player
·Digital Photo Frame
Figure 1. Package Type of AA4002
TSSOP-28 with Exposed-DAP
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
2
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Pin Configuration
Figure 2. Pin Configuration of AA4002
GND
SHUTDOWN
GAIN SELECT
MODE
MUTE
VDD
DC VOL
GND
RIGHT DOCK
RIGHT IN
BEEP IN
LEFT IN
LEFT DOCK
GND
RIGHT OUT+
VDD
RIGHT OUT-
RIGHT GAIN 2
RIGHT GAIN 1
GND
BYPASS
HP SENSE
GND
LEFT GAIN 1
LEFT GAIN 2
LEFT OUT-
VDD
LEFT OUT+
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
10
11
21
20
19
18
12
13
14
17
16
15
G Package
(
TSSOP-28 with Exposed-DAP
)
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
3
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Pin Description
Pin Number Pin Name Function
1, 8, 14, 20, 23 GND Ground for circuitry.
2 SHUTDOWN Shutdown mode control signal input, place entire IC in shutdown mode when held
high, IDD=0.7µA.
3 GAIN SELECT Gain select input pin, logic high will switch the amplifier to external gain mode, and
logic low will switch to internal unity gain.
4 MODE Mode select input pin, fixed gain when logic L and gain adjustable mode when
logic H.
5 MUTE Mute control input pin, active H.
6, 16, 27 VDD Supply voltage input pin.
7 DC VOL Volume control function input pin.
9 RIGHT DOCK Right docking output pin.
10 RIGHT IN Right channel audio input pin.
11 BEEP IN Beep signal input pin.
12 LEFT IN Left channel audio input pin.
13 LEFT DOCK Left docking output pin.
15 LEFT OUT+ Left channel positive output pin.
17 LEFT OUT- Left channel negative output pin.
18 LEFT GAIN 2 Connect pin 2 of the external gain setting resistor for left channel.
19 LEFT GAIN 1 Connect pin 1 of the external gain setting resistor for left channel.
21 HP SENSE Headphone sense control pin.
22 BYPASS Bypass pin.
24 RIGHT GAIN 1 Connect pin 1 of the external gain setting resistor for right channel.
25 RIGHT GAIN 2 Connect pin 2 of the external gain setting resistor for right channel.
26 RIGHT OUT- Right channel negative output pin.
28 RIGHT OUT+ Right channel positive output pin.
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
4
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Functional Block Diagram
Figure 3. Functional Block Diagram of AA4002
RIGHT OUT+
LEFT OUT-
LEFT OUT+
LEFT DOCK
LEFT IN
RIGHT IN
BEEP IN
RIGHT DOCK
Mode Control
+
_
Beep Detect
Power
Management
Click and Pop
Suppression
Circuitry
Volume
Control
31 Steps
10kΩ
20kΩ20kΩ
20kΩ20kΩ
10kΩ
10kΩ
10kΩ
GAIN SELECT
Mode
Mute
HP Sense
DC VOL
SHUTDOWN
Bypass
GND
VDD
+
_
+
_
+
_
+
_
+
_
Bias
1, 8, 14, 20, 23
2
3
4
5
6, 16, 27
7
9
10
11
12
13
15
17
1819
LEFT GAIN 2
LEFT GAIN 1
21
22
RIGHT GAIN 1
24
RIGHT GAIN 2
25
28
RIGHT OUT-
26
Bias
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
5
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Gain Sel Mode Headphone
Sense Mute Shutdown Output Stage
Set To DC Volume Output Stage
Configuration
0 0 0 0 0 Internal Gain Fixed BTL
0 0 1 0 0 Internal Gain Fixed SE
0 1 0 0 0 Internal Gain Adjustable BTL
0 1 1 0 0 Internal Gain Adjustable SE
1 0 0 0 0 External Gain Fixed BTL
1 0 1 0 0 External Gain Fixed SE
1 1 0 0 0 External Gain Adjustable BTL
1 1 1 0 0 External Gain Adjustable SE
XXX10MutedXMuted
X X X X 1 Shutdown X X
Ordering Information
Circuit Type
E1: Lead Free
AA4002 -
Truth Table for Logic Inputs (Note 1)
Note 1: If system beep is detected on the BEEP IN pin, the system beep will be passed through the bridged amplifier regardless
of the logic of the MUTE and HP SENSE pins.
Package Temperature Range Part Number Marking ID Packing Type
TSSOP-28
with Exposed-DAP -40 to 85 ℃
AA4002G-E1 AA4002G-E1 Tube
AA4002GTR-E1 AA4002G-E1 Tape & Reel
Package
G: TSSOP-28
with Exposed-DAP
TR: Tape and Reel
Blank: Tube
BCD Semiconductor's Pb-free products, as designated with "E1" suffix in the part number, are RoHS compliant.
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
6
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Parameter Symbol Value Unit
Supply Voltage VDD 6.0 V
Input Voltage VIN -0.3 to VDD + 0.3 V
Power Dissipation PD Internally limited
ESD (Machine Model) ESD 200 (Note 3) V
Operating Junction Temperature TJ150 oC
Storage Temperature TSTG -65 to 150 oC
Lead Temperature (Soldering 10s) TL260 oC
Package Thermal Resistance RθJA (Note 4) 45 oC/W
Absolute Maximum Ratings (Note 2)
Note 2: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operation is not implied. Exposure to "Absolute Maximum Ratings" for extended periods may af fect device reliability.
Note 3: This device is manufactured on a CMOS process. It is therefore gene ricall y suscep tible t o damage from excessive static
voltages. Proper ESD precautions must be taken during handling and storage of this device.
Note 4: The Chip is soldered to 200mm2 copper of 1oz. with 12x0.5mm vias.
Recommended Operating Conditions
Parameter Symbol Min Max Unit
Supply Voltage VDD 2.7 5.5 V
Operating Temperature TA-40 85 oC
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
7
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Parameter S ymbol Cond itions Min Typ M a x Unit
Standby and Logical Section
Supply Voltage VDD 2.7 5.5 V
Quiescent Power Supply Current IDD VIN=0V, IOUT=0A 11 30 mA
Shutdown Current ISD VSHUTDOWN=VDD 0.7 2.0 µA
Headphone Sense High Input Voltage VIH 4V
Headphone Sense Low Input Voltage VIL 0.8 V
(Mute, Shutdown, Mode, Gain
Select) High Input Voltage VIH 3V
(Mute, Shutdown, Mode, Gain
Select) Low Input Voltage VIL 1V
Volume Attenuators Section
Attenuator Range CRANGE VVOL=5V (DC), No load ±0.75 dB
VVOL=0V (DC), BTL and SE Mode -75 dB
Mute Attenuation AMVMUTE=5V, BTL Mode -78 dB
VMUTE=5V, SE Mode -78 dB
Single-ended (SE) Mode Section
Output Power POUT THD=1%, f=1kHz, R L=32Ω 85
mW
THD=10%, f=1k Hz, RL=32Ω 95
Total Harmonic Distortion + Noise THD+N VOUT=1VRMS, f=1kHz,
RL=10KΩ, AVD=1 0.065 %
Power Supply Rejection Ratio PSRR CB=1.0µF, f=120kHz, RL=32Ω,
VRIPPLE=200mVRMS
58 dB
Signal to Noise Ratio SNR POUT=75mW, RL=32Ω, A-Wtd Filter 102 dB
Channel Separation f=1kHz, CB=1.0µF65dB
BTL Mode Section
Output Offset Voltage VOS VIN=0V, No load ±5±50 mV
Output Power POUT
THD+N=1%, f=1kHz, RL=4Ω,
LPF=22kHz 2W
THD+N=1%, f=1kHz, RL=8Ω, 1.0 1.1
THD+N=10%, f=1kHz, RL=8Ω,1.5
Total Harmonic Distortion + Noise THD+N POUT=1.0W, RL=4Ω, AVD=2
20Hz<f<20kHz 0.3 %
Power Supply Rejection Ratio PSRR CB=1.0µF, f=120Hz,
VRIPPLE=200mVRMS, RL=8Ω
74 dB
Electrical Characteristics
(VDD=5V, TA=25oC, unless otherwise specified.)
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
8
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Par ameter S ymbol Cond itions Min Typ M a x Unit
BTL Mode Section (Continued)
Signal to Noise Ratio SNR POUT=1.1W, RL=8Ω, A-Wtd Filter 93 dB
Channel Separation CB=1.0µF, f=1kHz 70 dB
Electrical Characteristics (Continued)
(VDD=5V, TA=25oC, unless otherwise specified.)
Typical Performance Characteristics
Figure 5. THD+N vs. Output Power
Figure 6. THD+N vs. Output Power Figu r e 7. PSRR vs. Frequency
100m 1
0.1
1
10
1KHz
20KHz
20Hz
VDD=5V
BTL Mode
RL=3.9Ω
LPF=80KHz
THD+N (%)
Output Power (W)
10 100
0.01
0.1
1
10
VDD=5V
SE Mode
RL=33Ω
LPF=80KHz
1KHz (COUT=220µF)
20KHz (COUT=220µF)
20Hz (COUT=1000µF)
THD+N (%)
Output Power (mW)
100 1k 10k
-100
-80
-60
-40
-20
0
20K
20
VDD=5V
SE Mode
CB=1.0µF
VRIPPLE=200mVRMS
PSRR (dB)
Frequency (Hz)
10m 100m 1
0.1
1
10
1KHz
20KHz
20Hz
VDD=5V
BTL Mode
RL=8.2Ω
LPF=80KHz
THD+N (%)
Output Power (W)
Figure 4. THD+N vs. Output Power
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
9
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Figure 9. THD+N vs. Frequency
Typical Performance Characteristics (Continued)
Figure 10. Output Power vs. Supply Voltage Figure 11. Output Power vs. Supply Voltage
Figure 8. THD+N vs. Frequency
100 1k 10k
0.1
1
10 VDD=5V
SE Mode
RL=33Ω
Po=75mW
COUT=1000µF
LPF=80KHz
20
THD+N (%)
Frequency (Hz) 100 1k 10k
0.1
1
20
VDD=5V
BTL Mode
RL=3.9Ω
Po=1.5W
LPF=30KHz
THD+N (%)
Frequency (Hz)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
20
40
60
80
100
120
140
160
SE Mode
f=1KHz
RL=33Ω
THD=1%
LPF=80KHz
Output Power (mW)
Supply Voltage (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5
20
40
60
80
100
120
140
160
SE Mode
f=1KHz
RL=33Ω
THD=10%
LPF=80KHz
Output Power (mW)
Supply Voltage (V)
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
10
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Typical Performance Characteristics (Continued)
Figure 13. Output Power vs. Power Supply
Figure 14. Output Power vs. Load Resistance
Figure 12. Output Power vs. Supply Voltage
Figure 15. Output Power vs. Load Resistance
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 BTL Mode
RL=8.2Ω
f=1KHz
THD=1%
Output Power (W)
Supply Voltage (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
BTL Mode
RL=8.2Ω
f=1KHz
THD=10%
Output Power (W)
Supply Voltage (V)
8.0 16.0 24.0 32.0 40.0 48.0 56.0 64.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700 VDD=5V
SE Mode
f=1KHz
LPF=80KHz
Output Power (mW)
Load Resistance (Ω)
THD+N=1%
THD+N=10%
8.0 16.0 24.0 32.0 40.0 48.0 56.0 64.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Load Resistance (Ω)
VDD=5V
BTL Mode
f=1KHz
LPF=80KHz
Output Power (W)
THD+N=1%
THD+N=10%
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
11
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Typical Performance Characteristics (Continued)
Figure 16. Power Dissipation vs. Output Power Figure 17. Power Dissipation vs. Output Power
Figure 18. Supply Current vs. Supply Voltage Figure 19. Volume Control Characteristics
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-80
-70
-60
-50
-40
-30
-20
-10
0
Attenuation (dB)
Volume Control Voltage (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
2
4
6
8
10
12
14
16
18
20 VIN=0mV
IO=0mA
SE Mode
BTL Mode
Supply Current (mA)
Supply Voltage (V)
0.0 40.0m 80.0m 120.0m 160.0m 200.0m
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
AA4002 RL=33Ω
VDD=5V
SE Mode
f=1KHz
THD<1%
LPF=80KHz
Power Dissipation (W)
Output Power (W)
AA4002 RL=8Ω
0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VDD=5V
BTL Mode
f=1KHz
RL=3.9Ω
Power Dissipation (W)
Output Power (W)
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
12
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Typical Performance Characteristics (Continued)
Figure 21. External Gain/Bass Boost Characteristics Figure 20. Channel Separation vs. Frequency
20 50 100 200 300 500 1K 2K 5K 10K 20K
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VDD=5V
RL=8.2 Ω
RI=RBS=RF=20KΩ
CBS=0.1µF
CBS=0.22µF
CBS=0.068µF
Output Level (dB)
Frequency (Hz)
100 1k 10k
-80
-70
-60
-50
-40
20
VDD=5V
SE Mode
RL=33Ω
f=1KHz
CB=1µF
Channel Separation (dB)
Frequency (Hz)
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
13
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information
SE/BTL Mode, HP_SENSE Pin
The AA4002 can be operated in 2 types of output
configurations, SE (Single-Ended) mode and BTL
(Bridged-Tied-Load) mode, determined by
HP_SENSE pin (pin 21) logic level. (Here is the
discussion about left channel only, it also applies to
right channel.)
If applying high level t o pin 21, the outpu t of OP2 unit
is in high impedance, the chip operates in SE mode.
There is no current loop between OUT+ and OUT-,
also no power consumption.
When HP_SENSE pin is held low, OP2 unit is turned
on, the chip operates in BTL mode. AC signal at OUT+
is -180o phase shift of OUT-. OP2 has fix ed unity gain
internally, so DC components (Bias voltage, approx
1/2 VDD) between OUT+, OUT- is canceled. There is
no need for DC block capacitors in system.
In BTL mode, voltage between speaker lo ad is about 2
times that in SE mode, so there is 4 times output power
compared to SE mode with same load.
In SE mode, output audio signal rides on Bias voltage
at OUT-, so it is necessary to use capacitor to block
DC bias and couple AC signal. See Figure 28 typical
application circuit.
It is recommended to connect HP_SENSE to the
control pin of headpho ne jack, illustrated in Figu re 28.
When headphone plug is not inserted, the voltage of
HP_SENSE pin is determined by voltage divider
formed by RPU, RL. For given resist ors va lue in Fi gure
28, RPU=100k, RL=1.5k, DC voltage at HP_SENSE is
about 75mV. AC signal equals output amplitude of
OUT- through COUT, so signal at HP_SENSE node is
75mV DC plus AC signal. The maximum Peak-to-
Peak voltage at OUT- is not greater than VDD=5.0V
supply voltage, so the positive maximum voltage of
HP_SENSE node is not greater than
2.5V+75mV=2.575V, which can not reach HP_SENSE
input high level minimum value (4.0V), there is no risk
of mode switching between SE and BTL.
HP_SENSE pin can also be connected to MCU I/O
port, it is necessary to note that AA4002 still can drive
headphone even in BTL mode because OUT- is always
active whatever SE or BTL mode.
Internal/External Gain, Gain SELECT Pin
The AA4002 provides 2 selectable feedback loops,
Internal and External determ ined by SELECT pin (pin
3) logic level. Applying low level to SELECT pin, the
AA4002 switches to internal feedback loop, OP1
works as unity gain. If applying high l evel to SELECT
pin, external components are used as feedback loop,
and the gain is expressed by formula below.
..............................(1)
Here ZCBS is the impedance of bass boost capacitor,
ZCBS=1/2π*f*CBS. So AVFB approaches 2 points,
AVFBLF at low frequency, AVFBHF at high frequency,
expressed by formula 2 and 3.
.............................................(2)
........................................................(3)
Bass Boost
From above discussion, the AA4002 can im prove gain
of audio signal at low frequency, which is hard to
listening for hu man ears rel ative to midd le band (2k Hz
to 3kHz). The boost co rner frequency is de termin ed by
formula 4.
Figure 22. BTL Configuration in Left Channel
I
FBSBS
VFB RRZCR
A
+
=)//(
I
FBS
VDLF RRR
A
+
=
I
F
VFBHF R
R
A=
10kΩ
20kΩ20kΩ
10kΩ
Left Out-
Left Out+
+
_
+
_
17
15
Bias
+
COUT
220µF
RL
1.5kΩ
OP1
OP2
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
14
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information (Continued)
..............................................(4)
Assuming RBS=RF=RI=20kΩ, CBS=0.068µF and
fBS=117Hz, the bass boost characteristic is shown in
Figure 21.
Fixed Gain/Adjustable Gain Loop, MODE
pin, DC Volume Control
The AA4002 can be set in fixed gain or adjustable
gain, according to applying high or low level to MODE
pin (pin 4). Low level is for fixed gain, High level is
for adjustable gain, which permits to change volume by
applying various DC voltages to DC VOL pin (pin7).
Table 1 shows the relationship of Volume Attenuation
vs. the voltage of DC VOL pin.
There are 31 steps from 0 to -78dB; step size is
different for different vol ume control voltage,
1dB/step from 0dB to -6dB,
2dB/step from -6dB to -36dB,
3dB/step from -36dB to -47dB,
4dB/step from -47db to -51dB,
5dB/step from -51dB to -66dB,
The last step is 12dB from -66dB to -78dB.
For example, increasing voltage applied to DC VOL
pin from 3.437V (point B in Figure 23) to 3.562V
(point D), gai n wi l l ch an ge one step from -4dB to -3dB
(point F).
BSBSBS CRf
π
21=
Table 1. Volume Attenuatio n vs. DC VOL Pin Voltage
VDD=5V
Attenuation (dB) High Level (V) Low Level (V)
0 5 3.875
-1 3.937 3.750
-2 3.812 3.625
-3 3.687 3.500
-4 3.562 3.375
-5 3.437 3.250
-6 3.312 3.125
-8 3.187 3.000
-10 3.06 2.875
-12 2.937 2.750
-14 2.812 2.625
-16 2.687 2.500
-18 2.562 2.375
-20 2.437 2.250
-22 2.312 2.125
-24 2.187 2.000
-26 2.062 1.875
-28 1.937 1.750
-30 1.812 1.625
-32 1.687 1.500
-34 1.562 1.375
-36 1.437 1.250
-39 1.312 1.125
-42 1.187 1.000
-45 1.062 0.875
-47 0.937 0.750
-51 0.812 0.625
-56 0.687 0.500
-61 0.562 0.375
-66 0.437 0.250
-78 0.312 0
Figure 23. Volume Attenuation vs. DC VOL Pin Voltage
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
15
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information (Continued)
But, decreasing voltage from 3.562V (point F), gain
does not change immediately, the change occurs at
3.5V (point E). There is a hysteresis which guarantees
that the volume control is monotonic, with immunity
against noise coupled from system. In above Table 1,
the column of Low Level means the lower threshold
voltage with the voltage of DC VOL varying from high
to low, High Level column means the other upper
threshold voltage DC VOL voltage varying from low
to high.
Mute, Shutdown
When applying high level to MUTE pin (pin 5), the
AA4002 will mute output stage stereo dock output-
whatever in BTL or SE mode. The AA4002 offers
shutdown function which can further reduce power
consumption. SHUTDOWN pin (p in 2) sh ould be held
low in normal operation. If applying high level to
SHUTDOWN pin, the AA4002 will turn off internal
bias circuits, enter into shutdown mode with very low
quiescent current, 0.7µA Typ. MUTE, SHUTDOWN
pin should be tied to h igh or low level to avoid undes-
ired operation state.
Left/Right Dock Output
There are stereo amplifiers built-in AA4002 front-end
input stages. It provide very low distortion audio moni-
tor signal for line out, the pass-band gain is determined
by external feedback resistors,
.....................................(5)
The dock output is also used as in put source for back-
end amplifiers, so the gain of docking output
(AVDOCK) will affect total loop gain. The function of
COUT(L/R) (0.1µF) serial in Left/Right dock output is to
remove DC bias.
Beep Detect
Beep feature is used in Notebook PC system for alert-
ing. If peak-to-peak voltage of beep signal applied to
BEEP DETECT pin (pin 11) exceeds a certain voltage
called detect voltage, the feature will be activated, then
AA4002 will be forced at BTL mode with internal
fixed gain, ignoring MUTE and HP_SENSE pin logic
level. For AA4002, VDETECT is about 2.8V. Beep sig-
nal passes through Left/Right channel input path, the
gain under BTL load is only dependent on the ratio of
RF(L/R) to RBEEP.
.................................(6)
For resistors value given in Fi gure 28, AVBEEP is about
0.2 (-14dB). If this feature is not used, connecting the
capacitor (CBEEP) to ground, it is recommended
removing two resistors (RBEEP, 200kΩ), to minimize
crosstalk between left and right channel.
CI, COUT, CB and CS (Power Supply
Bypassing Capacitor) Selection
For input stages of Left/Right channel, input capacitors
(CIL, CIR), are used to accommodate different DC level
between input source an d AA4002 bias voltage (about
1/2 VDD). Input capacitors (CIL, CIR) and input
resistors (RIL, RIR) form first order High Pass Filters,
which determine the corner frequency,
..........................(7)
For given values in Figure 28, RIL=RIR=20kΩ,
CIL=CIR=0.33µF, the corner frequency of input stage is
about 24Hz.
Similarly, for output stage in SE mode, output
capacitor (COUT), and headphone load also form a first
order High Pass Filter, and its cut-off frequency is
determined by classic formula below.
....................(8)
For bypass capacitor (CB), the purpose is to filter
internal bias noise, reduce harmonic distortion, and
improve power supply rejection ratio performance.
Tantalum or ceramic capacitor with low ESR is
recommended, and is placed as close as possible to
chip bypass pin in PCB layout. Both input and output
)/(
)/(
)/( RLI
RLF
RLVDOCK R
R
A=
BEEP
RLF
RLVBEEP R
R
A)/(
)/( 2∗=
)/()/(
)/( 21
RLIRLI
RLCI CR
f∗
=
π
)/()/(
)/( 21
RLORLHP
RLCO CR
f∗
=
π
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
16
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information (Continued)
signal ride on such reference voltage, the chip can not
work until internal DC bias is set up completely. So the
size of CB can also affect the chip start-up time, which
is approx linearly proportional to the value of bypass
capacitor. For AA4002, here are the start-up times for
several typical capacitor values.
For AA4002 power supply, it is better to use individual
power source generated from voltage regulators split
from video, digital circuit units in system. For
bypassing capacitors, it is recommended to use one
electrolytic capacitor of 4.7µF to 10µF in parallel with
0.1µF ceramic capacitor which is located close to the
part.
Setup Proper Gain, Design Example
The total closed loop gain is determined by three
individual units - input stage, feedback network and
output stage.
Input stage, pass-band gain
...................................................(9)
Feedback network, Internal pass-band gain, AVFB=1,
for external gain, see formula 1, 2, 3.
Output stage, for BTL mode, AVOUT=2, for SE mode,
AVOUT=1.
So the total pass-band gain of AA4002 , AVTOTAL is,
........................(10)
According to formulas above, it is easy to plot
Amplitude-Frequency characteristic curve. The lower
corner frequency is dependant on AVIN, AVOUT, Bass
Boost feature relies on AVOUT.
Example
VDD=5V, RL=8Ω, BTL configuration, desired output
power each channel, PO=1.0W, THD+N ≤1%.
Input signal, VIN=1.0VRMS from D-A converter.
Step 1,
To check if the chip can deliver 1W to 8Ω load with the
limitation of THD+N ≤1%, VDD=5V by Figure 6, 15.
Step 2,
If yes, to calculate output voltage, . So tot al pass-band
gain (ignoring Bass boost feature, low frequency
attenuation caused by AC coupling capacitors,
AVFB=1x.),
AVTOTAL=VOUT/VIN=2.83x.
Step 3,
AVIN=AVTOTAL/( AVFB*AVOUT )=2.83/(1*2)=1.415,
RF(L/R)=AVIN*RI(L/R), assuming components values
are given in Figure 28, just changing RF(L/R) to
20kΩ*1.415=28.3kΩ. Select the closest standard value
28kΩ.
Optimizing CLICK/POP Noise
The AA4002 includes a circuit to suppress CLICK/
POP noise during po wer up/down transition. In practi-
cal application, the chip can effectively suppress
common mode signal including CLICK/POP noise in
BTL configuration. In SE mode, decreasing the size of
output capacitor (COUT) can minish POP noise, which
can also affect low frequency response according to
formula 8 above. Increasing bypass capacitor value
(CB) can slower ramp of charge, prolong start-up time,
mask most of transient noises before bias voltage is
set-up.
Proper power on/off sequence can also optimize
CLICK/POP noise. The recommended is shown in
Figure 24.
Table 2. CB vs. Start-up Time
CB (µF) Start-up Time (ms)
0.47 300
1.0 600
2.2 1300
)/(
)/(
RLI
RLF
VIN R
R
A=
VOUTVFBVINVTOTAL AAAA ∗∗=
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
17
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information (Continued)
1) Power ON operation, enable mute, then enable
shutdown; after VDD is stable, release shutdown first,
then mute.
2) Power OFF, enable mute, then enable shutdown;
after VDD is discharged completely, release shutdown
firstly, th en mute.
Efficiency, Power Dissipation and Thermal
Consideration in Design
For Class-AB amplifier, Figure 11 is the basic equation
of efficiency worked in BTL configuration,
........................................................(11)
Here VP is peak voltage of output swing.
Thermal dissipation becomes major concern when
output power is close to 2W especially in BTL mode.
The maximum power dissipation of package for
AA4002 can be calculated by following equation.
........................................(12)
Here TJMAX is maximum operating junction
temperature 150oC, TA is ambient temperature, θJA is
thermal resistance form junction to ambient. For G
package (TSSOP-28 with exposed DAP), it is 45oC/W
given in datasheet page 6.
Assuming TA is +25oC, the maximum allowed power
dissipation PDMAX is about 2.78W according to
formula 12.
There is the other formula about power dissipation
drawn from application for each channel which is
determined by supply voltage and load resistance.
(for SE mode)....................(13)
(for BTL mode).................(14)
If power dissipation calculat ed by application is larger
than permissible by package, it is necessary to
assemble additional heat sinking, or keep ambient
temperature around the chip very low, or increasing
load impedance, or decreasing power supply voltage.
Here is an example, assuming VDD=5.0V, RL=4Ω,
stereo in BTL mode,
, for 2 channels, total power dissipation PDTOTAL=2*
PDBTLMAX=2*1.266=2.53W, according to formula 13,
the maxim ambient temperature is,
=150-45*2.53=36.2 oC
That is to say, if user wants AA4002 can delivery
maximum out put power to 4Ω load, at VDD=5.0V, BTL
mode, ambient temperature has to hold less than
36.2oC. When junction temperature exceeds about
+165oC, thermal shutdown circuit built -in A A400 2
Figure 24. Recommended Sequences for Power ON/OFF
VDD(V)
(pin6,16,27)
Mute(V)
(pin5)
Shutdown(V)
(pin2)
STBY MUTE STBYMUTE OFF
OFF PLAY
DD
P
V
V
4
π
η
=
JA
AJMAX
DMAX TT
P
θ
−
=
L
DD
DSEMAX R
V
P2
2
2
π
=
L
DD
DBTLMAX R
V
P2
2
2
π
=
W
R
V
P
L
DD
DBTLMAX 266.1
414.3 522 2
2
2
2
=
×
×
==
π
DBTLMAXJAJMAXA PTT
∗
−
=
θ
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
18
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information (Continued)
will turn off output stage to limit total power
dissipation.
There is an exposed thermal p ad on b ottom of th e chip
to provide the direct thermal path from die to external
heat sink. It is recommended to use copper on the
surface of PC Board as heat sink for AA4002. To dig
some matrix regular hol es under chip, set diameter for
each hole at 0.8~1.0mm, keep distance around 1.7mm
between holes, remove copper solder mask of this area,
and make sure to keep them contact well when
soldering to PCB. See Figure 24.
Recommended PCB Layout for AA4002
Using wide traces for power supply, output power to
reduce losses caused by parasitic resistance is
recommended, which can also help to release heat
away from the chip. It is recommended to place bypass
capacitor, power supply bypassing capacitors as close
as possible to the chip. Figure 25, 26 shows the
recommended layout of double layer PCB.
Figure 25. Copper and Holes under the Chip
Figure 26. Top Route, Copper and Silkscreen
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
19
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Application Information (Continued)
Figure 27. Bottom Route, Copper and Silkscreen
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
20
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Typical Application
Figure 28. Typical Applicatio n of AA40 02
Mode
Control
+
_
Beep
Detect
RIR
20kΩ
Power
Management
Click and Pop
Suppression
Circuitry
Volume
Control
31 Steps
10kΩ
20kΩ20kΩ
20kΩ20kΩ
10kΩ
10kΩ
10kΩ
DC Volum e
Control
Gain Select
Mode
Mute
HP Sense
To Contro l Pin on
Headphone Jack RBS
20kΩ
RBS
20kΩ
CBS
0.068µF
Right Out+
Left Out-
Right Out -
Left Out+
Shutdown
+
_
+
_
+
_
+
_
+
_
Bias
RIL
20kΩ
RPU
100kΩ
CV
0.1µF
0.1µF
RFL
20kΩ
+
CB
1µF
RL
1.5kΩ
100kΩ
+
COUTL Left Dock
Audio In
Left
0.33µF
RBEEP
200kΩ
+
Beep
In
Audio In
Right RFR
20kΩ
CS1 CS
CS
10µF0.1µF0.1µF
224 25
22
1, 8, 14, 20, 23
6, 16, 27
GND
9
CIR
0.33µF
10
11
12
13
CIL
4
5
21
37
19 18
17
15
26
Left Gain 2
Left Gain 1
RI
20kΩ
Right Gain 1 Right Ga in 2
To
HP Sense
Circuit
CONTROL PIN PIN RING
SLEEVE
HEADPHONE
JACK
TIP
Bias
+
+
RS
+
COUTR
1µFVDD
Left In
Bypass
CBS
0.068µF
COUT
220µF
DC Vol
VDD
VDD
VDD
Right Dock
Right In 28
COUT
220µF
RL
1.5kΩ
BEEP In
Left Dock
Right Dock
RBEEP
200kΩ
RI
20kΩ
RF
20kΩ
RF
20kΩ
RW
10kΩ
+
STEREO 2W AUDIO POWER AMPLIFIER AA4002
Data Sheet
21
Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited
Mechanical Dimensions
TSSOP-28 with Exposed-DAP Unit: mm(inch)
0.090(0.004)
0.200(0.008)
0.650(0.026) BSC
0.190(0.007)
0.300(0.012)
0.050(0.002)
0.150(0.006)
0.800(0.032)
1.050(0.041)
1.200(0.047)MAX
2.740(0.108)
3.050(0.120)
5.640(0.222)
5.940(0.234)
EXPOSED PAD
0.450(0.018)
0.750(0.030)
4.300(0.169)
4.500(0.177)
0°
8°
GAUGE LINE 0.250(0.010)
SEATING PLANE
6.250(0.246)
6.550(0.258)
PIN #1 ID.
9.600(0.378)
9.800(0.386)
BASE PLANE
IMPORTANT NOTICE
BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifi-
cations herein. BCD Semiconductor Manufacturing Limited does not assume any responsibility f or use of any its products for any
particular purpose, nor does BCD Semiconductor Man ufacturing Limited assume any liability arising out of the application or use
of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or
other rights nor the rights of others.
- Wafer Fab
Shanghai SIM-BCD Semiconductor Manufacturing Limited
800, Yi Shan Road, Shanghai 200233, China
Tel: +86-21-6485 1491, Fax: +86-21-5450 0008
BCD Semiconductor Manufacturing Limited
MAIN SITE
REGIONAL SALES OFFICE
Shenzhen Office
Shanghai SIM-BCD Semiconductor Manufacturing Co., Ltd. Shenzhen Office
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Tel: +86-755-8826 7951, Fax: +86-755-8826 7865
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BCD Semiconductor (Taiwan) Company Limited
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Tel: +886-2-2656 2808, Fax: +886-2-2656 2806
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- IC Design Group
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Tel: +86-21-6495 9539, Fax: +86-21-6485 9673
BCD Semiconductor Manufacturing Limited
http://www.bcdsemi.com
