Very Low Power CMOS SRAM
512K X 8 bit BS62LV4006
R0201
-
B
S62LV4006
Revision
1.4
May. 2006
1
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :
V
CC = 3.0V Operation current : 30mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.25uA (Typ.) at 25 OC
V
CC = 5.0V Operation current : 70mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 1.5uA (Typ.) at 25OC
Ÿ High speed access time :
-55 55ns (Max.) at VCC=3.0~5.5V
-70 70ns (Max.) at VCC=2.7~5.5V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
n DESCRIPTION
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.25uA at 3.0V/25OC and maximum access time of 55ns at
3.0V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV4006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 600mil Plastic DIP, 400 mil TSOP II,
8mmx13.4mm STSOP and 8mmx20mm TSOP package.
n POWER CONSUMPTION
POWER DISSIPATION
STANDBY
(ICCSB1, Max) Operating
(ICC, Max)
VCC=5V VCC=3V
PRODUCT
FAMILY OPERATING
TEMPERATURE
VCC=5.0V
VCC=3.0V
1MHz 10MHz
fMax. 1MHz 10MHz
fMax.
PKG TYPE
BS62LV4006DC
DICE
BS62LV4006EC
TSOP II-32
BS62LV4006HC
BGA-36-0608
BS62LV4006PC
PDIP-32
BS62LV4006SC
SOP-32
BS62LV4006STC
STSOP-32
BS62LV4006TC
Commercial
+0OC to +70OC
10uA
2.0uA
9mA 43mA
68mA
1.5mA
18mA
29mA
TSOP-32
BS62LV4006EI TSOP II-32
BS62LV4006HI BGA-36-0608
BS62LV4006PI PDIP-32
BS62LV4006SI SOP-32
BS62LV4006STI
STSOP-32
BS62LV4006TI
Industrial
-40OC to +85OC
20uA
4.0uA
10mA
45mA
70mA
2mA 20mA
30mA
TSOP-32
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BS62LV4006
EC
BS62LV4006EI
BS62LV4006SC
BS62LV4006SI
BS62LV4006PC
BS62LV4006PI
•
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
•
BS62LV4006T
C
BS62LV4006TI
BS62LV4006STC
BS62LV4006STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Address
Input Buffer
A
4
A
3
A
2
A
1
A0
Data
Input
Buffer
Control
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A12
A14
A16
A18
A15
A17
A13
A8
A9
A11
8
8
8
8
9
256
4096
1024
10
A
5
A
7
CE
WE
OE
VCC
GND
Data
Output
Buffer
A
6
A0
G
H
F
E
D
C
B
A
1
2
3
4
5
6
A11
A13
A12
A14
CE
A18
A16
A17
A15
DQ3
DQ2
VSS
VCC
NC
A1
WE
NC
A5
A4
A3
A6
A8
A2
A7
DQ1
DQ0
36-ball BGA top view
A0
DQ4
DQ5
VSS
VCC
DQ6
DQ7
A9
OE
A10
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
2
n PIN DESCRIPTIONS
Name Function
A0-A18 Address Input These 19 address inputs select one of the 524,288 x 8-bit in the RAM
CE Chip Enable Input CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations
. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
There 8 bi-directional ports are used to read data from or write data into the RAM.
VCC Power Supply
GND Ground
n TRUTH TABLE
MODE CE WE OE I/O OPERATION VCC CURRENT
Not selected
(Power Down) H X X High Z ICCSB, ICCSB1
Output Disabled L H H High Z ICC
Read L H L DOUT ICC
Write L L X DIN ICC
n ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
PARAMETER RATING
UNITS
VTERM Terminal Voltage with
Respect to GND -0.5(2) to 7.0
V
TBIAS Temperature Under
Bias -40 to +125
OC
TSTG Storage Temperature -60 to +150
OC
PT Power Dissipation 1.0 W
IOUT DC Output Current 20 mA
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.
n OPERATING RANGE
RANG AMBIENT
TEMPERATURE
VCC
Commercial 0OC to + 70OC 2.4V ~ 5.5V
Industrial -40OC to + 85OC 2.4V ~ 5.5V
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
SYMBOL
PAMAMETER
CONDITIONS
MAX.
UNITS
CIN Input
Capacitance VIN = 0V 6 pF
CIO Input/Output
Capacitance VI/O = 0V 8 pF
1. This parameter is guaranteed and not 100% tested.
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
3
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP.(1)
MAX. UNITS
VCC Power Supply 2.4 -- 5.5 V
VIL Input Low Voltage -0.5(2) -- 0.8 V
VIH Input High Voltage 2.2 -- VCC+0.3(3)
V
IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -- -- 1 UA
ILO Output Leakage Current
VCC = Max, CE= VIH, or OE = VIH,
VI/O = 0V to VCC -- -- 1 UA
VOL Output Low Voltage VCC = Max, IOL = 2.0mA -- -- 0.4 V
VOH Output High Voltage VCC = Min, IOH = -1.0mA 2.4 -- -- V
VCC=3.0V
30
ICC(5) Operating Power Supply
Current CE = VIL,
IDQ = 0mA, f = FMAX(4) VCC=5.0V
-- -- 70 mA
VCC=3.0V
2
ICC1 Operating Power Supply
Current CE = VIL,
IDQ = 0mA, f = 1MHz VCC=5.0V
-- -- 10 mA
VCC=3.0V
0.5
ICCSB Standby Current – TTL CE = VIH,
I
DQ = 0mA VCC=5.0V
-- -- 1.0 mA
VCC=3.0V
0.25 4.0
ICCSB1(6) Standby Current – CMOS
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V VCC=5.0V
-- 1.5 20 uA
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 29mA/68mA at VCC=3.0V/5.0V and TA=70OC.
6. ICCSB1(MAX.) is 2.0uA/10uA at VCC=3.0V/5.0V and TA=70OC.
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1)
MAX. UNITS
VDR VCC for Data Retention CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V 1.5 -- -- V
ICCDR(3) Data Retention Current CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V -- 0.1 1.5 uA
tCDR Chip Deselect to Data
Retention Time 0 -- -- ns
tR Operation Recovery Time
See Retention Waveform tRC (2) -- -- ns
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCRD(Max.) is 1.0uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
CC
t
CDR
V
CC
tR
VIH
VIH
CE≧VCC - 0.2V
V
DR
≧1.5V
CE
VCC
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
4
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels Vcc / 0V
Input Rise and Fall Times 1V/ns
Input and Output Timing
Reference Level 0.5Vcc
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL
Output Load
Others CL = 30pF+1TTL
1. Including jig and scope capacitance.
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L” WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H” WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
CYCLE TIME : 55ns
(VCC = 3.0~5.5V) CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
JEDEC
PARAMETER
NAME
PARANETER
NAME DESCRIPTION MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns
tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns
tE1LQV tACS Chip Select Access Time -- -- 55 -- -- 70 ns
tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns
tE1LQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns
tGLQX tOLZ Output Enable to Output Low Z 5 -- -- 5 -- -- ns
tE1HQZ tCHZ Chip Select to Output High Z -- -- 30 -- -- 35 ns
tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns
tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns
CL
(1)
1
TTL
Output
ALL INPUT PULSES
→
←
90%
V
CC
GND
Rise Time :
1V/ns Fall Time :
1V/ns
90%
→
←
10%
10%
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
5
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
READ CYCLE 2 (1,3,4)
READ CYCLE 3 (1, 4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
tRC
t
OH
t
AA
DOUT
ADDRESS
tOH
tCLZ
(5)
D
OUT
CE
t
ACS
tCHZ
(5)
t
OH
t
RC
t
OE
DOUT
CE
OE
ADDRESS
tCLZ
(5)
t
ACS
t
CHZ
(1,5)
tOHZ
(5)
t
OLZ
t
AA
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
6
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
CYCLE TIME : 55ns
(VCC = 3.0~5.5V) CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
JEDEC
PARAMETER
NAME
PARANETER
NAME DESCRIPTION MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns
tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns
tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns
tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns
tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns
tWHAX tWR Write Recovery Time (CE, WE)
0 -- -- 0 -- -- ns
tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns
tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns
tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns
tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
tWR
(3)
tCW
(11)
tWP
(2)
tAW
tOHZ
(4,10)
t
AS
t
DH
t
DW
DIN
DOUT
WE
CE
OE
ADDRESS
(5)
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
7
WRITE CYCLE 2 (1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
3. t
WR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals
of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. t CW is measured from the later of CE going low to the end of write.
t
WC
tCW
(11)
tWP
(2)
tAW
tWHZ
(4,10)
t
AS
t
DH
t
DW
DIN
D
OUT
WE
CE
t
OW
(7)
(8)
(8,9)
ADDRESS
(
5
)
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
8
n ORDERING INFORMATION
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
PACKAGE
D: DICE
E: TSOP II
H: BGA-36-0608
P: PDIP
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
BS62LV4006 X X Z Y Y
GRADE
C: +0oC ~ +70oC
I:
-
40
o
C ~ +85
o
C
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
BASE METAL
WITH PLATING
c
c1
SECTION A-A
b1
b
SOP -32
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
9
n PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
10
n PACKAGE DIMENSIONS (continued)
PDIP - 32
36 mini-BGA (6 x 8mm)
D1
VIEW A
1.2 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0
6.0
E
N
48
3.75
E1
D1
5.25
NOTES
:
B
S
6
2L
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R0201-BS62LV4006
Revision
1.4
May. 2006
11
n PACKAGE DIMENSIONS (continued)
3. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
RAD R1
0°~8°
DETAIL "X"
RAD R
WITH PLATING BASE METAL
SECTION Y-Y
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
0.20 T X
E1
E
SEATING PLANE
Y
-T-
1Y Y 16 "X"
32
-X-
17
0.050 BASIC
0.8 REF 0.031 REF
0.95 REF
2. REFREENCE DOCUMENT : JEDEC MS-024
1. CONTROLLING DIMENSION : MILLIMETERS.
Y
NOTE:
R1
ZD
R
L2
0.12
0.12
0.10
0.005
0.005
0.25
0.037 REF
0.25 BASIC
1.27 BASIC
L1
L
e
E1
0.40 0.50
10.03 10.16
E
D
c1
c
11.56
20.82
11.76
20.95
0.10
0.12
0.127
0.016
0.394
0.60
10.29
0.010 BASIC
0.020
0.400
0.004
0.005
0.455
0.820
11.96
21.08
0.16
0.21
0.463
0.825
0.005
0.004
0.010
0.024
0.405
0.471
0.830
0.006
0.008
DIMENSION
NOM.
b1
b
A2
A1
0.30
0.30
0.40
0.95
0.05
1.00
0.10
A
MIN.
(MM)
0.012
0.012
0.037
0.002
0.52
0.45
1.05
0.15
0.016
0.039
0.004
MIN.MAX.
1.20
NOM.
(INCH)
DIMENSION
0.018
0.020
0.042
0.006
MAX.
0.047
eb
ZD
D
A2
A
A1
0.44 REF
0.44 REF
L1
GAGE PLANE
L2
L
c
b
b1
c1
c
TSOP II - 32
B
S
6
2L
V
4006
R0201-BS62LV4006
Revision
1.4
May. 2006
12
n Revision History
Revision No. History Draft Date Remark
1.2 To add Icc1 characteristic parameter Jan. 13, 2006
To improve Iccsb1 spec.
I-grade from 60uA to 20uA at 5.0V
10uA to 4.0uA at 3.0V
C-grade from 30uA to 10uA at 5.0V
5.0uA to 2.0uA at 3.0V
1.3 To Add 400 mil TSOP II package type March 20, 2006
1.4 Change I-grade operation temperature range May. 25, 2006
- from –25OC to –40OC
