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10-A, 12-V INPUT NON-ISOLATED WIDE-OUTPUT
FEATURES
APPLICATIONS
Nominal Size=1inx0.62 in
(25,4 mm x 15,75 mm)
DESCRIPTION
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
ADJUST POWER MODULE
•Point-of-Load Alliance (POLA™) Compatible
•Up to 10-A Output Current
•12-V Input Voltage •Complex Digital Systems
•Wide-Output Voltage Adjust
(1.2 V to 5.5 V)/(0.8 V to 1.8 V)
•Efficiencies up to 95%
•225 W/in3Power Density
•On/Off Inhibit
•Output Voltage Sense
•Margin Up/Down Controls
•Undervoltage Lockout
•Auto-Track™ Sequencing
•Output Overcurrent Protection (Non-latching,
Auto-Reset)
•Operating Temperature: –40°Cto85°C
•Safety Agency Approvals:
UL 60950, cUL 600950, EN60950 VDE
The PTH12060 series is a non-isolated power module, and part of a new class of complete dc/dc converters
from Texas Instruments. These modules are small in size, and are an alternative for applications requiring up to
10 A of load current.
The small footprint, (1 inch ×0.62 inch) and industry leading features makes this module suitable for space
conscious digital systems that incorporate multiple processors.
This series of modules operate from a 12-V input bus voltage to provide step-down power conversion to a wide
range of output voltages. The output voltage of the W-suffix device may be set to any voltage over the adjust
range, 1.2 V to 5.5 V. The L-suffix device has an adjustment range of 0.8 V to 1.8 V. The output voltage is set
within the adjust range using a single external resistor.
This product includes Auto-Track™ Sequencing. Auto-Track simplifies the task of supply voltage sequencing in a
power system, by enabling modules to track each other, or any other external voltage, during power up and
power down.
Other features include an on/off inhibit and margin up/down controls. An output voltage sense ensures tight load
regulation. Non-latching overcurrent trip protects against load faults.
Target applications are complex digital systems that incorporate the industry's high-speed TMS320™ DSP
family, ASICs, FPGAs, micro-processors, and bus drivers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Auto-Track, POLA, TMS320 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Margin Down
Margin Up
VI
C
560 F
(Required)
I
m
C1
330 F
(Optional)
O
m
C2
Ceramic
(Optional)
O
+
+
Inhibit
GND GND
VO
V Sense
O
Track
1
2
10 7
6
54
3
98
R,1%
(Required)
SET
L
O
A
D
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
STANDARD APPLICATION
A. RSET = Required to set the output voltage to a value higher than the minimum value. See the Application Information
section for values.
ORDERING INFORMATION
PTH12060 (Base Part Number)
Output Voltage Range Part Number (1) DESCRIPTION Pb – free and Mechanical
RoHS Package (2)
PTH12060WAH Horizontal T/H Yes (3) EUW
1.2 V–5.5 V (Adjustable) PTH12060WAS Standard SMD No (4) EUY
PTH12060WAZ Optional SMD Yes (3) EUY
PTH12060LAH Horizontal T/H Yes (3) EUW
0.8 V–1.8 V (Adjustable) PTH12060LAS Standard SMD No (4) EUY
PTH12060LAZ Optional SMD Yes (3) EUY
(1) Add Tto end of part number for tape and reel on SMD packages only.
(2) Reference the applicable package reference drawing for the dimensions and PC board layout.
(3) Lead (Pb) – free option specifies Sn/Ag pin solder material.
(4) Standard option specifies 63/37, Sn/Pb pin solder material.
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ABSOLUTE MAXIMUM RATINGS
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
voltages are with respect to GND
UNIT
VIInput voltage Track –0.3 V to VI+0.3 V
Operating temperature –40°Cto85°C(1)
TAOver VIrange
range
Wave solder PTH12060WAH 260°C(2)
Twave Surface temperature of module body or pins (5 seconds)
temperature
PTH12060WAS 235°C(2)
Solder reflow
Treflow Surface temperature of module body or pins
temperature PTH12060WAZ 260°C(2)
Tstg Storage temperature –40°C to 125°C
Mechanical shock Per Mil-STD-883D, Method 2002.3, 1 msec, ½ Sine, mounted 500 G
Mechanical vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz 20 G
Weight 5 grams
Flammability Meets UL 94V-O
(1) For operation below 0°C, the external capacitors must have stable characteristics. Use either a low ESR tantalum, Os-Con, or ceramic
capacitor.
(2) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated
maximum.
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ELECTRICAL CHARACTERISTICS
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
TA= 25°C; VI=12V;V
O= 3.3 V; CI= 560 µF, CO=0µF,andI
O=I
Omax (unless otherwise stated)
PTH12060W UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX
TA=60°C, 200 LFM airflow 0 10(1) A
IOOutput current Over ∆Vadj range TA=25°C, natural convection 10(1) A
VIInput voltage range Over IOrange 10.8 13.2 V
VOtol Set-point voltage tolerance ±2(2) %VO
∆Regtemp Temperature variation –40°C<T
A<85°C±0.5 %VO
∆Regline Line regulation Over Vin range ±10 mV
∆Regload Load regulation Over Iorange ±12 mV
∆Regtot Total output variation Includes set-point, line, load, –40°C≤TA≤85°C±3%V
O
∆Vadj Output voltage adjust range Over Vin range 1.2 5.5 V
RSET = 280 Ω,V
O= 5.0 V 94%
RSET =2.0kΩ,V
O= 3.3 V 92%
RSET =4.32kΩ,V
O= 2.5 V 90%
ηEfficiency IO=8A RSET = 11.5 kΩ,V
O= 1.8 V 87%
RSET = 24.3 kΩ,V
O= 1.5 V 85%
RSET = open circuit, VO= 1.2 V 83%
VO≤2.5 V 25(3) mVPP
20-MHz bandwidth,
VOripple (peak-to-peak) with CO2 = 10 µF ceramic VO>2.5V 1
(3) %VO
IOtrip Overcurrent threshold Reset, followed by auto-recovery 20 A
ttr 1 A/µs load step, 50 to Recovery time 70 µS
Transient response 100% Iomax, Voover/undershoot 100 mV
∆Vtr CO1 = 330 µF
VOadj Margin up/down adjust ±5%
IILmargin Margin input current (pins 9/10) Pin to GND –8 (4) µA
IILtrack Track input current (pin 8) Pin to GND –0.11(5) mA
dVtrack/dt Track slew rate capability CO≤CO(max) 1V/ms
VIincreasing 9.5 10.4
UVLO Undervoltage lockout V
VIdecreasing 8.8 9
Inhibit Control (pin 3) Referenced to GND
VIH Input high voltage VI– 0.5 Open(5)
V
VIL Input low voltage –0.2 0.5
IIL inhibit Input low current Pin to GND 0.24 mA
IIinhibit Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA
fsSwitching frequency Over VIand IOranges 300 350 400 kHz
CIExternal input capacitance 560(6) µF
Nonceramic 0 330(7) 5500(8)
Capacitance value µF
COExternal output capacitance Ceramic 0 300
Equivalent series resistance (nonceramic) 4(9) mΩ
6.4
MTBF Reliability Per Bellcore TR-332, 50% stress, TA=40°C, ground benign 106Hr
(1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with 100 ppm/°C or better temperature stability.
(3) The peak-to-peak output ripple voltage is measured with an external 10-µF ceramic capacitor. See the standard application schematic.
(4) A small, low leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(5) This control pin has an internal pull-up to the input voltage VI(7.5 V for pin 8). If it is left open-circuit, the module operates when input
power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control.
For further information, see the related application information section.
(6) A 560 µF input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms of
ripple current.
(7) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the
transient response.
(8) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 2200 µF. See the application notes for further guidance.
(9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 mΩas the minimum when using max-ESR values
to calculate.
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ELECTRICAL CHARACTERISTICS
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
TA= 25°C; VI=12V;V
O= 1.8 V; CI= 560 µF, CO=0µF,andI
O=I
Omax (unless otherwise stated)
PTH12060L UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX
Over ∆Vadj range 85°C, 200 LFM airflow 0 10(1)
IOOutput current A
25°C, natural convention 0 10(1)
VIInput voltage range Over IOrange 10.8 13.2 V
VOtol Set-point voltage tolerance ±2(2) %VO
∆Regtemp Temperature variation –40°C<T
A<85°C±0.5 %VO
∆Regline Line regulation Over VIrange ±10 mV
∆Regload Load regulation Over IOrange ±12 mV
∆Regtot Total output variation Includes set-point, line, load, –40°C≤TA≤85°C±3%V
O
∆Vadj Output voltage adjust range Over VIrange 0.8 1.8 V
RSET = 130 Ω,V
O= 1.8 V 88%
RSET =3.57kΩ,V
O= 1.5 V 87%
ηEfficiency IO=8A R
SET = 12.1 kΩ,V
O= 1.2 V 84%
RSET = 32.4 kΩ,V
O= 1 V 82%
RSET = open circuit, VO= 0.8 V 81%
VO>1V 20
(3)
20-MHz bandwidth,
VOripple (peak-to-peak) mVPP
with CO2 = 10 µF ceramic VO≤1V 30
(3)
IOtrip Overcurrent threshold Reset, followed by auto-recovery 20 A
ttr 1 A/µs load step, 50 to 100% Recovery time 70 µS
Transient response IOmax, VOover/undershoot 100 mV
∆Vtr CO1 = 330 µF
VOadj Margin up/dow adjust ±5%
IILmargin Margin input current (pins 9/10) Pin to GND –8(4) µA
IILtrack Track input current (pin 8) Pin to GND –0.11(5) mA
dVtrack/dt Track slew rate capability CO≤CO(max) 1V/ms
VIincreasing 9.5 10.4
UVLO Under-voltage lockout V
VIdecreasing 8.8 9
Inhibit Control (pin 3) Referenced to GND
VIH Input high voltage VI– 0.5 Open(5)
V
VIL Input low voltage –0.2 0.5
IIL inhibit Input low current Pin to GND 0.24 mA
IIinhibit Input standby current Inhibit (pin 3) to GND, Track (pin 8) open 10 mA
fsSwitching frequency Over VIand IOranges 200 250 300 kHz
CIExternal input capacitance 560(6) µF
Nonceramic 0 330(7) 5500(8)
Capacitance value µF
COExternal output capacitance Ceramic 0 300
Equivalent series resistance (nonceramic) 4(9) mΩ
Per Bellcore TR-332 6.4
MTBF Reliability 106Hr
50% stress, TA=40°C, ground benign
(1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with 100 ppm/°C or better temperature stability.
(3) The peak-to-peak output ripple voltage is measured with an external 10-µF ceramic capacitor. See the standard application schematic.
(4) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(5) This control pin has an internal pull-up to the input voltage VI(7.5 V for pin 8). If it is left open-circuit, the module operates when input
power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control.
For further information, see the application information section.
(6) A 560-µF input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms of
ripple current.
(7) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the
transient response.
(8) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 2200 µF. See the application notes for further guidance.
(9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 mΩas the minimum when using max-ESR values
to calculate.
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DEVICE INFORMATION
PTHXX060
(Top View)
1
2
10 9 8
7
6
543
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Terminal Functions
TERMINAL DESCRIPTION
NAME NO.
VI2 The positive input voltage power node to the module, which is referenced to common GND.
VO6 The regulated positive power output with respect to the GND node.
This is the common ground connection for the VIand VOpower connections. It is also the 0 Vdc reference for the
GND 1, 7 control inputs.
The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low level ground
signal to this input disables the module’s output and turns off the output voltage. When the Inhibit control is active,
Inhibit 3 the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open-circuit, the module
produces an output whenever a valid input source is applied.
A 1% resistor must be directly connected between this pin and GND (pin 1) to set the output voltage of the module
to a value higher than its lowest value. The temperature stability of the resistor should be 100 ppm/°C (or better).
The set-point range is 1.2 V to 5.5 V for W-suffix devices, and 0.8 V to 1.8 V for L-suffix devices. The resistor value
VOAdjust 4 required for a given output voltage may be calculated using a formula. If left open circuit, the output voltage defaults
to its lowest value. For further information on output voltage adjustment, see the application information section.
Table 2 gives the preferred resistor values for a number of standard output voltages.
The sense input allows the regulation circuit to compensate for voltage drop between the module and the load. For
VOSense 5 optimal voltage accuracy, VOSense should be connected to VO. It can also be left disconnected.
This is an analog control input that enables the output voltage to follow an external voltage. This pin becomes
active typically 20 ms after the input voltage has been applied, and allows direct control of the output voltage from
zero volts, up to the nominal set-point voltage. Within this range, the output follows the voltage at the Track pin on a
Track 8 volt-for-volt basis. When the control voltage is raised above this range, the module regulates at its set-point voltage.
The feature allows the output voltage to rise simultaneously with other modules powered from the same input bus.
If unused, this input should be connected to VI.
Note: Due to the undervoltage lockout feature, the output of the module cannot follow its own input voltage during
power up. For more information, see the application information section.
When this input is asserted to GND, the output voltage is decreased by 5% from the nominal. The input requires an
Margin Down 9 open-collector (open-drain) interface. It is not TTL compatible. A lower percent change can be accommodated with
a series resistor. For further information, see the application information section.
When this input is asserted to GND, the output voltage is increased by 5%. The input requires an open-collector
Margin Up 10 (open-drain) interface. It is not TTL compatible. The percent change can be reduced with a series resistor. For
further information, see the application information section.
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PTH12060W TYPICAL CHARACTERISTICS (VI=12V)
(1)(2)
0246810
Efficiency − %
IO − Output Current − A
50
60
70
80
90
100
VO = 3.3 V
VO = 2.5 V
VO = 1.8 V
VO = 1.5 V
VO = 1.2 V
VO = 5 V
Output Ripple − mV
0
20
40
60
80
100
02 46810
IO − Output Current − A
VO = 5 V VO = 2.5 V
VO = 1.8 V
VO = 1.5 V VO = 1.2 V
VO = 3.3 V
20
30
40
50
60
70
80
90 400LFM
200 LFM
100 LFM
Nat Conv
TA−Ambient Temperature −
5C
IO − Output Current − A
0246810
0
1
2
3
4
5
IO − Output Current − A
VO = 3.3 V
VO = 2.5 V
VO = 1.2 V
VO = 5 V
− Power Dissipation − W
PD
0246810
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
EFFICIENCY OUTPUT RIPPLE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
(see Note 3 of table)
Figure 1. Figure 2.
POWER DISSIPATION TEMPERATURE DERATING
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 3. Figure 4.
(1) Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the Converter.
Applies to Figure 1,Figure 2, and Figure 3.
(2) SOA graphs represent the conditions at which internal components are at or below the manufacturer's maximum operating
temperatures. Derating limits apply to modules soldered directly to a 4 in × 4 in, double-sided PCB with 1 oz copper. For surface mount
products (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer
to the mechanical specification for more information. Applies to Figure 4.
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PTH12060L TYPICAL CHARACTERISTICS (VI=12V)
(1)(2)
50
60
70
80
90
100
Efficiency − %
VO = 0.8 V
VO = 1.8 V
VO = 1.5 V
VO = 1.2 V
VO = 1 V
IO − Output Current − A
0246810
0
20
40
60
80
100
Output Ripple − mV
VO= 1.8 V
VO= 1.5 V
VO= 1.2
V
VO= 1 V
VO = 0.8 V
IO − Output Current − A
0246810
− Power Dissipation − W
P
D
0
0.5
1
1.5
2
2.5
3
IO − Output Current − A
0246810
VO= 1.8 V
VO= 1.5 V
VO= 1 V
VO = 0.8
V
VO= 1.2 V
20
30
40
50
60
70
80
90
IO − Output Current − A
0246810
100 LFM
Nat Conv
TA−Ambient Temperature −
5C
VO =≤1.8 V
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
EFFICIENCY OUTPUT RIPPLE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 5. Figure 6.
POWER DISSIPATION TEMPERATURE DERATING
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 7. Figure 8.
(1) Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the Converter.
Applies to Figure 5,Figure 6, and Figure 7.
(2) SOA graphs represent the conditions at which internal components are at or below the manufacturer's maximum operating
temperatures. Derating limits apply to modules soldered directly to a 4 in × 4 in, double-sided PCB with 1 oz copper. For surface mount
products (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer
to the mechanical specification for more information. Applies to Figure 8.
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APPLICATION INFORMATION
CAPACITOR RECOMMENDATIONS FOR THE PTH12060 SERIES OF POWER MODULES
Input Capacitor
Output Capacitors (Optional)
Ceramic Capacitors
Tantalum Capacitors
Capacitor Table
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
The recommended input capacitance is determined by the 560 µF minimum capacitance and 1050 mArms
minimum ripple current rating. A 10 µF X5R/X7R ceramic capacitor can be added to reduce the reflected input
ripple current. The ceramic capacitor should be located between the input electrolytic and the module.
Ripple current, less than 100 mΩequivalent series resistance (ESR) and temperature, are major considerations
when selecting input capacitors. Unlike polymer-tantalum capacitors, regular tantalum capacitors have a
recommended minimum voltage rating of 2 ×(max. dc voltage + ac ripple). No tantalum capacitors were found
with sufficient voltage rating to meet this requirement. At temperatures below 0°C, the ESR of aluminum
electrolytic capacitors increases. For these applications, Os-Con, polymer-tantalum, and polymer-aluminum types
should be considered.
For applications with load transients (sudden changes in load current), regulator response benefits from external
output capacitance. The value of 330 µF is used to define the transient response specification. For most
applications, a high quality, computer-grade aluminum electrolytic capacitor is adequate. These capacitors
provide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable for ambient temperatures
above 0°C. Below 0°C, tantalum, ceramic, or Os-Con type capacitors are recommended. When using one or
more nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 mΩ(7 mΩusing the
manufacturer's maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified in
Table 1.
In addition to electrolytic capacitance, adding a 10 µF X5R/X7R ceramic capacitor to the output reduces the
output ripple voltage and improves the regulator's transient response. The measurement of both the output ripple
and transient response is also best achieved across a 10 µF ceramic capacitor.
Above 150 kHz, the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramic
capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be
used to reduce the reflected ripple current at the input, and improve the transient response of the output. When
used on the output, their combined ESR is not critical as long as the total value of ceramic capacitance does not
exceed 300 µF. Also, to prevent the formation of local resonances, do not place more than five identical ceramic
capacitors in parallel with values of 10 µF or greater.
Tantalum type capacitors are most suited for use on the output bus, and are recommended for applications
where the ambient operating temperature can be less than 0°C. The AVX TPS, Sprague 593D/594/595, and
Kemet T495/T510 capacitor series are suggested over other tantalum types due to their higher rated surge,
power dissipation, and ripple current capability. As a caution, many general-purpose tantalum capacitors have
considerably higher ESR, reduced power dissipation, and lower ripple current capability. These capacitors are
also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do not
have a stated ESR or surge current rating are not recommended for power applications.
When specifying Os-con and polymer tantalum capacitors for the output, the minimum ESR limit is encountered
well before the maximum capacitance value is reached.
Table 1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple
current (rms) ratings. The recommended number of capacitors required at both the input and output buses is
identified for each capacitor type.
Note: This is not an extensive capacitor list. Capacitors from other vendors are available with comparable
specifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are critical
parameters necessary to insure both optimum regulator performance and long capacitor life.
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Designing for Very Fast Load Transients
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
The transient response of the dc/dc converter is characterized using a load transient with a di/dt of 1 A/µs. The
typical voltage deviation for this load transient is given in the data sheet specification table using the optional
value of output capacitance. As the di/dt of a transient is increased, the response of a converter's regulation
circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation with any dc/dc
converter once the speed of the transient exceeds its bandwidth capability. If the target application specifies a
higher di/dt or lower voltage deviation, the requirement is met with additional output capacitor decoupling. In
these cases, special attention must be paid to the type, value, and ESR of the capacitors selected.
If the transient performance requirements exceed that specified in this data sheet, or the total amount of load
capacitance is above 3,000 µF, the selection of output capacitors becomes more important.
Table 1. Input/Output Capacitors(1)
Capacitor Characteristics Quantity
Max Ripple
Capacitor Vendor, Working Max ESR Vendor Number
Value Current at Physical Size Input Output
Type/Series (Style) Voltage at 100 kHz
(µF) 85°C (Irms) (mm) Bus Bus
(V) (Ω)(mA)
Panasonic, Aluminum 25 560 0.065 1205 12,5 ×15 1 1 EEUFC1E561S
FC (Radial) 25 1000 0.060 1100 12,5 ×13,5 1 1 EEVFK1E102Q
FK (SMD) 35 680 0.060 1100 12,5 ×13,5 1 1 EEVFK1V681Q
United Chemi-Con
PS, Poly-Aluminum (Radial) 16 330 0.0014 5050 10 ×12,5 2 ≤2 16PS330MJ12
LXZ, Aluminum 16 680 0.068 1050 10 ×16 1 1 LXZ16VB681M10X16L
L
PXA, Poly-Aluminum (SMD) 16 330 0.014 5050 10 ×12,2 2 ≤2 PXA16VC331MJ12
Nichicon Aluminum PM 25 560 0.060 1060 12,5 ×15 1 1 UPM1E561MHH6
(Radial)
HD (Radial) 16 680 0.038 1430 10 ×16 1 1 UHD1C681MHR
PM (Radial) 35 560 0.048 1360 16 ×15 1 1 UPM1V561MHH6
Panasonic, Poly-Aluminum:
S/SE (SMD) 6.3 180 0.005 4000 7,3 ×4,3 ×4,2 N/R(2) ≤1(3) EEFSE0J181R
(VO≤5.1 V)
Sanyo
TPE, ps-Ccap (SMD) 10 330 0.025 3000 7,3 ×5,7 N/R(2) ≤4 10TPE330M
SEPC, Os-con (Radial) 16 470 0.010 >9700 10 ×13 2 ≤1 16SEPC470M
SVP, Os-con (SMD) 16 330 0.016 4700 11 ×12 2 ≤3 16SVP330M
AVX
TPS, Tantalum (SMD) 10 470 0.045 >1723 N/R(2) ≤5(3) TPSE477M019R0045
(VO≤5.1 V)
7,3 ×5,7 ×4,1
TPS, Tantalum (SMD) 10 330 0.045 >1723 2 ≤5(3) TPSE337M019R0045
(VO≤5.1 V)
Kemet
T520, Poly-Tantalum (SMD) 10 330 0.040 1800 N/R(2) ≤5(3) T520X337M010AS
T530, Tantalum/Organic 10 330 0.015 >3800 N/R(2) ≤2 T53X337M010AS
4,3 ×7,3 ×4,0
6.3 470 0.012 4200 N/R(2) ≤2(3) T530X477M0061S
(VO≤5.1 V)
(1) Capacitor Supplier Verification
Please verify availability of capacitors identified in this table. Capacitor suppliers may recommend alternative part numbers because of
limited availability or obsolete products. In some instances, the capacitor product life cycle may be in decline and have short-term
consideration for obsolescence.
RoHS, Lead-free and Material Details
Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process
requirements. Component designators or part number deviations can occur when material composition or soldering requirements are
updated.
(2) N/R – Not recommended. The capacitor voltage rating does not meet the minimum operating limits.
(3) The voltage rating of this capacitor only allows it to be used for output voltages that are equal to or less than 5.1 V.
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Adjusting the Output Voltage of the PTH12060x Series of Wide-Output Adjust Power Modules
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
Table 1. Input/Output Capacitors (continued)
Capacitor Characteristics Quantity
Max Ripple
Capacitor Vendor, Working Max ESR Vendor Number
Value Current at Physical Size Input Output
Type/Series (Style) Voltage at 100 kHz
(µF) 85°C (Irms) (mm) Bus Bus
(V) (Ω)(mA)
Vishay-Sprague 595D477X0010R2T
594D, Tantalum (SMD) 10 470 0.100 1440 7,2 ×6×4,1 N/R(2) (VO≤5.1 V)
94SP, Organic (Radial) 16 270 0.018 4200 10 ×10,5 2(4) ≤3 94SP277X0016FBP
94SVP, Organic (SMD) 16 330 0.017 4500 10 ×12.7 2 ≤2 94SVP337X0016F12
Kemet, Ceramic X5R (SMD) 16 10 0.002 1210 case 1(5) ≤5 C1210C106M4PAC
6.3 47 0.002 3225 mm N/R(2) ≤5(3) C1210C476K9PAC
Murata, Ceramic X5R (SMD) 6.3 100 0.002 1210 case N/R(2) ≤3 GRM32ER60J107M
6.3 47 3225 mm N/R(2) ≤5 GRM32ER60J476M
16 22 1(5) ≤5 GRM32ER61C226K
16 10 1(5) ≤5 GRM32DR61C106K
TDK, Ceramic X5R (SMD) 6.3 100 0.002 1210 case N/R(2) ≤3 C3225X5R0J107MT
6.3 47 3225 mm N/R(2) ≤5 C3225X5R0J476MT
16 22 1(5) ≤5 C3225X5R1C226MT
16 10 1(5) ≤5 C3225X5R1C106MT
(4) A total capacitance of 540 µF is acceptable based on the combined ripple current rating.
(5) Ceramic capacitors are required to complement electrolytic types at the input and to reduce high-frequency ripple current.
The VOAdjust control (pin 4) sets the output voltage of the PTH12060 product. The adjustment range is from 1.2
V to 5.5 V for the W-suffix modules, and 0.8 V to 1.8 V for L-suffix modules. The adjustment method requires the
addition of a single external resistor, RSET, that must be connected directly between the VOAdjust and GND pins.
Table 2 gives the preferred value of the external resistor for a number of standard voltages, along with the actual
output voltage that the resistance value provides. Figure 9 shows the placement of the required resistor.
Table 2. Preferred Values of RSET for Standard Output Voltages
PTH12060W PTH12060L
VOVOVO
RSET RSET
(Required) (Actual) (Actual)
5 V 280 Ω5.009 V N/A N/A
3.3V 2kΩ3.294 V N/A N/A
2.5 V 4.32 kΩ2.503 V N/A N/A
2 V 8.06 kΩ2.01 V N/A N/A
1.8 V 11.5 kΩ1.801 V 130 Ω1.8 V
1.5 V 24.3 kΩ1.506 V 3.57 kΩ1.499 V
1.2 V Open 1.2 V 12.1 kΩ1.201 V
1.1 V N/A N/A 18.7 kΩ1.101 V
1.0 V N/A N/A 32.4 kΩ0.999 V
0.9 V N/A N/A 71.5 kΩ0.901 V
0.8 V N/A N/A Open 0.8 V
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R=10kx
SET W0.8 V -R k
SW
V-V
Omin (1)
VI
++
GND
VO
V Sense
O
R
1%
SET
PTH12060
1
10
4
5
62
3
9
7
8
C
330 F
(Optional)
O
m
C
560 F
(Required)
I
m
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
For other output voltages, the value of the required resistor can either be calculated, or simply selected from the
range of values given in Table 4. The following formula is used for calculating the adjust resistor value. Select the
appropriate value for the parameters, RSand Vmin, from Table 3.
Table 3. Adjust Formula Parameters
Part Number PTH12060W PTH12060L
Vmin 1.2 V 0.8 V
Vmax 5.5 V 1.8 V
RS1.82 kΩ7.87 kΩ
(1) A 0.05-W rated resistor can be used. The tolerance should be 1%, with a temperature stability of 100 ppm/°Cor
better. Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 4 and 7
using dedicated PCB traces.
(2) Never connect capacitors from VOAdjust to either GND or VO. Any capacitance added to the VOAdjust pin affects the
stability of the regulator.
Figure 9. VOAdjust Resistor Placement
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Features of the PTH Family of Non-Isolated Wide Output Adjust Power Modules
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Table 4. Output Voltage Set-Point Resistor Values
PTH12060W PTH12060L
VORSET VORSET VORSET
1.2 Open 2.7 3.51 kΩ0.8 Open
1.225 318 kΩ2.75 3.34 kΩ0.825 312 kΩ
1.25 158 kΩ2.8 3.18 kΩ0.85 152 kΩ
1.275 105 kΩ2.85 3.03 kΩ0.875 98.8 kΩ
1.3 78.2 kΩ2.9 2.89 kΩ0.9 72.1 kΩ
1.325 62.2 kΩ2.95 2.75 kΩ0.925 56.1 kΩ
1.35 51.5 kΩ32.62kΩ0.95 45.5 kΩ
1.375 43.9 kΩ3.05 2.5 kΩ0.975 37.8 kΩ
1.4 38.2 kΩ3.1 2.39 kΩ1 32.1 kΩ
1.425 33.7 kΩ3.15 2.28 kΩ1.025 27.7 kΩ
1.45 30.2 kΩ3.2 2.18 kΩ1.05 24.1 kΩ
1.475 27.3 kΩ3.25 2.08 kΩ1.075 21.2 kΩ
1.5 24.8 kΩ3.3 1.99 kΩ1.1 18.8 kΩ
1.55 21 kΩ3.35 1.9 kΩ1.125 16.7 kΩ
1.6 18.2 kΩ3.4 1.82 kΩ1.15 15 kΩ
1.65 16 kΩ3.5 1.66 kΩ1.175 13.5 kΩ
1.7 14.2 kΩ3.6 1.51 kΩ1.2 12.1 kΩ
1.75 12.7 kΩ3.7 1.38 kΩ1.225 11 kΩ
1.8 11.5 kΩ3.8 1.26 kΩ1.25 9.91 kΩ
1.85 10.5 kΩ3.9 1.14 kΩ1.275 8.97 kΩ
1.9 9.61 kΩ41.04kΩ1.3 8.13 kΩ
1.95 8.85 kΩ4.1 939 Ω1.325 7.37 kΩ
28.18kΩ4.2 847 Ω1.35 6.68 kΩ
2.05 7.59 kΩ4.3 761 Ω1.375 6.04 kΩ
2.1 7.07 kΩ4.4 680 Ω1.4 5.46 kΩ
2.15 6.6 kΩ4.5 604 Ω1.425 4.93 kΩ
2.2 6.18 kΩ4.6 533 Ω1.45 4.44 kΩ
2.25 5.8 kΩ4.7 466 Ω1.475 3.98 kΩ
2.3 5.45 kΩ4.8 402 Ω1.5 3.56 kΩ
2.35 5.14 kΩ4.9 342 Ω1.55 2.8 kΩ
2.4 4.85 kΩ5 285 Ω1.6 2.13 kΩ
2.45 4.58 kΩ5.1 231 Ω1.65 1.54 kΩ
2.5 4.33 kΩ5.2 180 Ω1.7 1.02 kΩ
2.55 4.11 kΩ5.3 131 Ω1.75 551 Ω
2.6 3.89 kΩ5.4 85 Ω1.8 130 Ω
2.65 3.7 kΩ5.5 41 Ω
The PTH/PTV family of non-isolated, wide-output adjustable power modules are optimized for applications that
require a flexible, high performance module that is small in size. Each of these products are POLA™ compatible.
POLA-compatible products are produced by a number of manufacturers, and offer customers advanced,
nonisolated modules with the same footprint and form factor. POLA parts are also ensured to be interoperable,
thereby, providing customers with second-source availability.
From the basic, Just Plug it In functionality of the 6-A modules, to the 30-A rated feature-rich PTHxx030, these
products were designed to be very flexible, yet simple to use. The features vary with each product. Table 5
provides a quick reference to the features by product series and input bus voltage.
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Soft-Start Power Up
12 V
++
GND GND
3.3 V
PTH12020W
7
10
4
5
62
3
9
Track
VIVO
GNDInhibit
1
Up Dn
Adjust
8
Sense
R
2k
0.1 W, 1%
SET
W
C
330 F
O
m
C
1000 F
I
m
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Table 5. Operating Features by Series and Input Bus Voltage
Series Input Bus IOAdjust On/Off Over- Prebias Auto- Margin Output Thermal
(Trim) Inhibit Current Startup Track™ Up/Down Sense Shutdown
3.3V 6A •••••
PTHxx050 5 V 6 A •••••
12 V 6 A •••••
3.3V/5V 10A ••••• ••
PTHxx060 12 V 8 A ••••• ••
3.3V/5V 15A ••••• ••
PTHxx010 12 V 12 A ••••• ••
5V 8A ••••• •
PTVxx010 12 V 8 A ••••• •
3.3V/5V 22A ••••• •• •
PTHxx020 12 V 18 A ••••• •• •
5V 18A ••••• • •
PTVxx020 12 V 16 A ••••• • •
3.3V/5V 30A ••••• •• •
PTHxx030 12 V 26 A ••••• •• •
For simple point-of-use applications, the PTH12050 (6 A) provides operating features such as an on/off inhibit,
output voltage trim, prebias start-up and overcurrent protection. The PTH12060 (10 A), and PTH12010 (12 A)
include an output voltage sense, and margin up/down controls. Then the higher output current, PTH12020 (18 A)
and PTH12030 (26 A) products incorporate overtemperature shutdown protection.
The PTV12010 and PTV12020 are similar parts offered in a vertical, single in-line pin (SIP) profile, at slightly
lower current ratings.
All of the products referenced in Table 5 include Auto-Track™. This feature was specifically designed to simplify
the task of sequencing the supply voltages in a power system. This and other features are described in the
following sections.
The Auto-Track feature allows the power-up of multiple PTH modules to be directly controlled from the Track pin.
However in a stand-alone configuration, or when the Auto-Track feature is not being used, the Track pin should
be directly connected to the input voltage, VI(see Figure 10).
Figure 10. Power-Up Application Circuit
When the Track pin is connected to the input voltage, the Auto-Track function is permanently disengaged. This
allows the module to power up entirely under the control of its internal soft-start circuitry. When power up is
under soft-start control, the output voltage rises to the set-point at a quicker and more linear rate.
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V (1 V/Div)
O
V (5 V/Div)
I
I (5 A/Div)
I
t - Time = 5 s/Divm
Overcurrent Protection
Overtemperature Protection (OTP)
Output On/Off Inhibit
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Figure 11. Power-Up Waveforms
From the moment a valid input voltage is applied, the soft-start control introduces a short time delay (typically
8 ms–15 ms) before allowing the output voltage to rise. The output then progressively rises to the module’s
setpoint voltage. Figure 11 shows the soft-start power-up characteristic of the 18-A output product
(PTH12020W), operating from a 12-V input bus, and configured for a 3.3-V output. The waveforms were
measured with a 5-A resistive load and the Auto-Track feature disabled. The initial rise in input current when the
input voltage first starts to rise is the charge current drawn by the input capacitors. Power-up is complete within
25 ms.
For protection against load faults, all modules incorporate output overcurrent protection. Applying a load that
exceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, a
module periodically attempts to recover by initiating a soft-start power-up. This is described as a hiccup mode of
operation, whereby, the module continues in a cycle of successive shutdown and power up until the load fault is
removed. During this period, the average current flowing into the fault is significantly reduced. Once the fault is
removed, the module automatically recovers and returns to normal operation.
The PTH12020, PTV12020, and PTH12030 products have overtemperature protection. These products have an
on-board temperature sensor that protects the module's internal circuitry against excessively high temperatures.
A rise in the internal temperature may be the result of a drop in airflow, or a high ambient temperature. If the
internal temperature exceeds the OTP threshold, the module's Inhibit control is internally pulled low. This turns
the output off. The output voltage drops as the external output capacitors are discharged by the load circuit. The
recovery is automatic, and begins with a soft-start power up. It occurs when the sensed temperature decreases
by about 10°C below the trip point.
Note: The overtemperature protection is a last resort mechanism to prevent thermal stress to the regulator.
Operation at or close to the thermal shutdown temperature is not recommended and will reduce the
long-term reliability of the module. Always operate the regulator within the specified Safe Operating Area
(SOA) limits for the worst-case conditions of ambient temperature and airflow.
For applications requiring output voltage on/off control, each series of the PTH family incorporates an output
Inhibit control pin. The inhibit feature can be used wherever there is a requirement for the output voltage from the
regulator to be turned off.
The power modules function normally when the Inhibit pin is left open-circuit, providing a regulated output
whenever a valid source voltage is connected to VIwith respect to GND.
Figure 12 shows the typical application of the inhibit function. Note the discrete transistor (Q1). The Inhibit input
has its own internal pull-up to a potential of 5 V to 13.2 V (see footnotes to specification table). The input is not
compatible with TTL logic devices. An open-collector (or open-drain) discrete transistor is recommended for
control.
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PTH12060W
1
10
4
5
62
3
++
1 = Inhibit
GND
9
V Sense
O
8
Q1
BSS138
7
GND
L
O
A
D
R
2k
0.1 W, 1%
SET
W
C
330 F
O
m
C
560 F
I
m
VIVO
V (2 V/Div)
O
I (2 A/Div)
I
Q1Vds (5 V/Div)
t - Time = 10 s/Divm
Auto-Track™ Function
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Figure 12. Inhibit Control Circuit
Turning on Q1 applies a low voltage to the Inhibit control pin and disables the output of the module. If Q1 is then
turned off, the module executes a soft-start power-up sequence. A regulated output voltage is produced within 25
ms. Figure 13 shows the typical rise in both the output voltage and input current, following the turn off of Q1. The
turn off of Q1 corresponds to the rise in the waveform, Q1 Vds. The waveforms were measured with a 5-A
constant current load.
Figure 13. Power-Up from Inhibit Control
The Auto-Track function is unique to the PTH/PTV family, and is available with all POLA products. Auto-Track
was designed to simplify the amount of circuitry required to make the output voltage from each module power up
and power down in sequence. The sequencing of two or more supply voltages during power up is a common
requirement for complex mixed-signal applications that use dual-voltage VLSI ICs such as the TMS320™ DSP
family, microprocessors, and ASICs.
How Auto-Track™ Works
Auto-Track works by forcing the module output voltage to follow a voltage presented at the Track control pin (1).
This control range is limited to between 0 V and the module set-point voltage. Once the track-pin voltage is
raised above the set-point voltage, the module output remains at its set-point (2). As an example, if the Track pin
of a 2.5-V regulator is at 1 V, the regulated output is 1 V. If the voltage at the Track pin rises to 3 V, the regulated
output does not go higher than 2.5 V.
When under Auto-Track control, the regulated output from the module follows the voltage at its Track pin on a
volt-for-volt basis. By connecting the Track pin of a number of these modules together, the output voltages follow
a common signal during power up and power down. The control signal can be an externally generated master
ramp waveform, or the output voltage from another power supply circuit (3). For convenience, the Track input
incorporates an internal RC-charge circuit. This operates off the module input voltage to produce a suitable rising
waveform at power up.
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PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Typical Application
The basic implementation of Auto-Track allows for simultaneous voltage sequencing of a number of Auto-Track
compliant modules. Connecting the Track inputs of two or more modules forces their track input to follow the
same collective RC-ramp waveform, and allows their power-up sequence to be coordinated from a common
Track control signal. This can be an open-collector (or open-drain) device, such as a power-up reset voltage
supervisor IC. See U3 in Figure 14.
To coordinate a power-up sequence, the Track control must first be pulled to ground potential. This should be
done at or before input power is applied to the modules. The ground signal should be maintained for at least
40 ms after input power has been applied. This brief period gives the modules time to complete their internal
soft-start initialization (4), enabling them to produce an output voltage. A low-cost supply voltage supervisor IC,
that includes a built-in time delay, is an ideal component for automatically controlling the Track inputs at power
up.
Figure 14 shows how the TL7712A supply voltage supervisor IC (U3) can be used to coordinate the sequenced
power up of two 12-V input Auto-Track modules. The output of the TL7712A supervisor becomes active above
an input voltage of 3.6 V, enabling it to assert a ground signal to the common track control well before the input
voltage has reached the module's undervoltage lockout threshold. The ground signal is maintained until
approximately 43 ms after the input voltage has risen above U3's voltage threshold, which is 10.95 V. The 43-ms
time period is controlled by the capacitor C3. The value of 3.3 µF provides sufficient time delay for the modules
to complete their internal soft-start initialization. The output voltage of each module remains at zero until the track
control voltage is allowed to rise. When U3 removes the ground signal, the track control voltage automatically
rises. This causes the output voltage of each module to rise simultaneously with the other modules, until each
reaches its respective set-point voltage.
Figure 15 shows the output voltage waveforms from the circuit of Figure 14 after input voltage is applied to the
circuit. The waveforms, VO1 and VO2, represent the output voltages from the two power modules, U1 (3.3 V) and
U2 (1.8 V), respectively. VTRK,V
O1, and VO2 are shown rising together to produce the desired simultaneous
power-up characteristic.
The same circuit also provides a power-down sequence. When the input voltage falls below U3's voltage
threshold, the ground signal is re-applied to the common track control. This pulls the track inputs to zero volts,
forcing the output of each module to follow, as shown in Figure 16. In order for a simultaneous power-down to
occur, the track inputs must be pulled low before the input voltage has fallen below the modules' undervoltage
lockout. This is an important constraint. Once the modules recognize that a valid input voltage is no longer
present, their outputs can no longer follow the voltage applied at their track input. During a power-down
sequence, the fall in the output voltage from the modules is limited by the maximum output capacitance and the
Auto-Track slew rate. If the Track pin is pulled low at a slew rate greater than 1 V/ms, the discharge of the output
capacitors will induce large currents which could exceed the peak current rating of the module. This will result in
a reduction in the maximum allowable output capacitance as listed in the Electrical Characteristics table. When
controlling the Track pin of the PTH12060W using a voltage supervisor IC, the slew rate is increased, therefore
COmax is reduced to 2200 µF.
Notes on Use of Auto-Track™
1. The Track pin voltage must be allowed to rise above the module set-point voltage before the module
regulates at its adjusted set-point voltage.
2. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with ramp
speeds of up to 1 V/ms.
3. The absolute maximum voltage that may be applied to the Track pin is the input voltage VI.
4. The module cannot follow a voltage at its track control input until it has completed its soft-start initialization.
This takes about 40 ms from the time that a valid voltage has been applied to its input. During this period, it
is recommended that the Track pin be held at ground potential.
5. The Auto-Track function is disabled by connecting the Track pin to the input voltage (VI). When Auto-Track is
disabled, the output voltage rises at a quicker and more linear rate after input power has been applied.
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N = Number of Track pins connected together
10 kΩ
# RTRK = 100 Ω / N
VI = 12 V Vo1 = 3.3 V
RSET1
CO1
+
C
+
PTH12050W
5
63
4
2
Track
VIVO
GND
Inhibit
1
Adjust
TL7712A
VCC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
CT
CREF RRST
Vo2 = 1.8 V
CO2
+
C
+
PTH12060W
7
10
4
5
62
3
98
Track
VIVO
GND
Inhibit
1
Up Dn Sense
Adjust
SET2
U1
U2
U3
RTRK #
2.0 kΩ
11.5 kΩ
I2
0.1 µF3.3 µF
50 Ω
I1
R
t − Time − 20 ms
/
div
VTRK (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
t − Time − 400 µs/div
VTRK (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Figure 14. Sequenced Power Up and Power Down Using Auto-Track
Figure 15. Simultaneous Power Up With Auto-Track Figure 16. Simultaneous Power Down with Auto-Track
Control Control
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Margin Up/Down Controls
D%
RorR=
UD
499 - 99.8 kW(2)
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
The PTH12060, PTH12010, PTH12020, and PTH12030 products incorporate Margin Up and Margin Down
control inputs. These controls allow the output voltage to be momentarily adjusted [1], either up or down, by a
nominal 5%. This provides a convenient method for dynamically testing the operation of the load circuit over its
supply margin or range. It can also be used to verify the function of supply voltage supervisors. The ±5% change
is applied to the adjusted output voltage, as set by the external resistor, RSET at the VOAdjust pin.
The 5% adjustment is made by pulling the appropriate margin control input directly to the GND terminal [2].A
low-leakage, open-drain device, such as an n-channel MOSFET or p-channel JFET is recommended for this
purpose [3]. Adjustments of less than 5% can also be accommodated by adding series resistors to the control
inputs. The value of the resistor can be selected from Table 6, or calculated using Equation 2.
Up/Down Adjust Resistance Calculation
To reduce the margin adjustment to a value less than 5%, series resistors are required (See RDand RUin
Figure 17). For the same amount of adjustment, the resistor value calculated for RUand RDis the same. The
formula is as follows.
Where ∆% = The desired amount of margin adjust in percent.
Notes:
1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they are
activated simultaneously, the affect on the output voltage may not completely cancel, resulting in the
possibility of a slightly higher error in the output voltage set point.
2. The ground reference should be a direct connection to the module GND. This produces a more accurate
adjustment at the load circuit terminals. The transistors Q1 and Q2 should be located close to the regulator.
3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This
includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device
(preferably a discrete MOSFET transistor). The device selected should have low off-state leakage current.
Each input sources 8 µA when grounded, and has an open-circuit voltage of 0.8 V.
Table 6. Margin Up/Down Resistor Values
% Adjust RU/R
D
50.0kΩ
4 24.9 kΩ
3 66.5 kΩ
2 150.0 kΩ
1 397.0 kΩ
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CO
+
CI
VI
GND
Margin Down
L
O
A
D
Q2
+VO
+VO
Q1
+
Margin Up
0V
RDRU
PT H12010W
(Top View)
1
2
10 98 7
6
54
3
GND
R
0.1 W, 1%
SET
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Figure 17. Margin Up/Down Application Schematic
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Prebias Startup Capability
Start up
Period
UVLO
Threshold V (5 V/Div)
I
V (1 V/Div)
O
V 1 (1 V/Div)
O
V 2 (1 V/Div)
O
I 2 (5 A/Div)
O
t - Time = 10 s/Divm
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
The capability to start up into an output prebias condition is now available to all the 12-V input, PTH series of
power modules. (Note that this is a feature enhancement for the many of the W-suffix products) [1].
A prebias startup condition occurs as a result of an external voltage being present at the output of a power
module prior to its output becoming active. This often occurs in complex digital systems when current from
another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another
path might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. A
prebias can cause problems with power modules that incorporate synchronous rectifiers. This is because under
most operating conditions, such modules can sink as well as source output current. The 12-V input PTH modules
all incorporate synchronous rectifiers, but does not sink current during startup, or whenever the Inhibit pin is held
low. Startup includes an initial delay (approximately 8ms–15 ms), followed by the rise of the output voltage under
the control of the module's internal soft-start mechanism; see Figure 18.
Conditions for Prebias Holdoff
In order for the module to allow an output prebias voltage to exist (and not sink current), certain conditions must
be maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenever the output
is allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of the
ground signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track
disabled [2]. To further ensure that the regulator doesn’t sink output current, (even with a ground signal applied to
its Inhibit), the input voltage must always be greater than the applied prebias source. This condition must exist
throughout the power-up sequence [3].
The soft-start period is complete when the output begins rising above the prebias voltage. Once it is complete
the module functions as normal, and sinks current if a voltage higher than the nominal regulation value is applied
to its output.
Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risen
to either the set-point voltage, or the voltage applied at the module's Track control pin, whichever is lowest.
to its output.
Demonstration Circuit
Figure 19 shows the startup waveforms for the demonstration circuit shown in Figure 20. The initial rise in VO2is
the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the
output current from the PTH12010L module (IO2) is negligible until its output voltage rises above the applied
prebias.
Figure 18. PTH12020W Startup Figure 19. Prebias Startup Waveforms
21
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Up Dn Sense
V = 12 V
I
ASIC
VCORE VC CI O
I2
O
PTH12010L
1
10
4
5
62
3
9
Tra ck
GND
Inhibit
7
Vadj
Sense
+
V 1 = 3.3 V
O
V 2 = 1.8 V
O
R1
2kW
R5
10 k0
R4
100 kW
R3
11 k0
R1
130 W
C2
330 Fm
C4
330 Fm
C6
0.68 Fm
C5
0.1 Fm
C3
330 Fm
C1
330 Fm
+
+
PTH12020W
7
10
4
5
62
3
9
Tra ck
VI
VI
VO
VO
GND
Inhibit
1
Adjust
+
TL7702 B
VCC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
+
8
8
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Notes:
1. Output prebias holdoff is an inherent feature to all PTH120x0L and PTV120x0W/L modules. It has now been
incorporated into all modules (including W-suffix modules with part numbers of the form PTH120x0W), with a
production lot date code of 0423 or later.
2. The prebias start-up feature is not compatible with Auto-Track. If the rise in the output is limited by the
voltage applied to the Track control pin, the output sinks current during the period that the track control
voltage is below that of the back-feeding source. For this reason, it is recommended that Auto-Track be
disabled when not being used. This is accomplished by connecting the Track pin to the input voltage, VI. This
raises the Track pin voltage well above the set-point voltage prior to the module’s start up, thereby, defeating
the Auto-Track feature.
3. To further ensure that the regulator's output does not sink current when power is first applied (even with a
ground signal applied to the Inhibit control pin), the input voltage must always be greater than the applied
prebias source. This condition must exist throughout the power-up sequence of the power system.
Figure 20. Application Circuit Demonstrating Prebias Startup
22
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Remote Sense
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
Products with this feature incorporate an output voltage sense pin, VOSense. A remote sense improves the load
regulation performance of the module by allowing it to compensate for any IR voltage drop between its output
and the load. An IR drop is caused by the high output current flowing through the small amount of pin and trace
resistance.
To use this feature simply connect the VOSense pin to the VOnode, close to the load circuit (see data sheet
standard application circuit). If a sense pin is left open-circuit, an internal low-value resistor (15-Ωor less)
connected between the pin and the output node, ensures the output remains in regulation.
With the sense pin connected, the difference between the voltage measured directly between the VOand GND
pins, and that measured from VOSense to GND, is the amount of IR drop being compensated by the regulator.
This should be limited to a maximum of 0.3 V.
Note: The remote sense feature is not designed to compensate for the forward drop of nonlinear or
frequency dependent components that may be placed in series with the converter output. Examples include
OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the remote
sense connection, they are effectively placed inside the regulation control loop, which can adversely affect
the stability of the regulator.
23
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TAPE AND REEL SPECIFICATIONS
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
24
www.ti.com
TRAY SPECIFICATIONS
PTH12060W/L
SLTS217D–MAY 2003–REVISED OCTOBER 2005
25
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PTH12060LAH ACTIVE DIP MOD
ULE EUW 10 36 TBD Call TI Level-1-235C-UNLIM
PTH12060LAS ACTIVE DIP MOD
ULE EUY 10 36 TBD Call TI Level-1-235C-UNLIM
PTH12060LAST ACTIVE DIP MOD
ULE EUY 10 250 TBD Call TI Level-1-235C-UNLIM
PTH12060LAZ ACTIVE DIP MOD
ULE EUY 10 36 Pb-Free
(RoHS) Call TI Level-3-260C-168 HR
PTH12060LAZT ACTIVE DIP MOD
ULE EUY 10 250 Pb-Free
(RoHS) Call TI Level-3-260C-168 HR
PTH12060WAD ACTIVE DIP MOD
ULE EUW 10 36 Pb-Free
(RoHS) Call TI Level-NC-NC-NC
PTH12060WAH ACTIVE DIP MOD
ULE EUW 10 36 TBD Call TI Level-1-235C-UNLIM
PTH12060WAS ACTIVE DIP MOD
ULE EUY 10 36 TBD Call TI Level-1-235C-UNLIM
PTH12060WAST ACTIVE DIP MOD
ULE EUY 10 250 TBD Call TI Level-1-235C-UNLIM
PTH12060WAZ ACTIVE DIP MOD
ULE EUY 10 36 Pb-Free
(RoHS) Call TI Level-3-260C-168 HR
PTH12060WAZT ACTIVE DIP MOD
ULE EUY 10 250 Pb-Free
(RoHS) Call TI Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 26-Oct-2005
Addendum-Page 1
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