S9S12XS64J1MALR - Freescale Semiconductor, Inc.

HCS12

Microcontrollers

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MC9S12XS256

Reference Manual

Covers MC9S12XS Family

MC9S12XS256

MC9S12XS128

MC9S12XS64

MC9S12XS256RMV1

Rev. 1.10

05/2010

To provide the most up-to-date information, the document revision on the World Wide Web is the most

current.Aprintedcopymaybeanearlierrevision.Toverifyyouhavethelatestinformationavailable,refer

to: http://freescale.com/

This document contains information for the complete S12XS Family and thus includes a set of separate

flash (FTMR) module sections to cover the whole family. A full list of family members and options is

included in the appendices.

This document contains information for all constituent modules, with the exception of the CPU. For CPU

information please refer to CPU12XV1 in the CPU12/CPU12X Reference Manual.

Revision History

Date Revision

Level Description

May, 2009 1.08 Removed all KGD references

Corrected Detailed Register Map (FERSTAT)

Corrected statement on VDDA/VDDX protection diodes

September,

2009 1.09

Updated Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1)

Updated Chapter 14 Serial Communication Interface (S12SCIV5)

Updated Chapter 16 Timer Module (TIM16B8CV2)

Updated Chapter 18 256 KByte Flash Module (S12XFTMR256K1V1)

Updated Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1)

Updated Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1)

May, 2010 1.10 Updated Chapter 2 Port Integration Module (S12XSPIMV1)

Updated Chapter 16 Timer Module (TIM16B8CV2)

BDM Alternate clock source deﬁned in device overview

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Freescale Semiconductor 3

Chapter 1 Device Overview S12XS Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Chapter 2 Port Integration Module (S12XSPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Chapter 3 Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . . . . . . . . . .127

Chapter 4 Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Chapter 5 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . . . . . . . . . .167

Chapter 6 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

Chapter 7 Security (S12XS9SECV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) . . . . . . . . . . . . . . .235

Chapter 9 Pierce Oscillator (S12XOSCLCPV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

Chapter 10 Analog-to-Digital Converter (ADC12B16CV1) . . . . . . . . . . . . . . . . . . . . .269

Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) . . . . . .295

Chapter 12 Periodic Interrupt Timer (S12PIT24B4CV1) . . . . . . . . . . . . . . . . . . . . . . .349

Chapter 13 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . . . . . . . . . . .365

Chapter 14 Serial Communication Interface (S12SCIV5). . . . . . . . . . . . . . . . . . . . . .397

Chapter 15 Serial Peripheral Interface (S12SPIV5). . . . . . . . . . . . . . . . . . . . . . . . . . .435

Chapter 16 Timer Module (TIM16B8CV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461

Chapter 17 Voltage Regulator (S12VREGL3V3V1) . . . . . . . . . . . . . . . . . . . . . . . . . . .489

Chapter 18 256 KByte Flash Module (S12XFTMR256K1V1). . . . . . . . . . . . . . . . . . . .507

Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1). . . . . . . . . . . . . . . . . . . .557

Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1). . . . . . . . . . . . . . . . . . . . . .607

Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657

Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698

Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708

Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .712

Appendix E Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713

Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735

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Chapter 1

Device Overview S12XS Family

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.1.5 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

1.1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.1.7 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.2.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

1.3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

1.4.1 Chip Conﬁguration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

1.4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

1.4.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

1.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

1.6.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

1.6.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

1.6.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

1.7 ATD0 Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.7.1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.7.2 ATD0 Channel[17] Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.8 VREG Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.8.1 Temperature Sensor Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.9 BDM Clock Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

1.10 Oscillator Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Chapter 2

Port Integration Module (S12XSPIMV1)

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

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6 Freescale Semiconductor

2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

2.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2.3.7 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2.3.8 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2.3.9 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.3.10 Ports ABEK, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . 79

2.3.11 Ports ABEK Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

2.3.12 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.3.13 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

2.3.14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2.3.15 PIM Reserved Register PIMTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2.3.16 Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

2.3.17 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

2.3.18 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

2.3.19 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.3.20 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.3.21 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.3.22 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2.3.23 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2.3.24 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.3.25 Port T Routing Register (PTTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.3.26 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

2.3.27 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2.3.28 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

2.3.29 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2.3.30 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2.3.31 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.3.32 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2.3.33 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.3.34 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.3.35 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

2.3.36 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

2.3.37 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

2.3.38 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.3.39 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.3.40 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

2.3.41 Module Routing Register (MODRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

2.3.42 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

2.3.43 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2.3.44 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

2.3.45 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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2.3.46 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.3.47 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.3.48 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.3.49 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

2.3.50 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

2.3.51 Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.3.52 Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.3.53 Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

2.3.54 Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

2.3.55 Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

2.3.56 Port H Interrupt Enable Register (PIEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

2.3.57 Port H Interrupt Flag Register (PIFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2.3.58 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2.3.59 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2.3.60 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2.3.61 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.3.62 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.3.63 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.3.64 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.3.65 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

2.3.66 Port AD0 Data Register 0 (PT0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

2.3.67 Port AD0 Data Register 1 (PT1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

2.3.68 Port AD0 Data Direction Register 0 (DDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

2.3.70 Port AD0 Reduced Drive Register 0 (RDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

2.3.71 Port AD0 Reduced Drive Register 1 (RDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

2.3.72 Port AD0 Pull Up Enable Register 0 (PER0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.3.74 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

2.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Chapter 3

Memory Mapping Control (S12XMMCV4)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

3.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

3.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.4.3 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

3.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

3.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Chapter 4

Interrupt (S12XINTV2)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

4.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

4.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

4.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

4.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

4.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Chapter 5

Background Debug Module (S12XBDMV2)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

5.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

5.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Chapter 6

S12X Debug (S12XDBGV3) Module

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

6.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

6.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Chapter 7

Security (S12XS9SECV2)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

7.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

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7.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Chapter 8

S12XE Clocks and Reset Generator (S12XECRGV1)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

8.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

8.2.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

8.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

8.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

8.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

8.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

8.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Chapter 9

Pierce Oscillator (S12XOSCLCPV2)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

9.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 266

9.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

9.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

9.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

9.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

9.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

9.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Chapter 10

Analog-to-Digital Converter (ADC12B16CV1)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

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10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

10.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

10.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

10.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

10.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Chapter 11

Freescale’s Scalable Controller Area Network (S12MSCANV3)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

11.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

11.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

11.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

11.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

11.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

11.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

11.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

11.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

11.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

11.4.3 Identiﬁer Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

11.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

11.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

11.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

11.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

11.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Chapter 12

Periodic Interrupt Timer (S12PIT24B4CV1)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

12.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

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12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

12.3 Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

12.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

12.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

12.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Chapter 13

Pulse-Width Modulator (S12PWM8B8CV1)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

13.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

13.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

13.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Chapter 14

Serial Communication Interface (S12SCIV5)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

14.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

14.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

14.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

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14.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.3.1 Module Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

14.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

14.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

14.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

14.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

14.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

14.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

14.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

14.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

14.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

14.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

14.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

14.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

14.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Chapter 15

Serial Peripheral Interface (S12SPIV5)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

15.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

15.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

15.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

15.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

15.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

15.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

15.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

15.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

15.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

15.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

15.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

15.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

15.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

15.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

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15.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Chapter 16

Timer Module (TIM16B8CV2)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

16.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

16.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 465

16.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 465

16.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 465

16.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 465

16.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 465

16.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 465

16.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 466

16.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 466

16.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

16.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

16.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

16.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

16.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

16.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

16.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

16.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

16.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

16.6.3 Pulse Accumulator Overﬂow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

16.6.4 Timer Overﬂow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Chapter 17

Voltage Regulator (S12VREGL3V3V1)

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

17.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

17.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 492

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17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

17.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 493

17.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

17.2.7 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

17.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin . . . . . . . . . . . . . . 493

17.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

17.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

17.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

17.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

17.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

17.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

17.4.6 HTD - High Temperature Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

17.4.7 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

17.4.8 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

17.4.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

17.4.10Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

17.4.11Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Chapter 18

256 KByte Flash Module (S12XFTMR256K1V1)

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

18.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

18.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

18.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

18.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

18.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

18.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

18.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

18.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 555

18.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 556

18.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

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Chapter 19

128 KByte Flash Module (S12XFTMR128K1V1)

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

19.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

19.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

19.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

19.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

19.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

19.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

19.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

19.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

19.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

19.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 605

19.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 606

19.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Chapter 20

64 KByte Flash Module (S12XFTMR64K1V1)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

20.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

20.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

20.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

20.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

20.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

20.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

20.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 655

20.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 656

20.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

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Appendix A

Electrical Characteristics

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

A.1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

A.2.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

A.3 NVM, Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

A.5 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

A.5.1 Resistive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

A.5.2 Capacitive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

A.5.3 Chip Power-up and Voltage Drops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

A.6 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

A.6.1 Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

A.6.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

A.6.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

A.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

A.8 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

A.8.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

A.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Appendix B

Package Information

B.1 112-pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

B.2 80-Pin QFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

B.3 64-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

Appendix C

PCB Layout Guidelines

C.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

C.1.1 112-Pin LQFP Recommended PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

S12XS Family Reference Manual, Rev. 1.10

18 Freescale Semiconductor

C.1.2 80-Pin QFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

C.1.3 64-Pin LQFP Recommended PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Appendix D

Derivative Differences

D.1 Memory Sizes and Package Options S12XS family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Appendix E

Detailed Register Address Map

E.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Appendix F

Ordering Information

F.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 19

Chapter 1

Device Overview S12XS Family

1.1 Introduction

The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family.

These families provide an easy approach to develop common platforms from low-end to high-end

applications, minimizing the redesign of software and hardware.

Targeted at generic automotive applications and CAN nodes, some typical examples of these applications

are: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, Lighting

Modules and Smart Junction Boxes amongst many others.

The S12XS family retains many of the features of the S12XE family including Error Correction Code

(ECC) on Flash memory, a separate Data-Flash Module for code or data storage, a Frequency Modulated

Locked Loop (IPLL) that improves the EMC performance and a fast ATD converter.

S12XS family delivers 32-bit performance with all the advantages and efﬁciencies of a 16-bit MCU while

retaining the low cost, power consumption, EMC and code-size efﬁciency advantages currently enjoyed

by users of Freescale’s existing 16-bit S12 and S12X MCU families. Like members of other S12X

families, the S12XS family runs 16-bit wide accesses without wait states for all peripherals and memories.

The S12XS family is available in 112-pin LQFP, 80-pin QFP, 64-pin LQFP package options and maintains

a high level of pin compatibility with the S12XE family. In addition to the I/O ports available in each

module, up to 18 further I/O ports are available with interrupt capability allowing Wake-Up from stop or

wait modes.

The peripheral set includes MSCAN, SPI, two SCIs, an 8-channel 24-bit periodic interrupt timer, 8-

channel 16-bit Timer, 8-channel PWM and up to 16- channel 12-bit ATD converter.

Software controlled peripheral-to-port routing enables access to a ﬂexible mix of the peripheral modules

in the lower pin count package options.

1.1.1 Features

Features of the S12XS Family are listed here. Please see Table D-1 for memory options and Table D-2 for

the peripheral features that are available on the different family members.

• 16-bit CPU12X

— Upward compatible with S12 instruction set with the exception of ﬁve Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

20 Freescale Semiconductor

• INT (interrupt module)

— Seven levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— The following inputs can act as Wake-up Interrupts

– IRQ and non-maskable XIRQ

– CAN receive pins

– SCI receive pins

– Depending on the package option up to 20 pins on ports J, H and P conﬁgurable as rising or

falling edge sensitive

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU bus with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-ﬂow or memory access information

• BDM (background debug mode)

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally ﬁltered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Conﬁgurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 64K, 128K and 256K byte Flash

— Flash General Features

– 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

– Erase sector size 1024 bytes

– Automated program and erase algorithm

– Protection scheme to prevent accidental program or erase

– Security option to prevent unauthorized access

– Sense-amp margin level setting for reads

— 4K and 8K byte Data Flash space

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 21

– 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

– Erase sector size 256 bytes

– Automated program and erase algorithm

— 4K, 8K and 12K byte RAM

• 16-channel, 12-bit Analog-to-Digital converter

— 8/10/12 Bit resolution

—3µs, 10-bit single conversion time

— Left or right justiﬁed result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

— Continuous conversion mode

— Multiplexer for 16 analog input channels

— Multiple channel scans

— Pins can also be used as digital I/O

• MSCAN (1 M bit per second, CAN 2.0 A, B software compatible module)

— 1 Mbit per second, CAN 2.0 A, B software compatible module

– Standard and extended data frames

– 0 - 8 bytes data length

– Programmable bit rate up to 1 Mbps

— Five receive buffers with FIFO storage scheme

— Three transmit buffers with internal prioritization

— Flexible identiﬁer acceptance ﬁlter programmable as:

– 2 x 32-bit

– 4 x 16-bit

– 8 x 8-bit

— Wake-up with integrated low pass ﬁlter option

— Loop back for self test

— Listen-only mode to monitor CAN bus

— Bus-off recovery by software intervention or automatically

— 16-bit time stamp of transmitted/received messages

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

22 Freescale Semiconductor

— Time-out interrupt and peripheral triggers

— Start of timers can be aligned

• Up to 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— Programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

• Serial Peripheral Interface Module (SPI)

— Conﬁgurable for 8 or 16-bit data size

— Full-duplex or single-wire bidirectional

— Double-buffered transmit and receive

— Master or Slave mode

— MSB-ﬁrst or LSB-ﬁrst shifting

— Serial clock phase and polarity options

• Two Serial Communication Interfaces (SCI)

— Full-duplex or single wire operation

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

— 13-bit baud rate selection

— Programmable character length

— Programmable polarity for transmitter and receiver

— Receive wakeup on active edge

— Break detect and transmit collision detect supporting LIN

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Internal oscillator driving a down counter

— Trimmable to +/-10% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 91 general-purpose input/output (I/O) pins depending on the package option and 2 input-

only pins

— Hysteresis and conﬁgurable pull up/pull down device on all input pins

— Conﬁgurable drive strength on all output pins

• Package Options

— 112-pin low-proﬁle quad ﬂat-pack (LQFP)

— 80-pin quad ﬂat-pack (QFP)

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 23

— 64-pin low-proﬁle quad ﬂat-pack (LQFP)

• Operating Conditions

— Wide single Supply Voltage range 3.135 V to 5.5 V at full performance

– Separate supply for internal voltage regulator and I/O allow optimized EMC ﬁltering

— 40MHz maximum CPU bus frequency

— Ambient temperature range –40°C to 125°C

— Temperature Options:

– –40°C to 85°C

– –40°C to 105°C

– –40°C to 125°C

1.1.2 Modes of Operation

Operating modes:

• Normal single-chip mode

• Special single-chip mode with active background debug mode

NOTE

This chip family does not support external bus modes.

Low-power modes:

• System stop modes

— Pseudo stop mode

— Full stop mode with fast wake-up option

• System wait mode

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

24 Freescale Semiconductor

1.1.3 Block Diagram

Figure 1-1 shows a block diagram of the S12XS Family devices

Figure 1-1. S12XS Family Block Diagram

4K … 12K bytes RAM

RESET

EXTAL

XTAL

4K … 8K bytes Data Flash

BKGD

VDDR

Periodic Interrupt

Clock Monitor

Single-wire Background

TEST

Voltage Regulator

Debug Module

VDD

ATD

Multilevel

Interrupt Module

PTAD

SCI0

SCK

PS3

PS0

PS1

PS2

MOSI

MISO

SPI0

PTS

AN[15:0] PAD[15:0]

VDDPLL

8/10/12-bit 16-channel

Analog-Digital Converter

16-bit 8 channel

Timer

TIM

Asynchronous Serial IF

8-bit 8 channel

Pulse Width Modulator

PWM

PIT

PB[7:0]

PTB

PA[7:0]

PTA

PK[7,5:0]

PTK

XIRQ

IRQ

ECLK

PE4

PE3

PE2

PE1

PE0

PE7

PE6

PE5

PTE

VDDF

64K … 256K bytes Flash

CPU12X

Amplitude Controlled

Low Power Pierce or

Full drive Pierce

Oscillator

COP Watchdog

PLL with Frequency

Modulation option

Debug Module

4 address breakpoints

2 data breakpoints

512 Byte Trace Buffer

Reset Generation

and Test Entry

RXD

TXD

SCI1

Asynchronous Serial IF

RXD

TXD

PS7

PS4

PS5

PS6

PH3

PH0

PH1

PH2

PTH (Wake-up Int)

PH7

PH4

PH5

PH6

CAN0

PM3

PM0

PM1

PM2

PTM

msCAN 2.0B

RXCAN

TXCAN

PM7

PM4

PM5

PM6

Synchronous Serial IF

Async. Periodic Int.

4ch 24-bit Timer

PTJ (Wake-up Int)

PJ7

PJ6

PT3

PT0

PT1

PT2

PTT

PT7

PT4

PT5

PT6

PP3

PP0

PP1

PP2

PTP (Wake-Up Int)

PP7

PP4

PP5

PP6

PWM3

PWM0

PWM1

PWM2

PWM7

PWM4

PWM5

PWM6

IOC3

IOC0

IOC1

IOC2

IOC7

IOC4

IOC5

IOC6

VDDA

VSSA

VRH

VRL

PJ1

PJ0

XCLKS/ECLKX2

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 25

1.1.4 Device Memory Map

Table 1-1 shows the device register memory map.

Table 1-1. Device Register Memory Map

Address Module Size

(Bytes)

0x0000–0x0009 PIM (port integration module)10

0x000A–0x000B MMC (memory map control) 2

0x000C–0x000D PIM (port integration module) 2

0x000E–0x000F Reserved 2

0x0010–0x0017 MMC (memory map control) 8

0x0018–0x0019 Reserved 2

0x001A–0x001B Device ID register 2

0x001C–0x001F PIM (port integration module) 4

0x0020–0x002F DBG (debug module) 16

0x0030–0x0031 Reserved 2

0x0032–0x0033 PIM (port integration module) 2

0x0034–0x003F ECRG (clock and reset generator) 12

0x0040–0x006F TIM (timer module) 48

0x0070–0x00C7 Reserved 88

0x00C8–0x00CF SCI0 (serial communications interface) 8

0x00D0–0x00D7 SCI1 (serial communications interface) 8

0x00D8–0x00DF SPI0 (serial peripheral interface) 8

0x00E0–0x00FF Reserved 32

0x0100–0x0113 FTMR control registers 20

0x0114–0x011F Reserved 12

0x0120–0x012F INT (interrupt module) 16

0x0130–0x013F Reserved 16

0x0140–0x017F CAN0 64

0x0180–0x023F Reserved 192

0x0240–0x027F PIM (port integration module) 64

0x0280–0x02BF Reserved 64

0x02C0–0x02EF ATD0 (analog-to-digital converter 12 bit 16-channel) 48

0x02F0–0x02F7 Voltage regulator 8

0x02F8–0x02FF Reserved 8

0x0300–0x0327 PWM (pulse-width modulator 8 channels) 40

0x0328–0x033F Reserved 24

0x0340–0x0367 PIT (periodic interrupt timer) 40

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

26 Freescale Semiconductor

NOTE

Reserved register space shown in Table 1-1 is not allocated to any module.

This register space is reserved for future use. Writing to these locations has

no effect. Read access to these locations returns zero.

1.1.5 Address Mapping

Figure 1-2 shows S12XS CPU and BDM local address translation to the global memory map. It indicates

also the location of the internal resources in the memory map.

0x0368–0x07FF Reserved 1176

Table 1-1. Device Register Memory Map (continued)

Address Module Size

(Bytes)

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 27

Figure 1-2. S12XS Family Global Memory Map

0x7F_FFFF

0x00_0000

0x13_FFFF

0x0F_FFFF

DFLASH

RAM

0x00_07FF

RPAGE

PPAGE 0x3F_FFFF

CPU and BDM

Local Memory Map Global Memory Map

FLASH

FLASHSIZE

Unimplemented

FLASH

0xFFFF Vectors

0xC000

0x8000

Unpaged

0x4000

0x1000

0x0000

16K FLASH window

0x2000

0x0800

8K RAM

4K RAM window

2K REGISTERS

16K FLASH

Unpaged

16K FLASH

2K REGISTERS

Unimplemented

RAM

Unimplemented

Space

RAM_LOW

FLASH_LOW

RAMSIZE

DF_HIGH

DFLASH

Resources

Reserved

EPAGE

1K DFLASH window

0x0C00

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

28 Freescale Semiconductor

Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undeﬁned data values.

A CPU access to any unimplemented space causes an illegal address reset.

The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block

sizes are listed in Table 1-2.

Table 1-2. Derivative Dependent Memory Parameters of Device Internal Resources

1.1.6 Detailed Register Map

The detailed register map is listed in the appendix of the reference manual.

1.1.7 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).

The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID

number and Mask Set number.

The Version ID is a word located in a ﬂash information row at 0x40_00E8. The version ID number

indicates a speciﬁc version of internal NVM variables used to patch NVM errata. The default is no patch

(0xFFFF).

Device FLASH_LOW SIZE/

PPAGE1

1Number of 16K pages addressable via PPAGE register

RAM_LOW SIZE/

RPAGE2

2Number of 4K pages addressing the RAM.

DF_HIGH SIZE/

EPAGE3

3Number of 1K pages addressing the DFLASH

S12XS256 0x7C_0000 256K / 16 0x0F_D000 12K / 3 0x10_1FFF 8K / 8

S12XS128 0x7E_0000 128K / 8 0x0F_E000 8K / 2 0x10_1FFF 8K / 8

S12XS64 0x7F_0000 64K / 4 0x0F_F000 4K / 1 0x10_0FFF 4K / 4

Table 1-3. Assigned Part ID Numbers

Device Mask Set Number Part ID1

1The coding is as follows:

Bit 15-12: Major family identiﬁer

Bit 11-6: Minor family identiﬁer

Bit 5-4: Major mask set revision number including FAB transfers

Bit 3-0: Minor — non full — mask set revision

Version ID

MC9S12XS256 0M05M $C0C0 0xFFFF

MC9S12XS128 0M04M $C1C0 0xFFFF

1M04M $C1C1 0xFFFF

MC9S12XS64 0M04M $C1C0 0xFFFF

1M04M $C1C1 0xFFFF

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 29

1.2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal

properties, and detailed discussion of signals. It is built from the signal description sections of the

individual IP blocks on the device.

1.2.1 Device Pinout

The XS family of devices offers pin-compatible packaged devices to assist with system development and

accommodate expansion of the application.

The S12XS family devices are offered in the following package options:

• 112-pin LQFP

• 80-pin QFP

• 64-pin LQFP

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

30 Freescale Semiconductor

Figure 1-3. S12XS Family Pin Assignments 112-pin LQFP Package

VRH

VDDA

PAD15/AN15

PAD07/AN07

PAD14/AN14

PAD06/AN06

PAD13/AN13

PAD05/AN05

PAD12/AN12

PAD04/AN04

PAD11/AN11

PAD03/AN03

PAD10/AN10

PAD02/AN02

PAD09/AN09

PAD01/AN01

PAD08/AN08

PAD00/AN00

VSS2

VDD

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PP4/KWP4/PWM4

PP5/KPW5/PWM5

PP6/KWP6/PWM6

PP7/KWP7/PWM7

PK7

VDDX1

VSSX1

PM0/RXCAN0/RXD1

PM1/TXCAN0/TXD1

PM2/MISO0

PM3/SS0

PM4/MOSI0

PM5/SCK0

PJ6/KWJ6

PJ7/KWJ7

TEST

PS7/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

PM6

PM7

VSSA

VRL

PWM3/KWP3/PP3

TXD1/IOC2/PWM2/KWP2/PP2

IOC1/PWM1/KWP1/PP1

RXD1/IOC0/PWM0/KWP0/PP0

PK3

PK2

PK1

PK0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

VDDF

VSS1

PWM4/IOC4/PT4

VREG_API/PWM5/IOC5/PT5

PWM6/IOC6/PT6

PWM7/IOC7/PT7

PK5

PK4

KWJ1/PJ1

KWJ0/PJ0

MODC/BKGD

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

KWH7/PH7

KWH6/PH6

KWH5/PH5

KWH4/PH4

XCLKS/ECLKX2/PE7

PE6

PE5

ECLK/PE4

VSSX2

VDDX2

RESET

VDDR

VSS3

VSSPLL

EXTAL

XTAL

VDDPLL

KWH3/PH3

KWH2/PH2

KWH1/PH1

KWH0/PH0

PE3

PE2

IRQ/PE1

XIRQ/PE0

PinsshowninBOLDarenot

available on the 80 QFP

package

S12XS Family

112LQFP

112

111

110

109

108

107

106

105

104

103

102

101

100

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 31

Figure 1-4. S12XS Family Pin Assignments 80-pin QFP Package

VRH

VDDA

PAD07/AN07

PAD06/AN06

PAD05/AN05

PAD04/AN04

PAD03/AN03

PAD02/AN02

PAD01/AN01

PAD00/AN00

VSS2

VDD

PA7

PA6

PA5

PA4

PA 3

PA 2

PA 1

PA 0

PB5

PB6

PB7

XCLKS/ECLKX2/PE7

PE6

PE5

ECLK/PE5

VSSX2

VDDX2

RESET

VDDR

VSS3

VSSPLL

EXTAL

XTAL

VDDPLL

PE3

PE2

IRQ/PE1

XIRQ/PE0

S12XS Family

80QFP

PWM3/KWP3/PP3

TXD1/IOC2/PWM2/KWP2/PP2

IOC1/PWM1/KWP1/PP1

RXD1/IOC0/PWM0/KWP0/PP0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

VDDF

VSS1

PWM4/IOC4/PT4

VREG_API/PWM5/IOC5/PT5

PWM6/IOC6/PT6

PWM7/IOC7/PT7

MODC/BKGD

PB0

PB1

PB2

PB3

PB4

PP4/KWP4/PWM4

PP5/KPW5/PWM5

PP7/KPW7/PWM7

VDDX1

VSSX1

PM0/RXCAN0/RXD1

PM1/TXCAN0/TXD1

PM2/MISO0

PM3/SS0

PM4/MOSI0

PM5/SCK0

PJ6/KWJ6

PJ7/KWJ7

TEST

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VRL

Pins shown in BOLD are

not available on the 64

QFP package

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

32 Freescale Semiconductor

Figure 1-5. S12XS Family Pin Assignments 64-pin LQFP Package

S12XS Family

64LQFP

VRH

VDDA

PAD07/AN07

PAD06/AN06

PAD05/AN05

PAD04/AN04

PAD03/AN03

PAD02/AN02

PAD01/AN01

PAD00/AN00

VSS2

VDD

PA3

PA2

PA1

PA0

PB5

PB6

PB7

XCLKS/ECLKX2/PE7

ECLK/PE4

VSSX2

VDDX2

RESET

VDDR

VSS3

VSSPLL

EXTAL

XTAL

VDDPLL

IRQ/PE1

XIRQ/PE0

PWM3/KWP3/PP3

TXD1/IOC2/PWM2/KWP2/PP2

IOC1/PWM1/KWP1/PP1

RXD1/IOC0/PWM0/KWP0/PP0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

VDDF

VSS1

PWM4/IOC4/PT4

VREG_API/PWM5/IOC5/PT5

PWM6/IOC6/PT6

PWM7/IOC7/PT7

MODC/BKGD

PB0

PP5/KPW5/PWM5

PP7/KWP7/PWM7

VDDX1

VSSX1

PM0/RXCAN0/RXD1

PM1/TXCAN0/TXD1

PM2/MISO0

PM3/SS0

PM4/MOSI0

PM5/SCK0

TEST

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA/VRL

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 33

1.2.2 Pin Assignment Overview

Table 1-4 provides a summary of which ports are available for each package option. Routing of pin

functions is summarized in Table 1-5.

Table 1-4. Port Availability by Package Option

Port 112 LQFP 80 QFP 64 LQFP

Port AD/ADC Channels 16/16 8/8 8/8

Port A pins 8 8 4

Port B pins 8 8 4

Port E pins inc. IRQ/XIRQ input only 8 8 4

Port H 800

Port J 420

Port K 700

Port M 866

Port P 876

Port S 844

Port T 888

Sum of Ports 91 59 44

I/O Power Pairs VDDX/VSSX 2/2 2/2 2/2

Table 1-5. Peripheral - Port Routing Options1

1“X” denotes reset condition, “O” denotes a possible rerouting

under software control

SCI1 SPI0 PWM TIM

PM[1:0] O

PM[5:2] O

PP[2,0] O

PP[2:0] O

PP[7:4] X

PS[3:2] X

PS[7:4] X

PT[2:0] X

PT[7:4] O

S12XS Family Reference Manual, Rev. 1.10

34 Freescale Semiconductor

Device Overview S12XS Family

Table 1-6 provides a pin out summary listing the availability and functionality of individual pins for each package option.

Table 1-6. Pin-Out Summary1

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

1 1 1 PP3 KWP3 PWM3 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM channel

2 2 2 PP2 KWP2 PWM2 IOC2 TXD1 VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM/TIMchannel,TXD

of SCI1

3 3 3 PP1 KWP1 PWM1 IOC1 — VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM/TIM channel

4 4 4 PP0 KWP0 PWM0 IOC0 RXD1 VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM/TIM channel,

RXD of SCI1

5 - - PK3 — — — — VDDX PUCR Up Port K I/O

6 - - PK2 — — — — VDDX PUCR Up Port K I/O

7 - - PK1 — — — — VDDX PUCR Up Port K I/O

8 - - PK0 — — — — VDDX PUCR Up Port K I/O

9 5 5 PT0 IOC0 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel

10 6 6 PT1 IOC1 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel

11 7 7 PT2 IOC2 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel

12 8 8 PT3 IOC3 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel

13 9 9 VDDF — — — — — — — —

14 10 10 VSS1 — — — — — — — —

15 11 11 PT4 IOC4 PWM4 — — VDDX PERT/PPST Disabled Port T I/O, PWM/TIM

channel

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 35

16 12 12 PT5 IOC5 PWM5 VREG_

API —V

DDX PERT/PPST Disabled Port T I/O, PWM/TIM

channel, API output

17 13 13 PT6 IOC6 PWM6 — — VDDX PERT/PPST Disabled Port T I/O, channel of

PWM/TIM

18 14 14 PT7 IOC7 PWM7 — — VDDX PERT/PPST Disabled Port T I/O, channel of

PWM/TIM

19 - - PK5 — — — — VDDX PUCR Up Port K I/O

20 - - PK4 — — — — VDDX PUCR Up Port K I/O

21 - - PJ1 KWJ1 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt

22 - - PJ0 KWJ0 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt

23 15 15 BKGD MODC — — — VDDX Always on Up Background debug

24 16 16 PB0 — — — — VDDX PUCR Disabled Port B I/O

25 17 - PB1 — — — — VDDX PUCR Disabled Port B I/O

26 18 - PB2 — — — — VDDX PUCR Disabled Port B I/O

27 19 - PB3 — — — — VDDX PUCR Disabled Port B I/O

28 20 - PB4 — — — — VDDX PUCR Disabled Port B I/O

29 21 17 PB5 — — — — VDDX PUCR Disabled Port B I/O

30 22 18 PB6 — — — — VDDX PUCR Disabled Port B I/O

31 23 19 PB7 — — — — VDDX PUCR Disabled Port B I/O

32 - - PH7 KWH7 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

33 - - PH6 KWH6 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

34 - - PH5 KWH5 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

35 - - PH4 KWH4 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

Table 1-6. Pin-Out Summary1 (continued)

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

S12XS Family Reference Manual, Rev. 1.10

36 Freescale Semiconductor

Device Overview S12XS Family

36 24 20 PE7 XCLKS ECLKX2 — — VDDX PUCR Up Port E I/O, system clock

output, clock select

input

37 25 - PE6 — — — — VDDX While RESET pin

is low: down2Port E I/O

38 26 - PE5 — — — — VDDX While RESET pin

is low: down2Port E I/O

39 27 21 PE4 ECLK — — — VDDX PUCR Up Port E I/O, bus clock

output

40 28 22 VSSX2 — — — — — — — —

41 29 23 VDDX2 — — — — — — — —

42 30 24 RESET — — — — VDDX PULLUP External reset

43 31 25 VDDR — — — — — — — —

44 32 26 VSS3 — — — — — — — —

45 33 27 VSSPLL — — — — — — — —

46 34 28 EXTAL — — — — VDDPLL NA NA Oscillator pin

47 35 29 XTAL — — — — VDDPLL NA NA Oscillator pin

48 36 30 VDDPLL — — — — — — — —

49 - - PH3 KWH3 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

50 - - PH2 KWH2 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

51 - - PH1 KWH1 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

52 - - PH0 KWH0 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt

53 37 - PE3 — — — — VDDX PUCR Up Port E I/O

54 38 - PE2 — — — — VDDX PUCR Up Port E I/O

Table 1-6. Pin-Out Summary1 (continued)

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 37

55 39 31 PE1 IRQ — — — VDDX PUCR Up Port E Input, maskable

interrupt

56 40 32 PE0 XIRQ — — — VDDX PUCR Up Port E Input, non-

maskable interrupt

57 41 33 PA0 — — — — VDDX PUCR Disabled Port A I/O

58 42 34 PA1 — — — — VDDX PUCR Disabled Port A I/O

59 43 35 PA2 — — — — VDDX PUCR Disabled Port A I/O

60 44 36 PA3 — — — — VDDX PUCR Disabled Port A I/O

61 45 - PA4 — — — — VDDX PUCR Disabled Port A I/O

62 46 - PA5 — — — — VDDX PUCR Disabled Port A I/O

63 47 - PA6 — — — — VDDX PUCR Disabled Port A I/O

64 48 - PA7 — — — — VDDX PUCR Disabled Port A I/O

65 49 37 VDD — — — — — — — —

66 50 38 VSS2 — — — — — — — —

67 51 39 PAD00 AN00 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

68 - - PAD08 AN08 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

69 52 40 PAD01 AN01 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

70 - - PAD09 AN09 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

71 53 41 PAD02 AN02 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

Table 1-6. Pin-Out Summary1 (continued)

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

S12XS Family Reference Manual, Rev. 1.10

38 Freescale Semiconductor

Device Overview S12XS Family

72 - - PAD10 AN10 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

73 54 42 PAD03 AN03 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

74 - - PAD11 AN11 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

75 55 43 PAD04 AN04 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

76 - - PAD12 AN12 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

77 56 44 PAD05 AN05 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

78 - - PAD13 AN13 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

79 57 45 PAD06 AN06 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

80 - - PAD14 AN14 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

81 58 46 PAD07 AN07 — — — VDDA PER1AD Disabled Port AD I/O,

analog input of ATD

82 - - PAD15 AN15 — — — VDDA PER0AD Disabled Port AD I/O,

analog input of ATD

83 59 47 VDDA — — — — — — — —

84 60 48 VRH — — — — — — — —

85 61 49 VRL3————— — — —

86 62 49 VSSA — — — — — — — —

Table 1-6. Pin-Out Summary1 (continued)

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 39

87 - - PM7 — — — — VDDX PERM/PPSM Disabled Port M I/O

88 - - PM6 — — — — VDDX PERM/PPSM Disabled Port M I/O

89 63 50 PS0 RXD0 — — — VDDX PERS/PPSS Up Port S I/O, RXD of SCI0

90 64 51 PS1 TXD0 — — — VDDX PERS/PPSS Up Port S I/O, TXD of SCI0

91 65 52 PS2 RXD1 — — — VDDX PERS/PPSS Up Port S I/O, RXD of SCI1

92 66 53 PS3 TXD1 — — — VDDX PERS/PPSS Up Port S I/O, TXD of SCI1

93 - - PS4 MISO0 — — — VDDX PERS/PPSS Up PortS I/O,MISO of SPI0

94 - - PS5 MOSI0 — — — VDDX PERS/PPSS Up PortS I/O,MOSI of SPI0

95 - - PS6 SCK0 — — — VDDX PERS/PPSS Up Port S I/O, SCK of SPI0

96 - - PS7 SS0 — — — VDDX PERS/PPSS Up Port S I/O, SS of SPI0

97 67 54 TEST — — — — N.A. RESET pin DOWN Test input

98 68 - PJ7 KWJ7 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt

99 69 - PJ6 KWJ6 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt

100 70 55 PM5 SCK0 — — — VDDX PERM/PPSM Disabled Port M I/O, SCK of SPI0

101 71 56 PM4 MOSI0 — — — VDDX PERM/PPSM Disabled Port M I/O, MOSI of

SPI0

102 72 57 PM3 SS0 — — — VDDX PERM/PPSM Disabled Port M I/O, SS of SPI0

103 73 58 PM2 MISO0 — — — VDDX PERM/PPSM Disabled Port M I/O, MISO of

SPI0

104 74 59 PM1 TXCAN0 TXD1 — — VDDX PERM/PPSM Disabled Port M I/O, TX of CAN0,

TXD of SCI1

105 75 60 PM0 RXCAN0 RXD1 — — VDDX PERM/PPSM Disabled Port M I/O, RX of CAN0,

RXD of SCI1

Table 1-6. Pin-Out Summary1 (continued)

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

S12XS Family Reference Manual, Rev. 1.10

40 Freescale Semiconductor

Device Overview S12XS Family

106 76 61 VSSX1 — — — — — — — —

107 77 62 VDDX1 — — — — — — — —

108 - - PK7 — — — — VDDX PUCR Up Port K I/O

109 78 63 PP7 KWP7 PWM7 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM channel

110 - - PP6 KWP6 PWM6 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM channel

111 79 64 PP5 KWP5 PWM5 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM channel

112 80 - PP4 KWP4 PWM4 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,

PWM channel

1Table shows a superset of pin functions. Not all functions are available on all derivatives

2For compatibility to XE family

3VRL and VSSA share single pin on 64 package option

Table 1-6. Pin-Out Summary1 (continued)

Package Terminal Function Power

Supply

Internal Pull

Resistor Description

LQFP

112 QFP

80 LQFP

64 Pin 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 41

1.2.3 Detailed Signal Descriptions

NOTE

The pin list of the largest package version of each S12XS Family derivative

gives the complete of interface signals that also exist on smaller package

options, although some of them are not bonded out. For devices assembled

in smaller packages all non-bonded out pins should be conﬁgured as outputs

after reset in order to avoid current drawn from ﬂoating inputs. Refer to

Table 1-6 for affected pins.

1.2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the EXTAL input frequency. XTAL is the oscillator output.

1.2.3.2 RESET — External Reset Pin

The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a

known start-up state. As an output it is driven low to indicate when any internal MCU reset source triggers.

The RESET pin has an internal pull-up device.

1.2.3.3 TEST — Test Pin

This input only pin is reserved for factory test. This pin has a pull-down device.

NOTE

The TEST pin must be tied to VSS in all applications.

1.2.3.4 BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It

is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit

at the rising edge of RESET. The BKGD pin has an internal pull-up device.

1.2.3.5 PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD0

PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital

converter ATD0.

1.2.3.6 PA[7:0] — Port A I/O Pins

PA[7:0] are general-purpose input or output pins.

1.2.3.7 PB[7:0] — Port B I/O Pins

PB[7:0] are general-purpose input or output pins.

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

42 Freescale Semiconductor

1.2.3.8 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7

PE7 is a general-purpose input or output pin. ECLKX2 is a clock output of twice the internal bus

frequency. The XCLKS is an input signal which controls whether a crystal in combination with the internal

loop controlled Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is

used (refer to Section 1.10 Oscillator Conﬁguration). An internal pull-up is enabled during reset.

1.2.3.9 PE[6:5] — Port E I/O Pin 6-5

PE[6:5] are a general-purpose input or output pins.

1.2.3.10 PE4 / ECLK — Port E I/O Pin 4

PE4 is a general-purpose input or output pin. It can be conﬁgured to output the internal bus clock ECLK.

ECLK can be used as a timing reference. The ECLK output has a programmable prescaler.

1.2.3.11 PE[3:2] — Port E I/O Pin 3

PE[3:2] are a general-purpose input or output pins.

1.2.3.12 PE1 / IRQ — Port E Input Pin 1

PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of

applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.

1.2.3.13 PE0 / XIRQ — Port E Input Pin 0

PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of

applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ

interrupt is level sensitive and active low. As XIRQ is level sensitive, while this pin is low the MCU will

not enter STOP mode.

1.2.3.14 PH[7:0] / KWH[7:0] — Port H I/O Pins

PH[7:0] are a general-purpose input or output pins. They can be conﬁgured as keypad wakeup inputs.

1.2.3.15 PJ[7:6] / KWJ[7:6] — PORT J I/O Pins 7-6

PJ[7:6] are a general-purpose input or output pins. They can be conﬁgured as keypad wakeup inputs.

1.2.3.16 PJ[1:0] / KWJ[1:0] — PORT J I/O Pins 1-0

PJ[1:0] are a general-purpose input or output pins. They can be conﬁgured as keypad wakeup inputs.

1.2.3.17 PK[7,5:0] — Port K I/O Pins 7 and 5-0

PK[7,5:0] are a general-purpose input or output pins.

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 43

1.2.3.18 PM[7:6] — Port M I/O Pins 7-6

PM[7:6] are a general-purpose input or output pins.

1.2.3.19 PM5 / SCK0 — Port M I/O Pin 5

PM5 is a general-purpose input or output pin. It can be conﬁgured as the serial clock pin SCK of the serial

peripheral interface 0 (SPI0).

1.2.3.20 PM4 / MOSI0 — Port M I/O Pin 4

PM4 is a general-purpose input or output pin. It can be conﬁgured as the master output (during master

mode) or slave input pin (during slave mode) MOSI for the serial peripheral interface 0 (SPI0).

1.2.3.21 PM3 / SS0 — Port M I/O Pin 3

PM3 is a general-purpose input or output pin. It can be conﬁgured as the slave select pin SS of the serial

peripheral interface 0 (SPI0).

1.2.3.22 PM2 / MISO0 — Port M I/O Pin 2

PM2 is a general-purpose input or output pin. It can be conﬁgured as the master input (during master

mode) or slave output pin (during slave mode) MISO for the serial peripheral interface 0 (SPI0).

1.2.3.23 PM1 / TXCAN0 / TXD1 — Port M I/O Pin 1

PM1 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXCAN of the

scalable controller area network controller 0 (CAN0). It can be conﬁgured as the transmit pin TXD of

serial communication interface 1 (SCI1).

1.2.3.24 PM0 / RXCAN0 / RXD1 — Port M I/O Pin 0

PM0 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXCAN of the

scalable controller area network controller 0 (CAN0). It can be conﬁgured as the receive pin RXD of serial

communication interface 1 (SCI1).

1.2.3.25 PP7 / KWP7 / PWM7 — Port P I/O Pin 7

PP7 is a general-purpose input or output pin. It can be conﬁgured as keypad wakeup input. It can be

conﬁgured as pulse width modulator (PWM) channel 7 output or emergency shutdown input.

1.2.3.26 PP[6:3] / KWP[6:3] / PWM[6:3] — Port P I/O Pins 6-3

PP[6:3] are a general-purpose input or output pins. They can be conﬁgured as keypad wakeup inputs. They

can be conﬁgured as pulse width modulator (PWM) channel 6-3 output.

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

44 Freescale Semiconductor

1.2.3.27 PP2 / KWP2 / PWM2 / TXD1 / IOC2 — Port P I/O Pin 2

PP2 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be

conﬁgured as pulse width modulator (PWM) channel 2 output, TIM channel 2 or as the transmit pin TXD

of serial communication interface 1 (SCI1).

1.2.3.28 PP1 / KWP1 / PWM1 / IOC1 — Port P I/O Pin 1

PP1 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be

conﬁgured as pulse width modulator (PWM) channel 1 output, TIM channel 1.

1.2.3.29 PP0 / KWP0 / PWM0 / RXD1 / IOC0 — Port P I/O Pin 0

PP0 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be

conﬁgured as pulse width modulator (PWM) channel 0 output, TIM channel 0 or as the receive pin RXD

of serial communication interface 1 (SCI1).

1.2.3.30 PS7 / SS0 — Port S I/O Pin 7

PS7 is a general-purpose input or output pin. It can be conﬁgured as the slave select pin SS of the serial

peripheral interface 0 (SPI0).

1.2.3.31 PS6 / SCK0 — Port S I/O Pin 6

PS6 is a general-purpose input or output pin. It can be conﬁgured as the serial clock pin SCK of the serial

peripheral interface 0 (SPI0).

1.2.3.32 PS5 / MOSI0 — Port S I/O Pin 5

PS5 is a general-purpose input or output pin. It can be conﬁgured as master output (during master mode)

or slave input pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).

1.2.3.33 PS4 / MISO0 — Port S I/O Pin 4

PS4 is a general-purpose input or output pin. It can be conﬁgured as master input (during master mode) or

slave output pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).

1.2.3.34 PS3 / TXD1 — Port S I/O Pin 3

PS3 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial

communication interface 1 (SCI1).

1.2.3.35 PS2 / RXD1 — Port S I/O Pin 2

PS2 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXD of serial

communication interface 1 (SCI1).

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 45

1.2.3.36 PS1 / TXD0 — Port S I/O Pin 1

PS1 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial

communication interface 0 (SCI0).

1.2.3.37 PS0 / RXD0 — Port S I/O Pin 0

PS0 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXD of serial

communication interface 0 (SCI0).

1.2.3.38 PT[7:6] / IOC[7:6] / PWM[7:6] — Port T I/O Pins 7-6

PT[7:6] are general-purpose input or output pins. They can be conﬁgured as timer (TIM) channel 7-6 or

pulse width modulator (PWM) outputs 7-6

1.2.3.39 PT5 / IOC5 / VREG_API — Port T I/O Pin 5

PT[5] is a general-purpose input or output pin. It can be conﬁgured as timer (TIM) channel 5, pulse width

modulator (PWM) output 5 or as the VREG_API signal output.

1.2.3.40 PT4 / IOC4 / PWM4 — Port T I/O Pin 4

PT4 is a general-purpose input or output pin. It can be conﬁgured as timer (TIM) channel 4 or pulse width

modulator (PWM) output 4.

1.2.3.41 PT[3:0] / IOC[3:0] — Port T I/O Pin [3:0]

PT[3:0] are a general-purpose input or output pins. They can be conﬁgured as timer (TIM) channels 3-0.

1.2.4 Power Supply Pins

S12XS Family power and ground pins are described below.

Because fast signal transitions place high, short-duration current demands on the power supply, use bypass

capacitors with high-frequency characteristics and place them as close to the MCU as possible.

NOTE

All VSS pins must be connected together in the application.

1.2.4.1 VDDX[2:1], VSSX[2:1] — Power and Ground Pins for I/O Drivers

External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are

loaded. All VDDX pins are connected together internally. All VSSX pins are connected together internally.

1.2.4.2 VDDR — Power Pin for Internal Voltage Regulator

Power supply input to the internal voltage regulator.

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S12XS Family Reference Manual, Rev. 1.10

46 Freescale Semiconductor

1.2.4.3 VDD, VSS2, VSS3 — Core Power Pins

The voltage supply of nominally 1.8 V is derived from the internal voltage regulator. The return current

path is through the VSS2 and VSS3 pins. No static external loading of these pins is permitted.

1.2.4.4 VDDF, VSS1 — NVM Power Pins

The voltage supply of nominally 2.8 V is derived from the internal voltage regulator. The return current

path is through the VSS1 pin. No static external loading of these pins is permitted.

1.2.4.5 VDDA, VSSA — Power Supply Pins for ATD and Voltage Regulator

These are the power supply and ground input pins for the analog-to-digital converters and the voltage

regulator.

1.2.4.6 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog-to-digital converter.

1.2.4.7 VDDPLL, VSSPLL — Power Supply Pins for PLL

These pins provide operating voltage and ground for the oscillator and the phased-locked loop. The voltage

supply of nominally 1.8 V is derived from the internal voltage regulator. This allows the supply voltage to

the oscillator and PLL to be bypassed independently. This voltage is generated by the internal voltage

regulator. No static external loading of these pins is permitted.

Table 1-7. Power and Ground Connection Summary

Mnemonic Nominal

Voltage Description

VDDR 5.0 V External power supply to internal voltage

regulator

VDDX[2:1] 5.0 V External power and ground, supply to pin

drivers

VSSX[2:1] 0 V

VDDA 5.0 V Operating voltage and ground for the

analog-to-digital converters and the

reference for the internal voltage regulator,

allows the supply voltage to the A/D to be

bypassed independently.

VSSA 0 V

VRL 0 V Referencevoltagesfor the analog-to-digital

converter.

VRH 5.0 V

VDD 1.8 V Internal power and ground generated by

internal regulator for the internal core.

VSS1, VSS2,

VSS3 0 V

VDDF 2.8 V Internal power and ground generated by

internal regulator for the internal NVM.

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S12XS Family Reference Manual, Rev. 1.10

47 Freescale Semiconductor

VDDPLL 1.8 V Provides operating voltage and ground for

the phased-locked loop. This allows the

supply voltage to the PLL to be bypassed

independently. Internal power and ground

generated by internal regulator.

VSSPLL 0 V

Table 1-7. Power and Ground Connection Summary

Mnemonic Nominal

Voltage Description

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

48 Freescale Semiconductor

1.3 System Clock Description

The clock and reset generator module (CRG) provides the internal clock signals for the core and all

peripheral modules. Figure 1-6 shows the clock connections from the CRG to all modules.

Consult the S12XECRG section for details on clock generation.

NOTE

The XS family uses the XE family clock and reset generator module.

Therefore all CRG references are related to S12XECRG.

Figure 1-6. Clock Connections

The system clock can be supplied in several ways enabling a range of system operating frequencies to be

supported:

• The on-chip phase locked loop (PLL)

• the PLL self clocking

• the oscillator

SCI0 . . SCI 1

SPI0

ATD0

CAN0

CRG

Bus Clock

EXTAL

XTAL

Core Clock

Oscillator Clock

RAM S12X FLASH

PIT

TIM

PIM

PWM

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 49

The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and

bus clock. As shown in Figure 1-6, these system clocks are used throughout the MCU to drive the core,

the memories, and the peripherals.

The program Flash memory is supplied by the bus clock and the oscillator clock. The oscillator clock is

used as a time base to derive the program and erase times for the NVMs.

The CAN modules may be conﬁgured to have their clock sources derived either from the bus clock or

directly from the oscillator clock. This allows the user to select its clock based on the required jitter

performance.

In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the

output of the oscillator. The clock monitor can be conﬁgured to invoke the PLL self-clocking mode or to

generate a system reset if it is allowed to time out as a result of no oscillator clock being present.

In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more

accurate check of the clock. The clock quality checker counts a predetermined number of clock edges

within a deﬁned time window to insure that the clock is running. The checker can be invoked following

speciﬁc events such as on wake-up or clock monitor failure.

1.4 Modes of Operation

The MCU can operate in different modes. These are described in 1.4.1 Chip Conﬁguration Summary.

The MCU can operate in different power modes to facilitate power saving when full system performance

is not required. These are described in 1.4.2 Power Modes.

Some modules feature a software programmable option to freeze the module status whilst the background

debug module is active to facilitate debugging. This is described in 1.4.3 Freeze Mode.

1.4.1 Chip Conﬁguration Summary

The different modes and the security state of the MCU affect the debug features (enabled or disabled).

The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-

8). The MODC bit in the MODE register shows the current operating mode and provides limited mode

switching during operation. The state of the MODC signal is latched into this bit on the rising edge of

RESET.

1.4.1.1 Normal Single-Chip Mode

This mode is intended for normal device operation. The opcode from the on-chip memory is being

executed after reset (requires the reset vector to be programmed correctly). The processor program is

executed from internal memory.

Table 1-8. Chip Modes

Chip Modes MODC

Normal single chip 1

Special single chip 0

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S12XS Family Reference Manual, Rev. 1.10

50 Freescale Semiconductor

1.4.1.2 Special Single-Chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The

background debug module BDM is active in this mode. The CPU executes a monitor program located in

an on-chip ROM. BDM ﬁrmware waits for additional serial commands through the BKGD pin.

1.4.2 Power Modes

The MCU features two main low-power modes. Consult the respective section for module speciﬁc

behavior in system stop, system pseudo stop, and system wait mode. An important source of information

about the clock system is the Clock and Reset Generator section (CRG).

1.4.2.1 System Stop Modes

The system stop modes are entered if the CPU executes the STOP instruction unless an NVM command

is active. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop

mode or full stop mode. Please refer to CRG section. Asserting RESET, XIRQ, IRQ or any other interrupt

that is not masked exits system stop modes. System stop modes can be exited by CPU activity, depending

on the conﬁguration of the interrupt request.

If the CPU executes the STOP instruction whilst an NVM command is being processed, then the system

clocks continue running until NVM activity is completed. If a non-masked interrupt occurs within this time

then the system does not effectively enter stop mode although the STOP instruction has been executed.

1.4.2.2 Full Stop Mode

The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers

remain frozen. The Autonomous Periodic Interrupt (API) and ATD module may be enabled to self wake

the device. A Fast wake up mode is available to allow the device to wake from Full Stop mode immediately

on the PLL internal clock without starting the oscillator clock.

1.4.2.3 Pseudo Stop Mode

In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt

(RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This

mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed

wake up time from this mode is signiﬁcantly shorter.

1.4.2.4 Wait Mode

This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute

instructions. The internal CPU clock is switched off. All peripherals can be active in system wait mode.

For further power consumption the peripherals can individually turn off their local clocks. Asserting

RESET, XIRQ, IRQ or any other interrupt that is not masked ends system wait mode.

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 51

1.4.2.5 Run Mode

Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save

power.

1.4.3 Freeze Mode

The timer module, pulse width modulator, analog-to-digital converters, and the periodic interrupt timer

provide a software programmable option to freeze the module status when the background debug module

is active. This is useful when debugging application software. For detailed description of the behavior of

the ATD, TIM, PWM, and PIT when the background debug module is active consult the corresponding

section.

1.5 Security

The MCU security mechanism prevents unauthorized access to the Flash memory. For a detailed

description of the security features refer to the S12XS9SEC section.

1.6 Resets and Interrupts

Consult the CPU12/CPU12X Reference Manual and the S12XINT section for information on exception

processing.

NOTE

When referring to the S12XINT section please be aware that the XS family

neither features an XGATE nor an MPU module.

1.6.1 Resets

Resets are explained in detail in the Clock Reset Generator (S12XECRG) section.

Table 1-9. Reset Sources and Vector Locations

1.6.2 Vectors

Table 1-10 lists all interrupt sources and vectors in the default order of priority. The interrupt module

(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each

Vector Address Reset Source CCR

Mask Local Enable

$FFFE Power-On Reset (POR) None None

$FFFE Low Voltage Reset (LVR) None None

$FFFE External pin RESET None None

$FFFE Illegal Address Reset None None

$FFFC Clock monitor reset None PLLCTL (CME, SCME)

$FFFA COP watchdog reset None COP rate select

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S12XS Family Reference Manual, Rev. 1.10

52 Freescale Semiconductor

I-bit maskable service request is a conﬁguration register. It selects if the service request is enabled and the

service request priority level.

Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)

Vector Address1Interrupt Source CCR

Mask Local Enable STOP

Wake up WAIT

Wake up

Vector base + $F8 Unimplemented instruction trap None None — —

Vector base+ $F6 SWI None None — —

Vector base+ $F4 XIRQ X Bit None Yes Yes

Vector base+ $F2 IRQ I bit IRQCR (IRQEN) Yes Yes

Vector base+ $F0 Real time interrupt I bit CRGINT (RTIE) Refer to CRG

interrupt section

Vector base+ $EE TIM timer channel 0 I bit TIE (C0I) No Yes

Vector base + $EC TIM timer channel 1 I bit TIE (C1I) No Yes

Vector base+ $EA TIM timer channel 2 I bit TIE (C2I) No Yes

Vector base+ $E8 TIM timer channel 3 I bit TIE (C3I) No Yes

Vector base+ $E6 TIM timer channel 4 I bit TIE (C4I) No Yes

Vector base+ $E4 TIM timer channel 5 I bit TIE (C5I) No Yes

Vector base + $E2 TIM timer channel 6 I bit TIE (C6I) No Yes

Vector base+ $E0 TIM timer channel 7 I bit TIE (C7I) No Yes

Vector base+ $DE TIM timer overﬂow I bit TSRC2 (TOF) No Yes

Vector base+ $DC TIM Pulse accumulator A overﬂow I bit PACTL (PAOVI) No Yes

Vector base + $DA TIM Pulse accumulator input edge I bit PACTL (PAI) No Yes

Vector base + $D8 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes

Vector base+ $D6 SCI0 I bit SCI0CR2

(TIE, TCIE, RIE, ILIE) Yes Yes

Vector base + $D4 SCI1 I bit SCI1CR2

(TIE, TCIE, RIE, ILIE) Yes Yes

Vector base + $D2 ATD0 I bit ATD0CTL2 (ASCIE) Yes Yes

Vector base + $D0 Reserved

Vector base + $CE Port J I bit PIEJ (PIEJ7-PIEJ0) Yes Yes

Vector base + $CC Port H I bit PIEH (PIEH7-PIEH0) Yes Yes

Vector base + $CA Reserved

Vector base + $C8 Reserved

Vector base + $C6 CRG PLL lock I bit CRGINT(LOCKIE) Refer to CRG

interrupt section

Vector base + $C4 CRG self-clock mode I bit CRGINT (SCMIE) Refer to CRG

interrupt section

Vector base + $C2

Vector base + $BC Reserved

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 53

1.6.3 Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections

for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers.

Vector base + $BA FLASH Fault Detect I bit FCNFG2 (SFDIE, DFDIE) No No

Vector base + $B8 FLASH I bit FCNFG (CCIE) No Yes

Vector base + $B6 CAN0 wake-up I bit CAN0RIER (WUPIE) Yes Yes

Vector base + $B4 CAN0 errors I bit CAN0RIER (CSCIE,

OVRIE) No Yes

Vector base + $B2 CAN0 receive I bit CAN0RIER (RXFIE) No Yes

Vector base + $B0 CAN0 transmit I bit CAN0TIER (TXEIE[2:0]) No Yes

Vector base + $AE

Vector base + $90 Reserved

Vector base + $8E Port P Interrupt I bit PIEP (PIEP7-PIEP0) Yes Yes

Vector base+ $8C PWM emergency shutdown I bit PWMSDN (PWMIE) No Yes

Vector base + $8A

Vector base + $82 Reserved

Vector base + $80 Low-voltage interrupt (LVI) I bit VREGCTRL (LVIE) No Yes

Vector base + $7E Autonomous periodical interrupt (API) I bit VREGAPICTRL (APIE) Yes Yes

Vector base + $7C High Temperature Interrupt (HTI) I bit VREGHTCL (HTIE) No Yes

Vector base + $7A Periodic interrupt timer channel 0 I bit PITINTE (PINTE0) No Yes

Vector base + $78 Periodic interrupt timer channel 1 I bit PITINTE (PINTE1) No Yes

Vector base + $76 Periodic interrupt timer channel 2 I bit PITINTE (PINTE2) No Yes

Vector base + $74 Periodic interrupt timer channel 3 I bit PITINTE (PINTE3) No Yes

Vector base + $72

Vector base + $40 Reserved

Vector base + $3E ATD0 Compare Interrupt I bit ATD0CTL2 (ACMPIE) Yes Yes

Vector base + $3C

Vector base + $14 Reserved

Vector base + $12 System Call Interrupt (SYS) — None — —

Vector base + $10 Spurious interrupt — None — —

116 bits vector address based

Table 1-10. Interrupt Vector Locations (Sheet 2 of 2)

Vector Address1Interrupt Source CCR

Mask Local Enable STOP

Wake up WAIT

Wake up

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S12XS Family Reference Manual, Rev. 1.10

54 Freescale Semiconductor

1.6.3.1 Flash Conﬁguration Reset Sequence Phase

On each reset, the Flash module will hold CPU activity while loading Flash module registers from the

Flash memory. If double faults are detected in the reset phase, Flash module protection and security may

be active on leaving reset. This is explained in more detail in the Flash module section.

1.6.3.2 Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The

state of the word being programmed or the sector/block being erased is not guaranteed.

1.6.3.3 I/O Pins

Refer to the PIM section for reset conﬁgurations of all peripheral module ports.

1.6.3.4 Memory

The RAM arrays are not initialized out of reset.

1.6.3.5 COP Conﬁguration

The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded from the Flash

conﬁguration ﬁeld byte at global address $7FFF0E during the reset sequence.

If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any

reset into Special Single Chip mode.

Table 1-11. Initial COP Rate Conﬁguration

NV[2:0] in

FOPT Register CR[2:0] in

COPCTL Register

000 111

001 110

010 101

011 100

100 011

101 010

110 001

111 000

Table 1-12. Initial WCOP Conﬁguration

NV[3] in

FOPT Register WCOP in

COPCTL Register

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S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 55

1.7 ATD0 Conﬁguration

1.7.1 External Trigger Input Connection

The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The

external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-13

shows the connection of the external trigger inputs.

Consult the ATD section for information about the analog-to-digital converter module. References to

freeze mode are equivalent to active BDM mode.

1.7.2 ATD0 Channel[17] Connection

Further to the 16 externally available channels, ATD0 features an extra channel[17] that is connected to

the internal temperature sensor at device level. To access this channel ATD0 must use the channel encoding

SC:CD:CC:CB:CA = 1:0:0:0:1 in ATDCTL5. For more temperature sensor information, please refer to

1.8.1 Temperature Sensor Conﬁguration.

1.8 VREG Conﬁguration

The device must be conﬁgured with the internal voltage regulator enabled. Operation in conjunction with

an external voltage regulator is not supported.

The API trimming register APITR is loaded from the Flash IFR option ﬁeld at global address 0x40_00F0

bits[5:0] during the reset sequence. Currently factory programming of this IFR range is not supported.

Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does

not support access abort of reserved VREG register space.

1.8.1 Temperature Sensor Conﬁguration

The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the internal Flash

during the reset sequence. To use the high temperature interrupt within the speciﬁed limits (THTIA and

THTID) these bits must be loaded with 0x8. Currently factory programming is not supported.

The device temperature can be monitored on ATD0 channel[17]. The internal bandgap reference voltage

can also be mapped to ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps

the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17].

Table 1-13. ATD0 External Trigger Sources

ExternalTrigger

Input Connectivity

ETRIG0 Pulse width modulator channel 1

ETRIG1 Pulse width modulator channel 3

ETRIG2 Periodic interrupt timer hardware trigger 0

ETRIG3 Periodic interrupt timer hardware trigger 1

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

56 Freescale Semiconductor

1.9 BDM Clock Conﬁguration

The BDM alternate clock source is the oscillator clock.

1.10 Oscillator Conﬁguration

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop

controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock

circuitry is used.

The XCLKS signal selects the oscillator conﬁguration during reset low phase while a clock quality check

is ongoing. This is the case for:

• Power on reset or low-voltage reset

• Clock monitor reset

• Any reset while in self-clock mode or full stop mode

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 57

The selected oscillator conﬁguration is frozen with the rising edge of the RESET pin in any of these above

described reset cases.

Figure 1-7. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)

Figure 1-8. Full Swing Pierce Oscillator Connections (XCLKS = 0)

Figure 1-9. External Clock Connections (XCLKS = 0)

MCU

EXTAL

XTAL

VSSPLL

Crystal or

Ceramic Resonator

MCU

EXTAL

XTAL RS

VSSPLL

Crystal or

Ceramic Resonator

RB=1MΩ ; RS speciﬁed by crystal vendor

MCU

EXTAL

XTAL

CMOS-Compatible

External Oscillator

Not Connected

Device Overview S12XS Family

S12XS Family Reference Manual, Rev. 1.10

58 Freescale Semiconductor

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 59

Chapter 2

Port Integration Module (S12XSPIMV1)

Revision History

2.1 Introduction

2.1.1 Overview

The S12XS family Port Integration Module establishes the interface between the peripheral modules and

the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and

multiplexing on shared pins.

This document covers:

• Port A, B and K used as general purpose I/O

• Port E associated with the IRQ, XIRQ interrupt inputs

• Port T associated with 1 timer module

• Port S associated with 2 SCI module and 1 SPI module

• Port M associated with 1 MSCAN

• Port P connected to the PWM - inputs can be used as an external interrupt source

• Port H and J used as general purpose I/O - inputs can be used as an external interrupt source

• Port AD associated with one 16-channel ATD module

Most I/O pins can be conﬁgured by register bits to select data direction and drive strength, to enable and

select pull-up or pull-down devices.

Revision

Number Revision Date Sections

Affected Description of Changes

V01.04 02 Apr 2008 • Corrected reduced drive strength to 1/5

• Separated PE1,0 bit descriptions from other PE GPIO

V01.05 31 Mar 2009 • Corrected PERJ bit description

• Orthographical corrections

V01.06 18 Dec 2009 Table 2-1./2-61 • Corrected PP0, PM0 pin descriptions

• Added function independency to wired-or bit descriptions

• Minor corrections

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S12XS Family Reference Manual, Rev. 1.10

60 Freescale Semiconductor

NOTE

This document assumes the availability of all features (112-pin package

option). Some functions are not available on lower pin count package

options. Refer to the pin-out summary section.

2.1.2 Features

The Port Integration Module includes these distinctive registers:

• Data and data direction registers for Ports A, B, E, K, T, S, M, P, H, J, and AD when used as

general-purpose I/O

• Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,

H, and J on per-pin basis

• Control registers to enable/disable pull-up devices on Port AD on per-pin basis

• Single control register to enable/disable pull-ups on Ports A, B, E, and K on per-port basis and on

BKGD pin

• Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, and AD on per-pin

basis

• Single control register to enable/disable reduced output drive on Ports A, B, E, and K on per-port

basis

• Control registers to enable/disable open-drain (wired-or) mode on Ports S, and M

• Interrupt ﬂag register for pin interrupts on Ports P, H, and J

• Control register to conﬁgure IRQ pin operation

• Routing registers to support module port relocation

• Free-running clock outputs

A standard port pin has the following minimum features:

• Input/output selection

• 5V output drive with two selectable drive strengths

• 5V digital and analog input

• Input with selectable pull-up or pull-down device

Optional features supported on dedicated pins:

• Open drain for wired-or connections

• Interrupt inputs with glitch filtering

2.2 External Signal Description

This section lists and describes the signals that connect off-chip.

Table shows all the pins and their functions that are controlled by the Port Integration Module. Refer to

the device deﬁnition for the availability of the individual pins in the different package options.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 61

NOTE

If there is more than one function associated with a pin, the priority is

indicated by the position in the table from top (highest priority) to bottom

(lowest priority)

Table 2-1. Pin Functions and Priorities

Port Pin Name Pin Function

& Priority1I/O Description Pin Function

after Reset

- BKGD MODC 2I MODC input during RESET BKGD

BKGD I/O S12X_BDM communication pin

A PA[7:0] GPIO I/O General purpose GPIO

B PB[7:0] GPIO I/O General purpose GPIO

E PE[7] XCLKS 2I External clock selection input during RESET GPIO

ECLKX2 O Free-running clock at core clock rate (ECLK x 2)

GPIO I/O General purpose

PE[6:5] GPIO I/O General purpose

PE[4] ECLK O Free-running clock at bus clock rate or programmable

down-scaled bus clock

GPIO I/O General purpose

PE[3:2] GPIO I/O General purpose

PE[1] IRQ I Maskable level- or falling edge-sensitive interrupt

GPI I General-purpose

PE[0] XIRQ I Non-maskable level-sensitive interrupt

GPI I General-purpose

K PK[7,5:0] GPIO I/O General purpose GPIO

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

62 Freescale Semiconductor

T PT7 IOC7 I/O Timer Channel 7 GPIO

(PWM7) I/O Pulse Width Modulator channel 7; emergency shut-down

GPIO I/O General purpose

PT6 IOC6 I/O Timer Channel 6

(PWM6) O Pulse Width Modulator channel 6

GPIO I/O General purpose

PT5 IOC5 I/O Timer Channel 5

(PWM5) O Pulse Width Modulator channel 5

VREG_API O VREG Autonomous Periodical Interrupt Clock

GPIO I/O General purpose

PT4 IOC4 I/O Timer Channel 4

(PWM4) O Pulse Width Modulator channel 4

GPIO I/O General purpose

PT[3:0] IOC[3:0] I/O Timer Channel 3 - 0

GPIO I/O General purpose

S PS7 SS0 I/O Serial Peripheral Interface 0 slave select output in master mode,

input in slave mode or master mode. GPIO

GPIO I/O General purpose

PS6 SCK0 I/O Serial Peripheral Interface 0 serial clock pin

GPIO I/O General purpose

PS5 MOSI0 I/O Serial Peripheral Interface 0 master out/slave in pin

GPIO I/O General purpose

PS4 MISO0 I/O Serial Peripheral Interface 0 master in/slave out pin

GPIO I/O General purpose

PS3 TXD1 O Serial Communication Interface 1 transmit pin

GPIO I/O General purpose

PS2 RXD1 I Serial Communication Interface 1 receive pin

GPIO I/O General purpose

PS1 TXD0 O Serial Communication Interface 0 transmit pin

GPIO I/O General purpose

PS0 RXD0 I Serial Communication Interface 0 receive pin

GPIO I/O General purpose

Table 2-1. Pin Functions and Priorities (continued)

Port Pin Name Pin Function

& Priority1I/O Description Pin Function

after Reset

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 63

M PM[7:6] GPIO I/O General purpose GPIO

PM5 (SCK0) I/O Serial Peripheral Interface 0 serial clock pin

GPIO I/O General purpose

PM4 (MOSI0) I/O Serial Peripheral Interface 0 master out/slave in pin

GPIO I/O General purpose

PM3 (SS0) I/O Serial Peripheral Interface 0 slave select output in master mode,

input in slave mode or master mode.

GPIO I/O General purpose

PM2 (MISO0) I/O Serial Peripheral Interface 0 master in/slave out pin

GPIO I/O General purpose

PM1 TXCAN0 O MSCAN0 transmit pin

(TXD1) O Serial Communication Interface 1 transmit pin

GPIO I/O General purpose

PM0 RXCAN0 I MSCAN0 receive pin

(RXD1) I Serial Communication Interface 1 receive pin

GPIO I/O General purpose

Table 2-1. Pin Functions and Priorities (continued)

Port Pin Name Pin Function

& Priority1I/O Description Pin Function

after Reset

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

64 Freescale Semiconductor

2.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all Port Integration Module registers.

P PP7 PWM7 I/O Pulse Width Modulator channel 7; emergency shut-down GPIO

GPIO/KWP7 I/O General purpose; with interrupt

PP[6:3] PWM[6:3] O Pulse Width Modulator channel 6 - 3

GPIO/KWP[6:3] I/O General purpose; with interrupt

PP2 PWM2 O Pulse Width Modulator channel 2

(IOC2) I/O Timer Channel 2

(TXD1) O Serial Communication Interface 1 transmit pin

GPIO/KWP2 I/O General purpose; with interrupt

PP1 PWM1 O Pulse Width Modulator channel 1

(IOC1) I/O Timer Channel 1

GPIO/KWP1 I/O General purpose; with interrupt

PP0 PWM0 O Pulse Width Modulator channel 0

(IOC0) I/O Timer Channel 0

(RXD1) I Serial Communication Interface 1 receive pin

GPIO/KWP0 I/O General purpose; with interrupt

H PH[7:0] GPIO/KWH[7:0] I/O General purpose; with interrupt GPIO

J PJ[7:6] GPIO/KWJ[7:6] I/O General purpose; with interrupt GPIO

PJ[1:0] GPIO/KWJ[1:0] I/O General purpose; with interrupt

AD PAD[15:0] GPIO I/O General purpose GPIO

AN[15:0] I ATD analog

1Signals in brackets denote alternative module routing pins.

2Function active when RESET asserted.

Table 2-1. Pin Functions and Priorities (continued)

Port Pin Name Pin Function

& Priority1I/O Description Pin Function

after Reset

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 65

2.3.1 Memory Map

Table 2-2 shows the register map of the Port Integration Module.

Table 2-2. Block Memory Map

Port Offset or

Address Register Access Reset Value Section/Page

B0x0000 PORTA—Port A Data Register R/W 0x00 2.3.3/2-75

0x0001 PORTB—Port B Data Register R/W 0x00 2.3.4/2-75

0x0002 DDRA—Port A Data Direction Register R/W 0x00 2.3.5/2-76

0x0003 DDRB—Port B Data Direction Register R/W 0x00 2.3.6/2-76

0x0004

0x0007

PIM Reserved R 0x00 2.3.7/2-77

E 0x0008 PORTE—Port E Data Register R/W10x00 2.3.8/2-77

0x0009 DDRE—Port E Data Direction Register R/W10x00 2.3.9/2-78

0x000A

0x000B

Non-PIM address range2- - -

0x000C PUCR—Pull-up Control Register R/W10xD0 2.3.10/2-79

0x000D RDRIV—Reduced Drive Register R/W10x00 2.3.11/2-80

0x000E

0x001B

Non-PIM address range2- - -

E 0x001C ECLKCTL—ECLK Control Register R/W10b3100_0000 2.3.12/2-81

0x001D PIM Reserved R 0x00 2.3.13/2-82

0x001E IRQCR—IRQ Control Register R/W10x40 2.3.14/2-83

0x001F PIM Reserved R 0x00 2.3.15/2-83

0x0020

0x0031

Non-PIM address range2- - -

K 0x0032 PORTK—Port K Data Register R/W 0x00 2.3.16/2-84

0x0033 DDRK—Port K Data Direction Register R/W 0x00 2.3.17/2-84

0x0034

0x023F

Non-PIM address range2- - -

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

66 Freescale Semiconductor

T 0x0240 PTT—Port T Data Register R/W 0x00 2.3.18/2-85

0x0241 PTIT—Port T Input Register R 42.3.19/2-86

0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.3.20/2-87

0x0243 RDRT—Port T Reduced Drive Register R/W 0x00 2.3.21/2-87

0x0244 PERT—Port T Pull Device Enable Register R/W 0x00 2.3.22/2-88

0x0245 PPST—Port T Polarity Select Register R/W 0x00 2.3.23/2-88

0x0246 PIM Reserved R 0x00 2.3.24/2-89

0x0247 Port T Routing Register R/W 0x00 2.3.25/2-89

S 0x0248 PTS—Port S Data Register R/W 0x00 2.3.26/2-91

0x0249 PTIS—Port S Input Register R 42.3.27/2-92

0x024A DDRS—Port S Data Direction Register R/W 0x00 2.3.28/2-93

0x024B RDRS—Port S Reduced Drive Register R/W 0x00 2.3.29/2-94

0x024C PERS—Port S Pull Device Enable Register R/W 0xFF 2.3.30/2-94

0x024D PTPS—Port S Polarity Select Register R/W 0x00 2.3.31/2-95

0x024E WOMS—Port S Wired-Or Mode Register R/W 0x00 2.3.32/2-95

0x024F PIM Reserved R 0x00 2.3.33/2-96

M 0x0250 PTM—Port M Data Register R/W 0x00 2.3.34/2-96

0x0251 PTIM—Port M Input Register R 42.3.35/2-98

0x0252 DDRM—Port M Data Direction Register R/W 0x00 2.3.36/2-98

0x0253 RDRM—Port M Reduced Drive Register R/W 0x00 2.3.37/2-99

0x0254 PERM—Port M Pull Device Enable Register R/W 0x00 2.3.38/2-100

0x0255 PPSM—Port M Polarity Select Register R/W 0x00 2.3.39/2-100

0x0256 WOMM—Port M Wired-Or Mode Register R/W 0x00 2.3.40/2-101

0x0257 MODRR—Module Routing Register R/W 0x00 2.3.41/2-101

P 0x0258 PTP—Port P Data Register R/W 0x00 2.3.42/2-102

0x0259 PTIP—Port P Input Register R 42.3.43/2-104

0x025A DDRP—Port P Data Direction Register R/W 0x00 2.3.44/2-105

0x025B RDRP—Port P Reduced Drive Register R/W 0x00 2.3.45/2-106

0x025C PERP—Port P Pull Device Enable Register R/W 0x00 2.3.46/2-106

0x025D PTPP—Port P Polarity Select Register R/W 0x00 2.3.47/2-107

0x025E PIEP—Port P Interrupt Enable Register R/W 0x00 2.3.48/2-107

0x025F PIFP—Port P Interrupt Flag Register R/W 0x00 2.3.49/2-108

Table 2-2. Block Memory Map (continued)

Port Offset or

Address Register Access Reset Value Section/Page

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 67

H 0x0260 PTH—Port H Data Register R/W 0x00 2.3.50/2-108

0x0261 PTIH—Port H Input Register R 42.3.51/2-109

0x0262 DDRH—Port H Data Direction Register R/W 0x00 2.3.52/2-109

0x0263 RDRH—Port H Reduced Drive Register R/W 0x00 2.3.53/2-110

0x0264 PERH—Port H Pull Device Enable Register R/W 0x00 2.3.54/2-110

0x0265 PPSH—Port H Polarity Select Register R/W 0x00 2.3.55/2-111

0x0266 PIEH—Port H Interrupt Enable Register R/W 0x00 2.3.56/2-111

0x0267 PIFH—Port H Interrupt Flag Register R/W 0x00 2.3.57/2-112

J 0x0268 PTJ—Port J Data Register R/W 0x00 2.3.58/2-112

0x0269 PTIJ—Port J Input Register R 42.3.59/2-113

0x026A DDRJ—Port J Data Direction Register R/W 0x00 2.3.60/2-113

0x026B RDRJ—Port J Reduced Drive Register R/W 0x00 2.3.61/2-114

0x026C PERJ—Port J Pull Device Enable Register R/W 0xFF 2.3.62/2-114

0x026D PPSJ—Port J Polarity Select Register R/W 0x00 2.3.63/2-115

0x026E PIEJ—Port J Interrupt Enable Register R/W 0x00 2.3.64/2-115

0x026F PIFJ—Port J Interrupt Flag Register R/W 0x00 2.3.65/2-116

AD 0x0270 PT0AD0—Port AD0 Data Register 0 R/W 0x00 2.3.66/2-116

0x0271 PT1AD0—Port AD0 Data Register 1 R/W 0x00 2.3.67/2-117

0x0272 DDR0AD0—Port AD0 Data Direction Register 0 R/W 0x00 2.3.68/2-117

0x0273 DDR1AD0—Port AD0 Data Direction Register 1 R/W 0x00 2.3.69/2-118

0x0274 RDR0AD0—Port AD0 Reduced Drive Register 0 R/W 0x00 2.3.70/2-118

0x0275 RDR1AD0—Port AD0 Reduced Drive Register 1 R/W 0x00 2.3.71/2-119

0x0276 PER0AD0—Port AD0 Pull Up Enable Register 0 R/W 0x00 2.3.72/2-119

0x0277 PER1AD0—Port AD0 Pull Up Enable Register 1 R/W 0x00 2.3.73/2-120

0x0278

0x027F

PIM Reserved R 0x00 2.3.74/2-120

1Write access not applicable for one or more register bits. Refer to register description.

2Refer to memory map in SoC Guide to determine related module.

3Mode dependent.

4Read always returns logic level on pins.

Table 2-2. Block Memory Map (continued)

Port Offset or

Address Register Access Reset Value Section/Page

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

68 Freescale Semiconductor

Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000

PORTA RPA7PA6PA5PA4PA3PA2PA1PA0

0x0001

PORTB RPB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

0x0002

DDRA RDDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

0x0003

DDRB RDDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

0x0004

Reserved R00000000

0x0005

Reserved R00000000

0x0006

Reserved R00000000

0x0007

Reserved R00000000

0x0008

PORTE RPE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

0x0009

DDRE RDDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 00

0x000A

0x000B

Non-PIM

Address

Range

Non-PIM Address Range

0x000C

PUCR RPUPKE BKPUE 0PUPEE 00

PUPBE PUPAE

0x000D

RDRIV RRDPK 00

RDPE 00

RDPB RDPA

0x000E–

0x001B

Non-PIM

Address

Range

Non-PIM Address Range

= Unimplemented or Reserved

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 69

0x001C

ECLKCTL RNECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0

0x001D

Reserved R00000000

0x001E

IRQCR RIRQE IRQEN 000000

0x001F

Reserved

R00000000

0x0020–

0x0031

Non-PIM

Address

Range

Non-PIM Address Range

0x0032

PORTK RPK7 0PK5 PK4 PK3 PK2 PK1 PK0

0x0033

DDRK RDDRK7 0DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0

0x0034–

0x023F

Non-PIM

Address

Range

Non-PIM Address Range

0x0240

PTT RPTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0

0x0241

PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0

0x0242

DDRT RDDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0

0x0243

RDRT RRDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0

0x0244

PERT RPERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0

0x0245

PPST RPPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

70 Freescale Semiconductor

0x0246

Reserved R00000000

0x0247

PTTRR RPTTRR7 PTTRR6 PTTRR5 PTTRR4 0PTTRR2 PTTRR1 PTTRR0

0x0248

PTS RPTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0

0x0249

PTIS R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0

0x024A

DDRS RDDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0

0x024B

RDRS RRDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0

0x024C

PERS RPERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0

0x024D

PPSS RPPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0

0x024E

WOMS RWOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0

0x024F

Reserved R00000000

0x0250

PTM RPTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0

0x0251

PTIM R PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0

0x0252

DDRM RDDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0

0x0253

RDRM RRDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0

0x0254

PERM RPERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0

0x0255

PPSM RPPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 71

0x0256

WOMM RWOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0

0x0257

MODRR RMODRR7 MODRR6 0MODRR4 0000

0x0258

PTP RPTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0

0x0259

PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0

0x025A

DDRP RDDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0

0x025B

RDRP RRDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0

0x025C

PERP RPERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0

0x025D

PPSP RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0

0x025E

PIEP RPIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0

0x025F

PIFP RPIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0

0x0260

PTH RPTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0

0x0261

PTIH R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0

0x0262

DDRH RDDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0

0x0263

RDRH RRDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0

0x0264

PERH RPERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

72 Freescale Semiconductor

0x0265

PPSH RPPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0

0x0266

PIEH RPIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0

0x0267

PIFH RPIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0

0x0268

PTJ RPTJ7 PTJ6 0000

PTJ1 PTJ0

0x0269

PTIJ R PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0

0x026A

DDRJ RDDRJ7 DDRJ6 0000

DDRJ1 DDRJ0

0x026B

RDRJ RRDRJ7 RDRJ6 0000

RDRJ1 RDRJ0

0x026C

PERJ RPERJ7 PERJ6 0000

PERJ1 PERJ0

0x026D

PPSJ RPPSJ7 PPSJ6 0000

PPSJ1 PPSJ0

0x026E

PIEJ RPIEJ7 PIEJ6 0000

PIEJ1 PIEJ0

0x026F

PIFJ RPIFJ7 PIFJ6 0000

PIFJ1 PIFJ0

0x0270

PT0AD0 RPT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00

0x0271

PT1AD0 RPT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00

0x0272

DDR0AD0 RDDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00

0x0273

DDR1AD0 RDDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00

0x0274

RDR0AD0 RRDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 73

2.3.2 Register Descriptions

The following table summarizes the effect of the various conﬁguration bits, i.e. data direction (DDR),

output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull

device activity.

The conﬁguration bit PS is used for two purposes:

1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt enabled.

2. Select either a pull-up or pull-down device if PE is active.

0x0275

RDR1AD0 RRDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00

0x0276

PER0AD0 RPER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00

0x0277

PER1AD0 RPER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00

0x0278

Reserved R00000000

0x0279

Reserved R00000000

0x027A

Reserved R00000000

0x027B

Reserved R00000000

0x027C

Reserved R00000000

0x027D

Reserved R00000000

0x027E

Reserved R00000000

0x027F

Reserved R00000000

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

74 Freescale Semiconductor

Table 2-3. Pin Conﬁguration Summary

NOTE

All register bits in this module are completely synchronous to internal

clocks during a register read.

NOTE

Figures of port data registers also display the alternative functions if

applicable on the related pin as deﬁned in Table . Names in brackets denote

the availability of the function when using a speciﬁc routing option.

NOTE

Figures of module routing registers also display the module instance or

module channel associated with the related routing bit.

DDR IO RDR PE PS1

1Always “0” on Port A, B, E, K, and AD.

IE2

2Applicable only on Port P, H, and J.

Function Pull Device Interrupt

0 x x 0 x 0 Input Disabled Disabled

0 x x 1 0 0 Input Pull Up Disabled

0 x x 1 1 0 Input Pull Down Disabled

0 x x 0 0 1 Input Disabled Falling edge

0 x x 0 1 1 Input Disabled Rising edge

0 x x 1 0 1 Input Pull Up Falling edge

0 x x 1 1 1 Input Pull Down Rising edge

1 0 0 x x 0 Output, full drive to 0 Disabled Disabled

1 1 0 x x 0 Output, full drive to 1 Disabled Disabled

1 0 1 x x 0 Output, reduced drive to 0 Disabled Disabled

1 1 1 x x 0 Output, reduced drive to 1 Disabled Disabled

1 0 0 x 0 1 Output, full drive to 0 Disabled Falling edge

1 1 0 x 1 1 Output, full drive to 1 Disabled Rising edge

1 0 1 x 0 1 Output, reduced drive to 0 Disabled Falling edge

1 1 1 x 1 1 Output, reduced drive to 1 Disabled Rising edge

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 75

2.3.3 Port A Data Register (PORTA)

2.3.4 Port B Data Register (PORTB)

Address 0x0000 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Reset 00000000

Figure 2-1. Port A Data Register (PORTA)

Table 2-4. PORTA Register Field Descriptions

Field Description

7-0

PA Port A general purpose input/output data—Data Register

The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is

driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

Address 0x0001 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Reset 00000000

Figure 2-2. Port B Data Register (PORTB)

Table 2-5. PORTB Register Field Descriptions

Field Description

7-0

PB Port B general purpose input/output data—Data Register

The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is

driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

76 Freescale Semiconductor

2.3.5 Port A Data Direction Register (DDRA)

2.3.6 Port B Data Direction Register (DDRB)

Address 0x0002 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RDDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

Reset 00000000

Figure 2-3. Port A Data Direction Register (DDRA)

Table 2-6. DDRA Register Field Descriptions

Field Description

7-0

DDRA Port A Data Direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Address 0x0003 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RDDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Reset 00000000

Figure 2-4. Port B Data Direction Register (DDRB)

Table 2-7. DDRB Register Field Descriptions

Field Description

7-0

DDRB Port B Data Direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 77

2.3.7 PIM Reserved Registers

2.3.8 Port E Data Register (PORTE)

Address 0x0004 (PRR) to 0x0007 (PRR) Access: User read1

1Read: Always reads 0x00

Write: Unimplemented

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 2-5. PIM Reserved Registers

Address 0x0008 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Altern.

Function XCLKS — — ECLK — — IRQ XIRQ

ECLKX2 ———————

Reset 000000—

2These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

—2

= Unimplemented or Reserved

Figure 2-6. Port E Data Register (PORTE)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

78 Freescale Semiconductor

2.3.9 Port E Data Direction Register (DDRE)

Table 2-8. PORTE Register Field Descriptions

Field Description

PE Port E general purpose input/output data—Data Register, ECLKX2 output, XCLKS input

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.

• The external clock selection feature (XCLKS) is only active during RESET=0

6-5, 3-2

PE Port E general purpose input/output data—Data Register

The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is

driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

PE Port E general purpose input/output data—Data Register, ECLK output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The ECLK output function takes precedence over the general purpose I/O function if enabled.

PE Port E general purpose input data and interrupt—Data Register, IRQ input.

This pin can be used as general purpose and IRQ input.

PE Port E general purpose input data and interrupt—Data Register, XIRQ input.

This pin can be used as general purpose and XIRQ input.

Address 0x0009 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RDDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 00

Reset 00000000

= Unimplemented or Reserved

Figure 2-7. Port E Data Direction Register (DDRE)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 79

2.3.10 Ports ABEK, BKGD pin Pull-up Control Register (PUCR)

Table 2-9. DDRE Register Field Descriptions

Field Description

7-2

DDRE Port E Data Direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Address 0x000C (PRR) Access: User read/write1

1Read: Anytime in single-chip modes.

Write: Anytime, except BKPUE which is writable in Special Single-Chip Mode only.

76543210

RPUPKE BKPUE 0PUPEE 00

PUPBE PUPAE

Reset 11010000

= Unimplemented or Reserved

Figure 2-8. Ports ABEK, BKGD pin Pull-up Control Register (PUCR)

Table 2-10. PUCR Register Field Descriptions

Field Description

PUPKE Port K Pull-up Enable—Enable pull-up devices on all port input pins

This bit conﬁgures whether a pull-up device is activated on all associated port input pins. If a pin is used as output

this bit has no effect.

1 Pull-up device enabled

0 Pull-up device disabled

BKPUE BKGD pin pull-up Enable—Enable pull-up device on pin

This bit conﬁgures whether a pull-up device is activated, if the pin is used as input. If a pin is used as output this bit

has no effect.

1 Pull-up device enabled

0 Pull-up device disabled

PUPEE Port E Pull-up Enable—Enable pull-up devices on all port input pins except pins 5 and 6

This bit conﬁgures whether a pull-up device is activated on all associated port input pins. If a pin is used as output

this bit has no effect.

Pins 5 and 6 have pull-down devices enabled only during reset. This bit has no effect on these pins.

1 Pull-up device enabled

0 Pull-up device disabled

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

80 Freescale Semiconductor

2.3.11 Ports ABEK Reduced Drive Register (RDRIV)

This register is used to select reduced drive for the pins associated with ports A, B, E, and K. If enabled,

the pins drive at approx. 1/5 of the full drive strength.

PUPBE Port B Pull-up Enable—Enable pull-up devices on all port input pins

This bit conﬁgures whether a pull-up device is activated on all associated port input pins. If a pin is used as output

this bit has no effect.

1 Pull-up device enabled

0 Pull-up device disabled

PUPAE Port A Pull-up Enable—Enable pull-up devices on all port input pins

This bit conﬁgures whether a pull-up device is activated on all associated port input pins. If a pin is used as output

this bit has no effect.

1 Pull-up device enabled

0 Pull-up device disabled

Address 0x000D (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RRDPK 00

RDPE 00

RDPB RDPA

Reset 00000000

= Unimplemented or Reserved

Figure 2-9. Ports ABEK Reduced Drive Register (RDRIV)

Table 2-11. RDRIV Register Field Descriptions

Field Description

RDPK Port K reduced drive—Select reduced drive for output port

This bit conﬁgures the drive strength of all associated port output pins as either full or reduced. If a pin is used as

input this bit has no effect. The reduced drive function is independent of which function is being used on a particular

pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

RDPE Port E reduced drive—Select reduced drive for output port

This bit conﬁgures the drive strength of all associated port output pins as either full or reduced. If a pin is used as

input this bit has no effect. The reduced drive function is independent of which function is being used on a particular

pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Table 2-10. PUCR Register Field Descriptions (continued)

Field Description

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 81

2.3.12 ECLK Control Register (ECLKCTL)

RDPB Port B reduced drive—Select reduced drive for output port

This bit conﬁgures the drive strength of all associated port output pins as either full or reduced. If a pin is used as

input this bit has no effect. The reduced drive function is independent of which function is being used on a particular

pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

RDPA Port A reduced drive—Select reduced drive for output port

This bit conﬁgures the drive strength of all associated port output pins as either full or reduced. If a pin is used as

input this bit has no effect. The reduced drive function is independent of which function is being used on a particular

pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Address 0x001C (PRR) Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RNECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0

Reset: Mode

Depen-

dent 1000000

Special

single-chip 01000000

Normal

single-chip 11000000

= Unimplemented or Reserved

Figure 2-10. ECLK Control Register (ECLKCTL)

Table 2-11. RDRIV Register Field Descriptions (continued)

Field Description

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

82 Freescale Semiconductor

2.3.13 PIM Reserved Register

Table 2-12. ECLKCTL Register Field Descriptions

Field Description

NECLK No ECLK—Disable ECLK output

This bit controls the availability of a free-running clock on the ECLK pin. This clock has a ﬁxed rate equivalent to the

internal bus clock.

1 ECLK disabled

0 ECLK enabled

NCLKX2 No ECLKX2—Disable ECLKX2 output

This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a ﬁxed rate of twice the

internal bus clock.

1 ECLKX2 disabled

0 ECLKX2 enabled

DIV16 Free-running ECLK predivider—Divide by 16

This bit enables a divide-by-16 stage on the selected EDIV rate.

1 Divider enabled: ECLK rate = EDIV rate divided by 16

0 Divider disabled: ECLK rate = EDIV rate

4-0

EDIV Free-running ECLK Divider—Conﬁgure ECLK rate

These bits determine the rate of the free-running clock on the ECLK pin.

00000 ECLK rate = bus clock rate

00001 ECLK rate = bus clock rate divided by 2

00010 ECLK rate = bus clock rate divided by 3, ...

11111 ECLK rate = bus clock rate divided by 32

Address 0x001D (PRR) Access: User read1

1Read: Always reads 0x00

Write: Unimplemented

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 2-11. PIM Reserved Register

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 83

2.3.14 IRQ Control Register (IRQCR)

2.3.15 PIM Reserved Register PIMTEST1

This register is reserved for factory testing of the PIM module and is not available in normal operation.

Writing to this register when in special modes can alter the pin functionality.

Address 0x001E Access: User read/write1

1Read: See individual bit descriptions below.

Write: See individual bit descriptions below.

76543210

RIRQE IRQEN 000000

Reset 01000000

= Unimplemented or Reserved

Figure 2-12. IRQ Control Register (IRQCR)

Table 2-13. IRQCR Register Field Descriptions

Field Description

IRQE IRQ select edge sensitive only—

Special mode: Read or write anytime.

Normal mode: Read anytime, write once.

1IRQ conﬁgured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1

and will be cleared only upon a reset or the servicing of the IRQ interrupt.

0IRQ conﬁgured for low level recognition.

IRQEN IRQ enable—

Read or write anytime.

1IRQ pin is connected to interrupt logic.

0IRQ pin is disconnected from interrupt logic.

1. Implementation pim_xe.01.01 and later

Address 0x001F Access: User read1

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 2-13. PIM Reserved Register

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

84 Freescale Semiconductor

2.3.16 Port K Data Register (PORTK)

2.3.17 Port K Data Direction Register (DDRK)

1Read: Always reads 0x00

Write: Unimplemented

Address 0x0032 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPK7 0PK5 PK4 PK3 PK2 PK1 PK0

Reset 00000000

Figure 2-14. Port K Data Register (PORTK)

Table 2-14. PORTK Register Field Descriptions

Field Description

7,5-0

PK Port K general purpose input/output data—Data Register

The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is

driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

Address 0x0033 (PRR) Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RDDRK7 0DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0

Reset 00000000

Figure 2-15. Port K Data Direction Register (DDRK)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 85

2.3.18 Port T Data Register (PTT)

Table 2-15. DDRK Register Field Descriptions

Field Description

7,5-0

DDRK Port K Data Direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Address 0x0240 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0

Altern.

Function IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

(PWM7) (PWM6) (PWM5) (PWM4) ————

— — VREG_API —————

Reset 00000000

Figure 2-16. Port T Data Register (PTT)

Table 2-16. PTT Register Field Descriptions

Field Description

7-6, 4

PTT Port T general purpose input/output data—Data Register, TIM output, routed PWM output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The TIM output function takes precedence over the routed PWM and the general purpose I/O function if the

related channel is enabled.

• The routed PWM function takes precedence over the general purpose I/O function if the related channel is

enabled.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

86 Freescale Semiconductor

2.3.19 Port T Input Register (PTIT)

PTT Port T general purpose input/output data—Data Register, TIM output, routed PWM output, VREG_API output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The TIM output function takes precedence over the routed PWM, VREG_API function and the general purpose

I/O function if the related channel is enabled.

• The routed PWM function takes precedence over VREG_API and the general purpose I/O function if the related

channel is enabled.

• The VREG_API takes precedence over the general purpose I/O function if enabled.

3-0

PTT Port T general purpose input/output data—Data Register, TIM output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The TIM output function takes precedence over the general purpose I/O function if the related channel is enabled.

Address 0x0241 Access: User read1

1Read: Anytime.

Write:Never, writes to this register have no effect.

76543210

R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0

Reset uuuuuuuu

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-17. Port T Input Register (PTIT)

Table 2-17. PTIT Register Field Descriptions

Field Description

7-0

PTIT Port T input data—

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit

conditions on output pins.

Table 2-16. PTT Register Field Descriptions (continued)

Field Description

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 87

2.3.20 Port T Data Direction Register (DDRT)

2.3.21 Port T Reduced Drive Register (RDRT)

Address 0x0242 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0

Reset 00000000

Figure 2-18. Port T Data Direction Register (DDRT)

Table 2-18. DDRT Register Field Descriptions

Field Description

7-6, 4

DDRT Port T data direction—

This bit determines whether the pin is an input or output.

The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the

routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not

change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

DDRT Port T data direction—

This bit determines whether the pin is an input or output.

The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the

routed PWM forces the I/O state to be an output for an enabled channel. Else the VREG_API forces the I/O state to

be an output if enabled. In these cases the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

3-0

DDRT Port T data direction—

This bit determines whether the pin is an input or output.

The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case

the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Address 0x0243 Access: User read/write1

76543210

RRDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0

Reset 00000000

Figure 2-19. Port T Reduced Drive Register (RDRT)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

88 Freescale Semiconductor

2.3.22 Port T Pull Device Enable Register (PERT)

2.3.23 Port T Polarity Select Register (PPST)

1Read: Anytime.

Write: Anytime.

Table 2-19. RDRT Register Field Descriptions

Field Description

7-0

RDRT Port T reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Address 0x0244 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0

Reset 00000000

Figure 2-20. Port T Pull Device Enable Register (PERT)

Table 2-20. PERT Register Field Descriptions

Field Description

7-0

PERT Port T pull device enable—Enable pull device on input pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

Address 0x0245 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0

Reset 00000000

Figure 2-21. Port T Polarity Select Register (PPST)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 89

2.3.24 PIM Reserved Register

2.3.25 Port T Routing Register (PTTRR)

This register configures the re-routing of PWM and TIM channels on alternative pins.

Table 2-21. PPST Register Field Descriptions

Field Description

7-0

PPST Port T pull device select—Conﬁgure pull device polarity on input pin

This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.

1 A pull-down device selected

0 A pull-up device selected

Address 0x0246 Access: User read1

1Read: Always reads 0x00

Write: Unimplemented

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 2-22. PIM Reserved Register

Address 0x0247 Access: User read1

1Read: Anytime.

Write: Anytime.

76543210

RPTTRR7 PTTRR6 PTTRR5 PTTRR4 0PTTRR2 PTTRR1 PTTRR0

Routing

Option PWM7 PWM6 PWM5 PWM4 — IOC2 IOC1 IOC0

Reset 00000000

= Unimplemented or Reserved

Figure 2-23. Port T Routing Register (PTTRR)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

90 Freescale Semiconductor

Table 2-22. PTTRR Register Field Descriptions

Field Description

PTTRR Port T peripheral routing—

This register controls the routing of PWM channel 7.

1 PWM7 routed to PT7

0 PWM7 routed to PP7

PTTRR Port T peripheral routing—

This register controls the routing of PWM channel 6.

1 PWM6 routed to PT6

0 PWM6 routed to PP6

PTTRR Port T peripheral routing—

This register controls the routing of PWM channel 5.

1 PWM5 routed to PT5

0 PWM5 routed to PP5

PTTRR Port T peripheral routing—

This register controls the routing of PWM channel 4.

1 PWM4 routed to PT4

0 PWM4 routed to PP4

PTTRR Port T peripheral routing—

This register controls the routing of TIM channel 2.

1 IOC2 routed to PP2

0 IOC2 routed to PT2

PTTRR Port T peripheral routing—

This register controls the routing of TIM channel 1.

1 IOC1 routed to PP1

0 IOC1 routed to PT1

PTTRR Port T peripheral routing—

This register controls the routing of TIM channel 0.

1 IOC0 routed to PP0

0 IOC0 routed to PT0

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 91

2.3.26 Port S Data Register (PTS)

Address 0x0248 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0

Altern.

Function SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0

Reset 00000000

Figure 2-24. Port S Data Register (PTS)

Table 2-23. PTS Register Field Descriptions

Field Description

PTS Port S general purpose input/output data—Data Register, SPI0 SS input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

PTS Port S general purpose input/output data—Data Register, SPI0 SCK input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

PTS Port S general purpose input/output data—Data Register, SPI0 MOSI input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

PTS Port S general purpose input/output data—Data Register, SPI0 MISO input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

92 Freescale Semiconductor

2.3.27 Port S Input Register (PTIS)

PTS Port S general purpose input/output data—Data Register, SCI1 TXD output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SCI1 function takes precedence over the general purpose I/O function if enabled.

PTS Port S general purpose input/output data—Data Register, SCI1 RXD input

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SCI1 function takes precedence over the general purpose I/O function if enabled.

PTS Port S general purpose input/output data—Data Register, SCI0 TXD output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SCI0 function takes precedence over the general purpose I/O function if enabled.

PTS Port S general purpose input/output data—Data Register, SCI0 RXD input

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SCI0 function takes precedence over the general purpose I/O function if enabled.

Address 0x0249 Access: User read1

1Read: Anytime.

Write:Never, writes to this register have no effect.

76543210

R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0

Reset uuuuuuuu

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-25. Port S Input Register (PTIS)

Table 2-23. PTS Register Field Descriptions (continued)

Field Description

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 93

2.3.28 Port S Data Direction Register (DDRS)

Table 2-24. PTIS Register Field Descriptions

Field Description

7-0

PTIS Port S input data—

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit

conditions on output pins.

Address 0x0249 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0

Reset 00000000

Figure 2-26. Port S Data Direction Register (DDRS)

Table 2-25. DDRS Register Field Descriptions

Field Description

7-4

DDRS Port S data direction—

This bit determines whether the associated pin is an input or output.

Depending on the conﬁguration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the

data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

3-2

DDRS Port S data direction—

This bit determines whether the associated pin is an input or output.

Depending on the conﬁguration of the enabled SCI1 the I/O state will be forced to be input or output. In this case the

data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

1-0

DDRS Port S data direction—

This bit determines whether the associated pin is an input or output.

Depending on the conﬁguration of the enabled SCI0 the I/O state will be forced to be input or output. In this case the

data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

94 Freescale Semiconductor

2.3.29 Port S Reduced Drive Register (RDRS)

2.3.30 Port S Pull Device Enable Register (PERS)

Address 0x024A Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0

Reset 00000000

Figure 2-27. Port S Reduced Drive Register (RDRS)

Table 2-26. RDRS Register Field Descriptions

Field Description

7-0

RDRS Port S reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Address 0x024B Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0

Reset 11111111

Figure 2-28. Port S Pull Device Enable Register (PERS)

Table 2-27. PERS Register Field Descriptions

Field Description

7-0

PERS Port S pull device enable—Enable pull device on input pin or wired-or output pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 95

2.3.31 Port S Polarity Select Register (PPSS)

2.3.32 Port S Wired-Or Mode Register (WOMS)

Address 0x024C Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0

Reset 00000000

Figure 2-29. Port S Polarity Select Register (PPSS)

Table 2-28. PPSS Register Field Descriptions

Field Description

7-0

PPSS Port S pull device select—Conﬁgure pull device polarity on input pin

This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.

1 A pull-down device selected

0 A pull-up device selected

Address 0x024C Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RWOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0

Reset 00000000

Figure 2-30. Port S Wired-Or Mode Register (WOMS)

Table 2-29. WOMS Register Field Descriptions

Field Description

7-0

WOMS Port S wired-or mode—Enable open-drain functionality on output pin

This bit conﬁgures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins.

In wired-or mode a logic “0” is driven active low while a logic “1” remains undriven. This allows a multipoint

connection of several serial modules. The bit has no inﬂuence on pins used as input.

1 Output buffer operates as open-drain output.

0 Output buffer operates as push-pull output.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

96 Freescale Semiconductor

2.3.33 PIM Reserved Register

2.3.34 Port M Data Register (PTM)

Address 0x024F Access: User read1

1Read: Always reads 0x00

Write: Unimplemented

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-31. PIM Reserved Register

Address 0x0250 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0

Altern.

Function — — (SCK0) (MOSI0) (SS0) (MISO0) TXCAN0 RXCAN0

——————(TXD1) (RXD1)

Reset 00000000

Figure 2-32. Port M Data Register (PTM)

Table 2-30. PTM Register Field Descriptions

Field Description

7-6

PTM Port M general purpose input/output data—Data Register

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

PTM Port M general purpose input/output data—Data Register, routed SPI0 SCK input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 97

PTM Port M general purpose input/output data—Data Register, routed SPI0 MOSI input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

PTM Port M general purpose input/output data—Data Register, routed SPI0 SS input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

PTM Port M general purpose input/output data—Data Register, routed SPI0 MISO input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The SPI0 function takes precedence over the general purpose I/O function if enabled.

PTM Port M general purpose input/output data—Data Register, CAN0 TXCAN output, SCI1 TXD output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The CAN0 function takes precedence over the general purpose I/O function if enabled.

• The SCI1 function takes precedence over the general purpose I/O function if enabled.

PTM Port M general purpose input/output data—Data Register, CAN0 RXCAN input, SCI1 RXD input

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The CAN0 function takes precedence over the general purpose I/O function if enabled.

• The SCI1 function takes precedence over the general purpose I/O function if enabled.

Table 2-30. PTM Register Field Descriptions (continued)

Field Description

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

98 Freescale Semiconductor

2.3.35 Port M Input Register (PTIM)

2.3.36 Port M Data Direction Register (DDRM)

Address 0x0251 Access: User read1

1Read: Anytime.

Write:Never, writes to this register have no effect.

76543210

R PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0

Reset uuuuuuuu

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-33. Port M Input Register (PTIM)

Table 2-31. PTIM Register Field Descriptions

Field Description

7-0

PTIM Port M input data—

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit

conditions on output pins.

Address 0x0252 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0

Reset 00000000

Figure 2-34. Port M Data Direction Register (DDRM)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 99

2.3.37 Port M Reduced Drive Register (RDRM)

Table 2-32. DDRM Register Field Descriptions

Field Description

7-6

DDRM Port M data direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

5-2

DDRM Port M data direction—

This bit determines whether the associated pin is an input or output.

Depending on the conﬁguration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the

data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

DDRM Port M data direction—

This bit determines whether the associated pin is an input or output.

The enabled CAN0 or SCI1 forces the I/O state to be an output. In this case the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

DDRM Port M data direction—

This bit determines whether the associated pin is an input or output.

The enabled CAN0 or SCI1 forces the I/O state to be an input. In this case the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Address 0x0253 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0

Reset 00000000

Figure 2-35. Port M Reduced Drive Register (RDRM)

Table 2-33. RDRM Register Field Descriptions

Field Description

7-0

RDRM Port M reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

100 Freescale Semiconductor

2.3.38 Port M Pull Device Enable Register (PERM)

2.3.39 Port M Polarity Select Register (PPSM)

Address 0x0254 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0

Reset 00000000

Figure 2-36. Port M Pull Device Enable Register (PERM)

Table 2-34. PERM Register Field Descriptions

Field Description

7-0

PERM Port M pull device enable—Enable pull device on input pin or wired-or output pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

Address 0x0255 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0

Reset 00000000

Figure 2-37. Port M Polarity Select Register (PPSM)

Table 2-35. PPSM Register Field Descriptions

Field Description

7-0

PPSM Port M pull device select—Conﬁgure pull device polarity on input pin

This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.

If CAN0 is active the selection of a pull-down device on the RXCAN input will have no effect.

1 A pull-down device selected

0 A pull-up device selected

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 101

2.3.40 Port M Wired-Or Mode Register (WOMM)

2.3.41 Module Routing Register (MODRR)

This register configures the re-routing of SCI1 and SPI0 on alternative ports.

Address 0x0256 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RWOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0

Reset 00000000

Figure 2-38. Port M Wired-Or Mode Register (WOMM)

Table 2-36. WOMM Register Field Descriptions

Field Description

7-0

WOMM Port M wired-or mode—Enable open-drain functionality on output pin

This bit conﬁgures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins.

In wired-or mode a logic “0” is driven active low while a logic “1” remains undriven. This allows a multipoint

connection of several serial modules. The bit has no inﬂuence on pins used as input.

1 Output buffer operates as open-drain output.

0 Output buffer operates as push-pull output.

Address 0x0257 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RMODRR7 MODRR6 0MODRR4 0000

Routing

Option SCI1 SCI1 — SPI0 ————

Reset 00000000

= Unimplemented or Reserved

Figure 2-39. Module Routing Register (MODRR)

Table 2-37. SCI1 Routing

MODRRx Related Pins

7 6 TXD RXD

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

102 Freescale Semiconductor

2.3.42 Port P Data Register (PTP)

0 0 PS3 PS2

0 1 PP2 PP0

1 0 PM1 PM0

1 1 Reserved1Reserved1

1Defaults to reset value

Table 2-38. SPI0 Routing

MODRRx Related Pins

4 MISO0 MOSI0 SCK0 SS0

0 PS4 PS5 PS6 PS7

1 PM2 PM4 PM5 PM3

Address 0x0258 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0

Altern.

Function PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

—————(IOC2) (IOC1) (IOC0)

—————(TXD1) — (RXD1)

Reset 00000000

Figure 2-40. Port P Data Register (PTP)

Table 2-37. SCI1 Routing

MODRRx Related Pins

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 103

Table 2-39. PTP Register Field Descriptions

Field Description

PTP Port P general purpose input/output data—Data Register, PWM input/output, pin interrupt input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The PWM function takes precedence over the general purpose I/O function if the related channel or the

emergency shut-down feature is enabled.

• Pin interrupts can be generated if enabled in input or output mode.

6-3

PTP Port P general purpose input/output data—Data Register, PWM output, pin interrupt input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The PWM function takes precedence over the general purpose I/O function if the related channel is enabled.

• Pin interrupts can be generated if enabled in input or output mode.

PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, routed SCI1 TXD

output, pin interrupt input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The PWM function takes precedence over the TIM, SCI1 and general purpose I/O function if the related channel

is enabled.

• The TIM function takes precedence over SCI1 and the general purpose I/O function if the related channel is

enabled.

• The SCI1 function takes precedence over the general purpose I/O function if enabled.

• Pin interrupts can be generated if enabled in input or output mode.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

104 Freescale Semiconductor

2.3.43 Port P Input Register (PTIP)

PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, pin interrupt

input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The PWM function takes precedence over the TIM and general purpose I/O function if the related channel is

enabled.

• The TIM function takes precedence over the general purpose I/O function if the related channel is enabled.

• Pin interrupts can be generated if enabled in input or output mode.

PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, routed SCI1 RXD

output, pin interrupt input/output

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• The PWM function takes precedence over the TIM, SCI1 and general purpose I/O function if the related channel

is enabled.

• The TIM function takes precedence over SCI1 and the general purpose I/O function if the related channel is

enabled.

• The SCI1 function takes precedence over the general purpose I/O function if enabled.

• Pin interrupts can be generated if enabled in input or output mode.

Address 0x0259 Access: User read1

1Read: Anytime.

Write:Never, writes to this register have no effect.

76543210

R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0

Reset uuuuuuuu

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-41. Port P Input Register (PTIP)

Table 2-40. PTIP Register Field Descriptions

Field Description

7-0

PTIP Port P input data—

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit

conditions on output pins.

Table 2-39. PTP Register Field Descriptions (continued)

Field Description

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 105

2.3.44 Port P Data Direction Register (DDRP)

Address 0x025A Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0

Reset 00000000

Figure 2-42. Port P Data Direction Register (DDRP)

Table 2-41. DDRP Register Field Descriptions

Field Description

DDRP Port P data direction—

This bit determines whether the associated pin is an input or output.

The PWM forces the I/O state to be an output for an enabled channel. If the PWM shutdown feature is enabled this

pin is forced to be an input. In this case the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

6-3

DDRP Port P data direction—

This bit determines whether the associated pin is an input or output.

The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not

change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

2,0

DDRP Port P data direction—

This bit determines whether the associated pin is an input or output.

The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an

output for a timer port associated with an enabled output compare. Else depending on the conﬁguration of the

enabled SCI the I/O state will be forced to be input or output. In this case the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

DDRP Port P data direction—

This bit determines whether the associated pin is an input or output.

The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an

output for a timer port associated with an enabled output compare. In this case the data direction bit will not change.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

106 Freescale Semiconductor

2.3.45 Port P Reduced Drive Register (RDRP)

2.3.46 Port P Pull Device Enable Register (PERP)

Address 0x025B Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0

Reset 00000000

Figure 2-43. Port P Reduced Drive Register (RDRP)

Table 2-42. RDRP Register Field Descriptions

Field Description

7-0

RDRP Port P reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Address 0x025C Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0

Reset 00000000

Figure 2-44. Port P Pull Device Enable Register (PERP)

Table 2-43. PERP Register Field Descriptions

Field Description

7-0

PERP Port P pull device enable—Enable pull device on input pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 107

2.3.47 Port P Polarity Select Register (PPSP)

2.3.48 Port P Interrupt Enable Register (PIEP)

Read: Anytime.

Address 0x025D Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0

Reset 00000000

Figure 2-45. Port P Polarity Select Register (PPSP)

Table 2-44. PPSP Register Field Descriptions

Field Description

7-0

PPSP Port P pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin

This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.

This bit also selects the polarity of the active pin interrupt edge.

1 A pull-down device selected; rising edge selected

0 A pull-up device selected; falling edge selected

Address 0x025E Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0

Reset 00000000

Figure 2-46. Port P Interrupt Enable Register (PIEP)

Table 2-45. PIEP Register Field Descriptions

Field Description

7-0

PIEP Port P interrupt enable—

This bit enables or disables on the edge sensitive pin interrupt on the associated pin.

1 Interrupt enabled

0 Interrupt disabled (interrupt ﬂag masked)

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

108 Freescale Semiconductor

2.3.49 Port P Interrupt Flag Register (PIFP)

2.3.50 Port H Data Register (PTH)

Address 0x025F Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0

Reset 00000000

Figure 2-47. Port P Interrupt Flag Register (PIFP)

Table 2-46. PIFP Register Field Descriptions

Field Description

7-0

PIFP Port P interrupt ﬂag—

The ﬂag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge

based on the state of the polarity select register.

Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)

0 No active edge occurred

Address 0x0260 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0

Reset 00000000

Figure 2-48. Port H Data Register (PTH)

Table 2-47. PTH Register Field Descriptions

Field Description

7-0

PTH Port H general purpose input/output data—Data Register, pin interrupt input/output

The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is

driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• Pin interrupts can be generated if enabled in input or output mode.

Port Integration Module (S12XSPIMV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 109

2.3.51 Port H Input Register (PTIH)

2.3.52 Port H Data Direction Register (DDRH)

Address 0x0261 Access: User read1

1Read: Anytime.

Write:Never, writes to this register have no effect.

76543210

R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0

Reset uuuuuuuu

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-49. Port H Input Register (PTIH)

Table 2-48. PTIH Register Field Descriptions

Field Description

7-0

PTIH Port H input data—

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit

conditions on output pins.

Address 0x0262 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0

Reset 00000000

Figure 2-50. Port H Data Direction Register (DDRH)

Table 2-49. DDRH Register Field Descriptions

Field Description

7-0

DDRH Port H data direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

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S12XS Family Reference Manual, Rev. 1.10

110 Freescale Semiconductor

2.3.53 Port H Reduced Drive Register (RDRH)

2.3.54 Port H Pull Device Enable Register (PERH)

Address 0x0263 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0

Reset 00000000

Figure 2-51. Port H Reduced Drive Register (RDRH)

Table 2-50. RDRH Register Field Descriptions

Field Description

7-0

RDRH Port H reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Address 0x0264 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0

Reset 00000000

Figure 2-52. Port H Pull Device Enable Register (PERH)

Table 2-51. PERH Register Field Descriptions

Field Description

7-0

PERH Port H pull device enable—Enable pull device on input pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

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2.3.55 Port H Polarity Select Register (PPSH)

2.3.56 Port H Interrupt Enable Register (PIEH)

Read: Anytime.

Address 0x025D Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0

Reset 00000000

Figure 2-53. Port H Polarity Select Register (PPSH)

Table 2-52. PPSH Register Field Descriptions

Field Description

7-0

PPSH Port H pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin

This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.

This bit also selects the polarity of the active pin interrupt edge.

1 A pull-down device selected; rising edge selected

0 A pull-up device selected; falling edge selected

Address 0x025E Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0

Reset 00000000

Figure 2-54. Port H Interrupt Enable Register (PIEH)

Table 2-53. PIEH Register Field Descriptions

Field Description

7-0

PIEH Port H interrupt enable—

This bit enables or disables on the edge sensitive pin interrupt on the associated pin.

1 Interrupt enabled

0 Interrupt disabled (interrupt ﬂag masked)

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2.3.57 Port H Interrupt Flag Register (PIFH)

2.3.58 Port J Data Register (PTJ)

Address 0x025F Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0

Reset 00000000

Figure 2-55. Port H Interrupt Flag Register (PIFH)

Table 2-54. PIFH Register Field Descriptions

Field Description

7-0

PIFH Port H interrupt ﬂag—

The ﬂag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge

based on the state of the polarity select register.

Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)

0 No active edge occurred

Address 0x0268 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPTJ7 PTJ6 0000

PTJ1 PTJ0

Reset 00000000

Figure 2-56. Port J Data Register (PTJ)

Table 2-55. PTJ Register Field Descriptions

Field Description

7-6, 1-0

PTJ Port J general purpose input/output data—Data Register, pin interrupt input/output

The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is

driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

• Pin interrupts can be generated if enabled in input or output mode.

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2.3.59 Port J Input Register (PTIJ)

2.3.60 Port J Data Direction Register (DDRJ)

Address 0x0269 Access: User read1

1Read: Anytime.

Write:Never, writes to this register have no effect.

76543210

R PTIJ7 PTIJ6 0000PTIJ1 PTIJ0

Reset uuuuuuuu

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-57. Port J Input Register (PTIJ)

Table 2-56. PTIJ Register Field Descriptions

Field Description

7-6, 1-0

PTIJ Port J input data—

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit

conditions on output pins.

Address 0x026A Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDRJ7 DDRJ6 0000

DDRJ1 DDRJ0

Reset 00000000

Figure 2-58. Port J Data Direction Register (DDRJ)

Table 2-57. DDRJ Register Field Descriptions

Field Description

7-6, 1-0

DDRJ Port J data direction—

This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

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2.3.61 Port J Reduced Drive Register (RDRJ)

2.3.62 Port J Pull Device Enable Register (PERJ)

Address 0x026B Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDRJ7 RDRJ6 0000

RDRJ1 RDRJ0

Reset 00000000

Figure 2-59. Port J Reduced Drive Register (RDRJ)

Table 2-58. RDRJ Register Field Descriptions

Field Description

7-6, 1-0

RDRJ Port J reduced drive—Select reduced drive for outputs

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Address 0x026C Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPERJ7 PERJ6 0000

PERJ1 PERJ0

Reset 11111111

Figure 2-60. Port J Pull Device Enable Register (PERJ)

Table 2-59. PERJ Register Field Descriptions

Field Description

7-6, 1-0

PERJ Port J pull device enable—Enable pull device on input pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

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2.3.63 Port J Polarity Select Register (PPSJ)

2.3.64 Port J Interrupt Enable Register (PIEJ)

Read: Anytime.

Address 0x026D Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPPSJ7 PPSJ6 0000

PPSJ1 PPSJ0

Reset 00000000

Figure 2-61. Port J Polarity Select Register (PPSJ)

Table 2-60. PPSJ Register Field Descriptions

Field Description

7-6, 1-0

PPSJ Port J pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin

This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.

This bit also selects the polarity of the active pin interrupt edge.

1 A pull-down device selected; rising edge selected

0 A pull-up device selected; falling edge selected

Address 0x026E Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPIEJ7 PIEJ6 0000

PIEJ1 PIEJ0

Reset 00000000

Figure 2-62. Port J Interrupt Enable Register (PIEJ)

Table 2-61. PIEJ Register Field Descriptions

Field Description

7-6, 1-0

PIEJ Port J interrupt enable—

This bit enables or disables on the edge sensitive pin interrupt on the associated pin.

1 Interrupt enabled

0 Interrupt disabled (interrupt ﬂag masked)

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2.3.65 Port J Interrupt Flag Register (PIFJ)

2.3.66 Port AD0 Data Register 0 (PT0AD0)

Address 0x026F Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPIFJ7 PIFJ6 0000

PIFJ1 PIFJ0

Reset 00000000

Figure 2-63. Port J Interrupt Flag Register (PIFJ)

Table 2-62. PIFJ Register Field Descriptions

Field Description

7-6, 1-0

PIFJ Port J interrupt ﬂag—

The ﬂag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge

based on the state of the polarity select register.

Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)

0 No active edge occurred

Address 0x0270 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00

Altern.

Function AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8

Reset 00000000

Figure 2-64. Port AD0 Data Register 0 (PT0AD0)

Table 2-63. PT0AD0 Register Field Descriptions

Field Description

7-0

PT0AD0 Port AD0 general purpose input/output data—Data Register, ATD AN analog input

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

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2.3.67 Port AD0 Data Register 1 (PT1AD0)

2.3.68 Port AD0 Data Direction Register 0 (DDR0AD0)

Address 0x0271 Access: User read/write1

1Read: Anytime. The data source depends on the data direction value.

Write: Anytime.

76543210

RPT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00

Altern.

Function AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

Reset 00000000

Figure 2-65. Port AD0 Data Register 1 (PT1AD0)

Table 2-64. PT1AD0 Register Field Descriptions

Field Description

7-0

PT1AD0 Port AD0 general purpose input/output data—Data Register, ATD AN analog input

When not used with the alternative function, the associated pin can be used as general purpose I/O. In general

purpose output mode the register bit value is driven to the pin.

If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered

pin input state is read.

Address 0x0272 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00

Reset 00000000

Figure 2-66. Port AD0 Data Direction Register 0 (DDR0AD0)

Table 2-65. DDR0AD0 Register Field Descriptions

Field Description

7-0

DDR0AD0 Port AD0 data direction—

This bit determines whether the associated pin is an input or output.

To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

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2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0)

2.3.70 Port AD0 Reduced Drive Register 0 (RDR0AD0)

Address 0x0273 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RDDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00

Reset 00000000

Figure 2-67. Port AD0 Data Direction Register 1 (DDR1AD0)

Table 2-66. DDR1AD0 Register Field Descriptions

Field Description

7-0

DDR1AD0 Port AD0 data direction—

This bit determines whether the associated pin is an input or output.

To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

Address 0x0274 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00

Reset 00000000

Figure 2-68. Port AD0 Reduced Drive Register 0 (RDR0AD0)

Table 2-67. RDR0AD0 Register Field Descriptions

Field Description

7-0

RDR0AD0 Port AD0 reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

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2.3.71 Port AD0 Reduced Drive Register 1 (RDR1AD0)

2.3.72 Port AD0 Pull Up Enable Register 0 (PER0AD0)

Address 0x0275 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RRDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00

Reset 00000000

Figure 2-69. Port AD0 Reduced Drive Register 1 (RDR1AD0)

Table 2-68. RDR1AD0 Register Field Descriptions

Field Description

7-0

RDR1AD0 Port AD0 reduced drive—Select reduced drive for output pin

This bit conﬁgures the drive strength of the associated output pin as either full or reduced. If a pin is used as input

this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/5 of the full drive strength)

0 Full drive strength enabled

Address 0x0276 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00

Reset 00000000

Figure 2-70. Port AD0 Pull Device Up Register 0 (PER0AD0)

Table 2-69. PER0AD0 Register Field Descriptions

Field Description

7-0

PER0AD0 Port AD0 pull device enable—Enable pull-up device on input pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

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2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0)

2.3.74 PIM Reserved Registers

2.4 Functional Description

2.4.1 General

Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an

output or input of a peripheral module.

Address 0x0277 Access: User read/write1

1Read: Anytime.

Write: Anytime.

76543210

RPER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00

Reset 00000000

Figure 2-71. Port AD0 Pull Up Enable Register 1 (PER1AD0)

Table 2-70. PER1AD0 Register Field Descriptions

Field Description

7-0

PER1AD0 Port AD0 pull device enable—Enable pull-up device on input pin

This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has

no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

Address 0x0278-0x27F Access: User read1

1Read: Always reads 0x00

Write: Unimplemented

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved u = Unaffected by reset

Figure 2-72. PIM Reserved Registers

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2.4.2 Registers

A set of conﬁguration registers is common to all ports with exception of the ATD port (Table 2-71). All

registers can be written at any time, however a speciﬁc conﬁguration might not become active.

For example selecting a pull-up device: This device does not become active while the port is used as a

push-pull output.

2.4.2.1 Data register (PORTx, PTx)

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output. When

reading this address, the buffered state of the pin is returned if the associated data direction register bit is

set to “0”.

If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This

is independent of any other conﬁguration (Figure 2-73).

2.4.2.2 Input register (PTIx)

This is a read-only register and always returns the buffered state of the pin (Figure 2-73).

2.4.2.3 Data direction register (DDRx)

This register deﬁnes whether the pin is used as a input or an output.

If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-73).

Independent of the pin usage with a peripheral module this register determines the source of data when

reading the associated data register address (2.4.2.1/2-121).

Table 2-71. Register availability per port1

1Each cell represents one register with individual conﬁguration bits

Port Data Input Data

Direction Reduced

Drive Pull

Enable Polarity

Select Wired-

Or Mode Interrupt

Enable Interrupt

Flag Routing

Ayes-yesyesyes-----

Byes-yes -----

Eyes-yes -----

Kyes-yes -----

T yes yes yes yes yes yes - - - yes

S yes yes yes yes yes yes yes - - -

M yes yes yes yes yes yes yes - - yes

P yes yes yes yes yes yes - yes yes -

H yes yes yes yes yes yes - yes yes -

J yes yes yes yes yes yes - yes yes -

ADyes-yesyesyes-----

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122 Freescale Semiconductor

NOTE

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on port data or port input registers, when

changing the data direction register.

Figure 2-73. Illustration of I/O pin functionality

2.4.2.4 Reduced drive register (RDRx)

If the pin is used as an output this register allows the conﬁguration of the drive strength independent of the

use with a peripheral module.

2.4.2.5 Pull device enable register (PERx)

This register turns on a pull-up or pull-down device on the related pins determined by the associated

polarity select register (2.4.2.5/2-122).

The pull device becomes active only if the pin is used as an input or as a wired-or output. Some peripheral

modules only allow certain conﬁgurations of pull devices to become active. Refer to the respective bit

descriptions.

2.4.2.6 Polarity select register (PPSx)

This register selects either a pull-up or pull-down device if enabled.

It only becomes active if the pin is used as an input. A pull-up device can be activated if the pin is used as

a wired-or output.

DDR

output enable

module enable

PTI

data out

Module

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2.4.2.7 Wired-or mode register (WOMx)

If the pin is used as an output this register turns off the active high drive. This allows wired-or type

connections of outputs.

2.4.2.8 Interrupt enable register (PIEx)

If the pin is used as an interrupt input this register serves as a mask to the interrupt ﬂag to enable/disable

the interrupt.

2.4.2.9 Interrupt ﬂag register (PIFx)

If the pin is used as an interrupt input this register holds the interrupt ﬂag after a valid pin event.

2.4.2.10 Module routing registers (MODRR, PTTRR)

These registers allow software re-conﬁguration of the pinouts of the different package options for speciﬁc

peripherals:

• MODRR supports the re-routing of the SCI1 and SPI0 pins to alternative ports

• PTTRR supports the re-routing of the PWM and TIM channels to alternative ports

2.4.3 Pins and Ports

NOTE

Please refer to the device pinout section to determine the pin availability in

the different package options.

2.4.3.1 BKGD pin

The BKGD pin is associated with the BDM module.

During reset, the BKGD pin is used as MODC input.

2.4.3.2 Port A, B

Port A pins PA[7:0] and Port B pins PB[7:0] can be used for general-purpose I/O.

2.4.3.3 Port E

Port E is associated with the free-running clock outputs ECLK, ECLKX2 and interrupt inputs IRQ and

XIRQ.

Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.

Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output

running at the core clock rate.

Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output

running at the bus clock rate or at the programmed divided clock rate.

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Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ

interrupt input. IRQ will be enabled by setting the IRQEN conﬁguration bit (2.3.14/2-83) and clearing the

I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially conﬁgured as a simple

input with a pull-up.

PortEpin PE[0] can beusedfor either general-purpose inputoras the level-sensitiveXIRQinterrupt input.

XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so

this pin is initially conﬁgured as a high-impedance input with a pull-up.

2.4.3.4 Port K

Port K pins PK[7,5:0] can be used for general-purpose I/O.

2.4.3.5 Port T

This port is associated with TIM and PWM.

Port T pins PT[7:4] can be used for either general-purpose I/O, or with the PWM or with the channels of

the standard Timer subsystem.

Port T pins PT[3:0] can be used for either general-purpose I/O, or with the channels of the standard Timer

subsystem.

The TIM pins IOC2-0 can be re-routed.

2.4.3.6 Port S

This port is associated with SPI0, SCI0 and SCI1.

Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem.

Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem.

Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem.

The SPI0 and SCI1 pins can be re-routed.

2.4.3.7 Port M

This port is associated with CAN0 and SCI1.

Port M pins PM[7:6] can be used for either general purpose I/O.

Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN0 or with the SCI1

subsystem.

Port M pins PM[5:2] can be used for general purpose I/O.

2.4.3.8 Port P

This port is associated with the PWM, TIM and SCI1.

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Port P pins PP[7:3] can be used for either general purpose I/O with pin interrupt capability, or with the

PWM or with the channels of the standard Timer.subsystem.

Port P pins PP[2,0] can be used for either general purpose I/O, or with the PWM or with the TIM or with

the SCI1 subsystem.

Port P pin PP[1] can be used for either general purpose I/O, or with the PWM or with the TIM subsystem.

2.4.3.9 Port H

Port H pins PH[7:0] can be used for general purpose I/O with pin interrupt capability.

2.4.3.10 Port J

Port J pins PJ[7,6,1,0] can be used for general purpose I/O with pin-interrupt capability.

2.4.3.11 Port AD

This port is associated with the ATD.

Port AD pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.

2.4.4 Pin interrupts

Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or

falling edges can be individually conﬁgured on a per-pin basis. All bits/pins in a port share the same

interrupt vector. Interrupts can be used with the pins conﬁgured as inputs or outputs.

An interrupt is generated when a bit in the port interrupt ﬂag register and its corresponding port interrupt

enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or

WAIT mode.

A digital ﬁlter on each pin prevents pulses (Figure 2-75) shorter than a speciﬁed time from generating an

interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-74 and

Table 2-72).

Figure 2-74. Interrupt Glitch Filter on Port P, H and J (PPS=0)

Glitch, ﬁltered out, no interrupt ﬂag set

Valid pulse, interrupt ﬂag set

tpign

tpval

uncertain

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126 Freescale Semiconductor

Table 2-72. Pulse Detection Criteria

Figure 2-75. Pulse Illustration

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4

consecutive samples of an active level directly or indirectly.

The ﬁlters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock

is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC

oscillator runs only if the following condition is true on any pin individually:

Sample count <= 4 and interrupt enabled (PIE=1) and interrupt ﬂag not set (PIF=0).

2.5 Initialization Information

2.5.1 Port Data and Data Direction Register writes

It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins

from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data

Pulse

Mode

STOP STOP1

1These values include the spread of the oscillator frequency over tempera-

ture, voltage and process.

Unit

Ignored tpulse ≤ 3 bus clocks tpulse ≤ tpign

Uncertain 3 < tpulse < 4 bus clocks tpign < tpulse < tpval

Valid tpulse ≥ 4 bus clocks tpulse ≥ tpval

tpulse

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Freescale Semiconductor 127

Chapter 3

Memory Mapping Control (S12XMMCV4)

Revision History

3.1 Introduction

This section describes the functionality of the module mapping control (MMC) sub-block of the S12X

platform. The block diagram of the MMC is shown in Figure 3-1.

The MMC module controls the multi-master priority accesses, the selection of internal resources . Internal

buses, including internal memories and peripherals, are controlled in this module. The local address space

for each master is translated to a global memory space.

Rev. No.

(Item No.) Date (Submitted

By) Sections

Affected Substantial Change(s)

v04.08 04-May-07 - Clarifying RPAGE usage for less than 12KB RAMSIZE.

- Some Cleanups

v04.09 01-Feb-08 - Minor changes

v04.10 17-Feb-09 - Minor changes

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128 Freescale Semiconductor

3.1.1 Terminology

3.1.2 Features

The main features of this block are:

• Paging capability to support a global 8MB memory address space

• Bus arbitration between the masters CPU, BDM

• Simultaneous accesses to different resources1 (internal, and peripherals) (see Figure 3-1 )

• Resolution of target bus access collision

• MCU operation mode control

• MCU security control

• Separate memory map schemes for each master CPU, BDM

• ROM control bits to enable the on-chip FLASH or ROM selection

• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which

does not belong to any of the on-chip modules) in single-chip modes

Table 3-1. Acronyms and Abbreviations

Logic level “1” Voltage that corresponds to Boolean true state

Logic level “0” Voltage that corresponds to Boolean false state

0x Represents hexadecimal number

x Represents logic level ’don’t care’

Byte 8-bit data

word 16-bit data

local address based on the 64KB Memory Space (16-bit address)

global address based on the 8MB Memory Space (23-bit address)

Aligned address Address on even boundary

Mis-aligned address Address on odd boundary

Bus Clock System Clock. Refer to CRG Block Guide.

single-chip modes Normal Single-Chip Mode

Special Single-Chip Mode

normal modes Normal Single-Chip Mode

special modes Special Single-Chip Mode

NS Normal Single-Chip Mode

SS Special Single-Chip Mode

Unimplemented areas Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented

PRR Port Replacement Registers

PRU Port Replacement Unit located on the emulator side

MCU MicroController Unit

NVM Non-volatile Memory; Flash, Data FLASH or ROM

IFR Information Row sector located on the top of NVM. For Test purposes.

1. Resources are also called targets.

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3.1.3 S12X Memory Mapping

The S12X architecture implements a number of memory mapping schemes including

• a CPU 8MB global map, deﬁned using a global page (GPAGE) register and dedicated 23-bit

address load/store instructions.

• a BDM 8MB global map, deﬁned using a global page (BDMGPR) register and dedicated 23-bit

address load/store instructions.

• a (CPU or BDM) 64KB local map, deﬁned using speciﬁc resource page (RPAGE, EPAGE and

PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered

as the local map accessed by the 16-bit (CPU or BDM) address.

The MMC module performs translation of the different memory mapping schemes to the speciﬁc global

(physical) memory implementation.

3.1.4 Modes of Operation

This subsection lists and brieﬂy describes all operating modes supported by the MMC.

3.1.4.1 Power Saving Modes

• Run mode

MMC is functional during normal run mode.

• Wait mode

MMC is functional during wait mode.

• Stop mode

MMC is inactive during stop mode.

3.1.4.2 Functional Modes

• Single chip modes

In normal and special single chip mode the internal memory is used.

3.1.5 Block Diagram

Figure 3-1 shows a block diagram of the MMC.

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Figure 3-1. MMC Block Diagram

3.2 External Signal Description

The user is advised to refer to the SoC Guide for port conﬁguration and location of external bus signals.

Some pins may not be bonded out in all implementations.

Table 3-2 outlines the pin names and functions. It also provides a brief description of their operation.

Table 3-2. External Input Signals Associated with the MMC

Signal I/O Description Availability

MODC I Mode input Latched after

RESET (active low)

CPU

BDM

Target Bus Controller

DBG

MMC

Address Decoder & Priority

Peripherals

PGMFLASHData FLASH RAM

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3.3 Memory Map and Registers

3.3.1 Module Memory Map

A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions

of the registers and bits are given in the subsections that follow.

3.3.2 Register Descriptions

Address Register

Name Bit 7 6 5 4 3 2 1 Bit 0

0x000A Reserved R 0 0 0 0 0 0 0 0

0x000B MODE R MODC 0000000

0x0010 GPAGE R 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0

0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8

0x0012 Reserved R 0 0 0 0 0 0 0 0

0x0013 MMCCTL1 R MGRAMON 0DFIFRON PGMIFRON 0000

0x0014 Reserved R 0 0 0 0 0 0 0 0

0x0015 PPAGE R PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0

0x0016 RPAGE R RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0

0x0017 EPAGE R EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0

= Unimplemented or Reserved

Figure 3-2. MMC Register Summary

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3.3.2.1 Mode Register (MODE)

Read: Anytime. Write: Only if a transition is allowed (see Figure 3-5).

The MODE bits of the MODE register are used to establish the MCU operating mode.

Figure 3-4.

Figure 3-5. Mode Transition Diagram when MCU is Unsecured

Address: 0x000B PRR

76543210

RMODC 0000000

Reset MODC10000000

1. External signal (see Table 3-2).

= Unimplemented or Reserved

Figure 3-3. Mode Register (MODE)

Table 3-3. MODE Field Descriptions

Field Description

MODC Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external

mode pin MODC determines the operating mode during RESET low (active). The state of the pin is latched into

the respective register bit after the RESET signal goes inactive (see Figure 3-3).

Write restrictions exist to disallow transitions between certain modes. Figure 3-5 illustrates all allowed mode

changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to

these register bits except in special modes.

Write accesses to the MODE register are blocked when the device is secured.

Normal

Single-Chip

Special

Single-Chip

RESET

(SS) 0

RESET 1(NS)

RESET

Transition done by external pins (MODC)

Transition done by write access to the MODE register

State

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3.3.2.2 Global Page Index Register (GPAGE)

Read: Anytime

Write: Anytime

The global page index register is used to construct a 23 bit address in the global map format. It is only used

when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,

GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global

address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see

Figure 3-7).

Figure 3-7. GPAGE Address Mapping

Example 3-1. This example demonstrates usage of the GPAGE register

LDX #0x5000 ;Set GPAGE offset to the value of 0x5000

MOVB #0x14, GPAGE ;Initialize GPAGE register with the value of 0x14

GLDAA X ;Load Accu A from the global address 0x14_5000

Address: 0x0010

76543210

R0 GP6 GP5 GP4 GP3 GP2 GP1 GP0

Reset 00000000

= Unimplemented or Reserved

Figure 3-6. Global Page Index Register (GPAGE)

Table 3-4. GPAGE Field Descriptions

Field Description

6–0

GP[6:0] Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64KB pages is to be

accessed.

Bit16 Bit 0Bit15Bit22

CPU Address [15:0]GPAGE Register [6:0]

Global Address [22:0]

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3.3.2.3 Direct Page Register (DIRECT)

Read: Anytime

Write: anytime in special modes, one time only in other modes.

This register determines the position of the 256B direct page within the memory map.It is valid for both

global and local mapping scheme.

Figure 3-9. DIRECT Address Mapping

Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global

instruction in direct addressing mode or by the appropriate local address to the global address expansion

(refer to Section 3.4.2.1.1, “Expansion of the Local Address Map).

Example 3-2. This example demonstrates usage of the Direct Addressing Mode

MOVB #0x80,DIRECT ;Set DIRECT register to 0x80. Write once only.

;Global data accesses to the range 0xXX_80XX can be direct.

;Logical data accesses to the range 0x80XX are direct.

LDY <00 ;Load the Y index register from 0x8000 (direct access).

;< operator forces direct access on some assemblers but in

;many cases assemblers are “direct page aware” and can

;automatically select direct mode.

Address: 0x0011

76543210

RDP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8

Reset 00000000

Figure 3-8. Direct Register (DIRECT)

Table 3-5. DIRECT Field Descriptions

Field Description

7–0

DP[15:8] Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct

addressing mode. The bits from this register form bits [15:8] of the address (see Figure 3-9).

Bit15 Bit0

Bit7

Bit22

CPU Address [15:0]

Global Address [22:0]

Bit8

Bit16

DP [15:8]

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3.3.2.4 MMC Control Register (MMCCTL1)

Read: Anytime. .

Write: Refer to each bit description.

3.3.2.5 Program Page Index Register (PPAGE)

Read: Anytime

Address: 0x0013 PRR

76543210

RMGRAMON 0DFIFRON PGMIFRON 0000

Reset 00000000

= Unimplemented or Reserved

Figure 3-10. MMC Control Register (MMCCTL1)

Table 3-6. MMCCTL1 Field Descriptions

Field Description

MGRAMON Flash Memory Controller SCRATCH RAM visible in the global memory map

Write: Anytime

This bit is used to made the Flash Memory Controller SCRATCH RAM visible in the global memory map.

0 Not visible in the global memory map.

1 Visible in the global memory map.

DFIFRON Data Flash Information Row (IFR) visible in the global memory map

Write: Anytime

This bit is used to made the IFR sector of the Data Flash visible in the global memory map.

0 Not visible in the global memory map.

1 Visible in the global memory map.

PGMIFRON Program Flash Information Row (IFR) visible in the global memory map

Write: Anytime

Thisbit is used to map the IFR sector of theProgram Flash to address range 0x40_000-0x40_3FFF of the global

memory map.

0 Not visible in the global memory map.

1 Visible in the global memory map.

Address: 0x0015

76543210

RPIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0

Reset 11111110

Figure 3-11. Program Page Index Register (PPAGE)

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Write: Anytime

These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU

or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12). This supports

accessing up to 4MB of Flash (in the Global map) within the 64KB Local map. The PPAGE register is

effectively used to construct paged Flash addresses in the Local map format. The CPU has special access

to read and write this register directly during execution of CALL and RTC instructions..

Figure 3-12. PPAGE Address Mapping

NOTE

Writes to this register using the special access of the CALL and RTC

instructions will be complete before the end of the instruction execution.

The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and

0xFFFF out of reset.

The ﬁxed 16K page from 0xC000-0xFFFF is the page number 0xFF.

3.3.2.6 RAM Page Index Register (RPAGE)

Table 3-7. PPAGE Field Descriptions

Field Description

7–0

PIX[7:0] Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM

array pages is to be accessed in the Program Page Window.

Address: 0x0016

76543210

RRP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0

Reset 11111101

Figure 3-13. RAM Page Index Register (RPAGE)

Bit14 Bit0

Address [13:0]

PPAGE Register [7:0]

Global Address [22:0]

Bit13

Bit21

Address: CPU Local Address

or BDM Local Address

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Read: Anytime

Write: Anytime

These eight index bits are used to page 4KB blocks into the RAM page window located in the local (CPU

or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 3-14). This supports accessing

up to 1022KB of RAM (in the Global map) within the 64KB Local map. The RAM page index register is

effectively used to construct paged RAM addresses in the Local map format.

Figure 3-14. RPAGE Address Mapping

NOTE

Because RAM page 0 has the same global address as the register space, it is

possible to write to registers through the RAM space when RPAGE = 0x00.

The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and

0x3FFF out of reset.

The ﬁxed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).

The ﬁxed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).

NOTE

The page 0xFD (reset value) contains unimplemented area in the range not

occupied by RAM if RAMSIZE is less than 12KB (Refer to Section 3.4.2.3,

“Implemented Memory Map).

Table 3-8. RPAGE Field Descriptions

Field Description

7–0

RP[7:0] RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to

be accessed in the RAM Page Window.

Bit18 Bit0

Bit11

Address [11:0]

RPAGE Register [7:0]

Global Address [22:0]

Bit12

Bit19

Address: CPU Local Address

or BDM Local Address

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The two ﬁxed 4KB pages (0xFE, 0xFF) contain unimplemented area in the

range not occupied by RAM if RAMSIZE is less than 8KB (Refer to

Section 3.4.2.3, “Implemented Memory Map).

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3.3.2.7 Data FLASH Page Index Register (EPAGE)

Read: Anytime

Write: Anytime

These eight index bits are used to page 1KB blocks into the Data FLASH page window located in the local

(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 3-16). This supports

accessing up to 256KB of Data FLASH (in the Global map) within the 64KB Local map. The Data FLASH

page index register is effectively used to construct paged Data FLASH addresses in the Local map format.

Figure 3-16. EPAGE Address Mapping

The reset value of 0xFE ensures that there is a linear Data FLASH space available between addresses

0x0800 and 0x0FFF out of reset.

The ﬁxed 1K page 0x0C00–0x0FFF of Data FLASH is equivalent to page 255 (page number 0xFF).

Address: 0x0017

76543210

REP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0

Reset 11111110

Figure 3-15. Data FLASH Page Index Register (EPAGE)

Table 3-9. EPAGE Field Descriptions

Field Description

7–0

EP[7:0] Data FLASH Page Index Bits 7–0 — These page index bits are used to select which of the 256 Data FLASH

array pages is to be accessed in the Data FLASH Page Window.

Bit16 Bit0

Bit9

Address [9:0]

EPAGE Register [7:0]

Global Address [22:0]

Bit10

Bit17

00 100

Address: CPU Local Address

or BDM Local Address

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3.4 Functional Description

The MMC block performs several basic functions of the S12X sub-system operation: MCU operation

modes, priority control, address mapping, select signal generation and access limitations for the system.

Each aspect is described in the following subsections.

3.4.1 MCU Operating Mode

• Normal single-chip mode

There is no external bus in this mode. The MCU program is executed from the internal memory

and no external accesses are allowed.

• Special single-chip mode

This mode is generally used for debugging single-chip operation, boot-strapping or security related

operations. The active background debug mode is in control of the CPU code execution and the

BDM ﬁrmware is waiting for serial commands sent through the BKGD pin. There is no external

bus in this mode.

3.4.2 Memory Map Scheme

3.4.2.1 CPU and BDM Memory Map Scheme

The BDM ﬁrmware lookup tables and BDM register memory locations share addresses with other

modules; however they are not visible in the global memory map during user’s code execution. The BDM

memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish

between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block

Guide for further details).

When the MCU enters active BDM mode, the BDM ﬁrmware lookup tables and the BDM registers

become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x7F_FF00 -

0x7F_FFFF) and the CPU begins execution of ﬁrmware commands or the BDM begins execution of

hardware commands. The resources which share memory space with the BDM module will not be visible

in the global memory map during active BDM mode.

Please note that after the MCU enters active BDM mode the BDM ﬁrmware lookup tables and the BDM

registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value

of 0xFF.

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Figure 3-17. Expansion of the Local Address Map

0x7F_FFFF

0x00_0000

0x14_0000

0x10_0000

0x00_0800

EPAGE

RPAGE

PPAGE

CPU and BDM

Local Memory Map Global Memory Map

0xFFFF Reset Vectors

0xC000

0x8000

Unpaged

0x4000

0x1000

0x0000

16KB FLASH window

0x0C00

0x2000

0x0800

8KB RAM

4KB RAM window

Reserved

2KB REGISTERS

1KB Data Flash window

16KB FLASH

Unpaged

16KB FLASH

2KB REGISTERS

2KB RAM

253*4KB paged

RAM

256*1KB paged

Data FLASH

253 *16KB paged

FLASH

16KB FLASH

(PPAGE 0xFD)

8KB RAM

16KB FLASH

(PPAGE 0xFE)

16KB FLASH

(PPAGE 0xFF)

0x00_1000

0x0F_E000

0x13_FC00

0x40_0000

0x7F_4000

0x7F_8000

0x7F_C000

1M minus 2KB

256KB

4MB 2.75MB

Unimplemented

Space

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3.4.2.1.1 Expansion of the Local Address Map

Expansion of the CPU Local Address Map

The program page index register in MMC allows accessing up to 4MB of FLASH or ROM in the global

memory map by using the eight page index bits to page 256 16KB blocks into the program page window

located from address 0x8000 to address 0xBFFF in the local CPU memory map.

The page value for the program page window is stored in the PPAGE register. The value of the PPAGE

(see Section 3.5.1, “CALL and RTC Instructions).

Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the

64KB local CPU address space.

The starting address of an interrupt service routine must be located in unpaged memory unless the user is

certain that the PPAGE register will be set to the appropriate value when the service routine is called.

However an interrupt service routine can call other routines that are in paged memory. The upper 16KB

block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and

interrupt vectors point to locations in this area or to the other unpaged sections of the local CPU memory

map.

The RAM page index register allows accessing up to 1MB minus 2KB of RAM in the global memory map

by using the eight RPAGE index bits to page 4KB blocks into the RAM page window located in the local

CPU memory space from address 0x1000 to address 0x1FFF. The Data FLASH page index register

EPAGE allows accessing up to 256KB of Data Flash in the system by using the eight EPAGE index bits to

page 1KB blocks into the Data FLASH page window located in the local CPU memory space from address

0x0800 to address 0x0BFF.

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Expansion of the BDM Local Address Map

PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the

global address. These registers can be read and written by the BDM.

The BDM expansion scheme is the same as the CPU expansion scheme.

3.4.2.2 Global Addresses Based on the Global Page

CPU Global Addresses Based on the Global Page

The seven global page index bits allow access to the full 8MB address map that can be accessed with 23

address bits. This provides an alternative way to access all of the various pages of FLASH, RAM and Data

FLASH.

The GPAGE Register is used only when the CPU is executing a global instruction (see Section 3.3.2.2,

“Global Page Index Register (GPAGE)). The generated global address is the result of concatenation of the

CPU local address [15:0] with the GPAGE register [22:16] (see Figure 3-7).

BDM Global Addresses Based on the Global Page

The seven BDMGPR Global Page index bits allow access to the full 8MB address map that can be accessed

with 23 address bits. This provides an alternative way to access all of the various pages of FLASH, RAM

and Data FLASH.

The BDM global page index register (BDMGPR) is used only in the case the CPU is executing a ﬁrmware

command which uses a global instruction (like GLDD, GSTD) or by a BDM hardware command (like

WRITE_W, WRITE_BYTE, READ_W, READ_BYTE). See the BDM Block Guide for further details.

The generated global address is a result of concatenation of the BDM local address with the BDMGPR

BDMGPR register [22:16] in the case of a ﬁrmware command (see Figure 3-18).

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Figure 3-18. BDMGPR Address Mapping

3.4.2.3 Implemented Memory Map

The global memory spaces reserved for the internal resources (RAM, Data FLASH, and FLASH) are not

determined by the MMC module. Size of the individual internal resources are however ﬁxed in the design

of the device cannot be changed by the user. Please refer to the SoC Guide for further details. Figure 3-19

and Table 3-10 show the memory spaces occupied by the on-chip resources. Please note that the memory

spaces have ﬁxed top addresses.

Table 3-10. Global Implemented Memory Space

Internal Resource $Address

RAM RAM_LOW = 0x10_0000 minus RAMSIZE1

1RAMSIZE is the hexadecimal value of RAM SIZE in Bytes

Data FLASH DF_HIGH = 0x10_0000 plus DFLASHSIZE2

2DFLASHSIZE is the hexadecimal value of DFLASH SIZE in Bytes

FLASH FLASH_LOW = 0x80_0000 minus FLASHSIZE3

3FLASHSIZE is the hexadecimal value of FLASH SIZE in Bytes

Bit16 Bit0Bit15Bit22

BDM Local Address

BDMGPR Register [6:0]

Global Address [22:0]

Bit16 Bit0Bit15Bit22

CPU Local Address

BDMGPR Register [6:0]

Global Address [22:0]

BDM HARDWARE COMMAND

BDM FIRMWARE COMMAND

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In single-chip modes accesses by the CPU (except for ﬁrmware commands) to any of the unimplemented

areas (see Figure 3-19) will result in an illegal access reset (system reset) in case of no MPU error. BDM

accesses to the unimplemented areas are allowed but the data will be undeﬁned.No misaligned word access

from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block

Guide).

Misaligned word access to the last location of RAM is performed but the data will be undeﬁned.

Misaligned word access to the last location of any global page (64KB) by any global instruction, is

performed by accessing the last byte of the page and the ﬁrst byte of the same page, considering the above

mentioned misaligned access cases.

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Figure 3-19. S12X CPU & BDM Global Address Mapping

0x7F_FFFF

0x00_0000

0x13_FFFF

0x0F_FFFF

Data FLASH

RAM

0x00_07FF

EPAGE

RPAGE

PPAGE 0x3F_FFFF

CPU and BDM

Local Memory Map Global Memory Map

FLASHSIZE RAMSIZE

0xFFFF Reset Vectors

0xC000

0x8000

Unpaged

0x4000

0x1000

0x0000

16K FLASH window

0x0C00

0x2000

0x0800

8K RAM

4K RAM window

Reserved

2K REGISTERS

1K Data Flash window

16K FLASH

Unpaged

16K FLASH

2K REGISTERS

Unimplemented

RAM

RAM_LOW

FLASH

FLASH_LOW

Unimplemented

FLASH

Unimplemented

Space

DF_HIGH Data FLASH

Resources

DFLASHSIZE

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3.4.3 Chip Bus Control

The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM )

with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping

operations. All internal resources are connected to speciﬁc target buses (see Figure 3-20).

Figure 3-20. MMC Block Diagram

CPU

BDM

Target Bus Controller

DBG

MMC

Address Decoder & Priority

Peripherals

PGMFLASHData FLASH RAM

S12X1 S12X0

XBUS0

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3.4.3.1 Master Bus Prioritization regarding access conﬂicts on Target Buses

The arbitration scheme allows only one master to be connected to a target at any given time. The following

rules apply when prioritizing accesses from different masters to the same target bus:

• CPU always has priority over BDM .

• BDM has priority over CPU when its access is stalled for more than 128 cycles. In the later case

the suspect master will be stalled after ﬁnishing the current operation and the BDM will gain access

to the bus.

3.5 Initialization/Application Information

3.5.1 CALL and RTC Instructions

CALL and RTC instructions are uninterruptible CPU instructions that automate page switching in the

program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is

called can be located anywhere in the local address space or in any Flash or ROM page visible through the

program page window. The CALL instruction calculates and stacks a return address, stacks the current

PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value

controls which of the 256 possible pages is visible through the 16KB program page window in the 64KB

local CPU memory map. Execution then begins at the address of the called subroutine.

During the execution of the CALL instruction, the CPU performs the following steps:

1. Writes the current PPAGE value into an internal temporary register and writes the new instruction-

supplied PPAGE value into the PPAGE register

2. Calculates the address of the next instruction after the CALL instruction (the return address) and

pushes this 16-bit value onto the stack

3. Pushes the temporarily stored PPAGE value onto the stack

4. Calculates the effective address of the subroutine, reﬁlls the queue and begins execution at the new

address

This sequence is uninterruptible. There is no need to inhibit interrupts during the CALL instruction

execution. A CALL instruction can be performed from any address to any other address in the local CPU

memory space.

The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing

mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand

in the instruction. In indexed-indirect variations of the CALL instruction a pointer speciﬁes memory

locations where the new page value and the address of the called subroutine are stored. Using indirect

addressing for both the new page value and the address within the page allows usage of values calculated

at run time rather than immediate values that must be known at the time of assembly.

The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks

the PPAGE value and the return address and reﬁlls the queue. Execution resumes with the next instruction

after the CALL instruction.

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During the execution of an RTC instruction the CPU performs the following steps:

1. Pulls the previously stored PPAGE value from the stack

2. Pulls the 16-bit return address from the stack and loads it into the PC

3. Writes the PPAGE value into the PPAGE register

4. Reﬁlls the queue and resumes execution at the return address

This sequence is uninterruptible. The RTC can be executed from anywhere in the local CPU memory

space.

The CALL and RTC instructions behave like JSR and RTS instruction, they however require more

execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and

CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to

access subroutines that are already present in the local CPU memory map (i.e. in the same page in the

program memory page window for example). However calling a function located in a different page

requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because

the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the

RTC instruction must be called using the CALL instruction even when the correct page is already present

in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time

of the RTC instruction execution.

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Chapter 4

Interrupt (S12XINTV2)

4.1 Introduction

The XINT module decodes the priority of all system exception requests and provides the applicable vector

for processing the exception to either the CPU or the XGATE module. The XINT module supports:

• I bit and X bit maskable interrupt requests

• One non-maskable unimplemented op-code trap

• One non-maskable software interrupt (SWI) or background debug mode request

• One non-maskable system call interrupt (SYS)

• Three non-maskable access violation interrupt

• One spurious interrupt vector request

• Three system reset vector requests

Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a

ﬂexible priority scheme. For interrupt requests that are conﬁgured to be handled by the CPU, the priority

scheme can be used to implement nested interrupt capability where interrupts from a lower level are

automatically blocked if a higher level interrupt is being processed. Interrupt requests conﬁgured to be

handled by the XGATE module can be nested one level deep.

NOTE

The HPRIO register and functionality of the original S12 interrupt module

is no longer supported, since it is superseded by the 7-level interrupt request

priority scheme.

Table 4-1. Revision History

Revision

Number Revision Date Sections

Affected Description of Changes

V02.00 01 Jul 2005 4.1.2/4-152 Initial V2 release, added new features:

- XGATE threads can be interrupted.

- SYS instruction vector.

- Access violation interrupt vectors.

V02.04 11 Jan 2007 4.3.2.2/4-157

4.3.2.4/4-158 - Added Notes for devices without XGATE module.

V02.05 20 Mar 2007 4.4.6/4-164 - Fixed priority deﬁnition for software exceptions.

V02.06 07 Jan 2008 4.5.3.1/4-166 - Added clariﬁcation of “Wake-up from STOP or WAIT by XIRQ with X bit set”

feature.

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4.1.1 Glossary

The following terms and abbreviations are used in the document.

4.1.2 Features

• Interrupt vector base register (IVBR)

• One spurious interrupt vector (at address vector base1 + 0x0010).

• One non-maskable system call interrupt vector request (at address vector base + 0x0012).

• Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014−

0x0018).

• 2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).

• Each I bit maskable interrupt request has a conﬁgurable priority level and can be conﬁgured to be

handled by either the CPU or the XGATE module2.

• I bit maskable interrupts can be nested, depending on their priority levels.

• One X bit maskable interrupt vector request (at address vector base + 0x00F4).

• One non-maskable software interrupt request (SWI) or background debug mode vector request (at

address vector base + 0x00F6).

• One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).

• Three system reset vectors (at addresses 0xFFFA–0xFFFE).

• Determines the highest priority XGATE and interrupt vector requests, drives the vector to the

XGATE module or to the bus on CPU request, respectively.

• Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or

whenever XIRQ is asserted, even if X interrupt is masked.

• XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.

Table 4-2. Terminology

Term Meaning

CCR Condition Code Register (in the S12X CPU)

DMA Direct Memory Access

INT Interrupt

IPL Interrupt Processing Level

ISR Interrupt Service Routine

MCU Micro-Controller Unit

XGATE refers to the XGATE co-processor; XGATE is an optional feature

IRQ refers to the interrupt request associated with the IRQ pin

XIRQ refers to the interrupt request associated with the XIRQ pin

1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used

as upper byte) and 0x00 (used as lower byte).

2. The IRQ interrupt can only be handled by the CPU

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4.1.3 Modes of Operation

• Run mode

This is the basic mode of operation.

• Wait mode

In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an

interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to

Section 4.5.3, “Wake Up from Stop or Wait Mode” for details.

• Stop Mode

In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an

interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to

Section 4.5.3, “Wake Up from Stop or Wait Mode” for details.

• Freeze mode (BDM active)

In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please

refer to Section 4.3.2.1, “Interrupt Vector Base Register (IVBR)” for details.

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4.1.4 Block Diagram

Figure 4-1 shows a block diagram of the XINT module.

Figure 4-1. XINT Block Diagram

4.2 External Signal Description

The XINT module has no external signals.

Wake Up

Current

RQST

IVBR

One Set Per Channel

XGATE

Interrupts

XGATE

Requests

Interrupt

Requests

Interrupt Requests CPU

Vector

Address

New

IPL

(Up to 108 Channels)

RQST XGATE Request Route,

PRIOLVLn Priority Level

= bits from the channel conﬁguration

in the associated conﬁguration register

INT_XGPRIO = XGATE Interrupt Priority

IVBR = Interrupt Vector Base

IPL = Interrupt Processing Level

PRIOLVL0

PRIOLVL1

PRIOLVL2

INT_XGPRIO

Peripheral

Vector

To XGATE Module

Priority

Decoder

To CPU

Priority

Decoder

Non I Bit Maskable

Channels

Wake up

XGATE

IRQ Channel

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4.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the XINT module.

4.3.1 Module Memory Map

Table 4-3 gives an overview over all XINT module registers.

Table 4-3. XINT Memory Map

Address Use Access

0x0120 RESERVED —

0x0121 Interrupt Vector Base Register (IVBR) R/W

0x0122–0x0125 RESERVED —

0x0126 XGATE Interrupt Priority Conﬁguration Register

(INT_XGPRIO) R/W

0x0127 Interrupt Request Conﬁguration Address Register

(INT_CFADDR) R/W

0x0128 Interrupt Request Conﬁguration Data Register 0

(INT_CFDATA0) R/W

0x0129 Interrupt Request Conﬁguration Data Register 1

(INT_CFDATA1) R/W

0x012A Interrupt Request Conﬁguration Data Register 2

(INT_CFDATA2 R/W

0x012B Interrupt Request Conﬁguration Data Register 3

(INT_CFDATA3) R/W

0x012C Interrupt Request Conﬁguration Data Register 4

(INT_CFDATA4) R/W

0x012D Interrupt Request Conﬁguration Data Register 5

(INT_CFDATA5) R/W

0x012E Interrupt Request Conﬁguration Data Register 6

(INT_CFDATA6) R/W

0x012F Interrupt Request Conﬁguration Data Register 7

(INT_CFDATA7) R/W

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4.3.2 Register Descriptions

This section describes in address order all the XINT module registers and their individual bits.

Address Register

Name Bit 7 654321Bit 0

0x0121 IVBR R IVB_ADDR[7:0]7

0x0126 INT_XGPRIO R 00000 XILVL[2:0]

0x0127 INT_CFADDR R INT_CFADDR[7:4] 0000

0x0128 INT_CFDATA0 R RQST 0000 PRIOLVL[2:0]

0x0129 INT_CFDATA1 R RQST 0000 PRIOLVL[2:0]

0x012A INT_CFDATA2 R RQST 0000 PRIOLVL[2:0]

0x012B INT_CFDATA3 R RQST 0000 PRIOLVL[2:0]

0x012C INT_CFDATA4 R RQST 0000 PRIOLVL[2:0]

0x012D INT_CFDATA5 R RQST 0000 PRIOLVL[2:0]

0x012E INT_CFDATA6 R RQST 0000 PRIOLVL[2:0]

0x012F INT_CFDATA7 R RQST 0000 PRIOLVL[2:0]

= Unimplemented or Reserved

Figure 4-2. XINT Register Summary

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4.3.2.1 Interrupt Vector Base Register (IVBR)

Read: Anytime

Write: Anytime

4.3.2.2 XGATE Interrupt Priority Conﬁguration Register (INT_XGPRIO)

Read: Anytime

Write: Anytime

Address: 0x0121

76543210

RIVB_ADDR[7:0]

Reset 1 1 1 11111

Figure 4-3. Interrupt Vector Base Register (IVBR)

Table 4-4. IVBR Field Descriptions

Field Description

7–0

IVB_ADDR[7:0] Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of

reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to

previous S12 microcontrollers.

Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine

the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset

vectors (0xFFFA–0xFFFE).

Note: If the BDM is active (i.e., the CPU is in the process of executing BDM ﬁrmware code), the contents of

IVBR are ignored and the upper byte of the vector address is ﬁxed as “0xFF”.

Address: 0x0126

76543210

R00000 XILVL[2:0]

Reset 0 0 0 00001

= Unimplemented or Reserved

Figure 4-4. XGATE Interrupt Priority Conﬁguration Register (INT_XGPRIO)

Table 4-5. INT_XGPRIO Field Descriptions

Field Description

2–0

XILVL[2:0] XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE

interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).

Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read

accesses to this register will return all 0.

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4.3.2.3 Interrupt Request Conﬁguration Address Register (INT_CFADDR)

Read: Anytime

Write: Anytime

4.3.2.4 Interrupt Request Conﬁguration Data Registers (INT_CFDATA0–7)

The eight register window visible at addresses INT_CFDATA0–7 contains the conﬁguration data for the

block of eight interrupt requests (out of 128) selected by the interrupt conﬁguration address register

(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt conﬁguration data register

of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt

conﬁguration data register of the vector with the highest address, respectively.

Table 4-6. XGATE Interrupt Priority Levels

Priority XILVL2 XILVL1 XILVL0 Meaning

0 0 0 Interrupt request is disabled

low 0 0 1 Priority level 1

0 1 0 Priority level 2

0 1 1 Priority level 3

1 0 0 Priority level 4

1 0 1 Priority level 5

1 1 0 Priority level 6

high 1 1 1 Priority level 7

Address: 0x0127

76543210

RINT_CFADDR[7:4] 0000

Reset 0 0 0 10000

= Unimplemented or Reserved

Figure 4-5. Interrupt Conﬁguration Address Register (INT_CFADDR)

Table 4-7. INT_CFADDR Field Descriptions

Field Description

7–4

INT_CFADDR[7:4] Interrupt Request Conﬁguration Data Register Select Bits — These bits determine which of the 128

conﬁguration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal

valuewritten to thisregister corresponds tothe upper nibbleofthe lowerbyteof theaddress of theinterrupt

vector, i.e.,writing0xE0 to this register selectstheconﬁguration data registerblock forthe 8 interrupt vector

requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.

Note: Writing all 0s selects non-existing conﬁguration registers. In this case write accesses to

INT_CFDATA0–7 will be ignored and read accesses will return all 0.

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Address: 0x0128

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-6. Interrupt Request Conﬁguration Data Register 0 (INT_CFDATA0)

Address: 0x0129

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-7. Interrupt Request Conﬁguration Data Register 1 (INT_CFDATA1)

Address: 0x012A

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-8. Interrupt Request Conﬁguration Data Register 2 (INT_CFDATA2)

Address: 0x012B

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-9. Interrupt Request Conﬁguration Data Register 3 (INT_CFDATA3)

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Read: Anytime

Write: Anytime

Address: 0x012C

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-10. Interrupt Request Conﬁguration Data Register 4 (INT_CFDATA4)

Address: 0x012D

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-11. Interrupt Request Conﬁguration Data Register 5 (INT_CFDATA5)

Address: 0x012E

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-12. Interrupt Request Conﬁguration Data Register 6 (INT_CFDATA6)

Address: 0x012F

76543210

RRQST 0000 PRIOLVL[2:0]

Reset 0 0 0 00001

1Please refer to the notes following the PRIOLVL[2:0] description below.

= Unimplemented or Reserved

Figure 4-13. Interrupt Request Conﬁguration Data Register 7 (INT_CFDATA7)

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4.4 Functional Description

The XINT module processes all exception requests to be serviced by the CPU module. These exceptions

include interrupt vector requests and reset vector requests. Each of these exception types and their overall

priority level is discussed in the subsections below.

Table 4-8. INT_CFDATA0–7 Field Descriptions

Field Description

RQST XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by

the XGATE module.

0 Interrupt request is handled by the CPU

1 Interrupt request is handled by the XGATE module

Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the conﬁguration register

for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit. Writing a 1 to the

location of the RQST bit in this register will be ignored and a read access will return 0.

Note: If the XGATE module is not available on the device, writing a 1 to the location of the RQST bit in this

2–0

PRIOLVL[2:0] Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits conﬁgure the interrupt request priority level of

the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”)

to provide backwards compatibility with previous S12 interrupt controllers. Please also refer to Table 4-9 for

available interrupt request priority levels.

Note: Write accesses to conﬁguration data registers of unused interrupt channels will be ignored and read

accesses will return all 0. For information about what interrupt channels are used in a speciﬁc MCU,

please refer to the Device Reference Manual of that MCU.

Note: When vectors (vector base + 0x00F0–0x00FE) are selected by writing 0xF0 to INT_CFADDR, writes to

INT_CFDATA2–7 (0x00F4–0x00FE) will be ignored and read accesses will return all 0s. The

corresponding vectors do not have conﬁguration data registers associated with them.

Note: When vectors (vector base + 0x0010–0x001E) are selected by writing 0x10 to INT_CFADDR, writes to

INT_CFDATA1–INT_CFDATA4(0x0012–0x0018)willbe ignored and read accesseswillreturn all0s.The

corresponding vectors do not have conﬁguration data registers associated with them.

Note: Write accesses to the conﬁguration register for the spurious interrupt vector request

(vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the

CPU, PRIOLVL = 7).

Table 4-9. Interrupt Priority Levels

Priority PRIOLVL2 PRIOLVL1 PRIOLVL0 Meaning

0 0 0 Interrupt request is disabled

low 0 0 1 Priority level 1

0 1 0 Priority level 2

0 1 1 Priority level 3

1 0 0 Priority level 4

1 0 1 Priority level 5

1 1 0 Priority level 6

high 1 1 1 Priority level 7

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4.4.1 S12X Exception Requests

The CPU handles both reset requests and interrupt requests. The XINT module contains registers to

conﬁgure the priority level of each I bit maskable interrupt request which can be used to implement an

interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder

is used to evaluate the priority of a pending interrupt request.

4.4.2 Interrupt Prioritization

After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2)

are enabled, are set up to be handled by the CPU and have a pre-conﬁgured priority level of 1. Exceptions

to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base

+ 0x0010) which cannot be disabled, are always handled by the CPU and have a ﬁxed priority levels. A

priority level of 0 effectively disables the associated I bit maskable interrupt request.

If more than one interrupt request is conﬁgured to the same interrupt priority level the interrupt request

with the higher vector address wins the prioritization.

The following conditions must be met for an I bit maskable interrupt request to be processed.

1. The local interrupt enabled bit in the peripheral module must be set.

2. The setup in the conﬁguration register associated with the interrupt request channel must meet the

following conditions:

a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request.

b) The priority level must be set to non zero.

c) The priority level must be greater than the current interrupt processing level in the condition

code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]).

3. The I bit in the condition code register (CCR) of the CPU must be cleared.

4. There is no access violation interrupt request pending.

5. There is no SYS, SWI, BDM, TRAP, or XIRQ request pending.

NOTE

All non I bit maskable interrupt requests always have higher priority than

I bit maskable interrupt requests. If an I bit maskable interrupt request is

interrupted by a non I bit maskable interrupt request, the currently active

interrupt processing level (IPL) remains unaffected. It is possible to nest

non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.

4.4.2.1 Interrupt Priority Stack

The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This

way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The

new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel

which is conﬁgured to be handled by the CPU. The copying takes place when the interrupt vector is

fetched. The previous IPL is automatically restored by executing the RTI instruction.

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4.4.3 XGATE Requests

If the XGATE module is implemented on the device, the XINT module is also used to process all exception

requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed

in the subsections below.

4.4.3.1 XGATE Request Prioritization

An interrupt request channel is conﬁgured to be handled by the XGATE module, if the RQST bit of the

associated conﬁguration register is set to 1 (please refer to Section 4.3.2.4, “Interrupt Request

Conﬁguration Data Registers (INT_CFDATA0–7)”). The priority level conﬁguration (PRIOLVL) for this

channel becomes the XGATE priority which will be used to determine the highest priority XGATE request

to be serviced next by the XGATE module. Additionally, XGATE interrupts may be raised by the XGATE

module by setting one or more of the XGATE channel interrupt ﬂags (by using the SIF instruction). This

will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the

channel ID number corresponds to the highest set channel interrupt ﬂag, if the XGIE and channel RQST

bits are set.

The shared interrupt priority for the XGATE interrupt requests is taken from the XGATE interrupt priority

conﬁguration register (please refer to Section 4.3.2.2, “XGATE Interrupt Priority Conﬁguration Register

(INT_XGPRIO)”). If more than one XGATE interrupt request channel becomes active at the same time,

the channel with the highest vector address wins the prioritization.

4.4.4 Priority Decoders

The XINT module contains priority decoders to determine the priority for all interrupt requests pending

for the respective target.

There are two priority decoders, one for each interrupt request target, CPU or XGATE. The function of

both priority decoders is basically the same with one exception: the priority decoder for the XGATE

module does not take the current XGATE thread processing level into account. Instead, XGATE requests

are handed to the XGATE module including a 1-bit priority identiﬁer. The XGATE module uses this

additional information to decide if the new request can interrupt a currently running thread. The 1-bit

priority identiﬁer corresponds to the most signiﬁcant bit of the priority level conﬁguration of the requesting

channel. This means that XGATE requests with priority levels 4, 5, 6 or 7 can interrupt running XGATE

threads with priority levels 1, 2 and 3.

A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher

priority interrupt request could override the original exception which caused the CPU to request the vector.

In this case, the CPU will receive the highest priority vector and the system will process this exception

instead of the original request.

If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive

after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the

CPU will default to that of the spurious interrupt vector.

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NOTE

Care must be taken to ensure that all exception requests remain active until

the system begins execution of the applicable service routine; otherwise, the

exception request may not get processed at all or the result may be a

spurious interrupt request (vector at address (vector base + 0x0010)).

4.4.5 Reset Exception Requests

The XINT module supports three system reset exception request types (for details please refer to the Clock

and Reset Generator module (CRG)):

1. Pin reset, power-on reset, low-voltage reset, or illegal address reset

2. Clock monitor reset request

3. COP watchdog reset request

4.4.6 Exception Priority

The priority (from highest to lowest) and address of all exception vectors issued by the XINT module upon

request by the CPU is shown in Table 4-10. Generally, all non-maskable interrupts have higher priorities

than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code

trap request, SWI/BGND request, SYS request) there is no real priority deﬁned because they cannot occur

simultaneously (the S12XCPU executes one instruction at a time).

Table 4-10. Exception Vector Map and Priority

Vector Address1

116 bits vector address based

Source

0xFFFE Pin reset, power-on reset, low-voltage reset, illegal address reset

0xFFFC Clock monitor reset

0xFFFA COP watchdog reset

(Vector base + 0x00F8) Unimplemented op-code trap

(Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request

(Vector base + 0x0012) System call interrupt instruction (SYS)

(Vector base + 0x0018) (reserved for future use)

(Vector base + 0x0016) XGATE Access violation interrupt request2

2only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor

(Vector base + 0x0014) CPU Access violation interrupt request3

3only implemented if device features a Memory Protection Unit (MPU)

(Vector base + 0x00F4) XIRQ interrupt request

(Vector base + 0x00F2) IRQ interrupt request

(Vector base +

0x00F0–0x001A) Device speciﬁc I bit maskable interrupt sources (priority determined by the associated

conﬁguration registers, in descending order)

(Vector base + 0x0010) Spurious interrupt

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4.5 Initialization/Application Information

4.5.1 Initialization

After system reset, software should:

• Initialize the interrupt vector base register if the interrupt vector table is not located at the default

location (0xFF10–0xFFF9).

• Initialize the interrupt processing level conﬁguration data registers (INT_CFADDR,

INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request

target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.

• If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and

conﬁgure the XGATE module (please refer the XGATE Block Guide for details).

• Enable I maskable interrupts by clearing the I bit in the CCR.

• Enable the X maskable interrupt by clearing the X bit in the CCR (if required).

4.5.2 Interrupt Nesting

The interrupt request priority level scheme makes it possible to implement priority based interrupt request

nesting for the I bit maskable interrupt requests handled by the CPU.

• I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,

so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 4-

14 for an example using up to three nested interrupt requests).

I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per

default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the

I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can

interrupt the current ISR.

An ISR of an interruptible I bit maskable interrupt request could basically look like this:

• Service interrupt, e.g., clear interrupt ﬂags, copy data, etc.

• Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with

higher priority)

• Process data

• Return from interrupt by executing the instruction RTI

Interrupt (S12XINTV2)

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Figure 4-14. Interrupt Processing Example

4.5.3 Wake Up from Stop or Wait Mode

4.5.3.1 CPU Wake Up from Stop or Wait Mode

Every I bit maskable interrupt request which is conﬁgured to be handled by the CPU is capable of waking

the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualiﬁed to wake

up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:

• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.

• An I bit maskable interrupt is ignored if it is conﬁgured to a priority level below or equal to the

current IPL in CCR.

• I bit maskable interrupt requests which are conﬁgured to be handled by the XGATE module are not

capable of waking up the CPU.

The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the

X bit in CCR is set. If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in

the CCR set, the associated ISR is not called. The CPU then resumes program execution with the

instruction following the WAI or STOP instruction. This features works following the same rules like any

interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at

least until the system begins execution of the instruction following the WAI or STOP instruction;

otherwise, wake-up may not occur.

4.5.3.2 XGATE Wake Up from Stop or Wait Mode

Interrupt request channels which are conﬁgured to be handled by the XGATE module are capable of

waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect

the state of the CPU.

Reset

L1 (Pending)

L3 (Pending)

RTI

Stacked IPL

Processing Levels

IPL in CCR

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Chapter 5

Background Debug Module (S12XBDMV2)

5.1 Introduction

This section describes the functionality of the background debug module (BDM) sub-block of the

HCS12X core platform.

The background debug module (BDM) sub-block is a single-wire, background debug system implemented

in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD

pin.

The BDM has enhanced capability for maintaining synchronization between the target and host while

allowing more ﬂexibility in clock rates. This includes a sync signal to determine the communication rate

and a handshake signal to indicate when an operation is complete. The system is backwards compatible to

the BDM of the S12 family with the following exceptions:

• TAGGO command no longer supported by BDM

• External instruction tagging feature now part of DBG module

• BDM register map and register content extended/modiﬁed

• Global page access functionality

• Enabled but not active out of reset in emulation modes (if modes available)

• CLKSW bit set out of reset in emulation modes (if modes available).

• Family ID readable from ﬁrmware ROM at global address 0x7FFF0F (value for HCS12X devices

is 0xC1)

5.1.1 Features

The BDM includes these distinctive features:

• Single-wire communication with host development system

• Enhanced capability for allowing more ﬂexibility in clock rates

• SYNC command to determine communication rate

• GO_UNTIL command

• Hardware handshake protocol to increase the performance of the serial communication

Table 5-1. Revision History

Revision

Number Revision Date Sections

Affected Description of Changes

V02.00 07 Mar 2006 - First version of S12XBDMV2

V02.01 14 May 2008 - Introduced standardized Revision History Table

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• Active out of reset in special single chip mode

• Nine hardware commands using free cycles, if available, for minimal CPU intervention

• Hardware commands not requiring active BDM

• 14 ﬁrmware commands execute from the standard BDM ﬁrmware lookup table

• Software control of BDM operation during wait mode

• Software selectable clocks

• Global page access functionality

• Enabled but not active out of reset in emulation modes (if modes available)

• CLKSW bit set out of reset in emulation modes (if modes available).

• When secured, hardware commands are allowed to access the register space in special single chip

mode, if the non-volatile memory erase test fail.

• Family ID readable from ﬁrmware ROM at global address 0x7FFF0F (value for HCS12X devices

is 0xC1)

• BDM hardware commands are operational until system stop mode is entered (all bus masters are

in stop mode)

5.1.2 Modes of Operation

BDM is available in all operating modes but must be enabled before ﬁrmware commands are executed.

Some systems may have a control bit that allows suspending thefunction during background debug mode.

5.1.2.1 Regular Run Modes

All of these operations refer to the part in run mode and not being secured. The BDM does not provide

controls to conserve power during run mode.

• Normal modes

General operation of the BDM is available and operates the same in all normal modes.

• Special single chip mode

In special single chip mode, background operation is enabled and active out of reset. This allows

programming a system with blank memory.

• Emulation modes (if modes available)

In emulation mode, background operation is enabled but not active out of reset. This allows

debugging and programming a system in this mode more easily.

5.1.2.2 Secure Mode Operation

If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run

mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or

EEPROM) other than allowing erasure. For more information please see Section 5.4.1, “Security”.

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5.1.2.3 Low-Power Modes

The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters

are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all

BDM ﬁrmware commands as well as the hardware BACKGROUND command can not be used

respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and

write commands are available. Also the CPU can not enter a low power mode during BDM active mode.

If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled

and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft

reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM

is now ready to receive a new command.

5.1.3 Block Diagram

A block diagram of the BDM is shown in Figure 5-1.

Figure 5-1. BDM Block Diagram

5.2 External Signal Description

A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate

with the BDM system. During reset, this pin is a mode select input which selects between normal and

special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the

background debug mode.

ENBDM

CLKSW

BDMACT

TRACE

SDV

16-Bit Shift Register

BKGD

Host

System Serial

Interface Data

Control

UNSEC

BDMSTS

Instruction Code

and

Execution

Standard BDM Firmware

LOOKUP TABLE

Secured BDM Firmware

LOOKUP TABLE

Bus Interface

and

Control Logic

Address

Data

Control

Clocks

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5.3 Memory Map and Register Deﬁnition

5.3.1 Module Memory Map

Table 5-2 shows the BDM memory map when BDM is active.

5.3.2 Register Descriptions

A summary of the registers associated with the BDM is shown in Figure 5-2. Registers are accessed by

host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.

Table 5-2. BDM Memory Map

Global Address Module Size

(Bytes)

0x7FFF00–0x7FFF0B BDM registers 12

0x7FFF0C–0x7FFF0E BDM ﬁrmware ROM 3

0x7FFF0F Family ID (part of BDM ﬁrmware ROM) 1

0x7FFF10–0x7FFFFF BDM ﬁrmware ROM 240

Global

Address Register

Name Bit 7 6 5 4 3 2 1 Bit 0

0x7FFF00 Reserved R X X X X X X 0 0

0x7FFF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE CLKSW UNSEC 0

0x7FFF02 Reserved R X X X X X X X X

0x7FFF03 Reserved R X X X X X X X X

0x7FFF04 Reserved R X X X X X X X X

0x7FFF05 Reserved R X X X X X X X X

0x7FFF06 BDMCCRL R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

= Unimplemented, Reserved = Implemented (do not alter)

X = Indeterminate 0 = Always read zero

Figure 5-2. BDM Register Summary

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5.3.2.1 BDM Status Register (BDMSTS)

Figure 5-3. BDM Status Register (BDMSTS)

0x7FFF07 BDMCCRH R 0 0 0 0 0 CCR10 CCR9 CCR8

0x7FFF08 BDMGPR R BGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0

0x7FFF09 Reserved R 0 0 0 0 0 0 0 0

0x7FFF0A Reserved R 0 0 0 0 0 0 0 0

0x7FFF0B Reserved R 0 0 0 0 0 0 0 0

7 6 543 2 1 0

RENBDM BDMACT 0SDVTRACE CLKSW UNSEC 0

Reset

Special Single-Chip Mode 01

1ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but

fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard ﬁrmware before a BDM command

can be fully transmitted and executed.

1000 0 03

3UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,

else it is 0 and can only be read if not secure (see also bit description).

Emulation Modes

(if modes available) 1 0 000 12

2CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when

secured if emulation modes available.

0 0

All Other Modes 0 0 000 0 0 0

= Unimplemented, Reserved = Implemented (do not alter)

0 = Always read zero

Global

Address Register

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented, Reserved = Implemented (do not alter)

X = Indeterminate 0 = Always read zero

Figure 5-2. BDM Register Summary (continued)

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Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured, but subject to the following:

— ENBDM should only be set via a BDM hardware command if the BDM ﬁrmware commands

are needed. (This does not apply in special single chip and emulation modes).

— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by

the standard BDM ﬁrmware lookup table upon exit from BDM active mode.

— CLKSW can only be written via BDM hardware WRITE_BD commands.

— All other bits, while writable via BDM hardware or standard BDM ﬁrmware write commands,

should only be altered by the BDM hardware or standard ﬁrmware lookup table as part of BDM

command execution.

Table 5-3. BDMSTS Field Descriptions

Field Description

ENBDM Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made

active to allow ﬁrmware commands to be executed. When disabled, BDM cannot be made active but BDM

hardware commands are still allowed.

0 BDM disabled

1 BDM enabled

Note: ENBDM is set by the ﬁrmware out of reset in special single chip mode. In emulation modes (if modes

available) the ENBDM bit is set by BDM hardware out of reset. In special single chip mode with the device

secured, this bit will not be set by the ﬁrmware until after the non-volatile memory erase verify tests are

complete. In emulation modes (if modes available) with the device secured, the BDM operations are

blocked.

BDMACT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM ﬁrmware lookup table is

then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the

standard BDM ﬁrmware as part of the exit sequence to return to user code and remove the BDM memory from

the map.

0 BDM not active

1 BDM active

SDV Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as

part of a ﬁrmware or hardware read command or after data has been received as part of a ﬁrmware or hardware

write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used

by the standard BDM ﬁrmware to control program ﬂow execution.

0 Data phase of command not complete

1 Data phase of command is complete

TRACE TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 ﬁrmware

command is ﬁrst recognized. It will stay set until BDM ﬁrmware is exited by one of the following BDM commands:

GO or GO_UNTIL.

0 TRACE1 command is not being executed

1 TRACE1 command is being executed

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CLKSW Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware

BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the

command send to change the clock source should occur before the next command can be send. The delay

should be obtained no matter which bit is modiﬁed to effectively change the clock source (either PLLSEL bit or

CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent

BDM communications.

Table 5-4 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG

module, the bit is part of the CLKSEL register) bits.

Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial

interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency

restriction on the alternate clock which was required on previous versions. Refer to the device

speciﬁcation to determine which clock connects to the alternate clock source input.

Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new

rate for the write command which changes it.

Note: In emulation modes (if modes available), the CLKSW bit will be set out of RESET.

UNSEC Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure

ﬁrmware. It is in a zero state as secure mode is entered so that the secure BDM ﬁrmware lookup table is enabled

and put into the memory map overlapping the standard BDM ﬁrmware lookup table.

The secure BDM ﬁrmware lookup table veriﬁes that the non-volatile memories (e.g. on-chip EEPROM and/or

Flash EEPROM) are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start

of the standard BDM ﬁrmware lookup table and the secure BDM ﬁrmware lookup table is turned off. If the erase

test fails, the UNSEC bit will not be asserted.

0 System is in a secured mode.

1 System is in a unsecured mode.

Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip

Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the

system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect

when the security byte in the Flash EEPROM is conﬁgured for unsecure mode.

Table 5-4. BDM Clock Sources

PLLSEL CLKSW BDMCLK

0 0 Bus clock dependent on oscillator

0 1 Bus clock dependent on oscillator

1 0 Alternate clock (refer to the device speciﬁcation to determine the alternate clock source)

1 1 Bus clock dependent on the PLL

Table 5-3. BDMSTS Field Descriptions (continued)

Field Description

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5.3.2.2 BDM CCR LOW Holding Register (BDMCCRL)

Figure 5-4. BDM CCR LOW Holding Register (BDMCCRL)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

NOTE

When BDM is made active, the CPU stores the content of its CCRLregister

in the BDMCCRL register. However, out of special single-chip reset, the

BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the

CCRL register in this CPU mode. Out of reset in all other modes the

BDMCCRL register is read zero.

When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte

of the condition code register of the user’s program. It is also used for temporary storage in the standard

BDM ﬁrmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.

5.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH)

Figure 5-5. BDM CCR HIGH Holding Register (BDMCCRH)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

When entering background debug mode, the BDM CCR HIGH holding register is used to save the high

byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be

written to modify the CCR value.

7 6 5 4 3 2 1 0

RCCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

Reset

Special Single-Chip Mode 1 1 0 0 1 0 0 0

All Other Modes 0 0 0 0 0 0 0 0

76543210

R 0 0 0 0 0 CCR10 CCR9 CCR8

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

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5.3.2.4 BDM Global Page Index Register (BDMGPR)

Figure 5-6. BDM Global Page Register (BDMGPR)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

5.3.3 Family ID Assignment

The family ID is a 8-bit value located in the ﬁrmware ROM (at global address: 0x7FFF0F). The read-only

value is a unique family ID which is 0xC1 for S12X devices.

5.4 Functional Description

The BDM receives and executes commands from a host via a single wire serial interface. There are two

types of BDM commands: hardware and ﬁrmware commands.

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode, see Section 5.4.3, “BDM Hardware Commands”. Target system memory

includes all memory that is accessible by the CPU.

Firmware commands are used to read and write CPU resources and to exit from active background debug

mode, see Section 5.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the

accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).

Hardware commands can be executed at any time and in any mode excluding a few exceptions as

highlighted (see Section 5.4.3, “BDM Hardware Commands”) and in secure mode (see Section 5.4.1,

“Security”). Firmware commands can only be executed when the system is not secure and is in active

background debug mode (BDM).

7 6 5 4 3 2 1 0

RBGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0

Reset 0 0 0 0 0 0 0 0

Table 5-5. BDMGPR Field Descriptions

Field Description

BGAE BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and ﬁrmware

read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and

WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.

0 BDM Global Access disabled

1 BDM Global Access enabled

6–0

BGP[6:0] BDM Global Page Index Bits 6–0 — These bits deﬁne the extended address bits from 22 to 16. For more

detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.

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5.4.1 Security

If the user resets into special single chip mode with the system secured, a secured mode BDM ﬁrmware

lookup table is brought into the map overlapping a portion of the standard BDM ﬁrmware lookup table.

The secure BDM ﬁrmware veriﬁes that the on-chip non-volatile memory (e.g. EEPROM and Flash

EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program

jumps to the start of the standard BDM ﬁrmware and the secured mode BDM ﬁrmware is turned off and

all BDM commands are allowed. If the non-volatile memory does not verify as erased, the BDM ﬁrmware

sets the ENBDM bit, without asserting UNSEC, and the ﬁrmware enters a loop. This causes the BDM

hardware commands to become enabled, but does not enable the ﬁrmware commands. This allows the

BDM hardware to be used to erase the non-volatile memory.

BDM operation is not possible in any other mode than special single chip mode when the device is secured.

The device can be unsecured via BDM serial interface in special single chip mode only. For more

information regarding security, please see the S12X_9SEC Block Guide.

5.4.2 Enabling and Activating BDM

The system must be in active BDM to execute standard BDM ﬁrmware commands. BDM can be activated

only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)

interface, using a hardware command such as WRITE_BD_BYTE.

After being enabled, BDM is activated by one of the following1:

• Hardware BACKGROUND command

• CPU BGND instruction

• External instruction tagging mechanism2

• Breakpoint force or tag mechanism2

When BDM is activated, the CPU ﬁnishes executing the current instruction and then begins executing the

ﬁrmware in the standard BDM ﬁrmware lookup table. When BDM is activated by a breakpoint, the type

of breakpoint used determines if BDM becomes active before or after execution of the next instruction.

NOTE

If an attempt is made to activate BDM before being enabled, the CPU

resumes normal instruction execution after a brief delay. If BDM is not

enabled, any hardware BACKGROUND commands issued are ignored by

the BDM and the CPU is not delayed.

In active BDM, the BDM registers and standard BDM ﬁrmware lookup table are mapped to addresses

0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses

these registers which are readable anytime by the BDM. However, these registers are not readable by user

programs.

1. BDM is enabled and active immediately out of special single-chip reset.

2. This method is provided by the S12X_DBG module.

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5.4.3 BDM Hardware Commands

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode. Target system memory includes all memory that is accessible by the CPU on the

SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control

registers, and all external memory.

Hardware commands are executed with minimal or no CPU intervention and do not require the system to

be in active BDM for execution, although, they can still be executed in this mode. When executing a

hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not

disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is

momentarily frozen so that the BDM can steal a cycle. When the BDM ﬁnds a free cycle, the operation

does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,

if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the

BDM found a free cycle.

The BDM hardware commands are listed in Table 5-6.

The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations

are not normally in the system memory map but share addresses with the application in memory. To

distinguish between physical memory locations that share the same address, BDM memory resources are

enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM

locations unobtrusively, even if the addresses conﬂict with the application memory map.

Table 5-6. Hardware Commands

Command Opcode

(hex) Data Description

BACKGROUND 90 None Enter background mode if ﬁrmware is enabled. If enabled, an ACK will be

issued when the part enters active background mode.

ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed.

ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse.

READ_BD_BYTE E4 16-bit address

16-bit data out Read from memory with standard BDM ﬁrmware lookup table in map.

Odd address data on low byte; even address data on high byte.

READ_BD_WORD EC 16-bit address

16-bit data out Read from memory with standard BDM ﬁrmware lookup table in map.

Must be aligned access.

READ_BYTE E0 16-bit address

16-bit data out Read from memory with standard BDM ﬁrmware lookup table out of map.

Odd address data on low byte; even address data on high byte.

READ_WORD E8 16-bit address

16-bit data out Read from memory with standard BDM ﬁrmware lookup table out of map.

Must be aligned access.

WRITE_BD_BYTE C4 16-bit address

16-bit data in Write to memory with standard BDM ﬁrmware lookup table in map.

Odd address data on low byte; even address data on high byte.

WRITE_BD_WORD CC 16-bit address

16-bit data in Write to memory with standard BDM ﬁrmware lookup table in map.

Must be aligned access.

WRITE_BYTE C0 16-bit address

16-bit data in Write to memory with standard BDM ﬁrmware lookup table out of map.

Odd address data on low byte; even address data on high byte.

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5.4.4 Standard BDM Firmware Commands

Firmware commands are used to access and manipulate CPU resources. The system must be in active

BDM to execute standard BDM ﬁrmware commands, see Section 5.4.2, “Enabling and Activating BDM”.

Normal instruction execution is suspended while the CPU executes the ﬁrmware located in the standard

BDM ﬁrmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM.

As the system enters active BDM, the standard BDM ﬁrmware lookup table and BDM registers become

visible in the on-chip memory map at 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard

BDM ﬁrmware. The standard BDM ﬁrmware watches for serial commands and executes them as they are

received.

The ﬁrmware commands are shown in Table 5-7.

WRITE_WORD C8 16-bit address

16-bit data in Write to memory with standard BDM ﬁrmware lookup table out of map.

Must be aligned access.

NOTE:

If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is

complete for all BDM WRITE commands.

Table 5-6. Hardware Commands (continued)

Command Opcode

(hex) Data Description

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5.4.5 BDM Command Structure

Hardware and ﬁrmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a

16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte

or word implication in the command name.

8-bit reads return 16-bits of data, of which, only one byte will contain valid

data. If reading an even address, the valid data will appear in the MSB. If

reading an odd address, the valid data will appear in the LSB.

Table 5-7. Firmware Commands

Command1

1If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is

complete for all BDM WRITE commands.

Opcode

(hex) Data Description

READ_NEXT2

2When the ﬁrmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources

are accessed rather than user code. Writing BDM ﬁrmware is not possible.

62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.

READ_PC 63 16-bit data out Read program counter.

READ_D 64 16-bit data out Read D accumulator.

READ_X 65 16-bit data out Read X index register.

READ_Y 66 16-bit data out Read Y index register.

READ_SP 67 16-bit data out Read stack pointer.

WRITE_NEXT<f-

helvetica><st-

superscript>

42 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location

pointed to by X.

WRITE_PC 43 16-bit data in Write program counter.

WRITE_D 44 16-bit data in Write D accumulator.

WRITE_X 45 16-bit data in Write X index register.

WRITE_Y 46 16-bit data in Write Y index register.

WRITE_SP 47 16-bit data in Write stack pointer.

GO 08 none Go to user program. If enabled, ACK will occur when leaving active

background mode.

GO_UNTIL3

3System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode).

The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL”

condition (BDM active again) is reached (see Section 5.4.7, “Serial Interface Hardware Handshake Protocol” last Note).

0C none Go to user program. If enabled, ACK will occur upon returning to active

background mode.

TRACE1 10 none Execute one user instruction then return to active BDM. If enabled,

ACK will occur upon returning to active background mode.

TAGGO -> GO 18 none (Previous enable tagging and go to user program.)

This command will be deprecated and should not be used anymore.

Opcode will be executed as a GO command.

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180 Freescale Semiconductor

16-bit misaligned reads and writes are generally not allowed. If attempted

by BDM hardware command, the BDM will ignore the least signiﬁcant bit

of the address and will assume an even address from the remaining bits.

For devices with external bus:

The following cycle count information is only valid when the external wait

function is not used (see wait bit of EBI sub-block). During an external wait

the BDM can not steal a cycle. Hence be careful with the external wait

function if the BDM serial interface is much faster than the bus, because of

the BDM soft-reset after time-out (see Section 5.4.11, “Serial

Communication Time Out”).

For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending

the address before attempting to obtain the read data. This is to be certain that valid data is available in the

BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait

150 bus clock cycles after sending the data to be written before attempting to send a new command. This

is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle

delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a

free cycle before stealing a cycle.

For ﬁrmware read commands, the external host should wait at least 48 bus clock cycles after sending the

command opcode and before attempting to obtain the read data. This includes the potential of extra cycles

when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port

replacement unit) in emulation modes (if modes available). The 48 cycle wait allows enough time for the

requested data to be made available in the BDM shift register, ready to be shifted out.

NOTE

This timing has increased from previous BDM modules due to the new

capability in which the BDM serial interface can potentially run faster than

the bus. On previous BDM modules this extra time could be hidden within

the serial time.

For ﬁrmware write commands, the external host must wait 36 bus clock cycles after sending the data to be

written before attempting to send a new command. This is to avoid disturbing the BDM shift register

before the write has been completed.

The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before

starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM

ﬁrmware lookup table and resume execution of the user code. Disturbing the BDM shift register

prematurely may adversely affect the exit from the standard BDM ﬁrmware lookup table.

NOTE

If the bus rate of the target processor is unknown or could be changing or the

external wait function is used, it is recommended that the ACK

(acknowledge function) is used to indicate when an operation is complete.

When using ACK, the delay times are automated.

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Figure 5-7 represents the BDM command structure. The command blocks illustrate a series of eight bit

times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles

in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.1

Figure 5-7. BDM Command Structure

5.4.6 BDM Serial Interface

The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode

select input which selects between normal and special modes of operation. After reset, this pin becomes

the dedicated serial interface pin for the BDM.

The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see

Section 5.3.2.1, “BDM Status Register (BDMSTS)”. This clock will be referred to as the target clock in

the following explanation.

The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on

the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is

transmitted or received. Data is transferred most signiﬁcant bit (MSB) ﬁrst at 16 target clock cycles per

bit. The interface times out if 512 clock cycles occur between falling edges from the host.

The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all

times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically

drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide

brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host

for transmit cases and the target for receive cases.

1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 5.4.6, “BDM Serial Interface”

and Section 5.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.

Hardware

Firmware

GO,

48-BC

BC = Bus Clock Cycles

Command Address

150-BC

Delay

DELAY

8 Bits

AT ~16 TC/Bit

16 Bits

AT ~16 TC/Bit

16 Bits

AT ~16 TC/Bit

Command Address Data Next

Data

Read

Write

Read

Write

TRACE

Command Next

Command Data

76-BC

Delay

Command

150-BC

Delay

36-BC

DELAY

Command

Data

Command

TC = Target Clock Cycles

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182 Freescale Semiconductor

The timing for host-to-target is shown in Figure 5-8 and that of target-to-host in Figure 5-9 and

Figure 5-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since

the host and target are operating from separate clocks, it can take the target system up to one full clock

cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the

host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle

earlier. Synchronization between the host and target is established in this manner at the start of every bit

time.

Figure 5-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a

target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the

host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten

target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic

requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1

transmission.

Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven

signals.

Figure 5-8. BDM Host-to-Target Serial Bit Timing

The receive cases are more complicated. Figure 5-9 shows the host receiving a logic 1 from the target

system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-

generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the

BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must

release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the

perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it

started the bit time.

Target Senses Bit

10 Cycles

Synchronization

Uncertainty

BDM Clock

(Target MCU)

Host

Transmit 1

Host

Transmit 0

Perceived

Start of Bit Time Earliest

Start of

Next Bit

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Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1)

High-Impedance

Earliest

Start of

Next Bit

R-C Rise

10 Cycles

Host Samples

BKGD Pin

Perceived

Start of Bit Time

BKGD Pin

BDM Clock

(Target MCU)

Host

Drive to

BKGD Pin

Target System

Speedup

Pulse

High-Impedance

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184 Freescale Semiconductor

Figure 5-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,

there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit

time as perceived by the target. The host initiates the bit time but the target ﬁnishes it. Since the target

wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then brieﬂy drives

it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting

the bit time.

Figure 5-10. BDM Target-to-Host Serial Bit Timing (Logic 0)

5.4.7 Serial Interface Hardware Handshake Protocol

BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM

clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to

provide a handshake protocol in which the host could determine when an issued command is executed by

the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at

the slowest possible rate the clock could be running. This sub-section will describe the hardware

handshake protocol.

The hardware handshake protocol signals to the host controller when an issued command was successfully

executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a

brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued

by the host, has been successfully executed (see Figure 5-11). This pulse is referred to as the ACK pulse.

After the ACK pulse has ﬁnished: the host can start the bit retrieval if the last issued command was a read

command, or start a new command if the last command was a write command or a control command

(BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock

cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick

of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also

that, there is no upper limit for the delay between the command and the related ACK pulse, since the

command execution depends upon the CPU bus frequency, which in some cases could be very slow

Earliest

Start of

Next Bit

BDM Clock

(Target MCU)

Host

Drive to

BKGD Pin

Perceived

Start of Bit Time

10 Cycles

Host Samples

BKGD Pin

Target System

Drive and

Speedup Pulse

High-Impedance

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Freescale Semiconductor 185

compared to the serial communication rate. This protocol allows a great ﬂexibility for the POD designers,

since it does not rely on any accurate time measurement or short response time to any event in the serial

communication.

Figure 5-11. Target Acknowledge Pulse (ACK)

NOTE

If the ACK pulse was issued by the target, the host assumes the previous

command was executed. If the CPU enters wait or stop prior to executing a

hardware command, the ACK pulse will not be issued meaning that the

BDM command was not executed. After entering wait or stop mode, the

BDM command is no longer pending.

Figure 5-12 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE

instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the

address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed

(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the

BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.

After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form

of a word and the host needs to determine which is the appropriate byte based on whether the address was

odd or even.

Figure 5-12. Handshake Protocol at Command Level

16 Cycles

BDM Clock

(Target MCU)

Target

Transmits

ACK Pulse High-Impedance

BKGD Pin

Minimum Delay

From the BDM Command

32 Cycles

Earliest

Start of

Next Bit

Speedup Pulse

16th Tick of the

Last Command Bit

High-Impedance

READ_BYTE

BDM Issues the

BKGD Pin Byte Address

BDM Executes the

READ_BYTE Command

Host Target

HostTarget

BDM Decodes

the Command

ACK Pulse (out of scale)

Host Target

(2) Bytes are

Retrieved New BDM

Command

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186 Freescale Semiconductor

Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK

handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware

handshake protocol in Figure 5-11 speciﬁes the timing when the BKGD pin is being driven, so the host

should follow this timing constraint in order to avoid the risk of an electrical conﬂict in the BKGD pin.

NOTE

The only place the BKGD pin can have an electrical conﬂict is when one

side is driving low and the other side is issuing a speedup pulse (high). Other

“highs” are pulled rather than driven. However, at low rates the time of the

speedup pulse can become lengthy and so the potential conﬂict time

becomes longer as well.

The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not

acknowledge by an ACK pulse, the host needs to abort the pending command ﬁrst in order to be able to

issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command

(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.

Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be

issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any

possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol

provides a mechanism in which a command, and its corresponding ACK, can be aborted.

NOTE

The ACK pulse does not provide a time out. This means for the GO_UNTIL

command that it can not be distinguished if a stop or wait has been executed

(command discarded and ACK not issued) or if the “UNTIL” condition

(BDM active) is just not reached yet. Hence in any case where the ACK

pulse of a command is not issued the possible pending command should be

aborted before issuing a new command. See the handshake abort procedure

described in Section 5.4.8, “Hardware Handshake Abort Procedure”.

5.4.8 Hardware Handshake Abort Procedure

The abort procedure is based on the SYNC command. In order to abort a command, which had not issued

the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving

it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a

speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,

see Section 5.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command

and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been

completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it

can not be guaranteed that the pending command is aborted when issuing a SYNC before the

corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins

until it is ﬁnished and the corresponding ACK pulse is issued. The latency time depends on the ﬁrmware

READ or WRITE command that is issued and if the serial interface is running on a different clock rate

than the bus. When the SYNC command starts during this latency time the READ or WRITE command

will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or

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Freescale Semiconductor 187

GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the

SYNC command.

Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in

the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.

The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short

abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative

edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending

command will be aborted along with the ACK pulse. The potential problem with this abort procedure is

when there is a conﬂict between the ACK pulse and the short abort pulse. In this case, the target may not

perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,

READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new

command after the abort pulse was issued, while the target expects the host to retrieve the accessed

memory byte. In this case, host and target will run out of synchronism. However, if the command to be

aborted is not a read command the short abort pulse could be used. After a command is aborted the target

assumes the next negative edge, after the abort pulse, is the ﬁrst bit of a new BDM command.

NOTE

The details about the short abort pulse are being provided only as a reference

for the reader to better understand the BDM internal behavior. It is not

recommended that this procedure be used in a real application.

Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)

does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC

very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to

assure the SYNC pulse will not be misinterpreted by the target. See Section 5.4.9, “SYNC — Request

Timed Reference Pulse”.

Figure 5-13 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE

command. Note that, after the command is aborted a new command could be issued by the host computer.

Figure 5-13. ACK Abort Procedure at the Command Level

NOTE

Figure 5-13 does not represent the signals in a true timing scale

Figure 5-14 shows a conﬂict between the ACK pulse and the SYNC request pulse. This conﬂict could

occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.

READ_BYTE READ_STATUSBKGD Pin Memory Address New BDM Command

New BDM Command

Host Target Host Target Host Target

SYNC Response

From the Target

(Out of Scale)

BDM Decode

and Starts to Execute

the READ_BYTE Command

READ_BYTE CMD is Aborted

by the SYNC Request

(Out of Scale)

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Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being

connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this

case, there is an electrical conﬂict between the ACK speedup pulse and the SYNC pulse. Since this is not

a probable situation, the protocol does not prevent this conﬂict from happening.

Figure 5-14. ACK Pulse and SYNC Request Conﬂict

NOTE

This information is being provided so that the MCU integrator will be aware

that such a conﬂict could eventually occur.

The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE

BDM commands. This provides backwards compatibility with the existing POD devices which are not

able to execute the hardware handshake protocol. It also allows for new POD devices, that support the

hardware handshake protocol, to freely communicate with the target device. If desired, without the need

for waiting for the ACK pulse.

The commands are described as follows:

• ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse

when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the

ACK pulse as a response.

• ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst

case delay time at the appropriate places in the protocol.

The default state of the BDM after reset is hardware handshake protocol disabled.

All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then

ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data

has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See

Section 5.4.3, “BDM Hardware Commands” and Section 5.4.4, “Standard BDM Firmware Commands”

for more information on the BDM commands.

BDM Clock

(Target MCU)

Target MCU

Drives to

BKGD Pin

16 Cycles

Speedup Pulse

High-Impedance

Host

Drives SYNC

To BKGD Pin

ACK Pulse

Host SYNC Request Pulse

At Least 128 Cycles

Electrical Conﬂict

Host and

Target Drive

to BKGD Pin

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The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be

used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is

issued in response to this command, the host knows that the target supports the hardware handshake

protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In

this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid

command.

The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to

background mode. The ACK pulse related to this command could be aborted using the SYNC command.

The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse

related to this command could be aborted using the SYNC command.

The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this

case, is issued when the CPU enters into background mode. This command is an alternative to the GO

command and should be used when the host wants to trace if a breakpoint match occurs and causes the

CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which

could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related

to this command could be aborted using the SYNC command.

The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode

after one instruction of the application program is executed. The ACK pulse related to this command could

be aborted using the SYNC command.

5.4.9 SYNC — Request Timed Reference Pulse

The SYNC command is unlike other BDM commands because the host does not necessarily know the

correct communication speed to use for BDM communications until after it has analyzed the response to

the SYNC command. To issue a SYNC command, the host should perform the following steps:

1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication

frequency (the lowest serial communication frequency is determined by the crystal oscillator or the

clock chosen by CLKSW.)

2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically

one cycle of the host clock.)

3. Remove all drive to the BKGD pin so it reverts to high impedance.

4. Listen to the BKGD pin for the sync response pulse.

Upon detecting the SYNC request from the host, the target performs the following steps:

1. Discards any incomplete command received or bit retrieved.

2. Waits for BKGD to return to a logic one.

3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.

4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.

5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.

6. Removes all drive to the BKGD pin so it reverts to high impedance.

The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed

for subsequent BDM communications. Typically, the host can determine the correct communication speed

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190 Freescale Semiconductor

within a few percent of the actual target speed and the communication protocol can easily tolerate speed

errors of several percent.

As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is

discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the

SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new

BDM command or the start of new SYNC request.

Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the

same as in a regular SYNC command. Note that one of the possible causes for a command to not be

acknowledged by the target is a host-target synchronization problem. In this case, the command may not

have been understood by the target and so an ACK response pulse will not be issued.

5.4.10 Instruction Tracing

When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM

ﬁrmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to

return to the standard BDM ﬁrmware and the BDM is active and ready to receive a new command. If the

TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or

tracing through the user code one instruction at a time.

If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but

no user instruction is executed. Once back in standard BDM ﬁrmware execution, the program counter

points to the ﬁrst instruction in the interrupt service routine.

Be aware when tracing through the user code that the execution of the user code is done step by step but

all peripherals are free running. Hence possible timing relations between CPU code execution and

occurrence of events of other peripherals no longer exist.

Do not trace the CPU instruction BGND used for soft breakpoints. Tracing the BGND instruction will

result in a return address pointing to BDM ﬁrmware address space.

When tracing through user code which contains stop or wait instructions the following will happen when

the stop or wait instruction is traced:

The CPU enters stop or wait mode and the TRACE1 command can not be ﬁnished before leaving

the low power mode. This is the case because BDM active mode can not be entered after CPU

executed the stop instruction. However all BDM hardware commands except the BACKGROUND

command are operational after tracing a stop or wait instruction and still being in stop or wait

mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is

operational.

As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value

points to the entry of the corresponding interrupt service routine.

In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command

will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM

active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode.

All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or

wait mode will have an ACK pulse. The handshake feature becomes disabled only when system

Background Debug Module (S12XBDMV2)

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stop mode has been reached. Hence after a system stop mode the handshake feature must be

enabled again by sending the ACK_ENABLE command.

5.4.11 Serial Communication Time Out

The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If

BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command

was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the

SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any

time-out limit.

Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as

a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge

marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock

cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting

memory or the operating mode of the MCU. This is referred to as a soft-reset.

If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will

occur causing the command to be disregarded. The data is not available for retrieval after the time-out has

occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the

behavior where the BDM is running in a frequency much greater than the CPU frequency. In this case, the

command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved

even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake

protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the

host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued

read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-

activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve

the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period,

the read command is discarded and the data is no longer available for retrieval. Any negative edge in the

BKGD pin after the time-out period is considered to be a new command or a SYNC request.

Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the

serial communication is active. This means that if a time frame higher than 512 serial clock cycles is

observed between two consecutive negative edges and the command being issued or data being retrieved

is not complete, a soft-reset will occur causing the partially received command or data retrieved to be

disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the

target as the start of a new BDM command, or the start of a SYNC request pulse.

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Chapter 6

S12X Debug (S12XDBGV3) Module

Table 6-1. Revision History

6.1 Introduction

The S12XDBG module provides an on-chip trace buffer with ﬂexible triggering capability to allow non-

intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit

architecture and allows debugging of CPU12X module operations.

Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user

conﬁgures the S12XDBG module for a debugging session over the BDM interface. Once conﬁgured the

S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,

which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be conﬁgured

over a serial interface using SWI routines.

6.1.1 Glossary

Revision

Number Revision Date Sections

Affected Description of Changes

V03.20 14 Sep 2007 6.3.2.7/6-203 - Clariﬁed reserved State Sequencer encodings.

V03.21 23 Oct 2007 6.4.2.2/6-216

6.4.2.4/6-217 - Added single databyte comparison limitation information

- Added statement about interrupt vector fetches whilst tagging.

V03.22 12 Nov 2007 6.4.5.2/6-221

6.4.5.5/6-225 - Removed LOOP1 tracing restriction NOTE.

- Added pin reset effect NOTE.

V03.23 13 Nov 2007 General - Text readability improved, typo removed.

V03.24 04 Jan 2008 6.4.5.3/6-223 - Corrected bit name.

V03.25 14 May 2008 - Updated Revision History Table format. Corrected other paragraph formats.

Table 6-2. Glossary Of Terms

Term Deﬁnition

COF Change Of Flow.

Change in the program ﬂow due to a conditional branch, indexed jump or interrupt

BDM Background Debug Mode

DUG Device User Guide, describing the features of the device into which the DBG is integrated

WORD 16 bit data entity

Data Line 64 bit data entity

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6.1.2 Overview

The comparators monitor the bus activity of the CPU12X. When a match occurs the control logic can

trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or

a breakpoint can be generated.

Independent of comparator matches a transition to Final State with associated tracing and breakpoint can

be triggered by writing to the TRIG control bit.

The trace buffer is visible through a 2-byte window in the register address map and can be read out using

standard 16-bit word reads. Tracing is disabled when the MCU system is secured.

6.1.3 Features

• Four comparators (A, B, C, and D)

— Comparators A and C compare the full address bus and full 16-bit data bus

— Comparators A and C feature a data bus mask register

— Comparators B and D compare the full address bus only

— Each comparator can be conﬁgured to monitor CPU12X buses

— Each comparator features selection of read or write access cycles

— Comparators B and D allow selection of byte or word access cycles

— Comparisons can be used as triggers for the state sequencer

• Three comparator modes

— Simple address/data comparator match mode

— Inside address range mode, Addmin ≤ Address ≤Addmax

— Outside address range match mode, Address <Addmin or Address > Addmax

• Two types of triggers

— Tagged — This triggers just before a speciﬁc instruction begins execution

— Force — This triggers on the ﬁrst instruction boundary after a match occurs.

• The following types of breakpoints

— CPU12X breakpoint entering BDM on breakpoint (BDM)

— CPU12X breakpoint executing SWI on breakpoint (SWI)

• TRIG Immediate software trigger independent of comparators

• Four trace modes

— Normal: change of ﬂow (COF) PC information is stored (see Section 6.4.5.2.1) for change of

ﬂow deﬁnition.

CPU CPU12X module

Tag Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the

execution stage a tag hit occurs.

Table 6-2. Glossary Of Terms (continued)

Term Deﬁnition

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— Loop1: same as Normal but inhibits consecutive duplicate source address entries

— Detail: address and data for all cycles except free cycles and opcode fetches are stored

— Pure PC: All program counter addresses are stored.

• 4-stage state sequencer for trace buffer control

— Tracing session trigger linked to Final State of state sequencer

— Begin, End, and Mid alignment of tracing to trigger

6.1.4 Modes of Operation

The S12XDBG module can be used in all MCU functional modes.

During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.

Thus breakpoints, comparators, and CPU12X bus tracing are disabled . When the CPU12X enters active

BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG

remains armed.

The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be

generated if the MCU is secure.

Table 6-3. Mode Dependent Restriction Summary

BDM

Enable BDM

Active MCU

Secure Comparator

Matches Enabled Breakpoints

Possible Tagging

Possible Tracing

Possible

x x 1 Yes Yes Yes No

0 0 0 Yes Only SWI Yes Yes

0 1 0 Active BDM not possible when not enabled

1 0 0 Yes Yes Yes Yes

110 No No No No

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6.1.5 Block Diagram

Figure 6-1. Debug Module Block Diagram

6.2 External Signal Description

The S12XDBG sub-module features no external signals.

6.3 Memory Map and Registers

6.3.1 Module Memory Map

A summary of the registers associated with the S12XDBG sub-block is shown in Table 6-2. Detailed

descriptions of the registers and bits are given in the subsections that follow.

Address Name Bit 7 6 5 4 3 2 1 Bit 0

0x0020 DBGC1 RARM 0reserved BDM DBGBRK reserved COMRV

W TRIG

0x0021 DBGSR R TBF 0 0 0 0 SSF2 SSF1 SSF0

0x0022 DBGTCR Rreserved TSOURCE TRANGE TRCMOD TALIGN

0x0023 DBGC2 R0000 CDCM ABCM

Figure 6-2. Quick Reference to S12XDBG Registers

S12XCPU BUS

TRACE BUFFER

BUS INTERFACE

TRIGGER

MATCH0

STATE

COMPARATOR B

COMPARATOR C

COMPARATOR D

COMPARATOR A

STATE SEQUENCER

MATCH1

MATCH2

MATCH3

TRACE

READ TRACE DATA (DBG READ DATA BUS)

CONTROL

SECURE

BREAKPOINT REQUESTS

COMPARATOR

MATCH CONTROL

TRIGGER

TAG &

TRIGGER

CONTROL

LOGIC

TAGS

TAGHITS

STATE

S12XCPU

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6.3.2 Register Descriptions

This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each

comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F

in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the

S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]

0x0024 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

0x0025 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x0026 DBGCNT R 0 CNT

0x0027 DBGSCRX R0000

SC3 SC2 SC1 SC0

0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0

0x00281DBGXCTL

(COMPA/C) R0 NDB TAG BRK RW RWE reserved COMPE

0x00282DBGXCTL

(COMPB/D) RSZE SZ TAG BRK RW RWE reserved COMPE

0x0029 DBGXAH R0 Bit 22 21 20 19 18 17 Bit 16

0x002A DBGXAM RBit 15 14 13 12 11 10 9 Bit 8

0x002B DBGXAL RBit 7 6 5 4 3 2 1 Bit 0

0x002C DBGXDH RBit 15 14 13 12 11 10 9 Bit 8

0x002D DBGXDL RBit 7 6 5 4 3 2 1 Bit 0

0x002E DBGXDHM RBit 15 14 13 12 11 10 9 Bit 8

0x002F DBGXDLM RBit 7 6 5 4 3 2 1 Bit 0

1This represents the contents if the Comparator A or C control register is blended into this address.

2This represents the contents if the Comparator B or D control register is blended into this address

Address Name Bit 7 6 5 4 3 2 1 Bit 0

Figure 6-2. Quick Reference to S12XDBG Registers

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6.3.2.1 Debug Control Register 1 (DBGC1)

Read: Anytime

Write: Bits 7, 1, 0 anytime

Bit 6 can be written anytime but always reads back as 0.

Bits 5:2 anytime S12XDBG is not armed.

NOTE

If a write access to DBGC1 with the ARM bit position set occurs

simultaneously to a hardware disarm from an internal trigger event, then the

ARM bit is cleared due to the hardware disarm.

NOTE

When disarming the S12XDBG by clearing ARM with software, the

contents of bits[5:2] are not affected by the write, since up until the write

operation, ARM = 1 preventing these bits from being written. These bits

must be cleared using a second write if required.

Address: 0x0020

76543210

RARM 0reserved BDM DBGBRK reserved COMRV

W TRIG

Reset 00000000

Figure 6-3. Debug Control Register (DBGC1)

Table 6-4. DBGC1 Field Descriptions

Field Description

ARM Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by

user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with

tracing not enabled. On setting this bit the state sequencer enters State1.

0 Debugger disarmed

1 Debugger armed

TRIG Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of

comparator signal status. When tracing is complete a forced breakpoint may be generated depending upon

DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If TSOURCE

is clear no tracing is carried out. If tracing has already commenced using BEGIN- or MID trigger alignment, it

continues until the end of the tracing session as deﬁned by the TALIGN bit settings, thus TRIG has no affect. In

secure mode tracing is disabled and writing to this bit has no effect.

0 Do not trigger until the state sequencer enters the Final State.

1 Trigger immediately .

reserved This bit is reserved, setting it has no meaning or effect.

BDM Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter

Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled

by the ENBDM bit in the BDM module, then breakpoints default to SWI.

0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.

1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI

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6.3.2.2 Debug Status Register (DBGSR)

Read: Anytime

Write: Never

DBGBRK S12XDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint

to S12XCPU upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated

on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please

refer to Section 6.4.7 for further details.

0 No breakpoint on trigger.

1 Breakpoint on trigger

1–0

COMRV Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the

8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these

bits determine which register is visible at the address 0x0027. See Table 6-5.

Table 6-5. COMRV Encoding

COMRV Visible Comparator Visible Register at 0x0027

00 Comparator A DBGSCR1

01 Comparator B DBGSCR2

10 Comparator C DBGSCR3

11 Comparator D DBGMFR

Address: 0x0021

76543210

R TBF 0 0 0 0 SSF2 SSF1 SSF0

Reset

POR —

= Unimplemented or Reserved

Figure 6-4. Debug Status Register (DBGSR)

Table 6-6. DBGSR Field Descriptions

Field Description

TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was

last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].

The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset

initialization. Other system generated resets have no affect on this bit

2–0

SSF[2:0] State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During

a debug session on each transition to a new state these bits are updated. If the debug session is ended by

software clearing the ARM bit, then these bits retain their value to reﬂect the last state of the state sequencer

before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0

andthese bits are cleared to indicate that state0 wasentered during thesession. On arming the module the state

sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-7.

Table 6-4. DBGC1 Field Descriptions (continued)

Field Description

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6.3.2.3 Debug Trace Control Register (DBGTCR)

Read: Anytime

Write: Bits 7:6 only when S12XDBG is neither secure nor armed.

Bits 5:0 anytime the module is disarmed.

WARNING

DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus

preventing proper operation.

Table 6-7. SSF[2:0] — State Sequence Flag Bit Encoding

SSF[2:0] Current State

000 State0 (disarmed)

001 State1

010 State2

011 State3

100 Final State

101,110,111 Reserved

Address: 0x0022

76543210

Rreserved TSOURCE TRANGE TRCMOD TALIGN

Reset 00000000

Figure 6-5. Debug Trace Control Register (DBGTCR)

Table 6-8. DBGTCR Field Descriptions

Field Description

TSOURCE Trace Source Control Bits — The TSOURCE enables the tracing session. If the MCU system is secured, this

bit cannot be set and tracing is inhibited.

0 No tracing selected

1 Tracing selected

5–4

TRANGE Trace Range Bits — The TRANGE bits allow ﬁltering of trace information from a selected address range when

tracing from the CPU12X in Detail Mode. To use a comparator for range ﬁltering, the corresponding COMPE

bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state

sequence triggers. See Table 6-9.

3–2

TRCMOD Trace Mode Bits — See Section 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of ﬂow

information is stored. In Loop1 Mode, change of ﬂow information is stored but redundant entries into trace

memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See

Table 6-10.

1–0

TALIGN Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a

tracing session. See Table 6-11.

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6.3.2.4 Debug Control Register2 (DBGC2)

Read: Anytime

Write: Anytime the module is disarmed.

This register conﬁgures the comparators for range matching.

Table 6-9. TRANGE Trace Range Encoding

TRANGE Tracing Range

00 Trace from all addresses (No ﬁlter)

01 Trace only in address range from $00000 to Comparator D

10 Trace only in address range from Comparator C to $7FFFFF

11 Trace only in range from Comparator C to Comparator D

Table 6-10. TRCMOD Trace Mode Bit Encoding

TRCMOD Description

00 Normal

01 Loop1

10 Detail

11 Pure PC

Table 6-11. TALIGN Trace Alignment Encoding

TALIGN Description

00 Trigger at end of stored data

01 Trigger before storing data

10 Trace buffer entries before and after trigger

11 Reserved

Address: 0x0023

76543210

R0000 CDCM ABCM

Reset 00000000

= Unimplemented or Reserved

Figure 6-6. Debug Control Register2 (DBGC2)

Table 6-12. DBGC2 Field Descriptions

Field Description

3–2

CDCM[1:0] C and D Comparator Match Control — These bits determine the C and D comparator match mapping as

described in Table 6-13.

1–0

ABCM[1:0] A and B Comparator Match Control — These bits determine the A and B comparator match mapping as

described in Table 6-14.

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6.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)

Read: Only when unlocked AND not secured AND not armed AND with the TSOURCE bit set.

Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer

contents.

Table 6-13. CDCM Encoding

CDCM Description

00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match.

01 Match2 mapped to comparator C/D inside range....... Match3 disabled.

10 Match2 mapped to comparator C/D outside range....... Match3 disabled.

11 Reserved1

1Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D

Table 6-14. ABCM Encoding

ABCM Description

00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match.

01 Match 0 mapped to comparator A/B inside range....... Match1 disabled.

10 Match 0 mapped to comparator A/B outside range....... Match1 disabled.

11 Reserved1

1Currently defaults to Match0 mapped to comparator A : Match1 mapped to comparator B

Address: 0x0024, 0x0025

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PORXXXXXXXXXXXXXXXX

Other

Resets ————————————————

Figure 6-7. Debug Trace Buffer Register (DBGTB)

Table 6-15. DBGTB Field Descriptions

Field Description

15–0

Bit[15:0] Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the

Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer

which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent

reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when

the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned

access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace

buffer address. The same is true for word reads while the debugger is armed. The POR state is undeﬁned Other

resets do not affect the trace buffer contents. .

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6.3.2.6 Debug Count Register (DBGCNT)

Read: Anytime

Write: Never

6.3.2.7 Debug State Control Registers

There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if

transitions from that state are allowed, depending upon comparator matches or tag hits, and deﬁnes the

Address: 0x0026

76543210

R 0 CNT

Reset

POR 0

0—

= Unimplemented or Reserved

Figure 6-8. Debug Count Register (DBGCNT)

Table 6-16. DBGCNT Field Descriptions

Field Description

6–0

CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.

Table 6-17 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.

When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-

trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The

DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus

should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of

valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when

reading from the trace buffer.

Table 6-17. CNT Decoding Table

TBF (DBGSR) CNT[6:0] Description

0 0000000 No data valid

0 0000001 32 bits of one line valid

0 0000010

0000100

0000110

1111100

1 line valid

2 lines valid

3 lines valid

62 lines valid

0 1111110 63 lines valid

1 0000000 64 lines valid; if using Begin trigger alignment,

ARM bit will be cleared and the tracing session ends.

1 0000010

1111110

64 lines valid,

oldest data has been overwritten by most recent data

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next state for the state sequencer following a match. The three debug state control registers are located at

the same address in the register address map (0x0027). Each register can be accessed using the COMRV

bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match ﬂag register

(DBGMFR).

6.3.2.7.1 Debug State Control Register 1 (DBGSCR1)

Read: If COMRV[1:0] = 00

Write: If COMRV[1:0] = 00 and S12XDBG is not armed.

This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the

targeted next state whilst in State1. The matches refer to the match channels of the comparator match

control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1”. Comparators must be enabled

by setting the comparator enable bit in the associated DBGXCTL control register.

Table 6-18. State Control Register Access Encoding

COMRV Visible State Control Register

00 DBGSCR1

01 DBGSCR2

10 DBGSCR3

11 DBGMFR

Address: 0x0027

76543210

R0000

SC3 SC2 SC1 SC0

Reset 00000000

= Unimplemented or Reserved

Figure 6-9. Debug State Control Register 1 (DBGSCR1)

Table 6-19. DBGSCR1 Field Descriptions

Field Description

3–0

SC[3:0] These bits select the targeted next state whilst in State1, based upon the match event.

Table 6-20. State1 Sequencer Next State Selection

SC[3:0] Description

0000 Any match triggers to state2

0001 Any match triggers to state3

0010 Any match triggers to Final State

0011 Match2 triggers to State2....... Other matches have no effect

0100 Match2 triggers to State3....... Other matches have no effect

0101 Match2 triggers to Final State....... Other matches have no effect

0110 Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect

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The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match

on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to

ﬁnal state has priority over all other matches.

6.3.2.7.2 Debug State Control Register 2 (DBGSCR2)

Read: If COMRV[1:0] = 01

Write: If COMRV[1:0] = 01 and S12XDBG is not armed.

This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the

targeted next state whilst in State2. The matches refer to the match channels of the comparator match

control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1”. Comparators must be enabled

by setting the comparator enable bit in the associated DBGXCTL control register.

0111 Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect

1000 Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect

1001 Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect

1010 Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect

1011 Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect

1100 Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2

1101 Reserved. (No match triggers state sequencer transition)

1110 Reserved. (No match triggers state sequencer transition)

1111 Reserved. (No match triggers state sequencer transition)

Address: 0x0027

76543210

R0000

SC3 SC2 SC1 SC0

Reset 00000000

= Unimplemented or Reserved

Figure 6-10. Debug State Control Register 2 (DBGSCR2)

Table 6-21. DBGSCR2 Field Descriptions

Field Description

3–0

SC[3:0] These bits select the targeted next state whilst in State2, based upon the match event.

Table 6-22. State2 —Sequencer Next State Selection

SC[3:0] Description

0000 Any match triggers to state1

0001 Any match triggers to state3

0010 Any match triggers to Final State

0011 Match3 triggers to State1....... Other matches have no effect

0100 Match3 triggers to State3....... Other matches have no effect

Table 6-20. State1 Sequencer Next State Selection (continued)

SC[3:0] Description

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The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match

on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to

ﬁnal state has priority over all other matches.

6.3.2.7.3 Debug State Control Register 3 (DBGSCR3)

Read: If COMRV[1:0] = 10

Write: If COMRV[1:0] = 10 and S12XDBG is not armed.

This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the

targeted next state whilst in State3. The matches refer to the match channels of the comparator match

control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1”. Comparators must be enabled

by setting the comparator enable bit in the associated DBGXCTL control register.

0101 Match3 triggers to Final State....... Other matches have no effect

0110 Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect

0111 Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect

1000 Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect

1001 Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect

1010 Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect

1011 Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect

1100 Match2 triggers to State1..... Match3 trigger to Final State

1101 Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State

1110 Reserved. (No match triggers state sequencer transition)

1111 Reserved. (No match triggers state sequencer transition)

Address: 0x0027

76543210

R0000

SC3 SC2 SC1 SC0

Reset 00000000

= Unimplemented or Reserved

Figure 6-11. Debug State Control Register 3 (DBGSCR3)

Table 6-23. DBGSCR3 Field Descriptions

Field Description

3–0

SC[3:0] These bits select the targeted next state whilst in State3, based upon the match event.

Table 6-24. State3 — Sequencer Next State Selection

SC[3:0] Description

0000 Any match triggers to state1

0001 Any match triggers to state2

Table 6-22. State2 —Sequencer Next State Selection (continued)

SC[3:0] Description

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The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match

on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to

final state has priority over all other matches.

6.3.2.7.4 Debug Match Flag Register (DBGMFR)

Read: If COMRV[1:0] = 11

Write: Never

DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four ﬂag bits each mapped directly

to a channel. Should a match occur on the channel during the debug session, then the corresponding ﬂag

is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents

are retained after a debug session for evaluation purposes. These ﬂags cannot be cleared by software, they

are cleared only when arming the module. A set ﬂag does not inhibit the setting of other ﬂags. Once a ﬂag

is set, further triggers on the same channel have no affect.

6.3.2.8 Comparator Register Descriptions

Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG

module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare

registers, two data bus compare registers, two data bus mask registers and a control register).

0010 Any match triggers to Final State

0011 Match0 triggers to State1....... Other matches have no effect

0100 Match0 triggers to State2....... Other matches have no effect

0101 Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect

0110 Match1 triggers to State1....... Other matches have no effect

0111 Match1 triggers to State2....... Other matches have no effect

1000 Match1 triggers to Final State....... Other matches have no effect

1001 Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect

1010 Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect

1011 Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect

1100 Match2 triggers to Final State....... Other matches have no effect

1101 Match3 triggers to Final State....... Other matches have no effect

1110 Reserved. (No match triggers state sequencer transition)

1111 Reserved. (No match triggers state sequencer transition)

Address: 0x0027

76543210

R0000MC3MC2MC1MC0

Reset 00000000

= Unimplemented or Reserved

Figure 6-12. Debug Match Flag Register (DBGMFR)

Table 6-24. State3 — Sequencer Next State Selection

SC[3:0] Description

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Comparators B and D consist of four register bytes (three address bus compare registers and a control

Each set of comparator registers is accessible in the same 8-byte window of the register address map and

can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed

through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with

data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for

comparators B and D differ from those of comparators A and C.

6.3.2.8.1 Debug Comparator Control Register (DBGXCTL)

The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in

the 8-byte window of the DBG module register address map.

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

WARNING

DBGXCTL[1] is reserved. Setting this bit maps the corresponding comparator to an

Table 6-25. Comparator Register Layout

0x0028 CONTROL Read/Write Comparators A,B,C,D

0x0029 ADDRESS HIGH Read/Write Comparators A,B,C,D

0x002A ADDRESS MEDIUM Read/Write Comparators A,B,C,D

0x002B ADDRESS LOW Read/Write Comparators A,B,C,D

0x002C DATA HIGH COMPARATOR Read/Write Comparator A and C only

0x002D DATA LOW COMPARATOR Read/Write Comparator A and C only

0x002E DATA HIGH MASK Read/Write Comparator A and C only

0x002F DATA LOW MASK Read/Write Comparator A and C only

Address: 0x0028

76543210

R0 NDB TAG BRK RW RWE reserved COMPE

Reset 00000000

= Unimplemented or Reserved

Figure 6-13. Debug Comparator Control Register (Comparators A and C)

Address: 0x0028

76543210

RSZE SZ TAG BRK RW RWE reserved COMPE

Reset 00000000

Figure 6-14. Debug Comparator Control Register (Comparators B and D)

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unimplemented bus, thus preventing proper operation.

The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are

visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 6-26.

Table 6-26. Comparator Address Register Visibility

COMRV Visible Comparator

00 DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM

01 DBGBCTL, DBGBAH, DBGBAM, DBGBAL

10 DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM

11 DBGDCTL, DBGDAH, DBGDAM, DBGDAL

Table 6-27. DBGXCTL Field Descriptions

Field Description

SZE

(Comparators

B and D)

Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the

associated comparator. This bit is ignored if the TAG bit in the same register is set.

0 Word/Byte access size is not used in comparison

1 Word/Byte access size is used in comparison

NDB

(Comparators

A and C

Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator

individually masked using the comparator data mask registers. This bit is only available for comparators A

and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for

comparators B and D.

0 Match on data bus equivalence to comparator register contents

1 Match on data bus difference to comparator register contents

(Comparators

B and D)

Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the

associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.

This bit position has NDB functionality for comparators A and C

0 Word access size will be compared

1 Byte access size will be compared

TAG Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the

matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.

0 Trigger immediately on match

1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated

BRK Break — This bit controls whether a channel match terminates a debug session immediately, independent

of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled

using DBGBRK.

0 The debug session termination is dependent upon the state sequencer and trigger conditions.

1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,

tracing, if active, is terminated and the module disarmed.

RW Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the

associated comparator . The RW bit is not used if RWE = 0.

0 Write cycle will be matched

1 Read cycle will be matched

RWE Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the

associated comparator. This bit is not used for tagged operations.

0 Read/Write is not used in comparison

1 Read/Write is used in comparison

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Table 6-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for

tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the

instruction queue. Thus these bits are ignored if tagged triggering is selected.

6.3.2.8.2 Debug Comparator Address High Register (DBGXAH)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

COMPE Determines if comparator is enabled

0 The comparator is not enabled

1 The comparator is enabled for state sequence triggers or tag generation

Table 6-28. Read or Write Comparison Logic Table

RWE Bit RW Bit RW Signal Comment

0 x 0 RW not used in comparison

0 x 1 RW not used in comparison

1 0 0 Write

1 0 1 No match

1 1 0 No match

1 1 1 Read

Address: 0x0029

76543210

R0 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16

Reset 00000000

= Unimplemented or Reserved

Figure 6-15. Debug Comparator Address High Register (DBGXAH)

Table 6-29. DBGXAH Field Descriptions

Field Description

6–0

Bit[22:16] Comparator Address High Compare Bits — The Comparator address high compare bits control whether the

selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. .

0 Compare corresponding address bit to a logic zero

1 Compare corresponding address bit to a logic one

Table 6-27. DBGXCTL Field Descriptions (continued)

Field Description

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6.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

6.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

Address: 0x002A

76543210

RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Reset 00000000

Figure 6-16. Debug Comparator Address Mid Register (DBGXAM)

Table 6-30. DBGXAM Field Descriptions

Field Description

7–0

Bit[15:8] Comparator Address Mid Compare Bits— The Comparator address mid compare bits control whether the

selected comparator will compare the address bus bits [15:8] to a logic one or logic zero.

0 Compare corresponding address bit to a logic zero

1 Compare corresponding address bit to a logic one

Address: 0x002B

76543210

RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset 00000000

Figure 6-17. Debug Comparator Address Low Register (DBGXAL)

Table 6-31. DBGXAL Field Descriptions

Field Description

7–0

Bits[7:0] Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the

selected comparator will compare the address bus bits [7:0] to a logic one or logic zero.

0 Compare corresponding address bit to a logic zero

1 Compare corresponding address bit to a logic one

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6.3.2.8.5 Debug Comparator Data High Register (DBGXDH)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

6.3.2.8.6 Debug Comparator Data Low Register (DBGXDL)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

Address: 0x002C

76543210

RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Reset 00000000

Figure 6-18. Debug Comparator Data High Register (DBGXDH)

Table 6-32. DBGXAH Field Descriptions

Field Description

7–0

Bits[15:8] Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected

comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are

only used in comparison if the corresponding data mask bit is logic 1. This register is available only for

comparators A and C.

0 Compare corresponding data bit to a logic zero

1 Compare corresponding data bit to a logic one

Address: 0x002D

76543210

RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset 00000000

Figure 6-19. Debug Comparator Data Low Register (DBGXDL)

Table 6-33. DBGXDL Field Descriptions

Field Description

7–0

Bits[7:0] Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected

comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are

only used in comparison if the corresponding data mask bit is logic 1. This register is available only for

comparators A and C.

0 Compare corresponding data bit to a logic zero

1 Compare corresponding data bit to a logic one

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6.3.2.8.7 Debug Comparator Data High Mask Register (DBGXDHM)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

6.3.2.8.8 Debug Comparator Data Low Mask Register (DBGXDLM)

Read: Anytime. See Table 6-26 for visible register encoding.

Write: If DBG not armed. See Table 6-26 for visible register encoding.

6.4 Functional Description

This section provides a complete functional description of the S12XDBG module. If the part is in secure

mode, the S12XDBG module can generate breakpoints but tracing is not possible.

Address: 0x002E

76543210

RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Reset 00000000

Figure 6-20. Debug Comparator Data High Mask Register (DBGXDHM)

Table 6-34. DBGXDHM Field Descriptions

Field Description

7–0

Bits[15:8] Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected

comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register

is available only for comparators A and C.

0 Do not compare corresponding data bit

1 Compare corresponding data bit

Address: 0x002F

76543210

RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset 00000000

Figure 6-21. Debug Comparator Data Low Mask Register (DBGXDLM)

Table 6-35. DBGXDLM Field Descriptions

Field Description

7–0

Bits[7:0] Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected

comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register

is available only for comparators A and C.

0 Do not compare corresponding data bit

1 Compare corresponding data bit

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6.4.1 S12XDBG Operation

Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the

trace buffer and can be used to cause breakpoints to the CPU12X . The DBG module is made up of four

main blocks, the comparators, control logic, the state sequencer, and the trace buffer.

The comparators monitor the bus activity of the CPU12X . Comparators can be conﬁgured to monitor

address and databus. Comparators can also be conﬁgured to mask out individual data bus bits during a

compare and to use R/W and word/byte access qualiﬁcation in the comparison. When a match with a

comparator register value occurs the associated control logic can trigger the state sequencer to another state

(see Figure 6-22). Either forced or tagged triggers are possible. Using a forced trigger, the trigger is

generated immediately on a comparator match. Using a tagged trigger, at a comparator match, the

instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue

is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint

can be generated.

Independent of the state sequencer, a breakpoint can be triggered by writing to the TRIG bit in the DBGC1

control register.

The trace buffer is visible through a 2-byte window in the register address map and can be read out using

standard 16-bit word reads.

6.4.2 Comparator Modes

The S12XDBG contains four comparators, A, B, C, and D. Each comparator compares the selected address

bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C

also compare the data buses to the data stored in DBGXDH, DBGXDL and allow masking of individual

data bus bits.

S12X comparator matches are disabled in BDM and during BDM accesses.

The comparator match control logic conﬁgures comparators to monitor the buses for an exact address or

an address range. The comparator conﬁguration is controlled by the control register contents and the range

control by the DBGC2 contents.

On a match a trigger can initiate a transition to another state sequencer state (see Section 6.4.3”). The

comparator control register also allows the type of access to be included in the comparison through the use

of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled

for the associated comparator and the RW bit selects either a read or write access for a valid match.

Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare.

Only comparators B and D feature SZE and SZ.

The TAG bit in each comparator control register is used to determine the triggering condition. By setting

TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs

before the tagged instruction executes (tagged-type trigger). Whilst tagging, the RW, RWE, SZE, and SZ

bits are ignored and the comparator register must be loaded with the exact opcode address.

If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address

appears on the system address bus. If the selected address is an opcode address, the match is generated

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when the opcode is fetched from the memory. This precedes the instruction execution by an indeﬁnite

number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address

when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an

opcode at odd address (n), the comparator register must contain address (n–1).

Once a successful comparator match has occurred, the condition that caused the original match is not

veriﬁed again on subsequent matches. Thus if a particular data value is veriﬁed at a given address, this

address may not still contain that data value when a subsequent match occurs.

Comparators C and D can also be used to select an address range to trace from. This is determined by the

TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 6-9. If the TRANGE

bits select a range deﬁnition using comparator D, then comparator D is conﬁgured for trace range

deﬁnition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range

deﬁnition using comparator C, then comparator C is conﬁgured for trace range deﬁnition and cannot be

used for address bus comparisons.

Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see

Section 6.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 6.4.3.4”).

6.4.2.1 Exact Address Comparator Match (Comparators A and C)

With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the

value stored in the comparator address/data registers. Further qualiﬁcation of the type of access (R/W,

word/byte) is possible.

Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. Table 6-

37 lists access considerations without data bus compare. Table 6-36 lists access considerations with data

bus comparison. To compare byte accesses DBGxDH must be loaded with the data byte, the low byte must

be masked out using the DBGxDLM mask register. On word accesses the data byte of the lower address

is mapped to DBGxDH.

Code may contain various access forms of the same address, i.e. a word access of ADDR[n] or byte access

of ADDR[n+1] both access n+1. At a word access of ADDR[n], address ADDR[n+1] does not appear on

the address bus and so cannot cause a comparator match if the comparator contains ADDR[n]. Thus it is

not possible to monitor all data accesses of ADDR[n+1] with one comparator.

To detect an access of ADDR[n+1] through a word access of ADDR[n] the comparator can be configured

to ADDR[n], DBGxDL is loaded with the data pattern and DBGxDHM is cleared so only the data[n+1] is

compared on accesses of ADDR[n].

Table 6-36. Comparator A and C Data Bus Considerations

Access Address DBGxDH DBGxDL DBGxDHM DBGxDLM Example Valid Match

Word ADDR[n] Data[n] Data[n+1] $FF $FF MOVW #$WORD ADDR[n] conﬁg1

Byte ADDR[n] Data[n] x $FF $00 MOVB #$BYTE ADDR[n] conﬁg2

Word ADDR[n] Data[n] x $FF $00 MOVW #$WORD ADDR[n] conﬁg2

Word ADDR[n] x Data[n+1] $00 $FF MOVW #$WORD ADDR[n] conﬁg3

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NOTE

Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte

by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access

size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.

Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs

to comparator register contents or when the data bus is equivalent to the comparator register contents.

6.4.2.2 Exact Address Comparator Match (Comparators B and D)

Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match

qualiﬁcation functions the same as for comparators A and C.

If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the

speciﬁed type of access causes a match. Thus if conﬁgured for a byte access of a particular address, a word

access covering the same address does not lead to match.

6.4.2.3 Data Bus Comparison NDB Dependency

Comparators A and C each feature an NDB control bit, which allows data bus comparators to be conﬁgured

to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the

contents of an address location from an expected value.

When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by

clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A

match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register

bits are clear, then a match is based on the address bus only, the data bus is ignored.

When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any

data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored

and prevents a match because no difference can be detected. In this case address bus equivalence does not

cause a match.

Table 6-37. Comparator Access Size Considerations

Comparator Address SZE SZ8 Condition For Valid Match

Comparators

A and C ADDR[n] — — Word and byte accesses of ADDR[n]1

MOVB #$BYTE ADDR[n]

MOVW #$WORD ADDR[n]

1A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.

The comparator address register must contain the exact address used in the code.

Comparators

B and D ADDR[n] 0 X Word and byte accesses of ADDR[n]1

MOVB #$BYTE ADDR[n]

MOVW #$WORD ADDR[n]

Comparators

B and D ADDR[n] 1 0 Word accesses of ADDR[n]1

MOVW #$WORD ADDR[n]

Comparators

B and D ADDR[n] 1 1 Byte accesses of ADDR[n]

MOVB #$BYTE ADDR[n]

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6.4.2.4 Range Comparisons

When using the AB comparator pair for a range comparison, the data bus can also be used for qualiﬁcation

by using the comparator A data and data mask registers. Furthermore the DBGACTL RW and RWE bits

can be used to qualify the range comparison on either a read or a write access. The corresponding

DBGBCTL bits are ignored. Similarly when using the CD comparator pair for a range comparison, the

data bus can also be used for qualiﬁcation by using the comparator C data and data mask registers.

Furthermore the DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a

read or a write access if tagging is not selected. The corresponding DBGDCTL bits are ignored. The SZE

and SZ control bits are ignored in range mode. The comparator A and C TAG bits are used to tag range

comparisons for the AB and CD ranges respectively. The comparator B and D TAG bits are ignored in

range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB

must be set; to disable range comparisons both must be cleared. Similarly for a range CD comparison, both

COMPEC and COMPED must be set. The comparator A and C BRK bits are used for the AB and CD

ranges respectively, the comparator B and D BRK bits are ignored in range mode. When conﬁgured for

range comparisons and tagging, the ranges are accurate only to word boundaries.

6.4.2.4.1 Inside Range (CompAC_Addr ≤ address ≤ CompBD_Addr)

In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be

conﬁgured for range comparisons by the control register (DBGC2). The match condition requires that a

valid match for both comparators happens on the same bus cycle. A match condition on only one

comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger

only if the aligned address is inside the range.

6.4.2.4.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr)

In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can

be conﬁgured for range comparisons. A single match condition on either of the comparators is recognized

as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned

address is outside the range.

Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are

from an unexpected range. In forced trigger modes the outside range trigger would typically be activated

at any interrupt vector fetch or register access. This can be avoided by setting the upper or lower range limit

to $7FFFFF or $000000 respectively. Interrupt vector fetches do not cause taghits

Table 6-38. NDB and MASK bit dependency

NDB DBGxDHM[n] /

DBGxDLM[n] Comment

0 0 Do not compare data bus bit.

0 1 Compare data bus bit. Match on equivalence.

1 0 Do not compare data bus bit.

1 1 Compare data bus bit. Match on difference.

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6.4.3 Trigger Modes

Trigger modes are used as qualiﬁers for a state sequencer change of state. The control logic determines the

trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in

the following sections.

6.4.3.1 Forced Trigger On Comparator Match

If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state

sequencer state whereby the corresponding ﬂags in DBGSR are set. The state control register for the

current state determines the next state for each trigger. Forced triggers are generated as soon as the

matching address appears on the address bus, which in the case of opcode fetches occurs several cycles

before the opcode execution. For this reason a forced trigger at an opcode address precedes a tagged trigger

at the same address by several cycles.

6.4.3.2 Trigger On Comparator Related Taghit

If a CPU12X taghit occurs, a transition to another state sequencer state is initiated and the corresponding

DBGSR ﬂags are set. For a comparator related taghit to occur, the S12XDBG must ﬁrst generate tags based

on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue

a taghit is generated by the CPU12X. The state control register for the current state determines the next

state for each trigger.

6.4.3.3 TRIG Immediate Trigger

Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing

the TRIG bit in DBGC1 to a logic “1”. If conﬁgured for begin or mid aligned tracing, this triggers the state

sequencer into the Final State, if conﬁgured for end alignment, setting the TRIG bit disarms the module,

ending the session. If breakpoints are enabled, a forced breakpoint request is issued immediately (end

alignment) or when tracing has completed (begin or mid alignment).

6.4.3.4 Trigger Priorities

In case of simultaneous triggers, the priority is resolved according to Table 6-39. The lower priority trigger

is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger

of a higher priority. The trigger priorities described in Table 6-39 dictate that in the case of simultaneous

matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that

a match leading to ﬁnal state has priority over all other matches in each state sequencer state. When

conﬁgured for range modes a simultaneous match of comparators A and C generates an active match0

whilst match2 is suppressed.

If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm

from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.

Table 6-39. Trigger Priorities

Priority Source Action

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6.4.4 State Sequence Control

Figure 6-22. State Sequencer Diagram

The state sequencer allows a deﬁned sequence of events to provide a trigger point for tracing of data in the

trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,

then state1 of the state sequencer is entered. Further transitions between the states are then controlled by

the state control registers and depend upon a selected trigger mode condition being met. From Final State

the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is

not restricted. Each transition updates the SSF[2:0] ﬂags in DBGSR accordingly to indicate the current

state.

Alternatively by setting the TRIG bit in DBGSC1, the state machine can be triggered to state0 or Final

State depending on tracing alignment.

Independent of the state sequencer, each comparator channel can be individually conﬁgured to generate an

immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.

Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer

transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a

channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This

is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state

sequencer enters state0 and the debug module is disarmed.

Highest TRIG Trigger immediately to ﬁnal state (begin or mid aligned tracing enabled)

Trigger immediately to state 0 (end aligned or no tracing enabled)

Match0 (force or tag hit) Trigger to next state as deﬁned by state control registers

Match1 (force or tag hit) Trigger to next state as deﬁned by state control registers

Match2 (force or tag hit) Trigger to next state as deﬁned by state control registers

Lowest Match3 (force or tag hit) Trigger to next state as deﬁned by state control registers

Table 6-39. Trigger Priorities

State1

Final State State3

ARM = 1

Session Complete

(Disarm)

State2

State 0

(Disarmed) ARM = 0

ARM = 0

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6.4.4.1 Final State

On entering Final State a trigger may be issued to the trace buffer according to the trace position control

as deﬁned by the TALIGN ﬁeld (see Section 6.3.2.3”). If TSOURCE in the trace control register DBGTCR

is cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint

request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the

DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled, a breakpoint

request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when

the ﬁnal state is reached it returns automatically to state0 and the debug module is disarmed.

6.4.5 Trace Buffer Operation

The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace

information in the RAM array in a circular buffer format. The RAM array can be accessed through a

buffer line is read, an internal pointer into the RAM is incremented so that the next read will receive fresh

information. Data is stored in the format shown in Table 6-40. After each store the counter register bits

DBGCNT[6:0] are incremented. Tracing of CPU12X activity is disabled when the BDM is active. Reading

the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not

incremented.

6.4.5.1 Trace Trigger Alignment

Using the TALIGN bits (see Section 6.3.2.3”) it is possible to align the trigger with the end, the middle, or

the beginning of a tracing session.

If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered.

The transition to Final State if End is selected signals the end of the tracing session. The transition to Final

State if Mid is selected signals that another 32 lines will be traced before ending the tracing session.

Tracing with Begin-Trigger starts at the opcode of the trigger.

6.4.5.1.1 Storing with Begin-Trigger

Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the

trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace

Buffer. If the trigger is at the address of the change-of-ﬂow instruction the change of ﬂow associated with

the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged

instruction is about to be executed then the trace is started. Upon completion of the tracing session the

breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.

6.4.5.1.2 Storing with Mid-Trigger

Storing with Mid-Trigger, data is stored in the Trace Buffer as soon as the S12XDBG module is armed.

When the trigger condition is met, another 32 lines will be traced before ending the tracing session,

irrespective of the number of lines stored before the trigger occurred, then the S12XDBG module is

disarmed and no more data is stored. Using Mid-trigger with tagging, if the tagged instruction is about to

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be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is

generated, thus the breakpoint does not occur at the tagged instruction boundary.

6.4.5.1.3 Storing with End-Trigger

Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point

the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the

address of a change of ﬂow instruction the trigger event will not be stored in the Trace Buffer.

6.4.5.2 Trace Modes

The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in

the DBGTCR register. The modes are described in the following subsections. The trace buffer organization

is shown in Table 6-40.

6.4.5.2.1 Normal Mode

In Normal Mode, change of ﬂow (COF) program counter (PC) addresses will be stored.

COF addresses are deﬁned as follows :

• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)

• Destination address of indexed JMP, JSR, and CALL instruction

• Destination address of RTI, RTS, and RTC instructions.

• Vector address of interrupts, except for SWI and BDM vectors

LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classiﬁed as

change of ﬂow and are not stored in the trace buffer.

Change-of-ﬂow addresses stored include the full 23-bit address bus of CPU12X and an information byte,

which contains a source/destination bit to indicate whether the stored address was a source address or

destination address.

NOTE

When an CPU12X COF instruction with destination address is executed, the

destination address is stored to the trace buffer on instruction completion,

indicating the COF has taken place. If an interrupt occurs simultaneously

then the next instruction carried out is actually from the interrupt service

routine. The instruction at the destination address of the original program

ﬂow gets exectuted after the interrupt service routine.

In the following example an IRQ interrupt occurs during execution of the

indexed JMP at address MARK1. The BRN at the destination (SUB_1) is

not executed until after the IRQ service routine but the destination address

is entered into the trace buffer to indicate that the indexed JMP COF has

taken place.

LDX #SUB_1

MARK1 JMP 0,X ; IRQ interrupt occurs during execution of this

MARK2 NOP ;

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SUB_1 BRN * ; JMP Destination address TRACE BUFFER ENTRY 1

; RTI Destination address TRACE BUFFER ENTRY 3

NOP ;

ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4

IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2

STAB VAR_C1

RTI ;

The execution ﬂow taking into account the IRQ is as follows

LDX #SUB_1

MARK1 JMP 0,X ;

IRQ_ISR LDAB #$F0 ;

STAB VAR_C1

RTI ;

SUB_1 BRN *

NOP ;

ADDR1 DBNE A,PART5 ;

6.4.5.2.2 Loop1 Mode

Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it

however allows the ﬁltering out of redundant information.

The intent of Loop1 Mode is to prevent the Trace Buffer from being ﬁlled entirely with duplicate

information from a looping construct such as delays using the DBNE instruction or polling loops using

BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the

S12XDBG module writes this value into a background register. This prevents consecutive duplicate

address entries in the Trace Buffer resulting from repeated branches.

Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in

most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector

addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the

S12XDBG module is designed to help ﬁnd.

6.4.5.2.3 Detail Mode

In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This

mode also features information byte entries to the trace buffer, for each address byte entry. The information

byte indicates the size of access (word or byte) and the type of access (read or write).

When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is

either in a free or opcode fetch cycle, the address range can be limited to a range speciﬁed by the TRANGE

bits in DBGTCR. This function uses comparators C and D to deﬁne an address range inside which

CPU12X activity should be traced (see Table 6-40). Thus the traced CPU12X activity can be restricted to

particular register range accesses.

6.4.5.2.4 Pure PC Mode

In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal

opcodes, are stored.

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6.4.5.3 Trace Buffer Organization

Referring to Table 6-40. ADRH, ADRM, ADRL denote address high, middle and low byte respectively.

INF bytes contain control information (R/W, S/D etc.). The numerical sufﬁx indicates which tracing step.

The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst

tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0]

is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other

DBGCNT bits are incremented on each trace buffer entry.

When a COF occurs a trace buffer entry is made and the corresponding CDV bit is set.

Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL )

and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to

trace buffer byte3 and the byte at the higher address is stored to byte2

Table 6-40. Trace Buffer Organization

Mode 8-Byte Wide Word Buffer

76543210

S12XCPU

Detail CXINF1 CADRH1 CADRM1 CADRL1 CDATAH1 CDATAL1

CXINF2 CADRH2 CADRM2 CADRL2 CDATAH2 CDATAL2

CPU12X

Other Modes CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0

CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2

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6.4.5.3.1 Information Byte Organization

The format of the control information byte is dependent upon the active trace mode as described below.

In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control

information. In Detail Mode, CXINF contains the control information

CPU12X Information Byte

CXINF Information Byte

This describes the format of the information byte used only when tracing in Detail Mode. When tracing

from the CPU12X in Detail Mode, information is stored to the trace buffer on all cycles except opcode

fetch and free cycles. In this case the CSZ and CRW bits indicate the type of access being made by the

CPU12X.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CSD CVA 0 CDV 0 0 0 0

Figure 6-23. CPU12X Information Byte CINF

Table 6-41. CINF Field Descriptions

Field Description

CSD Source Destination Indicator —Thisbitindicates if the corresponding storedaddressis a source ordestination

address. This is only used in Normal and Loop1 mode tracing.

0 Source address

1 Destination address

CVA Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses

are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal

and Loop1 mode tracing. This bit has no meaning in Pure PC mode.

0 Indexed jump destination address

1 Vector destination address

CDV Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from

both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid.

0 Trace buffer entry is invalid

1 Trace buffer entry is valid

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CSZ CRW

Figure 6-24. Information Byte CXINF

Table 6-42. CXINF Field Descriptions

Field Description

CSZ Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains

valid information when tracing CPU12X activity in Detail Mode.

0 Word Access

1 Byte Access

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6.4.5.4 Reading Data from Trace Buffer

The data stored in the Trace Buffer can be read using either the background debug module (BDM) module

or the CPU12X provided the S12XDBG module is not armed, is conﬁgured for tracing and the system not

secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer

can only be unlocked for reading by an aligned word write to DBGTB when the module is disarmed.

The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or

misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer

address. The Trace Buffer data is read out ﬁrst-in ﬁrst-out. By reading CNT in DBGCNT the number of

valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.

Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the

pointer points to the oldest data entry, thus if no overﬂow has occurred, the pointer points to line0,

otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to

DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be

easily restarted from the oldest data entry.

The least signiﬁcant word of each 64-bit wide array line is read out ﬁrst. This corresponds to the bytes 1

and 0 of Table 6-40. The bytes containing invalid information (shaded in Table 6-40) are also read out.

Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of

the RAM pointer will occur.

6.4.5.5 Trace Buffer Reset State

The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace

session information from immediately before the reset occurred can be read out. The DBGCNT bits are

not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is

indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking

the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session.

Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since

the reset may occur before the trace trigger, which in the begin trigger alignment case means no

information would be stored in the trace buffer.

NOTE

An external pin RESET that occurs simultaneous to a trace buffer entry can,

in very seldom cases, lead to either that entry being corrupted or the ﬁrst

entry of the session being corrupted. In such cases the other contents of the

trace buffer still contain valid tracing information. The case occurs when the

reset assertion coincides with the trace buffer entry clock edge.

CRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write

access. This bit only contains valid information when tracing CPU12X activity in Detail Mode.

0 Write Access

1 Read Access

Table 6-42. CXINF Field Descriptions (continued)

Field Description

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6.4.6 Tagging

A tag follows program information as it advances through the instruction queue. When a tagged instruction

reaches the head of the queue a tag hit occurs and triggers the state sequencer.

Each comparator control register features a TAG bit, which controls whether the comparator match will

cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged

comparisons, the address stored in the comparator match address registers must be an opcode address for

the trigger to occur.

Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the

transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started.

Only upon completion of the tracing session can a breakpoint be generated. Similarly using Mid trigger

with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32

lines. Upon tracing completion the breakpoint is generated. Using End trigger, when the tagged instruction

is about to be executed and the next transition is to Final State then a breakpoint is generated immediately,

before the tagged instruction is carried out.

Read/Write (R/W), access size (SZ) monitoring and data bus monitoring is not useful if tagged triggering

is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data

bus nor on the type of access. Thus these bits are ignored if tagged triggering is selected.

When conﬁgured for range comparisons and tagging, the ranges are accurate only to word boundaries.

S12X tagging is disabled when the BDM becomes active.

6.4.7 Breakpoints

Breakpoints can be generated as follows.

• From comparator channel triggers to ﬁnal state.

• Using software to write to the TRIG bit in the DBGC1 register.

Breakpoints generated via the BDM BACKGROUND command have no affect on the CPU12X in STOP

or WAIT mode.

6.4.7.1 Breakpoints From Internal Comparator Channel Final State Triggers

Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final

State. If conﬁgured for tagging, then the breakpoint is generated when the tagged opcode reaches the

execution stage of the instruction queue.

If a tracing session is selected by TSOURCE, breakpoints are requested when the tracing session has

completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on

completion of the subsequent trace (see Table 6-43). If no tracing session is selected, breakpoints are

requested immediately.

If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent

of tracing trigger alignment.

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6.4.7.2 Breakpoints Generated Via The TRIG Bit

If a TRIG triggers occur, the Final State is entered. If a tracing session is selected by TSOURCE,

breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering

is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 6-43). If no

tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if

the S12XDBG module is disarmed.

6.4.7.3 S12XDBG Breakpoint Priorities

If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator

instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session

is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a

comparator channel, it has no effect, since tracing has already started.

6.4.7.3.1 S12XDBG Breakpoint Priorities And BDM Interfacing

Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is

active, the CPU12X is executing out of BDM ﬁrmware and S12X breakpoints are disabled. In addition,

while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the

breakpoint will give priority to BDM requests over SWI requests if the breakpoint coincides with a SWI

instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.

Table 6-43. Breakpoint Setup

BRK TALIGN DBGBRK Breakpoint Alignment

0 00 0 Fill Trace Buffer until trigger

(no breakpoints — keep running)

0 00 1 Fill Trace Buffer until trigger, then breakpoint request occurs

0 01 0 Start Trace Buffer at trigger

(no breakpoints — keep running)

0 01 1 Start Trace Buffer at trigger

A breakpoint request occurs when Trace Buffer is full

0 10 0 Store a further 32 Trace Buffer line entries after trigger

(no breakpoints — keep running)

0 10 1 Store a further 32 Trace Buffer line entries after trigger

Request breakpoint after the 32 further Trace Buffer entries

1 00,01,10 1 Terminate tracing and generate breakpoint immediately on trigger

1 00,01,10 0 Terminate tracing immediately on trigger

x 11 x Reserved

Table 6-44. Breakpoint Mapping Summary

DBGBRK

(DBGC1[3]) BDM Bit

(DBGC1[4]) BDM

Enabled BDM

Active S12X Breakpoint

Mapping

0 X X X No Breakpoint

1 0 X 0 Breakpoint to SWI

1 0 X 1 No Breakpoint

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BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via

a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually

executes the BDM ﬁrmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced

by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU12X ﬂow.

If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code

and DBG breakpoint could occur simultaneously. The CPU12X ensures that BDM requests have a higher

priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re

triggering a breakpoint.

NOTE

When program control returns from a tagged breakpoint using an RTI or

BDM GO command without program counter modiﬁcation it will return to

the instruction whose tag generated the breakpoint. To avoid re triggering a

breakpoint at the same location reconﬁgure the S12XDBG module in the

SWI routine, if conﬁgured for an SWI breakpoint, or over the BDM

interface by executing a TRACE command before the GO to increment the

program ﬂow past the tagged instruction.

1 1 0 X Breakpoint to SWI

1 1 1 0 Breakpoint to BDM

1 1 1 1 No Breakpoint

Table 6-44. Breakpoint Mapping Summary

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Chapter 7

Security (S12XS9SECV2)

7.1 Introduction

This speciﬁcation describes the function of the security mechanism in the S12XS chip family (9SEC).

NOTE

No security feature is absolutely secure. However, Freescale’s strategy is to

make reading or copying the FLASH and/or EEPROM difﬁcult for

unauthorized users.

7.1.1 Features

The user must be reminded that part of the security must lie with the application code. An extreme example

would be application code that dumps the contents of the internal memory. This would defeat the purpose

of security. At the same time, the user may also wish to put a backdoor in the application program. An

example of this is the user downloads a security key through the SCI, which allows access to a

programming routine that updates parameters stored in another section of the Flash memory.

The security features of the S12XS chip family (in secure mode) are:

• Protect the content of non-volatile memories (Flash, EEPROM)

• Execution of NVM commands is restricted

• Disable access to internal memory via background debug module (BDM)

Table 7-2 gives an overview over availability of security relevant features in unsecure and secure modes.

Table 7-1. Revision History

Version

Number Revision

Date Effective

Date Author Description of Changes

02.00 27 Aug

2004 08 Sep

2004 reviewed and updated for S12XD architecture

02.01 21 Feb

2007 21 Feb

2007 added S12XE, S12XF and S12XS architectures

02.02 19 Apr

2007 19 Apr

2007 correctedstatementaboutBackdoorkeyaccessviaBDM onXE,XF,

Table 7-2. Feature Availability in Unsecure and Secure Modes on S12XS

Unsecure Mode Secure Mode

NS SS NX ES EX ST NS SS NX ES EX ST

Flash Array Access ✔✔ ✔✔

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7.1.2 Modes of Operation

7.1.3 Securing the Microcontroller

Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the

security bits located in the options/security byte in the Flash memory array. These non-volatile bits will

keep the device secured through reset and power-down.

The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory

array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used

for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte

is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this

byte are copied into the Flash security register (FSEC) during a reset sequence.

The meaning of the bits KEYEN[1:0] is shown in Table 7-3. Please refer to Section 7.1.5.1, “Unsecuring

the MCU Using the Backdoor Key Access” for more information.

The meaning of the security bits SEC[1:0] is shown in Table 7-4. For security reasons, the state of device

security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to

EEPROM Array Access ✔✔ ✔✔

NVM Commands ✔1✔ ✔1✔1

BDM ✔✔ —✔2

DBG Module Trace ✔✔ ——

1Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information.

2BDM hardware commands restricted to peripheral registers only.

76543210

0xFF0F KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0

Figure 7-1. Flash Options/Security Byte

Table 7-3. Backdoor Key Access Enable Bits

KEYEN[1:0] Backdoor Key

Access Enabled

00 0 (disabled)

01 0 (disabled)

10 1 (enabled)

11 0 (disabled)

Table 7-2. Feature Availability in Unsecure and Secure Modes on S12XS

Unsecure Mode Secure Mode

NS SS NX ES EX ST NS SS NX ES EX ST

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SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put

the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.

NOTE

Please refer to the Flash block guide for actual security conﬁguration (in

section “Flash Module Security”).

7.1.4 Operation of the Secured Microcontroller

By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented.

However, it must be understood that the security of the EEPROM and Flash memory contents also depends

on the design of the application program. For example, if the application has the capability of downloading

code through a serial port and then executing that code (e.g. an application containing bootloader code),

then this capability could potentially be used to read the EEPROM and Flash memory contents even when

the microcontroller is in the secure state. In this example, the security of the application could be enhanced

by requiring a challenge/response authentication before any code can be downloaded.

Secured operation has the following effects on the microcontroller:

Table 7-4. Security Bits

SEC[1:0] Security State

00 1 (secured)

01 1 (secured)

10 0 (unsecured)

11 1 (secured)

Security (S12XS9SECV2)

S12XS Family Reference Manual, Rev. 1.10

232 Freescale Semiconductor

7.1.4.1 Normal Single Chip Mode (NS)

• Background debug module (BDM) operation is completely disabled.

• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for

details.

• Tracing code execution using the DBG module is disabled.

7.1.4.2 Special Single Chip Mode (SS)

• BDM ﬁrmware commands are disabled.

• BDM hardware commands are restricted to the register space.

• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for

details.

• Tracing code execution using the DBG module is disabled.

Special single chip mode means BDM is active after reset. The availability of BDM ﬁrmware commands

depends on the security state of the device. The BDM secure ﬁrmware ﬁrst performs a blank check of both

the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off

and the state of the security bits in the appropriate Flash memory location can be changed If the blank

check fails, security will remain active, only the BDM hardware commands will be enabled, and the

accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used

to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash

memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed

and the options/security byte can be programmed to “unsecured” state via BDM.

While the BDM is executing the blank check, the BDM interface is completely blocked, which means that

all BDM commands are temporarily blocked.

Security (S12XS9SECV2)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 233

7.1.5 Unsecuring the Microcontroller

Unsecuring the microcontroller can be done by three different methods:

1. Backdoor key access

2. Reprogramming the security bits

3. Complete memory erase (special modes)

7.1.5.1 Unsecuring the MCU Using the Backdoor Key Access

In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key

access method. This method requires that:

• The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been

programmed to a valid value.

• The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.

• In single chip mode, the application program programmed into the microcontroller must be

designed to have the capability to write to the backdoor key locations.

The backdoor key values themselves would not normally be stored within the application data, which

means the application program would have to be designed to receive the backdoor key values from an

external source (e.g. through a serial port).

The backdoor key access method allows debugging of a secured microcontroller without having to erase

the Flash. This is particularly useful for failure analysis.

NOTE

No word of the backdoor key is allowed to have the value 0x0000 or

0xFFFF.

7.1.6 Reprogramming the Security Bits

In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security

bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the

entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors

will also be erased; this method is not recommended for normal single chip mode. The application

software can only erase and program the Flash options/security byte if the Flash sector containing the Flash

options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of

preventing this method. The microcontroller will enter the unsecured state after the next reset following

the programming of the security bits to the unsecured value.

This method requires that:

• The application software previously programmed into the microcontroller has been designed to

have the capability to erase and program the Flash options/security byte, or security is ﬁrst disabled

using the backdoor key method, allowing BDM to be used to issue commands to erase and program

the Flash options/security byte.

• The Flash sector containing the Flash options/security byte is not protected.

Security (S12XS9SECV2)

S12XS Family Reference Manual, Rev. 1.10

234 Freescale Semiconductor

7.1.7 Complete Memory Erase (Special Modes)

The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory

contents.

When a secure microcontroller is reset into special single chip mode (SS), the BDM ﬁrmware veriﬁes

whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not

erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write

to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks.

When next reset into special single chip mode, the BDM ﬁrmware will again verify whether all EEPROM

and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash

options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash

security register will indicate the unsecure state following the next reset.

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 235

Chapter 8

S12XE Clocks and Reset Generator (S12XECRGV1)

8.1 Introduction

This specification describes the function of the Clocks and Reset Generator (S12XECRG).

8.1.1 Features

The main features of this block are:

• Phase Locked Loop (IPLL) frequency multiplier with internal ﬁlter

— Reference divider

— Post divider

— Conﬁgurable internal ﬁlter (no external pin)

— Optional frequency modulation for deﬁned jitter and reduced emission

— Automatic frequency lock detector

— Interrupt request on entry or exit from locked condition

— Self Clock Mode in absence of reference clock

• System Clock Generator

— Clock Quality Check

— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate

program execution

— Clock switch for either Oscillator or PLL based system clocks

• Computer Operating Properly (COP) watchdog timer with time-out clear window.

• System Reset generation from the following possible sources:

— Power on reset

Table 8-1. Revision History

Revision

Number Revision

Date Sections

Affected Description of Changes

V01.00 26 Oct. 2005 Initial release

V01.01 02 Nov 2006 8.4.1.1/8-252 Table “Examples of IPLL Divider settings”: corrected $32 to $31

V01.02 4 Mar. 2008 8.4.1.4/8-255

8.4.3.3/8-259 Corrected details

V01.03 1 Sep. 2008 Table 8-14 added 100MHz example for PLL

V01.04 20 Nov. 2008 8.3.2.4/8-241 S12XECRG Flags Register: corrected address to Module Base + 0x0003

V01.05 19. Sep 2009 8.5.1/8-261 Modiﬁed Note below Table 8-17./8-261

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual, Rev. 1.10

236 Freescale Semiconductor

— Low voltage reset

— Illegal address reset

— COP reset

— Loss of clock reset

— External pin reset

• Real-Time Interrupt (RTI)

8.1.2 Modes of Operation

This subsection lists and briefly describes all operating modes supported by the S12XECRG.

• Run Mode

All functional parts of the S12XECRG are running during normal Run Mode. If RTI or COP

functionality is required the individual bits of the associated rate select registers (COPCTL,

RTICTL) have to be set to a non zero value.

• Wait Mode

In this mode the IPLL can be disabled automatically depending on the PLLWAI bit.

• Stop Mode

Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode

(PSTP = 0) and Pseudo Stop Mode (PSTP = 1).

— Full Stop Mode

The oscillator is disabled and thus all system and core clocks are stopped. The COP and the

RTI remain frozen.

— Pseudo Stop Mode

The oscillator continues to run and most of the system and core clocks are stopped. If the

respective enable bits are set the COP and RTI will continue to run, else they remain frozen.

• Self Clock Mode

Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode

Enable Bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of

clock. As soon as Self Clock Mode is entered the S12XECRG starts to perform a clock quality

check. Self Clock Mode remains active until the clock quality check indicates that the required

quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be

used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock

is causing severe system conditions.

8.1.3 Block Diagram

Figure 8-1 shows a block diagram of the S12XECRG.

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 237

Figure 8-1. Block diagram of S12XECRG

8.2 Signal Description

This section lists and describes the signals that connect off chip.

8.2.1 VDDPLL, VSSPLL

These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the IPLL circuitry. This allows

the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required VDDPLL

and VSSPLL must be connected to properly.

8.2.2 RESET

RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a

known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been

triggered.

ICRG

Registers

COP

RESET

RTI

IPLL

VDDPLL

VSSPLL

EXTAL

XTAL

Bus Clock

System Reset

Oscillator Clock

PLLCLK

OSCCLK

Core Clock

CM Fail

XCLKS

Power on Reset

Low Voltage Reset

COP Timeout

Real Time Interrupt

PLL Lock Interrupt

Self Clock Mode

Interrupt

S12X_MMC Illegal Address Reset

Reset

Generator

Clock Quality

Checker

Clock and Reset Control

Voltage

Regulator

Clock

Monitor

Oscillator

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual, Rev. 1.10

238 Freescale Semiconductor

8.3 Memory Map and Registers

This section provides a detailed description of all registers accessible in the S12XECRG.

8.3.1 Module Memory Map

Figure 8-2 gives an overview on all S12XECRG registers.

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

Address Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000 SYNR RVCOFRQ[1:0] SYNDIV[5:0]

0x0001 REFDV RREFFRQ[1:0] REFDIV[5:0]

0x0002 POSTDIV R0 0 0 POSTDIV[4:0]

0x0003 CRGFLG RRTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM

0x0004 CRGINT RRTIE 00

LOCKIE 00

SCMIE 0

0x0005 CLKSEL RPLLSEL PSTP XCLKS 0 PLLWAI 0RTIWAI COPWAI

0x0006 PLLCTL RCME PLLON FM1 FM0 FSTWKP PRE PCE SCME

0x0007 RTICTL RRTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0

0x0008 COPCTL RWCOP RSBCK 000

CR2 CR1 CR0

W WRTMASK

0x0009 FORBYP2R0 0 0 000 0 0

0x000A CTCTL2R0 0 0 000 0 0

0x000B ARMCOP R0 0 0 000 0 0

W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2. FORBYP and CTCTL are intended for factory test purposes only.

= Unimplemented or Reserved

Figure 8-2. CRG Register Summary

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 239

8.3.2 Register Descriptions

This section describes in address order all the S12XECRG registers and their individual bits.

8.3.2.1 S12XECRG Synthesizer Register (SYNR)

The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.

Read: Anytime

Write: Anytime except if PLLSEL = 1

NOTE

Write to this register initializes the lock detector bit.

NOTE

fVCO must be within the speciﬁed VCO frequency lock range. F.BUS (Bus

Clock) must not exceed the speciﬁed maximum. If POSTDIV = $00 then

fPLL is same as fVCO (divide by one).

The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct

IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK

frequency as shown in Table 8-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional IPLL

(no locking and/or insufficient stability).

Module Base + 0x0000

76543210

RVCOFRQ[1:0] SYNDIV[5:0]

Reset 0 0 0 00000

Figure 8-3. S12XECRG Synthesizer Register (SYNR)

Table 8-2. VCO Clock Frequency Selection

VCOCLK Frequency Ranges VCOFRQ[1:0]

32MHz <= fVCO<= 48MHz 00

48MHz < fVCO<= 80MHz 01

Reserved 10

80MHz < fVCO <= 120MHz 11

fVCO 2f

OSC

×SYNDIV 1+()

REFDIV 1+()

-------------------------------------

×=

fPLL

fVCO

2 POSTDIV×

------------------------------------=

fBUS

fPLL

-------------=

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240 Freescale Semiconductor

8.3.2.2 S12XECRG Reference Divider Register (REFDV)

The REFDV register provides a finer granularity for the IPLL multiplier steps.

Read: Anytime

Write: Anytime except when PLLSEL = 1

NOTE

Write to this register initializes the lock detector bit.

The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For

correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK

frequency as shown in Figure 8-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional IPLL

(no locking and/or insufficient stability).

8.3.2.3 S12XECRG Post Divider Register (POSTDIV)

The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the

final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 fPLL= fVCO

(divide by one).

Module Base + 0x0001

76543210

RREFFRQ[1:0] REFDIV[5:0]

Reset 0 0 0 00000

Figure 8-4. S12XECRG Reference Divider Register (REFDV)

Table 8-3. Reference Clock Frequency Selection

REFCLK Frequency Ranges REFFRQ[1:0]

1MHz <= fREF <= 2MHz 00

2MHz < fREF <= 6MHz 01

6MHz < fREF <= 12MHz 10

fREF >12MHz 11

fREF

fOSC

REFDIV 1+()

------------------------------------=

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 241

Read: Anytime

Write: Anytime except if PLLSEL = 1

NOTE

If POSTDIV = $00 then fPLL is identical to fVCO (divide by one).

8.3.2.4 S12XECRG Flags Register (CRGFLG)

This register provides S12XECRG status bits and flags.

Read: Anytime

Write: Refer to each bit for individual write conditions

Module Base + 0x0002

76543210

R000 POSTDIV[4:0]

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 8-5. S12XECRG Post Divider Register (POSTDIV)

Module Base + 0x0003

76543210

RRTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM

Reset 0 Note 1 Note 2 Note 3 0000

1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.

2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.

3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.

= Unimplemented or Reserved

Figure 8-6. S12XECRG Flags Register (CRGFLG)

fPLL

fVCO

2xPOSTDIV()

--------------------------------------=

S12XE Clocks and Reset Generator (S12XECRGV1)

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242 Freescale Semiconductor

8.3.2.5 S12XECRG Interrupt Enable Register (CRGINT)

This register enables S12XECRG interrupt requests.

Table 8-4. CRGFLG Field Descriptions

Field Description

RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This ﬂag can only be cleared by writing

a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.

0 RTI time-out has not yet occurred.

1 RTI time-out has occurred.

PORF Power on Reset Flag —PORF is set to 1 when a power on reset occurs. This ﬂag can only be cleared by writing

a 1. Writing a 0 has no effect.

0 Power on reset has not occurred.

1 Power on reset has occurred.

LVRF Low Voltage Reset Flag —LVRF is set to 1 when a low voltage reset occurs. This ﬂag can only be cleared by

writing a 1. Writing a 0 has no effect.

0 Low voltage reset has not occurred.

1 Low voltage reset has occurred.

LOCKIF IPLL Lock Interrupt Flag —LOCKIF is set to 1 when LOCK status bit changes. This ﬂag can only be cleared

by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.

0 No change in LOCK bit.

1 LOCK bit has changed.

LOCK Lock Status Bit —LOCK reﬂects the current state of IPLL lock condition. This bit is cleared in Self Clock Mode.

Writes have no effect.

0 VCOCLK is not within the desired tolerance of the target frequency.

1 VCOCLK is within the desired tolerance of the target frequency.

ILAF Illegal Address Reset Flag —ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block

Guide for details. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect.

0 Illegal address reset has not occurred.

1 Illegal address reset has occurred.

SCMIF Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This ﬂag can only be

cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.

0 No change in SCM bit.

1 SCM bit has changed.

SCM Self Clock Mode Status Bit — SCM reﬂects the current clocking mode. Writes have no effect.

0 MCU is operating normally with OSCCLK available.

1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK

running at its minimum frequency fSCM.

Module Base + 0x0004

76543210

RRTIE 00

LOCKIE 00

SCMIE 0

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 8-7. S12XECRG Interrupt Enable Register (CRGINT)

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 243

Read: Anytime

Write: Anytime

8.3.2.6 S12XECRG Clock Select Register (CLKSEL)

This register controls S12XECRG clock selection. Refer toFigure 8-16 for more details on the effect of each

bit.

Read: Anytime

Write: Refer to each bit for individual write conditions

Table 8-5. CRGINT Field Descriptions

Field Description

RTIE Real Time Interrupt Enable Bit

0 Interrupt requests from RTI are disabled.

1 Interrupt will be requested whenever RTIF is set.

LOCKIE Lock Interrupt Enable Bit

0 LOCK interrupt requests are disabled.

1 Interrupt will be requested whenever LOCKIF is set.

SCMIE Self Clock Mode Interrupt Enable Bit

0 SCM interrupt requests are disabled.

1 Interrupt will be requested whenever SCMIF is set.

Module Base + 0x0005

76543210

RPLLSEL PSTP XCLKS 0 PLLWAI 0RTIWAI COPWAI

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 8-8. S12XECRG Clock Select Register (CLKSEL)

S12XE Clocks and Reset Generator (S12XECRGV1)

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244 Freescale Semiconductor

8.3.2.7 S12XECRG IPLL Control Register (PLLCTL)

This register controls the IPLL functionality.

Table 8-6. CLKSEL Field Descriptions

Field Description

PLLSEL PLL Select Bit

Write: Anytime.

Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK.

PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.

It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as

SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.

0 System clocks are derived from OSCCLK (fBUS = fOSC / 2).

1 System clocks are derived from PLLCLK (fBUS = fPLL / 2).

PSTP Pseudo Stop Bit

Write: Anytime

This bit controls the functionality of the oscillator during Stop Mode.

0 Oscillator is disabled in Stop Mode.

1 Oscillator continues to run in Stop Mode (Pseudo Stop).

Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the

resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.

XCLKS Oscillator Conﬁguration Status Bit — This read-only bit shows the oscillator conﬁguration status.

0 Loop controlled Pierce Oscillator is selected.

1 External clock / full swing Pierce Oscillator is selected.

PLLWAI PLL Stops in Wait Mode Bit

Write: Anytime

If PLLWAI is set, the S12XECRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains

set during Wait Mode but the IPLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set

manually if PLL clock is required.

0 IPLL keeps running in Wait Mode.

1 IPLL stops in Wait Mode.

RTIWAI RTI Stops in Wait Mode Bit

Write: Anytime

0 RTI keeps running in Wait Mode.

1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.

COPWAI COP Stops in Wait Mode Bit

Normal modes: Write once

Special modes: Write anytime

0 COP keeps running in Wait Mode.

1 COP stops and initializes the COP counter whenever the part goes into Wait Mode.

Module Base + 0x0006

76543210

RCME PLLON FM1 FM0 FSTWKP PRE PCE SCME

Reset 1 1 0 00001

Figure 8-9. S12XECRG IPLL Control Register (PLLCTL)

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 245

Read: Anytime

Write: Refer to each bit for individual write conditions

Table 8-7. PLLCTL Field Descriptions

Field Description

CME Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.

0 Clock monitor is disabled.

1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock

Mode.

Note: Operating with CME=0 will not detect any loss of clock. In case of poor clock quality this could cause

unpredictable operation of the MCU!

In Stop Mode (PSTP=0) the clock monitor is disabled independently of the CME bit setting and any loss

of external clock will not be detected.

Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor

is disabled independently of the CME bit setting and any loss of external clock will not be detected.

PLLON Phase Lock Loop On Bit — PLLON turns on the IPLL circuitry. In Self Clock Mode, the IPLL is turned on, but

the PLLON bit reads the last written value. Write anytime except when PLLSEL = 1.

0 IPLL is turned off.

1 IPLL is turned on.

5, 4

FM1, FM0 IPLL Frequency Modulation Enable Bit — FM1 and FM0 enable additional frequency modulation on the

VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. Write anytime except

when PLLSEL = 1. See Table 8-8 for coding.

FSTWKP Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If Self-

Clock Mode is disabled (SCME = 0) this bit has no effect.

0 Fast wake-up from full stop mode is disabled.

1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately

resume operation in Self-Clock Mode (see Section 8.4.1.4, “Clock Quality Checker”). The SCMIF ﬂag will not

be set. The system will remain in Self-Clock Mode with oscillator and clock monitor disabled until FSTWKP bit

is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If

the clock quality check is successful, the S12XECRG will switch all system clocks to OSCCLK. The SCMIF

ﬂag will be set. See application examples in Figure 8-19 and Figure 8-20.

PRE RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.

Write anytime.

0 RTI stops running during Pseudo Stop Mode.

1 RTI continues running during Pseudo Stop Mode.

Note: If the PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active. The RTI dividers

will not initialize like in Wait Mode with RTIWAI bit set.

PCE COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.

Write anytime.

0 COP stops running during Pseudo Stop Mode

1 COP continues running during Pseudo Stop Mode

Note: If the PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active. The COP

dividers will not initialize like in Wait Mode with COPWAI bit set.

SCME Self Clock Mode Enable Bit

Normal modes: Write once

Special modes: Write anytime

SCME can not be cleared while operating in Self Clock Mode (SCM = 1).

0 Detection of crystal clock failure causes clock monitor reset (see Section 8.5.1.1, “Clock Monitor Reset”).

1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see Section 8.4.2.2, “Self Clock Mode”).

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual, Rev. 1.10

246 Freescale Semiconductor

8.3.2.8 S12XECRG RTI Control Register (RTICTL)

This register selects the timeout period for the Real Time Interrupt.

Read: Anytime

Write: Anytime

NOTE

A write to this register initializes the RTI counter.

Table 8-8. FM Amplitude selection

FM1 FM0 FM Amplitude /

fVCO Variation

0 0 FM off

01 ±1%

10 ±2%

11 ±4%

Module Base + 0x0007

76543210

RRTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0

Reset 0 0 0 00000

Figure 8-10. S12XECRG RTI Control Register (RTICTL)

Table 8-9. RTICTL Field Descriptions

Field Description

RTDEC Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.

0 Binary based divider value. See Table 8-10

1 Decimal based divider value. See Table 8-11

6–4

RTR[6:4] Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 8-

10 and Table 8-11.

3–0

RTR[3:0] Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to

provide additional granularity.Table 8-10 and Table 8-11 show all possible divide values selectable by the

RTICTL register. The source clock for the RTI is OSCCLK.

Table 8-10. RTI Frequency Divide Rates for RTDEC = 0

RTR[3:0]

RTR[6:4] =

000

(OFF) 001

(210)010

(211)011

(212)100

(213)101

(214)110

(215)111

(216)

0000 (÷1) OFF1210 211 212 213 214 215 216

S12XE Clocks and Reset Generator (S12XECRGV1)

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0001 (÷2) OFF 2x210 2x211 2x212 2x213 2x214 2x215 2x216

0010 (÷3) OFF 3x210 3x211 3x212 3x213 3x214 3x215 3x216

0011 (÷4) OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216

0100 (÷5) OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216

0101 (÷6) OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216

0110 (÷7) OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216

0111 (÷8) OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216

1000 (÷9) OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216

1001 (÷10) OFF 10x210 10x211 10x212 10x213 10x214 10x215 10x216

1010 (÷11) OFF 11x210 11x211 11x212 11x213 11x214 11x215 11x216

1011 (÷12) OFF 12x210 12x211 12x212 12x213 12x214 12x215 12x216

1100 (÷13) OFF 13x210 13x211 13x212 13x213 13x214 13x215 13x216

1101 (÷14) OFF 14x210 14x211 14x212 14x213 14x214 14x215 14x216

1110 (÷15) OFF 15x210 15x211 15x212 15x213 15x214 15x215 15x216

1111 (÷16) OFF 16x210 16x211 16x212 16x213 16x214 16x215 16x216

1Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.

Table 8-11. RTI Frequency Divide Rates for RTDEC=1

RTR[3:0]

RTR[6:4] =

000

(1x103)001

(2x103)010

(5x103)011

(10x103)100

(20x103)101

(50x103)110

(100x103)111

(200x103)

0000 (÷1) 1x1032x1035x10310x10320x10350x103100x103200x103

0001 (÷2) 2x1034x10310x10320x10340x103100x103200x103400x103

0010 (÷3) 3x1036x10315x10330x10360x103150x103300x103600x103

0011 (÷4) 4x1038x10320x10340x10380x103200x103400x103800x103

0100 (÷5) 5x10310x10325x10350x103100x103250x103500x1031x106

0101 (÷6) 6x10312x10330x10360x103120x103300x103600x1031.2x106

Table 8-10. RTI Frequency Divide Rates for RTDEC = 0

RTR[3:0]

RTR[6:4] =

000

(OFF) 001

(210)010

(211)011

(212)100

(213)101

(214)110

(215)111

(216)

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248 Freescale Semiconductor

8.3.2.9 S12XECRG COP Control Register (COPCTL)

This register controls the COP (Computer Operating Properly) watchdog.

Read: Anytime

Write:

1. RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes

2. WCOP, CR2, CR1, CR0:

— Anytime in special modes

— Write once in all other modes

– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.

– Writing WCOP to “0” has no effect, but counts for the “write once” condition.

0110 (÷7) 7x10314x10335x10370x103140x103350x103700x1031.4x106

0111 (÷8) 8x10316x10340x10380x103160x103400x103800x1031.6x106

1000 (÷9) 9x10318x10345x10390x103180x103450x103900x1031.8x106

1001 (÷10) 10 x10320x10350x103100x103200x103500x1031x1062x106

1010 (÷11) 11 x10322x10355x103110x103220x103550x1031.1x1062.2x106

1011 (÷12) 12x10324x10360x103120x103240x103600x1031.2x1062.4x106

1100 (÷13) 13x10326x10365x103130x103260x103650x1031.3x1062.6x106

1101 (÷14) 14x10328x10370x103140x103280x103700x1031.4x1062.8x106

1110 (÷15) 15x10330x10375x103150x103300x103750x1031.5x1063x106

1111 (÷16) 16x10332x10380x103160x103320x103800x1031.6x1063.2x106

Module Base + 0x0008

76543210

RWCOP RSBCK 000

CR2 CR1 CR0

W WRTMASK

Reset100000000

1. Refer to Device User Guide (Section: S12XECRG) for reset values of WCOP, CR2, CR1 and CR0.

= Unimplemented or Reserved

Figure 8-11. S12XECRG COP Control Register (COPCTL)

Table 8-11. RTI Frequency Divide Rates for RTDEC=1

RTR[3:0]

RTR[6:4] =

000

(1x103)001

(2x103)010

(5x103)011

(10x103)100

(20x103)101

(50x103)110

(100x103)111

(200x103)

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The COP time-out period is restarted if one these two conditions is true:

1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with

WRTMASK = 0.

2. Changing RSBCK bit from “0” to “1”.

Table 8-12. COPCTL Field Descriptions

Field Description

WCOP Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected

period. A write during the ﬁrst 75% of the selected period will reset the part. As long as all writes occur during

this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts

and the user must wait until the next window before writing to ARMCOP. Table 8-13 shows the duration of this

window for the seven available COP rates.

0 Normal COP operation

1 Window COP operation

RSBCK COP and RTI Stop in Active BDM Mode Bit

0 Allows the COP and RTI to keep running in Active BDM mode.

1 Stops the COP and RTI counters whenever the part is in Active BDM mode.

WRTMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits

while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of

WCOP and CR[2:0].

0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL

1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.

(Does not count for “write once”.)

2–0

CR[2:0] COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 8-13). Writing a

nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out

causes a system reset. This can be avoided by periodically (before time-out) reinitialize the COP counter via the

ARMCOP register.

While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at

highest time-out period (224 cycles) in normal COP mode (Window COP mode disabled):

1) COP is enabled (CR[2:0] is not 000)

2) BDM mode active

3) RSBCK = 0

4) Operation in emulation or special modes

Table 8-13. COP Watchdog Rates1

CR2 CR1 CR0 OSCCLK

Cycles to Timeout

0 0 0 COP disabled

001 2

010 2

011 2

100 2

101 2

110 2

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250 Freescale Semiconductor

8.3.2.10 Reserved Register (FORBYP)

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special

modes can alter the S12XECRG’s functionality.

Read: Always read $00 except in special modes

Write: Only in special modes

8.3.2.11 Reserved Register (CTCTL)

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special test

modes can alter the S12XECRG’s functionality.

Read: Always read $00 except in special modes

111 2

1OSCCLK cycles are referenced from the previous COP time-out reset

(writing $55/$AA to the ARMCOP register)

Module Base + 0x0009

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 8-12. Reserved Register (FORBYP)

Module Base + 0x000A

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 8-13. Reserved Register (CTCTL)

Table 8-13. COP Watchdog Rates1

CR2 CR1 CR0 OSCCLK

Cycles to Timeout

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Freescale Semiconductor 251

Write: Only in special modes

8.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP)

This register is used to restart the COP time-out period.

Read: Always reads $00

Write: Anytime

When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.

When the COP is enabled by setting CR[2:0] nonzero, the following applies:

Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period

you must write $55 followed by a write of $AA. Other instructions may be executed between these

writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to

avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed. When the

WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period;

writing any value in the ﬁrst 75% of the selected period will cause a COP reset.

Module Base + 0x000B

76543210

R00000000

W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset 0 0 0 00000

Figure 8-14. S12XECRG ARMCOP Register Diagram

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252 Freescale Semiconductor

8.4 Functional Description

8.4.1 Functional Blocks

8.4.1.1 Phase Locked Loop with Internal Filter (IPLL)

The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 8-15

shows a block diagram of the IPLL.

Figure 8-15. IPLL Functional Diagram

For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency

REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the

SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of 2,

4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,... to

62 to generate the PLLCLK.

NOTE

Although it is possible to set the dividers to command a very high clock

frequency, do not exceed the speciﬁed bus frequency limit for the MCU.

If (PLLSEL = 1) then fBUS = fPLL / 2.

IF POSTDIV = $00 the fPLL is identical to fVCO (divide by one)

Several examples of IPLL divider settings are shown in Table 8-14. Shaded rows indicated that these

settings are not recommended. The following rules help to achieve optimum stability and shortest lock

time:

• Use lowest possible fVCO / fREF ratio (SYNDIV value).

• Use highest possible REFCLK frequency fREF.

REDUCED

CONSUMPTION

OSCILLATOR

EXTAL

XTAL

OSCCLK

PLLCLK

REFERENCE

PROGRAMMABLE

DIVIDER PDET

PHASE

DETECTOR

REFDIV[5:0]

LOOP

PROGRAMMABLE

DIVIDER

SYNDIV[5:0]

VCO

LOCK

DOWN

LOCK

DETECTOR

REFCLK

FBCLK

VDDPLL/VSSPLL

CLOCK

MONITOR

VDDPLL/VSSPLL

VDD/VSS

Supplied by:

CPUMP

AND

FILTER

POST

PROGRAMMABLE

DIVIDER

POSTDIV[4:0]

VCOCLK

fPLL 2f

OSC

SYNDIV 1+

REFDIV 1+[]2 POSTDIV×[]

------------------------------------------------------------------------------

××=

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8.4.1.1.1 IPLL Operation

The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is

divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is

fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2

x (SYNDIV +1)] to output the FBCLK. The VCOCLK is fed to the final programmable divider and is

divided in a range of 1,2,4,6,8,... to 62 (2*POSTDIV) to output the PLLCLK. See Figure 8-15.

The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based

on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the

internal filter capacitor, based on the width and direction of the correction pulse.

The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to

ensure that the correct IPLL loop bandwidth is set.

The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the

lock detector is directly proportional to the reference clock frequency. The circuit determines the lock

condition based on this comparison.

If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check

the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during IPLL

start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, the PLLCLK can

be selected as the source for the system and core clocks. If the IPLL is selected as the source for the system

and core clocks and the LOCK bit is clear, the IPLL has suffered a severe noise hit and the software must

take appropriate action, depending on the application.

• The LOCK bit is a read-only indicator of the locked state of the IPLL.

• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared

when the VCO frequency is out of a certain tolerance, ∆unl.

• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling

the LOCK bit.

Table 8-14. Examples of IPLL Divider Settings

fOSC REFDIV[5:0] fREF REFFRQ[1:0] SYNDIV[5:0] fVCO VCOFRQ[1:0] POSTDIV[4:0] fPLL fBUS

4MHz $01 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz

8MHz $03 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz

4MHz $00 4MHz 01 $09 80MHz 01 $00 80MHz 40MHz

8MHz $00 8MHz 10 $04 80MHz 01 $00 80MHz 40MHz

4MHz $00 4MHz 01 $03 32MHz 00 $01 16MHz 8MHz

4MHz $01 2MHz 01 $18 100MHz 11 $01 50MHz 25MHz

4MHz $03 1MHz 00 $18 50MHz 01 $00 50MHz 25MHz

4MHz $03 1MHz 00 $31 100MHz 11 $01 50MHz 25MHz

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254 Freescale Semiconductor

8.4.1.2 System Clocks Generator

Figure 8-16. System Clocks Generator

The clock generator creates the clocks used in the MCU (see Figure 8-16). The gating condition placed on

top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the

setting of the respective configuration bits.

The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the

MCU enters Self Clock Mode (see Section 8.4.2.2, “Self Clock Mode”) Oscillator clock source is switched

to PLLCLK running at its minimum frequency fSCM. The Bus Clock is used to generate the clock visible at

the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus Clock. But

note that a CPU cycle corresponds to one Bus Clock.

IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output clock

drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned off by

clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a maximum of 4

OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU

activity ceases.

OSCILLATOR

PHASE

LOCK

LOOP (IIPLL)

EXTAL

XTAL

SYSCLK

RTI

OSCCLK

PLLCLK

CLOCK PHASE

GENERATOR Bus Clock

Clock

Monitor

PLLSEL or SCM

÷2

Core Clock

COP

Oscillator

= Clock Gate

Gating

Condition

WAIT(RTIWAI),

STOP(PSTP, PRE),

RTI ENABLE

WAIT(COPWAI),

STOP(PSTP, PCE),

COP ENABLE

STOP

SCM

Clock

STOP

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8.4.1.3 Clock Monitor (CM)

If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block

generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system

reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is

detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by

the CME control bit.

8.4.1.4 Clock Quality Checker

The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker

provides a more accurate check in addition to the clock monitor.

A clock quality check is triggered by any of the following events:

• Power on reset (POR)

• Low voltage reset (LVR)

• Wake-up from Full Stop Mode (exit full stop)

• Clock Monitor fail indication (CM fail)

A time window of 50000 PLLCLK cycles1 is called check window.

A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that

osc ok immediately terminates the current check window. See Figure 8-17 as an example.

Figure 8-17. Check Window Example

1. IPLL is running at self clock mode frequency fSCM.

12 49999 50000

PLLCLK

CHECK WINDOW

12345

4095

4096

OSCCLK

OSC OK

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The Sequence for clock quality check is shown in Figure 8-18.

Figure 8-18. Sequence for Clock Quality Check

NOTE

Remember that in parallel to additional actions caused by Self Clock Mode

or Clock Monitor Reset1 handling the clock quality checker continues to

check the OSCCLK signal.

NOTE

The Clock Quality Checker enables the IPLL and the voltage regulator

(VREG) anytime a clock check has to be performed. An ongoing clock

quality check could also cause a running IPLL (fSCM) and an active VREG

during Pseudo Stop Mode.

1. A Clock Monitor Reset will always set the SCME bit to logical’1’.

CHECK WINDOW

OSC OK

SCM

ACTIVE?

SWITCH TO OSCCLK

EXIT SCM

CLOCK OK

NUM = 50

NUM > 0

NUM = NUM-1

YES

SCME = 1

ENTER SCM

SCM

ACTIVE?

YES

CLOCK MONITOR RESET

YES

NUM = 0

YES

POR

EXIT FULL STOP

CM FAIL

LVR

SCME=1 &

FSTWKP=1

YES

FSTWKP = 0

NUM = 0 ENTER SCM

YES

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8.4.1.5 Computer Operating Properly Watchdog (COP)

The COP (free running watchdog timer) enables the user to check that a program is running and

sequencing properly. When the COP is being used, software is responsible for keeping the COP from

timing out. If the COP times out it is an indication that the software is no longer being executed in the

intended sequence; thus a system reset is initiated (see Section 8.4.1.5, “Computer Operating Properly

Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register

allow selection of seven COP time-out periods.

When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register

during the selected time-out period. Once this is done, the COP time-out period is restarted. If the

program fails to do this and the COP times out, the part will reset. Also, if any value other than $55 or $AA

is written, the part is immediately reset.

Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to

the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.

A premature write will immediately reset the part.

If PCE bit is set, the COP will continue to run in Pseudo Stop Mode.

8.4.1.6 Real Time Interrupt (RTI)

The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting

RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated

OSCCLK. At the end of the RTI time-out period the RTIF flag is set to one and a new RTI time-out period

starts immediately.

A write to the RTICTL register restarts the RTI time-out period.

If the PRE bit is set, the RTI will continue to run in Pseudo Stop Mode.

8.4.2 Operation Modes

8.4.2.1 Normal Mode

The S12XECRG block behaves as described within this specification in all normal modes.

8.4.2.2 Self Clock Mode

If the external clock frequency is not available due to a failure or due to long crystal start-up time, the Bus

Clock and the Core Clock are derived from the PLLCLK running at self clock mode frequency fSCM; this

mode of operation is called Self Clock Mode. This requires CME = 1 and SCME = 1, which is the default

after reset. If the MCU was clocked by the PLLCLK prior to entering Self Clock Mode, the PLLSEL bit will

be cleared. If the external clock signal has stabilized again, the S12XECRG will automatically select

OSCCLK to be the system clock and return to normal mode. See Section 8.4.1.4, “Clock Quality Checker”

for more information on entering and leaving Self Clock Mode.

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258 Freescale Semiconductor

NOTE

In order to detect a potential clock loss the CME bit should always be

enabled (CME = 1).

If CME bit is disabled and the MCU is conﬁgured to run on PLLCLK, a loss

of external clock (OSCCLK) will not be detected and will cause the system

clock to drift towards lower frequencies. As soon as the external clock is

available again the system clock ramps up to its IPLL target frequency. If

the MCU is running on external clock any loss of clock will cause the

system to go static.

8.4.3 Low Power Options

This section summarizes the low power options available in the S12XECRG.

8.4.3.1 Run Mode

This is the default mode after reset.

The RTI can be stopped by setting the associated rate select bits to zero.

The COP can be stopped by setting the associated rate select bits to zero.

8.4.3.2 Wait Mode

The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of

the individual bits in the CLKSEL register. All individual Wait Mode configuration bits can be superposed.

This provides enhanced granularity in reducing the level of power consumption during Wait Mode.

Table 8-15 lists the individual configuration bits and the parts of the MCU that are affected in Wait Mode.

After executing the WAI instruction the core requests the S12XECRG to switch MCU into Wait Mode.

The S12XECRG then checks whether the PLLWAI bit is asserted. Depending on the configuration the

S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the

IPLL.

There are two ways to restart the MCU from Wait Mode:

1. Any reset

2. Any interrupt

Table 8-15. MCU Conﬁguration During Wait Mode

PLLWAI RTIWAI COPWAI

IPLL Stopped — —

RTI — Stopped —

COP — — Stopped

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8.4.3.3 Stop Mode

All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The

oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or

COP continues to run in Pseudo Stop Mode. In addition to disabling system and core clocks the

S12XECRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual

power saving modes (if available).

If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core

clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core

clock and finally disables the remaining system clocks.

If Pseudo Stop Mode is entered from Self-Clock Mode the S12XECRG will continue to check the clock

quality until clock check is successful. In this case the IPLL and the voltage regulator (VREG) will remain

enabled. If Full Stop Mode (PSTP = 0) is entered from Self-Clock Mode the ongoing clock quality check

will be stopped. A complete timeout window check will be started when Stop Mode is left again.

There are two ways to restart the MCU from Stop Mode:

1. Any reset

2. Any interrupt

If the MCU is woken-up from Full Stop Mode by an interrupt and the fast wake-up feature is enabled

(FSTWKP=1 and SCME=1), the system will immediately (no clock quality check) resume operation in

Self-Clock Mode (see Section 8.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set for this

special case. The system will remain in Self-Clock Mode with oscillator disabled until FSTWKP bit is

cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality

check is successful, the S12XECRG will switch all system clocks to oscillator clock. The SCMIF flag will be

set. See application examples in Figure 8-19 and Figure 8-20.

Because the IPLL has been powered-down during Stop Mode the PLLSEL bit is cleared and the MCU runs

on OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to

switch system and core clocks to the PLLCLK.

NOTE

In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature

the clock monitor and the oscillator are disabled.

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Figure 8-19. Fast Wake-up from Full Stop Mode: Example 1

Figure 8-20. Fast Wake-up from Full Stop Mode: Example 2

8.5 Resets

All reset sources are listed in Table 8-16. Refer to MCU specification for related vector addresses and

priorities. Table 8-16. Reset Summary

Reset Source Local Enable

Power on Reset None

Low Voltage Reset None

External Reset None

Illegal Address Reset None

Clock Monitor Reset PLLCTL (CME=1, SCME=0)

Oscillator Clock

PLL Clock

Core Clock

Instruction STOP IRQ service

FSTWKP=1 IRQ service STOP STOP IRQ service

Oscillator Disabled

Power Saving

Self-Clock Mode

SCME=1

CPU resumes program execution immediately

Interrupt Interrupt Interrupt

Oscillator Clock

PLL Clock

Core Clock

Instruction

Clock Quality Check

STOP IRQ Service

FSTWKP=1 IRQ Interrupt FSTWKP=0 SCMIE=1

Osc StartupOscillator Disabled

CPU resumes program execution immediately

Self-Clock Mode

SCME=1

Frequent Uncritical

Instructions Frequent Critical

Instructions Possible

SCM Interrupt

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 261

8.5.1 Description of Reset Operation

The reset sequence is initiated by any of the following events:

• Low level is detected at the RESET pin (External Reset).

• Power on is detected.

• Low voltage is detected.

• Illegal Address Reset is detected (see S12XMMC Block Guide for details).

• COP watchdog times out.

• Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).

Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see

Figure 8-21). Since entry into reset is asynchronous it does not require a running SYSCLK. However, the

internal reset circuit of the S12XECRG cannot sequence out of current reset condition without a running

SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles

depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released.

The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and then samples the RESET

pin to determine the originating source. Table 8-17 shows which vector will be fetched.

NOTE

External circuitry connected to the RESET pin should be able to raise the

signal to a valid logic one within 64 SYSCLK cycles after the low drive is

released by the MCU. If this requirement is not adhered to the reset source

will always be recognized as “External Reset” even if the reset was initially

caused by an other reset source.

COP Watchdog Reset COPCTL (CR[2:0] nonzero)

Table 8-17. Reset Vector Selection

Sampled RESET Pin

(64 cycles after release) Clock Monitor

Reset Pending COP

Reset Pending Vector Fetch

1 0 0 POR / LVR /

Illegal Address Reset/

External Reset

1 1 X Clock Monitor Reset

1 0 1 COP Reset

0 X X POR / LVR /

Illegal Address Reset/ External Reset

with rise of RESET pin

Table 8-16. Reset Summary

Reset Source Local Enable

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual, Rev. 1.10

262 Freescale Semiconductor

The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long

reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles

(External Reset), the internal reset remains asserted longer.

Figure 8-21. RESET Timing

8.5.1.1 Clock Monitor Reset

The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:

• Clock monitor is enabled (CME = 1)

• Loss of clock is detected

• Self-Clock Mode is disabled (SCME = 0).

The reset event asynchronously forces the configuration registers to their default settings. In detail the

CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence the

S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the clock

quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the S12XECRG

switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running in parallel to

the reset generator, the S12XECRG may leave Self Clock Mode while still completing the internal reset

sequence.

8.5.1.2 Computer Operating Properly Watchdog (COP) Reset

When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the

ARMCOP register during the selected time-out period. Once this is done, the COP time-out period

restarts. If the program fails to do this the S12XECRG will generate a reset.

8.5.1.3 Power On Reset, Low Voltage Reset

The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power

on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the

) ( ) (

)(

)

SYSCLK

128+n cycles 64 cycles

with nbeing

min 3 / max 6

cycles depending

on internal

synchronization

delay

ICRG drives RESET pin low

possibly

SYSCLK

not

running

possibly

RESET

driven low

externally

)(

(

RESET

RESET pin

released

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 263

S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates

a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50 check windows

the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts using Self-Clock

Mode.

Figure 8-22 and Figure 8-23 show the power-up sequence for cases when the RESET pin is tied to VDD and

when the RESET pin is held low.

Figure 8-22. RESET Pin Tied to VDD (by a Pull-up Resistor)

Figure 8-23. RESET Pin Held Low Externally

8.6 Interrupts

The interrupts/reset vectors requested by the S12XECRG are listed in Table 8-18. Refer to MCU

specification for related vector addresses and priorities.

Table 8-18. S12XECRG Interrupt Vectors

Interrupt Source CCR

Mask Local Enable

Real time interrupt I bit CRGINT (RTIE)

LOCK interrupt I bit CRGINT (LOCKIE)

SCM interrupt I bit CRGINT (SCMIE)

RESET

Internal POR

128 SYSCLK

64 SYSCLK

Internal RESET

Clock Quality Check

(no Self-Clock Mode)

) (

Clock Quality Check

RESET

Internal POR

Internal RESET

128 SYSCLK

64 SYSCLK

(no Self Clock Mode)

) (

S12XE Clocks and Reset Generator (S12XECRGV1)

S12XS Family Reference Manual, Rev. 1.10

264 Freescale Semiconductor

8.6.1 Description of Interrupt Operation

8.6.1.1 Real Time Interrupt

The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI

interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1

when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.

The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1. This feature can be used for

periodic wakeup from Pseudo Stop if the RTI interrupt is enabled.

8.6.1.2 IPLL Lock Interrupt

The S12XECRG generates a IPLL Lock interrupt when the LOCK condition of the IPLL has changed,

either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting

the LOCKIE bit to zero. The IPLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has

changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.

8.6.1.3 Self Clock Mode Interrupt

The S12XECRG generates a Self Clock Mode interrupt when the SCM condition of the system has

changed, either entered or exited Self Clock Mode. SCM conditions are caused by a failing clock quality

check after power on reset (POR) or low voltage reset (LVR) or recovery from Full Stop Mode (PSTP = 0)

or Clock Monitor failure. For details on the clock quality check refer to Section 8.4.1.4, “Clock Quality

Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM

condition (SCME = 1).

SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is

set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 265

Chapter 9

Pierce Oscillator (S12XOSCLCPV2)

9.1 Introduction

The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The

module will be operated from the VDDPLL supply rail (1.8 V nominal) and require the minimum number

of external components. It is designed for optimal start-up margin with typical crystal oscillators.

9.1.1 Features

The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures

a signal with low harmonic distortion, low power and good noise immunity.

• High noise immunity due to input hysteresis

• Low RF emissions with peak-to-peak swing limited dynamically

• Transconductance (gm) sized for optimum start-up margin for typical oscillators

• Dynamic gain control eliminates the need for external current limiting resistor

• Integrated resistor eliminates the need for external bias resistor in loop controlled Pierce mode.

• Low power consumption:

— Operates from 1.8 V (nominal) supply

— Amplitude control limits power

• Clock monitor

9.1.2 Modes of Operation

Two modes of operation exist:

1. Loop controlled Pierce (LCP) oscillator

2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor

The oscillator mode selection is described in the Device Overview section, subsection Oscillator

Conﬁguration.

Table 9-1. Revision History

Revision

Number Revision

Date Sections

Affected Description of Changes

V01.05 19 Jul 2006 - All xclks info was removed

V02.00 04 Aug 2006 - Incremented revision to match the design system spec revision

Pierce Oscillator (S12XOSCLCPV2)

S12XS Family Reference Manual, Rev. 1.10

266 Freescale Semiconductor

9.1.3 Block Diagram

Figure 9-1 shows a block diagram of the XOSC.

Figure 9-1. XOSC Block Diagram

9.2 External Signal Description

This section lists and describes the signals that connect off chip

9.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins

Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This

allows the supply voltage to the XOSC to use an independent bypass capacitor.

9.2.2 EXTAL and XTAL — Input and Output Pins

These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the

internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator

ampliﬁer. XTAL is the output of the crystal oscillator ampliﬁer. The MCU internal system clock is derived

EXTAL XTAL

Gain Control

VDDPLL = 1.8 V

OSCCLK

Monitor_Failure

Clock

Monitor

Peak

Detector

Pierce Oscillator (S12XOSCLCPV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 267

from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an

internal resistor of typical 200 kΩ.

NOTE

Freescale recommends an evaluation of the application board and chosen

resonator or crystal by the resonator or crystal supplier.

Loop controlled circuit is not suited for overtone resonators and crystals.

Figure 9-2. Loop Controlled Pierce Oscillator Connections (LCP mode selected)

NOTE

Full swing Pierce circuit is not suited for overtone resonators and crystals

without a careful component selection.

Figure 9-3. Full Swing Pierce Oscillator Connections (FSP mode selected)

Figure 9-4. External Clock Connections (FSP mode selected)

MCU

EXTAL

XTAL

VSSPLL

Crystal or

Ceramic Resonator

* Rs can be zero (shorted) when use with higher frequency crystals.

Refer to manufacturer’s data.

MCU

EXTAL

XTAL RS*

VSSPLL

Crystal or

Ceramic Resonator

MCU

EXTAL

XTAL Not Connected

CMOS Compatible

External Oscillator

(VDDPLL Level)

Pierce Oscillator (S12XOSCLCPV2)

S12XS Family Reference Manual, Rev. 1.10

268 Freescale Semiconductor

9.3 Memory Map and Register Deﬁnition

The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.

9.4 Functional Description

The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal

level which is determined by the amount of hysteresis being used and the maximum oscillation range.

The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is

intended to be connected to either a crystal or an external clock source. The XTAL pin is an output signal

that provides crystal circuit feedback.

A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is

9.4.1 Gain Control

In LCP mode a closed loop control system will be utilized whereby the ampliﬁer is modulated to keep the

output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be

kept above twice the maximum hysteresis level of the input buffer. Electrical speciﬁcation details are

provided in the Electrical Characteristics appendix.

9.4.2 Clock Monitor

The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU

clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure

which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock

monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function

is enabled/disabled by the CME control bit, described in the CRG block description chapter.

9.4.3 Wait Mode Operation

During wait mode, XOSC is not impacted.

9.4.4 Stop Mode Operation

XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled.

During pseudo-stop mode, XOSC is not impacted.

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 269

Chapter 10

Analog-to-Digital Converter (ADC12B16CV1)

Revision History

10.1 Introduction

The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital

converter. Refer to device electrical speciﬁcations for ATD accuracy.

10.1.1 Features

• 8-, 10-, or 12-bit resolution.

• Conversion in Stop Mode using internally generated clock

• Automatic return to low power after conversion sequence

• Automatic compare with interrupt for higher than or less/equal than programmable value

• Programmable sample time.

• Left/right justiﬁed result data.

• External trigger control.

• Sequence complete interrupt.

• Analog input multiplexer for 16 analog input channels.

• Special conversions for VRH, VRL, (VRL+VRH)/2.

• 1-to-16 conversion sequence lengths.

• Continuous conversion mode.

• Multiple channel scans.

• Conﬁgurable external trigger functionality on any AD channel or any of four additional trigger

inputs. The four additional trigger inputs can be chip external or internal. Refer to device

speciﬁcation for availability and connectivity.

Version

Number Revision

Date Effective

Date Author Description of Changes

V01.00 13 Oct. 2005 13 Oct. 2005 Initial version

V01.01 4 Mar. 2008 4 Mar. 2008 correchted reference that DJM bit is in ATDCTL3

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

270 Freescale Semiconductor

• Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence).

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 271

10.1.2 Modes of Operation

10.1.2.1 Conversion Modes

There is software programmable selection between performing single or continuous conversion on a

single channel or multiple channels.

10.1.2.2 MCU Operating Modes

• Stop Mode

—ICLKSTP=0 (in ATDCTL2 register)

Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted

restarts it after exiting stop mode. This has the same effect/consequences as starting a

conversion sequence with write to ATDCTL5. So after exiting from stop mode with a

previously aborted sequence all ﬂags are cleared etc.

—ICLKSTP=1 (in ATDCTL2 register)

A/D conversion sequence seamless continues in Stop Mode based on the internally generated

clock ICLK as ATD clock. For conversions during transition from Run to Stop Mode or vice

versa the result is not written to the results register, no CCF ﬂag is set and no compare is done.

When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is

required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access

ATD registers during this time.

•Wait Mode

ADC12B16C behaves same in Run and Wait Mode. For reduced power consumption continuos

conversions should be aborted before entering Wait mode.

•Freeze Mode

In Freeze Mode the ADC12B16C will either continue or ﬁnish or stop converting according to the

FRZ1 and FRZ0 bits. This is useful for debugging and emulation.

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

272 Freescale Semiconductor

10.1.3 Block Diagram

Figure 10-1. ADC12B16C Block Diagram

VSSA

AN8

ATD_12B16C

Analog

MUX

Mode and

Successive

Approximation

Results

ATD 0

ATD 1

ATD 2

ATD 3

ATD 4

ATD 5

ATD 6

ATD 7

and DAC

Sample & Hold

VDDA

VRL

VRH

Sequence Complete

Comparator

Clock

Prescaler

Bus Clock

ATD Clock

ATD 8

ATD 9

ATD 10

ATD 11

ATD 12

ATD 13

ATD 14

ATD 15

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

AN9

AN10

AN11

AN12

AN13

AN14

AN15

ETRIG0

(See device speciﬁ-

cation for availability

ETRIG1

ETRIG2

ETRIG3

and connectivity)

Timing Control

ATDDIENATDCTL1

Trigger

Mux

Internal

Clock

Interrupt

Compare Interrupt

ICLK

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 273

10.2 Signal Description

This section lists all inputs to the ADC12B16C block.

10.2.1 Detailed Signal Descriptions

10.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)

This pin serves as the analog input Channel x. It can also be conﬁgured as digital port or external trigger

for the ATD conversion.

10.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion.

Refer to device speciﬁcation for availability and connection of these inputs!

10.2.1.3 VRH, VRL

VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.

10.2.1.4 VDDA, VSSA

These pins are the power supplies for the analog circuitry of the ADC12B16C block.

10.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ADC12B16C.

10.3.1 Module Memory Map

Figure 10-2 gives an overview on all ADC12B16C registers.

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

Address Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000 ATDCTL0 RReserved 000

WRAP3 WRAP2 WRAP1 WRAP0

0x0001 ATDCTL1 RETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0

0x0002 ATDCTL2 R0 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE

= Unimplemented or Reserved

Figure 10-2. ADC12B16C Register Summary (Sheet 1 of 3)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

274 Freescale Semiconductor

0x0003 ATDCTL3 RDJM S8C S4C S2C S1C FIFO FRZ1 FRZ0

0x0004 ATDCTL4 RSMP2 SMP1 SMP0 PRS[4:0]

0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CA

0x0006 ATDSTAT0 RSCF 0ETORF FIFOR CC3 CC2 CC1 CC0

0x0007 Unimple-

mented R0 000 0 0 0 0

0x0008 ATDCMPEH RCMPE[15:8]

0x0009 ATDCMPEL RCMPE[7:0]

0x000A ATDSTAT2H R CCF[15:8]

0x000B ATDSTAT2L R CCF[7:0]

0x000C ATDDIENH RIEN[15:8]

0x000D ATDDIENL RIEN[7:0]

0x000E ATDCMPHTH RCMPHT[15:8]

0x000F ATDCMPHTL RCMPHT[7:0]

0x0010 ATDDR0 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0012 ATDDR1 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0014 ATDDR2 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0016 ATDDR3 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0018 ATDDR4 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x001A ATDDR5 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x001C ATDDR6 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x001E ATDDR7 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0020 ATDDR8 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0022 ATDDR9 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

Address Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 10-2. ADC12B16C Register Summary (Sheet 2 of 3)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 275

0x0024 ATDDR10 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0026 ATDDR11 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x0028 ATDDR12 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x002A ATDDR13 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x002C ATDDR14 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

0x002E ATDDR15 RSee Section 10.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)”

and Section 10.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”

Address Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 10-2. ADC12B16C Register Summary (Sheet 3 of 3)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

276 Freescale Semiconductor

10.3.2 Register Descriptions

This section describes in address order all the ADC12B16C registers and their individual bits.

10.3.2.1 ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime, in special modes always write 0 to Reserved Bit 7.

Module Base + 0x0000

76543210

RReserved 000

WRAP3 WRAP2 WRAP1 WRAP0

Reset 0 0 0 01111

= Unimplemented or Reserved

Figure 10-3. ATD Control Register 0 (ATDCTL0)

Table 10-1. ATDCTL0 Field Descriptions

Field Description

3-0

WRAP[3-0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-

channel conversions. The coding is summarized in Table 10-2.

Table 10-2. Multi-Channel Wrap Around Coding

WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1)

Wraparound to AN0 after Converting

0000 Reserved1

0001 AN1

0010 AN2

0011 AN3

0100 AN4

0101 AN5

0110 AN6

0111 AN7

1000 AN8

1001 AN9

1010 AN10

1011 AN11

1100 AN12

1101 AN13

1110 AN14

1111 AN15

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 277

10.3.2.2 ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

1If only AN0 should be converted use MULT=0.

Module Base + 0x0001

76543210

RETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0

Reset 0 0 1 01111

Figure 10-4. ATD Control Register 1 (ATDCTL1)

Table 10-3. ATDCTL1 Field Descriptions

Field Description

ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD

channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-

0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has

not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for

external trigger. The coding is summarized in Table 10-5.

6–5

SRES[1:0] A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 10-4 for

coding.

SMP_DIS Discharge Before Sampling Bit

0 No discharge before sampling.

1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to

the sampling time. This can help to detect an open circuit instead of measuring the previous sampled

channel.

3–0

ETRIGCH[3:0] External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs

as source for the external trigger. The coding is summarized in Table 10-5.

Table 10-4. A/D Resolution Coding

SRES1 SRES0 A/D Resolution

0 0 8-bit data

0 1 10-bit data

1 0 12-bit data

1 1 Reserved

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

278 Freescale Semiconductor

10.3.2.3 ATD Control Register 2 (ATDCTL2)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

Table 10-5. External Trigger Channel Select Coding

ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is

0 0 0 0 0 AN0

0 0 0 0 1 AN1

0 0 0 1 0 AN2

0 0 0 1 1 AN3

0 0 1 0 0 AN4

0 0 1 0 1 AN5

0 0 1 1 0 AN6

0 0 1 1 1 AN7

0 1 0 0 0 AN8

0 1 0 0 1 AN9

0 1 0 1 0 AN10

0 1 0 1 1 AN11

0 1 1 0 0 AN12

0 1 1 0 1 AN13

0 1 1 1 0 AN14

0 1 1 1 1 AN15

1 0 0 0 0 ETRIG01

1Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means

external trigger source is still on one of the AD channels selected by ETRIGCH3-0

1 0 0 0 1 ETRIG11

1 0 0 1 0 ETRIG21

1 0 0 1 1 ETRIG31

1 0 1 X X Reserved

1 1 X X X Reserved

Module Base + 0x0002

76543210

R0 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 10-5. ATD Control Register 2 (ATDCTL2)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 279

Table 10-6. ATDCTL2 Field Descriptions

Field Description

AFFC ATD Fast Flag Clear All

0 ATD ﬂag clearing done by write 1 to respective CCF[n] ﬂag.

1 Changes all ATD conversion complete ﬂags to a fast clear sequence.

For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ﬂag

to clear automatically.

For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ﬂag

to clear automatically.

ICLKSTP Internal Clock in Stop Mode Bit — This bit enables A/D conversions in stop mode. When going into stop mode

and ICLKSTP=1 the ATD conversion clock is automatically switched to the internally generated clock ICLK.

Current conversion sequence will seamless continue. Conversion speed will change from prescaled bus

frequency to the ICLK frequency (see ATD Electrical Characteristics in device description). The prescaler bits

PRS4-0 in ATDCTL4 have no effect on the ICLK frequency. For conversions during stop mode the automatic

compare interrupt or the sequence complete interrupt can be used to inform software handler about changing

A/D values. External trigger will not work while converting in stop mode. For conversions during transition from

Run to Stop Mode or vice versa the result is not written to the results register, no CCF ﬂag is set and no compare

is done. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to

switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.

0 If A/D conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be

aborted and automatically restarted when exiting stop mode.

1 A/D continues to convert in stop mode using internally generated clock (ICLK)

ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See

Table 10-7 for details.

ETRIGP External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 10-7 for details.

ETRIGE External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the

ETRIG3-0 inputs as described in Table 10-5. If external trigger source is one of the AD channels, the digital input

buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external

events. External trigger will not work while converting in stop mode.

0 Disable external trigger

1 Enable external trigger

ASCIE ATD Sequence Complete Interrupt Enable

0 ATD Sequence Complete interrupt requests are disabled.

1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.

ACMPIE ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n(CMPE[n]=1 in ATDCMPE

conversion n), the compare interrupt is triggered.

0 ATD Compare interrupt requests are disabled.

1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare

Interrupt will be requested whenever any of the respective CCF ﬂags is set.

Table 10-7. External Trigger Conﬁgurations

ETRIGLE ETRIGP External Trigger Sensitivity

0 0 Falling edge

0 1 Rising edge

1 0 Low level

1 1 High level

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280 Freescale Semiconductor

10.3.2.4 ATD Control Register 3 (ATDCTL3)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

Module Base + 0x0003

76543210

RDJM S8C S4C S2C S1C FIFO FRZ1 FRZ0

Reset 0 0 1 00000

= Unimplemented or Reserved

Figure 10-6. ATD Control Register 3 (ATDCTL3)

Table 10-8. ATDCTL3 Field Descriptions

Field Description

DJM Result Register Data Justiﬁcation — Result data format is always unsigned. This bit controls justiﬁcation of

conversion data in the result registers.

0 Left justiﬁed data in the result registers.

1 Right justiﬁed data in the result registers.

Table 10-9 gives examples ATD results for an input signal range between 0 and 5.12 Volts.

6–3

S8C, S4C,

S2C, S1C

Conversion Sequence Length — These bits control the number of conversions per sequence. Table 10-10

shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity

to HC12 family.

FIFO Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result

registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result register

(ATDDR0), the second result in the second result register (ATDDR1), and so on.

If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion

sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning

conversion sequence, the result register counter will wrap around when it reaches the end of the result register

ﬁle. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register

ﬁle, the current conversion result will be placed.

Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the ﬁrst

resultof anewconversion sequence,started bywriting to ATDCTL5,willalwaysbeplace inthe ﬁrst resultregister

(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion

(ETRIG=1).

Which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear mode

may or may not be useful in a particular application to track valid data.

If this bit is one, automatic compare of result registers is always disabled, that is ADC12B16C will behave as if

ACMPIE and all CPME[n] were zero.

0 Conversion results are placed in the corresponding result register up to the selected sequence length.

1 Conversion results are placed in consecutive result registers (wrap around at end).

1–0

FRZ[1:0] Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the

ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond

to a breakpoint as shown in Table 10-11. Leakage onto the storage node and comparator reference capacitors

may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 281

Table 10-9. Examples of ideal decimal ATD Results

Input Signal

VRL = 0 Volts

VRH = 5.12 Volts

8-Bit

Codes

(resolution=20mV)

10-Bit

Codes

(resolution=5mV)

12-Bit

Codes

(transfer curve has

1.25mV offset)

(resolution=1.25mV)

5.120 Volts

...

0.022

0.020

0.018

0.016

0.014

0.012

0.010

0.008

0.006

0.004

0.003

0.002

0.000

255

...

1023

...

4095

...

Table 10-10. Conversion Sequence Length Coding

S8C S4C S2C S1C Number of Conversions

per Sequence

00 0 0 16

00 0 1 1

00 1 0 2

00 1 1 3

01 0 0 4

01 0 1 5

01 1 0 6

01 1 1 7

10 0 0 8

10 0 1 9

10 1 0 10

10 1 1 11

11 0 0 12

11 0 1 13

11 1 0 14

11 1 1 15

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282 Freescale Semiconductor

10.3.2.5 ATD Control Register 4 (ATDCTL4)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

Table 10-11. ATD Behavior in Freeze Mode (Breakpoint)

FRZ1 FRZ0 Behavior in Freeze Mode

0 0 Continue conversion

0 1 Reserved

1 0 Finish current conversion, then freeze

1 1 Freeze Immediately

Module Base + 0x0004

76543210

RSMP2 SMP1 SMP0 PRS[4:0]

Reset 0 0 0 00101

Figure 10-7. ATD Control Register 4 (ATDCTL4)

Table 10-12. ATDCTL4 Field Descriptions

Field Description

7–5

SMP[2:0] Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock

cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).

Table 10-13 lists the available sample time lengths.

4–0

PRS[4:0] ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency

is calculated as follows:

Refer to Device Speciﬁcation for allowed frequency range of fATDCLK.

Table 10-13. Sample Time Select

SMP2 SMP1 SMP0 Sample Time

in Number of

ATD Clock Cycles

000 4

001 6

010 8

011 10

100 12

101 16

110 20

fATDCLK fBUS

2 PRS 1+()×

-------------------------------------=

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Freescale Semiconductor 283

10.3.2.6 ATD Control Register 5 (ATDCTL5)

Writes to this register will abort current conversion sequence and start a new conversion sequence. If

external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a

conversion sequence which will then occur on each trigger event. Start of conversion means the beginning

of the sampling phase.

Read: Anytime

Write: Anytime

111 24

Module Base + 0x0005

76543210

R0 SC SCAN MULT CD CC CB CA

Reset 0 0 0 00000

Figure 10-8. ATD Control Register 5 (ATDCTL5)

Table 10-14. ATDCTL5 Field Descriptions

Field Description

SC Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,

CC, CB and CA of ATDCTL5. Table 10-15 lists the coding.

0 Special channel conversions disabled

1 Special channel conversions enabled

SCAN Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed

continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means

external trigger always starts a single conversion sequence.

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

Table 10-13. Sample Time Select

SMP2 SMP1 SMP0 Sample Time

in Number of

ATD Clock Cycles

Analog-to-Digital Converter (ADC12B16CV1)

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284 Freescale Semiconductor

MULT Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the speciﬁed

analog input channel for an entire conversion sequence. The analog channel is selected by channel selection

code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples

acrosschannels. The number ofchannelssampledisdetermined bythe sequence length value(S8C,S4C,S2C,

S1C). The ﬁrst analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);

subsequent channels sampled in the sequence are determined by incrementing the channel selection code or

wrapping around to AN0 (channel 0).

0 Sample only one channel

1 Sample across several channels

3–0

CD, CC,

CB, CA

Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are

sampled and converted to digital codes. Table 10-15 lists the coding used to select the various analog input

channels.

In the case of single channel conversions (MULT=0), this selection code speciﬁes the channel to be examined.

In the case of multiple channel conversions (MULT=1), this selection code speciﬁes the ﬁrst channel to be

examined in the conversion sequence. Subsequent channels are determined by incrementing the channel

selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel

Select Bits WRAP3-0 in ATDCTL0). In case of starting with a channel number higher than the one deﬁned by

WRAP3-0 the ﬁrst wrap around will be AN15 to AN0.

Table 10-15. Analog Input Channel Select Coding

SC CD CC CB CA Analog Input

Channel

00000 AN0

0001 AN1

0010 AN2

0011 AN3

0100 AN4

0101 AN5

0110 AN6

0111 AN7

1000 AN8

1001 AN9

1 0 1 0 AN10

1 0 1 1 AN11

1 1 0 0 AN12

1 1 0 1 AN13

1 1 1 0 AN14

1 1 1 1 AN15

Table 10-14. ATDCTL5 Field Descriptions (continued)

Field Description

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 285

1 0 0 0 0 Reserved

0 0 0 1 Reserved

0 0 1 X Reserved

0100 V

0101 V

0110 (V

RH+VRL) / 2

0 1 1 1 Reserved

1 X X X Reserved

Table 10-15. Analog Input Channel Select Coding

SC CD CC CB CA Analog Input

Channel

Analog-to-Digital Converter (ADC12B16CV1)

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286 Freescale Semiconductor

10.3.2.7 ATD Status Register 0 (ATDSTAT0)

This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and

the conversion counter.

Read: Anytime

Write: Anytime (No effect on (CC3, CC2, CC1, CC0))

Module Base + 0x0006

76543210

RSCF 0ETORF FIFOR CC3 CC2 CC1 CC0

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 10-9. ATD Status Register 0 (ATDSTAT0)

Table 10-16. ATDSTAT0 Field Descriptions

Field Description

SCF Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion

sequencesare continuously performed(SCAN=1),theﬂag is set after each one iscompleted.Thisﬂag is cleared

when one of the following occurs:

A) Write “1” to SCF

B) Write to ATDCTL5 (a new conversion sequence is started)

C) If AFFC=1 and read of a result register

0 Conversion sequence not completed

1 Conversion sequence has completed

ETORF External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE=0), if additional active edges are

detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the

following occurs:

A) Write “1” to ETORF

B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)

C) Write to ATDCTL5 (a new conversion sequence is started)

0 No External trigger over run error has occurred

1 External trigger over run error has occurred

FIFOR Result Register Over Run Flag — This bit indicates that a result register has been written to before its

associatedconversioncompleteﬂag (CCF)has been cleared.Thisﬂag ismostuseful whenusingthe FIFO mode

because the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is

also practical for non-FIFO modes, and indicates that a result register has been over written before it has been

read (i.e. the old data has been lost). This ﬂag is cleared when one of the following occurs:

A) Write “1” to FIFOR

B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)

C) Write to ATDCTL5 (a new conversion sequence is started)

0 No over run has occurred

1 Overrun condition exists (result register has been written while associated CCFx ﬂag was still set)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 287

10.3.2.8 ATD Compare Enable Register (ATDCMPE)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

3–0

CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion

counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,

CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO

mode (FIFO=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If

in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counters wraps around when its

maximum value is reached.

Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.

Module Base + 0x0008

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RCMPE[15:0]

Reset 0 0 0 0 0 0 0 0 0 0000000

Figure 10-10. ATD Compare Enable Register (ATDCMPE)

Table 10-17. ATDCMPE Field Descriptions

Field Description

15–0

CMPE[15:0] Compare Enable for Conversion Number n(n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence

— These bits enable automatic compare of conversion results individually for conversions of a sequence. The

sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register.

For each conversion number with CMPE[n]=1 do the following:

1) Write compare value to ATDDRnresult register

2) Write compare operator with CMPHT[n] in ATDCPMHT register

CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison.

0 No automatic compare

1 Automatic compare of results for conversion n of a sequence is enabled.

Table 10-16. ATDSTAT0 Field Descriptions (continued)

Field Description

Analog-to-Digital Converter (ADC12B16CV1)

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288 Freescale Semiconductor

10.3.2.9 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF[15:0].

Read: Anytime

Write: Anytime, no effect

Module Base + 0x000A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CCF[15:0]

Reset 0 0 0 0 0 0 0 0 0 0000000

= Unimplemented or Reserved

Figure 10-11. ATD Status Register 2 (ATDSTAT2)

Table 10-18. ATDSTAT2 Field Descriptions

Field Description

15–0

CCF[15:0] Conversion Complete Flag n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete

ﬂag is set at the end of each conversion in a sequence. The ﬂags are associated with the conversion position in

a sequence (and also the result register number). Therefore in non-ﬁfo mode, CCF[8] is set when the ninth

conversion in a sequence is complete and the result is available in result register ATDDR8; CCF[9] is set when

the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth.

If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete ﬂag

is only set if comparison with ATDDRn is true and if ACMPIE=1 a compare interrupt will be requested. In this

case, as the ATDDRnresult register is used to hold the compare value, the result will not be stored there at the

end of the conversion but is lost.

A ﬂag CCF[n] is cleared when one of the following occurs:

A) Write to ATDCTL5 (a new conversion sequence is started)

B) If AFFC=0, write “1” to CCF[n]

C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn

D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn

In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing

by methods B) or C) or D) will be overwritten by the set.

0 Conversion number n not completed or successfully compared

1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn.

If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare

operator CMPGT[n] is true. (No result available in ATDDRn)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 289

10.3.2.10 ATD Input Enable Register (ATDDIEN)

Read: Anytime

Write: Anytime

10.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

Module Base + 0x000C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RIEN[15:0]

Reset 0 0 0 0 0 0 0 0 0 0000000

Figure 10-12. ATD Input Enable Register (ATDDIEN)

Table 10-19. ATDDIEN Field Descriptions

Field Description

15–0

IEN[15:0] ATD Digital Input Enable on channel x(x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls

the digital input buffer from the analog input pin (ANx) to the digital data register.

0 Disable digital input buffer to ANx pin

1 Enable digital input buffer on ANx pin.

Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while

simultaneously using it as an analog port, there is potentially increased power consumption because the

digital input buffer maybe in the linear region.

Module Base + 0x000E

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RCMPHT[15:0]

Reset 0 0 0 0 0 0 0 0 0 0000000

Figure 10-13. ATD Compare Higher Than Register (ATDCMPHT)

Table 10-20. ATDCMPHT Field Descriptions

Field Description

15–0

CMPHT[15:0] Compare Operation Higher Than Enable for conversion number n(n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5,

4, 3, 2, 1, 0) of a Sequence — This bit selects the operator for comparison of conversion results.

0 If result of conversion n is lower or same than compare value in ATDDRn, this is ﬂagged in ATDSTAT2

1 If result of conversion n is higher than compare value in ATDDRn, this is ﬂagged in ATDSTAT2

Analog-to-Digital Converter (ADC12B16CV1)

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290 Freescale Semiconductor

10.3.2.12 ATD Conversion Result Registers (ATDDRn)

The A/D conversion results are stored in 16 result registers. Results are always in unsigned data

representation. Left and right justiﬁcation is selected using the DJM control bit in ATDCTL3.

If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must

be written with the compare values in left or right justiﬁed format depending on the actual value of the

DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be

stored there at the end of the conversion but is lost.

Read: Anytime

Write: Anytime

NOTE

For conversions not using automatic compare, results are stored in the result

registers after each conversion. In this case avoid writing to ATDDRn except

for initial values, because an A/D result might be overwritten.

10.3.2.12.1 Left Justiﬁed Result Data (DJM=0)

10.3.2.12.2 Right Justiﬁed Result Data (DJM=1)

Table 10-15 shows how depending on the A/D resolution the conversion result is transferred to the ATD

result registers. Compare is always done using all 12 bits of both the conversion result and the compare

value in ATDDRn.

Module Base +

0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3

0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7

0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11

0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RBit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000

Reset 0 0 0 0 0 0 0 0 0 0000000

Figure 10-14. Left justiﬁed ATD conversion result register (ATDDRn)

Module Base +

0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3

0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7

0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11

0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 000

Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi1 1 Bit 0

Reset 0 0 0 0 0 0 0 0 0 0000000

Figure 10-15. Right justiﬁed ATD conversion result register (ATDDRn)

Analog-to-Digital Converter (ADC12B16CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 291

Table 10-21. Conversion result mapping to ATDDRn

A/D

resolution DJM conversion result mapping to

ATDDRn

8-bit data 0 Bit[11:4] = result, Bit[3:0]=0000

8-bit data 1 Bit[7:0] = result, Bit[11:8]=0000

10-bit data 0 Bit[11:2] = result, Bit[1:0]=00

10-bit data 1 Bit[9:0] = result, Bit[11:10]=00

12-bit data X Bit[11:0] = result

Analog-to-Digital Converter (ADC12B16CV1)

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292 Freescale Semiconductor

10.4 Functional Description

The ADC12B16C is structured into an analog sub-block and a digital sub-block.

10.4.1 Analog Sub-Block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate

power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.

10.4.1.1 Sample and Hold Machine

The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as

capacitor charge on a storage node.

During the sample process the analog input connects directly to the storage node.

The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.

During the hold process the analog input is disconnected from the storage node.

10.4.1.2 Analog Input Multiplexer

The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold

machine.

10.4.1.3 Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8

or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing

the stored analog sample potential with a series of digitally generated analog potentials. By following a

binary search algorithm, the A/D machine locates the approximating potential that is nearest to the

sampled potential.

When not converting the A/D machine is automatically powered down.

Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result

in a non-railed digital output code.

10.4.2 Digital Sub-Block

This subsection explains some of the digital features in more detail. See Section 10.3.2, “Register

Descriptions” for all details.

10.4.2.1 External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to the external environment

events rather than relying on software to signal the ATD module when ATD conversions are to take place.

The external trigger signal (out of reset ATD channel 15, conﬁgurable in ATDCTL1) is programmable to

Analog-to-Digital Converter (ADC12B16CV1)

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be edge or level sensitive with polarity control. Table 10-22 gives a brief description of the different

combinations of control bits and their effect on the external trigger function.

During a conversion, if additional active edges are detected the overrun error ﬂag ETORF is set.

In either level or edge triggered modes, the ﬁrst conversion begins when the trigger is received.

Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be

triggered externally.

If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion

sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger is left asserted in

level mode while a sequence is completing, another sequence will be triggered immediately.

10.4.2.2 General-Purpose Digital Port Operation

The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are

multiplexed and sampled as analog channels to the A/D converter. The analog/digital multiplex operation

is performed in the input pads. The input pad is always connected to the analog input channels of the

ADC12B16C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or

off with the ATDDIEN register. This is important so that the buffer does not draw excess current when

analog potentials are presented at its input.

10.5 Resets

At reset the ADC12B16C is in a power down state. The reset state of each individual bit is listed within

the Register Description section (see Section 10.3.2, “Register Descriptions”) which details the registers

and their bit-ﬁeld.

Table 10-22. External Trigger Control Bits

ETRIGLE ETRIGP ETRIGE SCAN Description

X X 0 0 Ignores external trigger. Performs one

conversion sequence and stops.

X X 0 1 Ignores external trigger. Performs

continuous conversion sequences.

0 0 1 X Falling edge triggered. Performs one

conversion sequence per trigger.

0 1 1 X Rising edge triggered. Performs one

conversion sequence per trigger.

1 0 1 X Trigger active low. Performs continuous

conversions while trigger is active.

1 1 1 X Trigger active high. Performs continuous

conversions while trigger is active.

Analog-to-Digital Converter (ADC12B16CV1)

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10.6 Interrupts

The interrupts requested by the ADC12B16C are listed in Table 10-23. Refer to MCU speciﬁcation for

related vector address and priority.

See Section 10.3.2, “Register Descriptions” for further details.

Table 10-23. ATD Interrupt Vectors

Interrupt Source CCR

Mask Local Enable

Sequence Complete Interrupt I bit ASCIE in ATDCTL2

Compare Interrupt I bit ACMPIE in ATDCTL2

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Chapter 11

Freescale’s Scalable Controller Area Network

(S12MSCANV3)

11.1 Introduction

Freescale’s scalable controller area network (S12MSCANV3) deﬁnition is based on the MSCAN12

deﬁnition, which is the speciﬁc implementation of the MSCAN concept targeted for the M68HC12

microcontroller family.

The module is a communication controller implementing the CAN 2.0A/B protocol as deﬁned in the

Bosch speciﬁcation dated September 1991. For users to fully understand the MSCAN speciﬁcation, it is

recommended that the Bosch speciﬁcation be read ﬁrst to familiarize the reader with the terms and

concepts contained within this document.

Though not exclusively intended for automotive applications, CAN protocol is designed to meet the

speciﬁc requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI

environment of a vehicle, cost-effectiveness, and required bandwidth.

MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simpliﬁed

application software.

Table 11-1. Revision History

Revision

Number Revision Date Sections

Affected Description of Changes

V03.09 04 May 2007 11.3.2.11/11-

313 - Corrected mnemonics of code example in CANTBSEL register description

V03.10 19 Aug 2008 11.4.7.4/11-347

11.4.4.5/11-341

11.2/11-298

- Corrected wake-up description

- Relocated initialization section

- Added note to external pin descriptions for use with integrated physical layer

- Minor corrections

V03.11 31 Mar 2009 - Orthographic corrections

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11.1.1 Glossary

11.1.2 Block Diagram

Figure 11-1. MSCAN Block Diagram

Table 11-2. Terminology

ACK Acknowledge of CAN message

CAN Controller Area Network

CRC Cyclic Redundancy Code

EOF End of Frame

FIFO First-In-First-Out Memory

IFS Inter-Frame Sequence

SOF Start of Frame

CPU bus CPU related read/write data bus

CAN bus CAN protocol related serial bus

oscillator clock Direct clock from external oscillator

bus clock CPU bus related clock

CAN clock CAN protocol related clock

RXCAN

TXCAN

Receive/

Transmit

Engine

Message

Filtering

and

Buffering

Control

and

Status

Wake-Up Interrupt Req.

Errors Interrupt Req.

Receive Interrupt Req.

Transmit Interrupt Req.

CANCLK

Bus Clock

Conﬁguration

Oscillator Clock

MUX

Presc.

Tq Clk

MSCAN

Low Pass Filter

Wake-Up

Registers

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11.1.3 Features

The basic features of the MSCAN are as follows:

• Implementation of the CAN protocol — Version 2.0A/B

— Standard and extended data frames

— Zero to eight bytes data length

— Programmable bit rate up to 1 Mbps1

— Support for remote frames

• Five receive buffers with FIFO storage scheme

• Three transmit buffers with internal prioritization using a “local priority” concept

• Flexible maskable identiﬁer ﬁlter supports two full-size (32-bit) extended identiﬁer ﬁlters, or four

16-bit ﬁlters, or eight 8-bit ﬁlters

• Programmable wake-up functionality with integrated low-pass ﬁlter

• Programmable loopback mode supports self-test operation

• Programmable listen-only mode for monitoring of CAN bus

• Programmable bus-off recovery functionality

• Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states

(warning, error passive, bus-off)

• Programmable MSCAN clock source either bus clock or oscillator clock

• Internal timer for time-stamping of received and transmitted messages

• Three low-power modes: sleep, power down, and MSCAN enable

• Global initialization of conﬁguration registers

11.1.4 Modes of Operation

For a description of the speciﬁc MSCAN modes and the module operation related to the system operating

modes refer to Section 11.4.4, “Modes of Operation”.

1. Depending on the actual bit timing and the clock jitter of the PLL.

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11.2 External Signal Description

The MSCAN uses two external pins.

NOTE

On MCUs with an integrated CAN physical interface (transceiver) the

MSCAN interface is connected internally to the transceiver interface. In

these cases the external availability of signals TXCAN and RXCAN is

optional.

11.2.1 RXCAN — CAN Receiver Input Pin

RXCAN is the MSCAN receiver input pin.

11.2.2 TXCAN — CAN Transmitter Output Pin

TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the

CAN bus:

0 = Dominant state

1 = Recessive state

11.2.3 CAN System

A typical CAN system with MSCAN is shown in Figure 11-2. Each CAN station is connected physically

to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current

needed for the CAN bus and has current protection against defective CAN or defective stations.

Figure 11-2. CAN System

CAN Bus

CAN Controller

(MSCAN)

Transceiver

CAN node 1

CAN node 2

CAN node n

CANL

CANH

MCU

TXCAN RXCAN

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11.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the MSCAN.

11.3.1 Module Memory Map

Figure 11-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The

determined at the MCU level and can be found in the MCU memory map description. The address offset

is deﬁned at the module level.

The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is

determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the

ﬁrst address of the module address offset.

The detailed register descriptions follow in the order they appear in the register map.

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Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000

CANCTL0 RRXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ

0x0001

CANCTL1 RCANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK

0x0002

CANBTR0 RSJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

0x0003

CANBTR1 RSAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

0x0004

CANRFLG RWUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF

0x0005

CANRIER RWUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE

0x0006

CANTFLG R0 0000

TXE2 TXE1 TXE0

0x0007

CANTIER R00000

TXEIE2 TXEIE1 TXEIE0

0x0008

CANTARQ R00000

ABTRQ2 ABTRQ1 ABTRQ0

0x0009

CANTAAK R00000ABTAK2 ABTAK1 ABTAK0

0x000A

CANTBSEL R00000

TX2 TX1 TX0

0x000B

CANIDAC R0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0

0x000C

Reserved R00000000

0x000D

CANMISC R0000000

BOHOLD

0x000E

CANRXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

= Unimplemented or Reserved

Figure 11-3. MSCAN Register Summary

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11.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the MSCAN module. Each description

includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld

function follow the register diagrams, in bit order. All bits of all registers in this module are completely

synchronous to internal clocks during a register read.

11.3.2.1 MSCAN Control Register 0 (CANCTL0)

The CANCTL0 register provides various control bits of the MSCAN module as described below.

0x000F

CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

0x0010–0x0013

CANIDAR0–3 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

0x0014–0x0017

CANIDMRx RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

0x0018–0x001B

CANIDAR4–7 RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

0x001C–0x001F

CANIDMR4–7 RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

0x0020–0x002F

CANRXFG RSee Section 11.3.3, “Programmer’s Model of Message Storage”

0x0030–0x003F

CANTXFG RSee Section 11.3.3, “Programmer’s Model of Message Storage”

Module Base + 0x0000 Access: User read/write(1)

76543210

RRXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ

Reset: 00000001

= Unimplemented

Figure 11-4. MSCAN Control Register 0 (CANCTL0)

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 11-3. MSCAN Register Summary (continued)

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NOTE

The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the

reset state when the initialization mode is active (INITRQ = 1 and

INITAK = 1). This register is writable again as soon as the initialization

mode is exited (INITRQ = 0 and INITAK = 0).

1. Read: Anytime

Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the

module only), and INITRQ (which is also writable in initialization mode)

Table 11-3. CANCTL0 Register Field Descriptions

Field Description

RXFRM(1) Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message

correctly, independently of the ﬁlter conﬁguration. After it is set, it remains set until cleared by software or reset.

Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.

0 No valid message was received since last clearing this ﬂag

1 A valid message was received since last clearing of this ﬂag

RXACT Receiver Active Status — This read-only ﬂag indicates the MSCAN is receiving a message. The ﬂag is

controlled by the receiver front end. This bit is not valid in loopback mode.

0 MSCAN is transmitting or idle2

1 MSCAN is receiving a message (including when arbitration is lost)(2)

CSWAI(3) CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all

the clocks at the CPU bus interface to the MSCAN module.

0 The module is not affected during wait mode

1 The module ceases to be clocked during wait mode

SYNCH Synchronized Status — This read-only ﬂag indicates whether the MSCAN is synchronized to the CAN bus and

able to participate in the communication process. It is set and cleared by the MSCAN.

0 MSCAN is not synchronized to the CAN bus

1 MSCAN is synchronized to the CAN bus

TIME Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.

If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the

active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the

highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 11.3.3, “Programmer’s Model of Message

Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode.

0 Disable internal MSCAN timer

1 Enable internal MSCAN timer

WUPE(4) Wake-Up Enable — This conﬁguration bit allows the MSCAN to restart from sleep mode or from power down

mode (entered from sleep) when trafﬁc on CAN is detected (see Section 11.4.5.5, “MSCAN Sleep Mode”). This

bit must be conﬁgured before sleep mode entry for the selected function to take effect.

0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN

1 Wake-up enabled — The MSCAN is able to restart

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11.3.2.2 MSCAN Control Register 1 (CANCTL1)

The CANCTL1 register provides various control bits and handshake status information of the MSCAN

module as described below.

SLPRQ(5) Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving

mode (see Section 11.4.5.5, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is

idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry

to sleep mode by setting SLPAK = 1 (see Section 11.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ

cannot be set while the WUPIF ﬂag is set (see Section 11.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).

Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN

detects activity on the CAN bus and clears SLPRQ itself.

0 Running — The MSCAN functions normally

1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle

INITRQ(6),(7) Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see

Section 11.4.4.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and

synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1

(Section 11.3.2.2, “MSCAN Control Register 1 (CANCTL1)”).

The following registers enter their hard reset state and restore their default values: CANCTL0(8), CANRFLG(9),

CANRIER(10), CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.

The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be

written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the

error counters are not affected by initialization mode.

When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the

MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN

is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.

Writing to otherbits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after

initialization mode is exited, which is INITRQ = 0 and INITAK = 0.

0 Normal operation

1 MSCAN in initialization mode

1. The MSCAN must be in normal mode for this bit to become set.

2. See the Bosch CAN 2.0A/B speciﬁcation for a detailed deﬁnition of transmitter and receiver states.

3. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the

CPU enters wait (CSWAI = 1) or stop mode (see Section 11.4.5.2, “Operation in Wait Mode” and Section 11.4.5.3, “Operation

in Stop Mode”).

4. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 11.3.2.6,

“MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.

5. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).

6. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).

7. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the

initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode

(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.

8. Not including WUPE, INITRQ, and SLPRQ.

9. TSTAT1 and TSTAT0 are not affected by initialization mode.

10. RSTAT1 and RSTAT0 are not affected by initialization mode.

Table 11-3. CANCTL0 Register Field Descriptions (continued)

Field Description

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Module Base + 0x0001 Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1); CANE is write once

76543210

RCANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK

Reset: 00010001

= Unimplemented

Figure 11-5. MSCAN Control Register 1 (CANCTL1)

Table 11-4. CANCTL1 Register Field Descriptions

Field Description

CANE MSCAN Enable

0 MSCAN module is disabled

1 MSCAN module is enabled

CLKSRC MSCAN Clock Source — This bit deﬁnes the clock source for the MSCAN module (only for systems with a clock

generation module; Section 11.4.3.2, “Clock System,” and Section Figure 11-43., “MSCAN Clocking Scheme,”).

0 MSCAN clock source is the oscillator clock

1 MSCAN clock source is the bus clock

LOOPB Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used

for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN

input is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does

normally when transmitting and treats its own transmitted message as a message received from a remote node.

In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge ﬁeld to ensure

proper reception of its own message. Both transmit and receive interrupts are generated.

0 Loopback self test disabled

1 Loopback self test enabled

LISTEN Listen Only Mode — This bit conﬁgures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN

messages with matching ID are received, but no acknowledgement or error frames are sent out (see

Section 11.4.4.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports

applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any

messages when listen only mode is active.

0 Normal operation

1 Listen only mode activated

BORM Bus-Off Recovery Mode — This bit conﬁgures the bus-off state recovery mode of the MSCAN. Refer to

Section 11.5.2, “Bus-Off Recovery,” for details.

0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol speciﬁcation)

1 Bus-off recovery upon user request

WUPM Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit deﬁnes whether the integrated low-pass ﬁlter is

applied to protect the MSCAN from spurious wake-up (see Section 11.4.5.5, “MSCAN Sleep Mode”).

0 MSCAN wakes up on any dominant level on the CAN bus

1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup

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11.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)

The CANBTR0 register conﬁgures various CAN bus timing parameters of the MSCAN module.

SLPAK Sleep Mode Acknowledge — This ﬂag indicates whether the MSCAN module has entered sleep mode (see

Section 11.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake ﬂag for the SLPRQ sleep mode request.

Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will

clear the ﬂag if it detects activity on the CAN bus while in sleep mode.

0 Running — The MSCAN operates normally

1 Sleep mode active — The MSCAN has entered sleep mode

INITAK Initialization Mode Acknowledge — This ﬂag indicates whether the MSCAN module is in initialization mode

(see Section 11.4.4.5, “MSCAN Initialization Mode”). It is used as a handshake ﬂag for the INITRQ initialization

mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,

CANBTR0,CANBTR1,CANIDAC,CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by

the CPU when the MSCAN is in initialization mode.

0 Running — The MSCAN operates normally

1 Initialization mode active — The MSCAN has entered initialization mode

Module Base + 0x0002 Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

76543210

RSJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

Reset: 00000000

Figure 11-6. MSCAN Bus Timing Register 0 (CANBTR0)

Table 11-5. CANBTR0Register Field Descriptions

Field Description

7-6

SJW[1:0] Synchronization Jump Width — The synchronization jump width deﬁnes the maximum number of time quanta

(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the

CAN bus (see Table 11-6).

5-0

BRP[5:0] Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing

(see Table 11-7).

Table 11-6. Synchronization Jump Width

SJW1 SJW0 Synchronization Jump Width

0 0 1 Tq clock cycle

0 1 2 Tq clock cycles

1 0 3 Tq clock cycles

1 1 4 Tq clock cycles

Table 11-4. CANCTL1 Register Field Descriptions (continued)

Field Description

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11.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)

The CANBTR1 register conﬁgures various CAN bus timing parameters of the MSCAN module.

Table 11-7. Baud Rate Prescaler

BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P)

000000 1

000001 2

000010 3

000011 4

:::::: :

111111 64

Module Base + 0x0003 Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

76543210

RSAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

Reset: 00000000

Figure 11-7. MSCAN Bus Timing Register 1 (CANBTR1)

Table 11-8. CANBTR1 Register Field Descriptions

Field Description

SAMP Sampling — This bit determines the number of CAN bus samples taken per bit time.

0 One sample per bit.

1 Three samples per bit(1).

If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If

SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit

rates, it is recommended that only one sample is taken per bit time (SAMP = 0).

1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).

6-4

TSEG2[2:0] Time Segment 2 — Time segments within the bit time ﬁx the number of clock cycles per bit time and the location

of the sample point (see Figure 11-44). Time segment 2 (TSEG2) values are programmable as shown in

Table 11-9.

3-0

TSEG1[3:0] Time Segment 1 — Time segments within the bit time ﬁx the number of clock cycles per bit time and the location

of the sample point (see Figure 11-44). Time segment 1 (TSEG1) values are programmable as shown in

Table 11-10.

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The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time

quanta (Tq) clock cycles per bit (as shown in Table 11-9 and Table 11-10).

Eqn. 11-1

11.3.2.5 MSCAN Receiver Flag Register (CANRFLG)

A ﬂag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition

which caused the setting is no longer valid. Every ﬂag has an associated interrupt enable bit in the

CANRIER register.

Table 11-9. Time Segment 2 Values

TSEG22 TSEG21 TSEG20 Time Segment 2

0 0 0 1 Tq clock cycle(1)

1. This setting is not valid. Please refer to Table 11-37 for valid settings.

0 0 1 2 Tq clock cycles

::: :

1 1 0 7 Tq clock cycles

1 1 1 8 Tq clock cycles

Table 11-10. Time Segment 1 Values

TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1

0 0 0 0 1 Tq clock cycle(1)

1. This setting is not valid. Please refer to Table 11-37 for valid settings.

0 0 0 1 2 Tq clock cycles1

0 0 1 0 3 Tq clock cycles1

0 0 1 1 4 Tq clock cycles

:::: :

1 1 1 0 15 Tq clock cycles

1 1 1 1 16 Tq clock cycles

Module Base + 0x0004 Access: User read/write(1)

76543210

RWUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF

Reset: 00000000

= Unimplemented

Figure 11-8. MSCAN Receiver Flag Register (CANRFLG)

Bit Time Prescaler value()

fCANCLK

------------------------------------------------------1 TimeSegment1 TimeSegment2++()•=

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NOTE

The CANRFLG register is held in the reset state1 when the initialization

modeisactive(INITRQ= 1 andINITAK =1).This registeris writable again

as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).

1. Read: Anytime

Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] ﬂags which are read-only; write of 1 clears

ﬂag; write of 0 is ignored

1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.

Table 11-11. CANRFLG Register Field Descriptions

Field Description

WUPIF Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 11.4.5.5,

“MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 11.3.2.1, “MSCAN Control Register 0

(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ﬂag is set.

0 No wake-up activity observed while in sleep mode

1 MSCAN detected activity on the CAN bus and requested wake-up

CSCIF CAN Status Change Interrupt Flag — This ﬂag is set when the MSCAN changes its current CAN bus status

due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-

bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the

system on the actual CAN bus status (see Section 11.3.2.6, “MSCAN Receiver Interrupt Enable Register

(CANRIER)”). If not masked, an error interrupt is pending while this ﬂag is set. CSCIF provides a blocking

interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no

CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is

asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status

until the current CSCIF interrupt is cleared again.

0 No change in CAN bus status occurred since last interrupt

1 MSCAN changed current CAN bus status

5-4

RSTAT[1:0] Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As

soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate receiver related CAN

bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:

00 RxOK: 0 ≤ receive error counter ≤ 96

01 RxWRN: 96 < receive error counter ≤ 127

10 RxERR: 127 < receive error counter

11 Bus-off(1): transmit error counter > 255

3-2

TSTAT[1:0] Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.

As soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate transmitter related

CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:

00 TxOK: 0 ≤transmit error counter ≤ 96

01 TxWRN: 96 < transmit error counter ≤ 127

10 TxERR: 127 < transmit error counter ≤ 255

11 Bus-Off: transmit error counter > 255

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11.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)

This register contains the interrupt enable bits for the interrupt ﬂags described in the CANRFLG register.

NOTE

TheCANRIER registeris held inthereset statewhenthe initialization mode

is active (INITRQ=1 and INITAK=1). This register is writable when not in

initialization mode (INITRQ=0 and INITAK=0).

The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization

mode.

OVRIF Overrun Interrupt Flag — This ﬂag is set when a data overrun condition occurs. If not masked, an error interrupt

is pending while this ﬂag is set.

0 No data overrun condition

1 A data overrun detected

RXF(2) Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.

This ﬂag indicates whether the shifted buffer is loaded with a correctly received message (matching identiﬁer,

matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message

from the RxFG buffer in the receiver FIFO, the RXF ﬂag must be cleared to release the buffer. A set RXF ﬂag

prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt

is pending while this ﬂag is set.

0 No new message available within the RxFG

1 The receiver FIFO is not empty. A new message is available in the RxFG

1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds

a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state

skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.

2. To ensure data integrity, do not read the receive buffer registers while the RXF ﬂag is cleared. For MCUs with dual CPUs,

reading the receive buffer registers while the RXF ﬂag is cleared may result in a CPU fault condition.

Module Base + 0x0005 Access: User read/write(1)

1. Read: Anytime

Write: Anytime when not in initialization mode

76543210

RWUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE

Reset: 00000000

Figure 11-9. MSCAN Receiver Interrupt Enable Register (CANRIER)

Table 11-11. CANRFLG Register Field Descriptions (continued)

Field Description

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11.3.2.7 MSCAN Transmitter Flag Register (CANTFLG)

The transmit buffer empty ﬂags each have an associated interrupt enable bit in the CANTIER register.

Table 11-12. CANRIER Register Field Descriptions

Field Description

WUPIE(1)

1. WUPIE and WUPE (see Section 11.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery

mechanism from stop or wait is required.

Wake-Up Interrupt Enable

0 No interrupt request is generated from this event.

1 A wake-up event causes a Wake-Up interrupt request.

CSCIE CAN Status Change Interrupt Enable

0 No interrupt request is generated from this event.

1 A CAN Status Change event causes an error interrupt request.

5-4

RSTATE[1:0] Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state

changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT ﬂags continue to

indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.

00 Do not generate any CSCIF interrupt caused by receiver state changes.

01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state

changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”(2) state. Discard other

receiver state changes for generating CSCIF interrupt.

11 Generate CSCIF interrupt on all state changes.

2. Bus-off state is only deﬁned for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol speciﬁcation). Because

theonlypossiblestate change forthe transmitterfrom bus-off to TxOK also forcesthe receiverto skip its current state to RxOK,

the coding of the RXSTAT[1:0] ﬂags deﬁne an additional bus-off state for the receiver (see Section 11.3.2.5, “MSCAN Receiver

Flag Register (CANRFLG)”).

3-2

TSTATE[1:0] Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter

state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT ﬂags

continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.

00 Do not generate any CSCIF interrupt caused by transmitter state changes.

01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter

state changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other

transmitter state changes for generating CSCIF interrupt.

11 Generate CSCIF interrupt on all state changes.

OVRIE Overrun Interrupt Enable

0 No interrupt request is generated from this event.

1 An overrun event causes an error interrupt request.

RXFIE Receiver Full Interrupt Enable

0 No interrupt request is generated from this event.

1 A receive buffer full (successful message reception) event causes a receiver interrupt request.

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NOTE

The CANTFLG register is held in the reset state when the initialization

modeisactive(INITRQ= 1 andINITAK =1).This registeris writable when

not in initialization mode (INITRQ = 0 and INITAK = 0).

11.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)

This register contains the interrupt enable bits for the transmit buffer empty interrupt ﬂags.

Module Base + 0x0006 Access: User read/write(1)

1. Read: Anytime

Write: Anytime when not in initialization mode; write of 1 clears ﬂag, write of 0 is ignored

76543210

R0 0000

TXE2 TXE1 TXE0

Reset: 00000111

= Unimplemented

Figure 11-10. MSCAN Transmitter Flag Register (CANTFLG)

Table 11-13. CANTFLG Register Field Descriptions

Field Description

2-0

TXE[2:0] Transmitter Buffer Empty — This ﬂag indicates that the associated transmit message buffer is empty, and thus

not scheduled for transmission. The CPU must clear the ﬂag after a message is set up in the transmit buffer and

is due for transmission. The MSCAN sets the ﬂag after the message is sent successfully. The ﬂag is also set by

the MSCAN when the transmission request is successfully aborted due to a pending abort request (see

Section 11.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a

transmit interrupt is pending while this ﬂag is set.

Clearing a TXEx ﬂag also clears the corresponding ABTAKx (see Section 11.3.2.10, “MSCAN Transmitter

Message Abort Acknowledge Register (CANTAAK)”). When a TXEx ﬂag is set, the corresponding ABTRQx bit

is cleared (see Section 11.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”).

When listen-mode is active (see Section 11.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx ﬂags

cannot be cleared and no transmission is started.

Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared

(TXEx = 0) and the buffer is scheduled for transmission.

0 The associated message buffer is full (loaded with a message due for transmission)

1 The associated message buffer is empty (not scheduled)

Module Base + 0x0007 Access: User read/write(1)

76543210

R00000

TXEIE2 TXEIE1 TXEIE0

Reset: 00000000

= Unimplemented

Figure 11-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)

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NOTE

TheCANTIERregister isheldinthe reset state when theinitializationmode

is active (INITRQ = 1 and INITAK = 1). This register is writable when not

in initialization mode (INITRQ = 0 and INITAK = 0).

11.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ)

The CANTARQ register allows abort request of queued messages as described below.

NOTE

The CANTARQ register is held in the reset state when the initialization

modeisactive(INITRQ= 1 andINITAK =1).This registeris writable when

not in initialization mode (INITRQ = 0 and INITAK = 0).

1. Read: Anytime

Write: Anytime when not in initialization mode

Table 11-14. CANTIER Register Field Descriptions

Field Description

2-0

TXEIE[2:0] Transmitter Empty Interrupt Enable

0 No interrupt request is generated from this event.

1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt

request.

Module Base + 0x0008 Access: User read/write(1)

1. Read: Anytime

Write: Anytime when not in initialization mode

76543210

R00000

ABTRQ2 ABTRQ1 ABTRQ0

Reset: 00000000

= Unimplemented

Figure 11-12. MSCAN Transmitter Message Abort Request Register (CANTARQ)

Table 11-15. CANTARQ Register Field Descriptions

Field Description

2-0

ABTRQ[2:0] Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be

aborted. The MSCAN grants the request if the message has not already started transmission, or if the

transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see

Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge ﬂags (ABTAK, see

Section 11.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a

transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated

TXE ﬂag is set.

0 No abort request

1 Abort request pending

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11.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

The CANTAAK register indicates the successful abort of a queued message, if requested by the

appropriate bits in the CANTARQ register.

NOTE

The CANTAAK register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK = 1).

11.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)

The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be

accessible in the CANTXFG register space.

Module Base + 0x0009 Access: User read/write(1)

1. Read: Anytime

Write: Unimplemented

76543210

R00000ABTAK2 ABTAK1 ABTAK0

Reset: 00000000

= Unimplemented

Figure 11-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

Table 11-16. CANTAAK Register Field Descriptions

Field Description

2-0

ABTAK[2:0] Abort Acknowledge — This ﬂag acknowledges that a message was aborted due to a pending abort request

from the CPU. After a particular message buffer is ﬂagged empty, this ﬂag can be used by the application

software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx ﬂag is

cleared whenever the corresponding TXE ﬂag is cleared.

0 The message was not aborted.

1 The message was aborted.

Module Base + 0x000A Access: User read/write(1)

1. Read: Find the lowest ordered bit set to 1, all other bits will be read as 0

Write: Anytime when not in initialization mode

76543210

R00000

TX2 TX1 TX0

Reset: 00000000

= Unimplemented

Figure 11-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)

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NOTE

The CANTBSEL register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK=1). This register is writable when

not in initialization mode (INITRQ = 0 and INITAK = 0).

The following gives a short programming example of the usage of the CANTBSEL register:

To get the next available transmit buffer, application software must read the CANTFLG register and write

this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The

value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the

Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1.

Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered

bit position set to 1 is presented. This mechanism eases the application software’s selection of the next

available Tx buffer.

• LDAA CANTFLG; value read is 0b0000_0110

• STAA CANTBSEL; value written is 0b0000_0110

• LDAA CANTBSEL; value read is 0b0000_0010

If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.

11.3.2.12 MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

The CANIDAC register is used for identiﬁer acceptance control as described below.

Table 11-17. CANTBSEL Register Field Descriptions

Field Description

2-0

TX[2:0] Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG

buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx

bit is cleared and the buffer is scheduled for transmission (see Section 11.3.2.7, “MSCAN Transmitter Flag

0 The associated message buffer is deselected

1 The associated message buffer is selected, if lowest numbered bit

Module Base + 0x000B Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only

76543210

R0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0

Reset: 00000000

= Unimplemented

Figure 11-15. MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

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The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a

message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.

11.3.2.13 MSCAN Reserved Register

This register is reserved for factory testing of the MSCAN module and is not available in normal system

operating modes.

Table 11-18. CANIDAC Register Field Descriptions

Field Description

5-4

IDAM[1:0] Identiﬁer Acceptance Mode — The CPU sets these ﬂags to deﬁne the identiﬁer acceptance ﬁlter organization

(see Section 11.4.3, “Identiﬁer Acceptance Filter”). Table 11-19 summarizes the different settings. In ﬁlter closed

mode, no message is accepted such that the foreground buffer is never reloaded.

2-0

IDHIT[2:0] Identiﬁer Acceptance Hit Indicator — The MSCAN sets these ﬂags to indicate an identiﬁer acceptance hit (see

Section 11.4.3, “Identiﬁer Acceptance Filter”). Table 11-20 summarizes the different settings.

Table 11-19. Identiﬁer Acceptance Mode Settings

IDAM1 IDAM0 Identiﬁer Acceptance Mode

0 0 Two 32-bit acceptance ﬁlters

0 1 Four 16-bit acceptance ﬁlters

1 0 Eight 8-bit acceptance ﬁlters

1 1 Filter closed

Table 11-20. Identiﬁer Acceptance Hit Indication

IDHIT2 IDHIT1 IDHIT0 Identiﬁer Acceptance Hit

0 0 0 Filter 0 hit

0 0 1 Filter 1 hit

0 1 0 Filter 2 hit

0 1 1 Filter 3 hit

1 0 0 Filter 4 hit

1 0 1 Filter 5 hit

1 1 0 Filter 6 hit

1 1 1 Filter 7 hit

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NOTE

Writing to this register when in special system operating modes can alter the

MSCAN functionality.

11.3.2.14 MSCAN Miscellaneous Register (CANMISC)

This register provides additional features.

11.3.2.15 MSCAN Receive Error Counter (CANRXERR)

This register reﬂects the status of the MSCAN receive error counter.

Module Base + 0x000C to Module Base + 0x000D Access: User read/write(1)

1. Read: Always reads zero in normal system operation modes

Write: Unimplemented in normal system operation modes

76543210

R00000000

Reset: 00000000

= Unimplemented

Figure 11-16. MSCAN Reserved Register

Module Base + 0x000D Access: User read/write(1)

1. Read: Anytime

Write: Anytime; write of ‘1’ clears ﬂag; write of ‘0’ ignored

76543210

R0000000

BOHOLD

Reset: 00000000

= Unimplemented

Figure 11-17. MSCAN Miscellaneous Register (CANMISC)

Table 11-21. CANMISC Register Field Descriptions

Field Description

BOHOLD Bus-off State Hold Until User Request — If BORM is set in MSCAN Control Register 1 (CANCTL1), this bit

indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off.

Refer to Section 11.5.2, “Bus-Off Recovery,” for details.

0 Module is not bus-off or recovery has been requested by user in bus-off state

1 Module is bus-off and holds this state until user request

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NOTE

Reading this register when in any other mode other than sleep or

initialization mode may return an incorrect value. For MCUs with dual

CPUs, this may result in a CPU fault condition.

Writing to this register when in special modes can alter the MSCAN

functionality.

11.3.2.16 MSCAN Transmit Error Counter (CANTXERR)

This register reﬂects the status of the MSCAN transmit error counter.

NOTE

Reading this register when in any other mode other than sleep or

initialization mode, may return an incorrect value. For MCUs with dual

CPUs, this may result in a CPU fault condition.

Writing to this register when in special modes can alter the MSCAN

functionality.

Module Base + 0x000E Access: User read/write(1)

1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)

Write: Unimplemented

76543210

R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

Reset: 00000000

= Unimplemented

Figure 11-18. MSCAN Receive Error Counter (CANRXERR)

Module Base + 0x000F Access: User read/write(1)

1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)

Write: Unimplemented

76543210

R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

Reset: 00000000

= Unimplemented

Figure 11-19. MSCAN Transmit Error Counter (CANTXERR)

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11.3.2.17 MSCAN Identiﬁer Acceptance Registers (CANIDAR0-7)

On reception, each message is written into the background receive buffer. The CPU is only signalled to

read the message if it passes the criteria in the identiﬁer acceptance and identiﬁer mask registers

(accepted); otherwise, the message is overwritten by the next message (dropped).

The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 11.3.3.1,

“Identiﬁer Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 11.4.3,

“Identiﬁer Acceptance Filter”).

For extended identiﬁers, all four acceptance and mask registers are applied. For standard identiﬁers, only

the ﬁrst two (CANIDAR0/1, CANIDMR0/1) are applied.

Module Base + 0x0010 to Module Base + 0x0013 Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

76543210

RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Reset 00000000

Figure 11-20. MSCAN Identiﬁer Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3

Table 11-22. CANIDAR0–CANIDAR3 Register Field Descriptions

Field Description

7-0

AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

ofthe related identiﬁer register (IDRn) of the receivemessage buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

Module Base + 0x0018 to Module Base + 0x001B Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

76543210

RAC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Reset 00000000

Figure 11-21. MSCAN Identiﬁer Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7

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11.3.2.18 MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)

The identiﬁer mask register speciﬁes which of the corresponding bits in the identiﬁer acceptance register

are relevant for acceptance ﬁltering. To receive standard identiﬁers in 32 bit ﬁlter mode, it is required to

program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”

To receive standard identiﬁers in 16 bit ﬁlter mode, it is required to program the last three bits (AM[2:0])

in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”

Table 11-23. CANIDAR4–CANIDAR7 Register Field Descriptions

Field Description

7-0

AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

ofthe related identiﬁer register (IDRn) of the receivemessage buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

Module Base + 0x0014 to Module Base + 0x0017 Access: User read/write(1)

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

76543210

RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

Reset 00000000

Figure 11-22. MSCAN Identiﬁer Mask Registers (First Bank) — CANIDMR0–CANIDMR3

Table 11-24. CANIDMR0–CANIDMR3 Register Field Descriptions

Field Description

7-0

AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in

the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message

is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer

acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identiﬁer bits

1 Ignore corresponding acceptance code register bit

Module Base + 0x001C to Module Base + 0x001F Access: User read/write(1)

76543210

RAM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

Reset 00000000

Figure 11-23. MSCAN Identiﬁer Mask Registers (Second Bank) — CANIDMR4–CANIDMR7

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11.3.3 Programmer’s Model of Message Storage

The following section details the organization of the receive and transmit message buffers and the

associated control registers.

To simplify the programmer interface, the receive and transmit message buffers have the same outline.

Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.

An additional transmit buffer priority register (TBPR) is deﬁned for the transmit buffers. Within the last

two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an

internal timer after successful transmission or reception of a message. This feature is only available for

transmit and receiver buffers, if the TIME bit is set (see Section 11.3.2.1, “MSCAN Control Register 0

(CANCTL0)”).

The time stamp register is written by the MSCAN. The CPU can only read these registers.

1. Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 11-25. CANIDMR4–CANIDMR7 Register Field Descriptions

Field Description

7-0

AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in

the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message

is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer

acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identiﬁer bits

1 Ignore corresponding acceptance code register bit

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Figure 11-24 shows the common 13-byte data structure of receive and transmit buffers for extended

identiﬁers. The mapping of standard identiﬁers into the IDR registers is shown in Figure 11-25.

All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1.

All reserved or unused bits of the receive and transmit buffers always read ‘x’.

Table 11-26. Message Buffer Organization

Offset

Address Register Access

0x00X0 Identiﬁer Register 0 R/W

0x00X1 Identiﬁer Register 1 R/W

0x00X2 Identiﬁer Register 2 R/W

0x00X3 Identiﬁer Register 3 R/W

0x00X4 Data Segment Register 0 R/W

0x00X5 Data Segment Register 1 R/W

0x00X6 Data Segment Register 2 R/W

0x00X7 Data Segment Register 3 R/W

0x00X8 Data Segment Register 4 R/W

0x00X9 Data Segment Register 5 R/W

0x00XA Data Segment Register 6 R/W

0x00XB Data Segment Register 7 R/W

0x00XC Data Length Register R/W

0x00XD Transmit Buffer Priority Register(1)

1. Not applicable for receive buffers

R/W

0x00XE Time Stamp Register (High Byte) R

0x00XF Time Stamp Register (Low Byte) R

1. Exception: The transmit buffer priority registers are 0 out of reset.

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Figure 11-24. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping

Name Bit 7 654321Bit0

0x00X0

IDR0 RID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

0x00X1

IDR1 RID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15

0x00X2

IDR2 RID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7

0x00X3

IDR3 RID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

0x00X4

DSR0 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00X5

DSR1 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00X6

DSR2 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00X7

DSR3 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00X8

DSR4 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00X9

DSR5 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00XA

DSR6 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00XB

DSR7 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0x00XC

DLR RDLC3 DLC2 DLC1 DLC0

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Read:

• For transmit buffers, anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter

FlagRegister(CANTFLG)”) andthecorresponding transmit buffer is selected inCANTBSEL(see

Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).

• For receive buffers, only when RXF ﬂag is set (see Section 11.3.2.5, “MSCAN Receiver Flag

Write:

• For transmit buffers, anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter

FlagRegister(CANTFLG)”) andthecorresponding transmit buffer is selected inCANTBSEL(see

Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).

• Unimplemented for receive buffers.

Reset: Undeﬁned because of RAM-based implementation

11.3.3.1 Identiﬁer Registers (IDR0–IDR3)

The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits: ID[28:0], SRR, IDE,

and RTR. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits: ID[10:0],

RTR, and IDE.

= Unused, always read ‘x’

Figure 11-25. Receive/Transmit Message Buffer — Standard Identiﬁer Mapping

Name Bit 7 654321Bit 0

IDR0

0x00X0 RID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

IDR1

0x00X1 RID2 ID1 ID0 RTR IDE (=0)

IDR2

0x00X2 R

IDR3

0x00X3 R

= Unused, always read ‘x’

Figure 11-24. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping (continued)

Name Bit 7 654321Bit0

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11.3.3.1.1 IDR0–IDR3 for Extended Identiﬁer Mapping

Module Base + 0x00X0

76543210

RID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

Reset: xxxxxxxx

Figure 11-26. Identiﬁer Register 0 (IDR0) — Extended Identiﬁer Mapping

Table 11-27. IDR0 Register Field Descriptions — Extended

Field Description

7-0

ID[28:21] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

Module Base + 0x00X1

76543210

RID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15

Reset: xxxxxxxx

Figure 11-27. Identiﬁer Register 1 (IDR1) — Extended Identiﬁer Mapping

Table 11-28. IDR1 Register Field Descriptions — Extended

Field Description

7-5

ID[20:18] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

SRR Substitute Remote Request — This ﬁxed recessive bit is used only in extended format. It must be set to 1 by

the user for transmission buffers and is stored as received on the CAN bus for receive buffers.

IDE ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In

the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer

identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

2-0

ID[17:15] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

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Module Base + 0x00X2

76543210

RID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7

Reset: xxxxxxxx

Figure 11-28. Identiﬁer Register 2 (IDR2) — Extended Identiﬁer Mapping

Table 11-29. IDR2 Register Field Descriptions — Extended

Field Description

7-0

ID[14:7] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

Module Base + 0x00X3

76543210

RID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

Reset: xxxxxxxx

Figure 11-29. Identiﬁer Register 3 (IDR3) — Extended Identiﬁer Mapping

Table 11-30. IDR3 Register Field Descriptions — Extended

Field Description

7-1

ID[6:0] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

RTR Remote Transmission Request — This ﬂag reﬂects the status of the remote transmission request bit in the

CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the

transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of

the RTR bit to be sent.

0 Data frame

1 Remote frame

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11.3.3.1.2 IDR0–IDR3 for Standard Identiﬁer Mapping

Module Base + 0x00X0

76543210

RID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

Reset: xxxxxxxx

Figure 11-30. Identiﬁer Register 0 — Standard Mapping

Table 11-31. IDR0 Register Field Descriptions — Standard

Field Description

7-0

ID[10:3] Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 11-32.

Module Base + 0x00X1

76543210

RID2 ID1 ID0 RTR IDE (=0)

Reset: xxxxxxxx

= Unused; always read ‘x’

Figure 11-31. Identiﬁer Register 1 — Standard Mapping

Table 11-32. IDR1 Register Field Descriptions

Field Description

7-5

ID[2:0] Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 11-31.

RTR Remote Transmission Request — This ﬂag reﬂects the status of the Remote Transmission Request bit in the

CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the

transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of

the RTR bit to be sent.

0 Data frame

1 Remote frame

IDE ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In

the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer

identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

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11.3.3.2 Data Segment Registers (DSR0-7)

The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.

The number of bytes to be transmitted or received is determined by the data length code in the

corresponding DLR register.

Module Base + 0x00X2

76543210

Reset: xxxxxxxx

= Unused; always read ‘x’

Figure 11-32. Identiﬁer Register 2 — Standard Mapping

Module Base + 0x00X3

76543210

Reset: xxxxxxxx

= Unused; always read ‘x’

Figure 11-33. Identiﬁer Register 3 — Standard Mapping

Module Base + 0x00X4 to Module Base + 0x00XB

76543210

RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Reset: xxxxxxxx

Figure 11-34. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping

Table 11-33. DSR0–DSR7 Register Field Descriptions

Field Description

7-0

DB[7:0] Data bits 7-0

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11.3.3.3 Data Length Register (DLR)

This register keeps the data length ﬁeld of the CAN frame.

11.3.3.4 Transmit Buffer Priority Register (TBPR)

This register deﬁnes the local priority of the associated message buffer. The local priority is used for the

internal prioritization process of the MSCAN and is deﬁned to be highest for the smallest binary number.

The MSCAN implements the following internal prioritization mechanisms:

• All transmission buffers with a cleared TXEx ﬂag participate in the prioritization immediately

before the SOF (start of frame) is sent.

Module Base + 0x00XC

76543210

RDLC3 DLC2 DLC1 DLC0

Reset: xxxxxxxx

= Unused; always read “x”

Figure 11-35. Data Length Register (DLR) — Extended Identiﬁer Mapping

Table 11-34. DLR Register Field Descriptions

Field Description

3-0

DLC[3:0] Data Length Code Bits —Thedata length code contains the numberofbytes(data bytecount) of therespective

message. During the transmission of a remote frame, the data length code is transmitted as programmed while

the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.

Table 11-35 shows the effect of setting the DLC bits.

Table 11-35. Data Length Codes

Data Length Code Data Byte

Count

DLC3 DLC2 DLC1 DLC0

00000

00011

00102

00113

01004

01015

01106

01117

10008

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• The transmission buffer with the lowest local priority ﬁeld wins the prioritization.

In cases of more than one buffer having the same lowest priority, the message buffer with the lower index

number wins.

11.3.3.5 Time Stamp Register (TSRH–TSRL)

If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active

transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 11.3.2.1,

“MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time

stamp after the respective transmit buffer has been ﬂagged empty.

The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer

overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The

CPU can only read the time stamp registers.

Module Base + 0x00XD Access: User read/write(1)

1. Read: Anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the

corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”)

Write: Anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the

corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”)

76543210

RPRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0

Reset: 00000000

Figure 11-36. Transmit Buffer Priority Register (TBPR)

Module Base + 0x00XE Access: User read/write(1)

1. Read: Anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the

corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”)

Write: Unimplemented

76543210

R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8

Reset: xxxxxxxx

Figure 11-37. Time Stamp Register — High Byte (TSRH)

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Module Base + 0x00XF Access: User read/write(1)

1. Read: Anytime when TXEx ﬂag is set (see Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the

corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”)

Write: Unimplemented

76543210

R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0

Reset: xxxxxxxx

Figure 11-38. Time Stamp Register — Low Byte (TSRL)

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11.4 Functional Description

11.4.1 General

This section provides a complete functional description of the MSCAN.

11.4.2 Message Storage

Figure 11-39. User Model for Message Buffer Organization

MSCAN

Rx0

Rx1

CAN Receive / Transmit Engine Memory Mapped I/O

CPU bus

MSCAN

Tx2

TXE2

PRIO

Receiver

Transmitter

RxBG

TxBG

Tx0

TXE0

PRIO

TxBG

Tx1

PRIO

TXE1

TxFG

CPU bus

Rx2

Rx3

Rx4

RXF

RxFG

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The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a

broad range of network applications.

11.4.2.1 Message Transmit Background

Modern application layer software is built upon two fundamental assumptions:

• Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus

between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the

previous message and only release the CAN bus in case of lost arbitration.

• The internal message queue within any CAN node is organized such that the highest priority

message is sent out ﬁrst, if more than one message is ready to be sent.

The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer

must be reloaded immediately after the previous message is sent. This loading process lasts a ﬁnite amount

of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted

stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts

with short latencies to the transmit interrupt.

A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending

and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a

message is ﬁnished while the CPU re-loads the second buffer. No buffer would then be ready for

transmission, and the CAN bus would be released.

At least three transmit buffers are required to meet the ﬁrst of the above requirements under all

circumstances. The MSCAN has three transmit buffers.

The second requirement calls for some sort of internal prioritization which the MSCAN implements with

the “local priority” concept described in Section 11.4.2.2, “Transmit Structures.”

11.4.2.2 Transmit Structures

The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple

messages to be set up in advance. The three buffers are arranged as shown in Figure 11-39.

All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see

Section 11.3.3, “Programmer’s Model of Message Storage”). An additional Transmit Buffer Priority

Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a message, if required

(see Section 11.3.3.5, “Time Stamp Register (TSRH–TSRL)”).

To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set

transmitter buffer empty (TXEx) ﬂag (see Section 11.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the

CANTBSEL register (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see

Section 11.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the

CANTBSEL register simpliﬁes the transmit buffer selection. In addition, this scheme makes the handler

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software simpler because only one address area is applicable for the transmit process, and the required

address space is minimized.

The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers.

Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag.

The MSCAN then schedules the message for transmission and signals the successful transmission of the

buffer by setting the associated TXE ﬂag. A transmit interrupt (see Section 11.4.7.2, “Transmit Interrupt”)

is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.

If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,

the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this

purpose, every transmit buffer has an 8-bit local priority ﬁeld (PRIO). The application software programs

this ﬁeld when the message is set up. The local priority reﬂects the priority of this particular message

relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO ﬁeld

is deﬁned to be the highest priority. The internal scheduling process takes place whenever the MSCAN

arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.

When a high priority message is scheduled by the application software, it may become necessary to abort

a lower priority message in one of the three transmit buffers. Because messages that are already in

transmission cannot be aborted, the user must request the abort by setting the corresponding abort request

bit (ABTRQ) (see Section 11.3.2.9, “MSCAN Transmitter Message Abort Request Register

(CANTARQ)”.) The MSCAN then grants the request, if possible, by:

1. Setting the corresponding abort acknowledge ﬂag (ABTAK) in the CANTAAK register.

2. Setting the associated TXE ﬂag to release the buffer.

3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the

setting of the ABTAK ﬂag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).

11.4.2.3 Receive Structures

The received messages are stored in a ﬁve stage input FIFO. The ﬁve message buffers are alternately

mapped into a single memory area (see Figure 11-39). The background receive buffer (RxBG) is

exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the

CPU (see Figure 11-39). This scheme simpliﬁes the handler software because only one address area is

applicable for the receive process.

All receive buffers have a size of 15 bytes to store the CAN control bits, the identiﬁer (standard or

extended), the data contents, and a time stamp, if enabled (see Section 11.3.3, “Programmer’s Model of

Message Storage”).

The receiver full ﬂag (RXF) (see Section 11.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”)

signals the status of the foreground receive buffer. When the buffer contains a correctly received message

with a matching identiﬁer, this ﬂag is set.

On reception, each message is checked to see whether it passes the ﬁlter (see Section 11.4.3, “Identiﬁer

Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a

valid message, the MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF ﬂag, and

1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.

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generates a receive interrupt1 (see Section 11.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive

handler must read the received message from the RxFG and then reset the RXF ﬂag to acknowledge the

interrupt and to release the foreground buffer. A new message, which can follow immediatelyafter the IFS

ﬁeld of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid

message in its RxBG (wrong identiﬁer, transmission errors, etc.) the actual contents of the buffer will be

over-written by the next message. The buffer will then not be shifted into the FIFO.

When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the

background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt,

or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see

Section 11.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages

exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event

that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver.

An overrun condition occurs when all receive message buffers in the FIFO are ﬁlled with correctly

received messages with accepted identiﬁers and another message is correctly received from the CAN bus

with an accepted identiﬁer. The latter message is discarded and an error interrupt with overrun indication

is generated if enabled (see Section 11.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit

messages while the receiver FIFO is being ﬁlled, but all incoming messages are discarded. As soon as a

receive buffer in the FIFO is available again, new valid messages will be accepted.

11.4.3 Identiﬁer Acceptance Filter

The MSCAN identiﬁer acceptance registers (see Section 11.3.2.12, “MSCAN Identiﬁer Acceptance

Control Register (CANIDAC)”) deﬁne the acceptable patterns of the standard or extended identiﬁer

(ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identiﬁer mask

registers (see Section 11.3.2.18, “MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)”).

A ﬁlter hit is indicated to the application software by a set receive buffer full ﬂag (RXF = 1) and three bits

in the CANIDAC register (see Section 11.3.2.12, “MSCAN Identiﬁer Acceptance Control Register

(CANIDAC)”). These identiﬁer hit ﬂags (IDHIT[2:0]) clearly identify the ﬁlter section that caused the

acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If

more than one hit occurs (two or more ﬁlters match), the lower hit has priority.

A very ﬂexible programmable generic identiﬁer acceptance ﬁlter has been introduced to reduce the CPU

interrupt loading. The ﬁlter is programmable to operate in four different modes:

• Two identiﬁer acceptance ﬁlters, each to be applied to:

— The full 29 bits of the extended identiﬁer and to the following bits of the CAN 2.0B frame:

– Remote transmission request (RTR)

– Identiﬁer extension (IDE)

– Substitute remote request (SRR)

— The 11 bits of the standard identiﬁer plus the RTR and IDE bits of the CAN 2.0A/B messages.

This mode implements two ﬁlters for a full length CAN 2.0B compliant extended identiﬁer.

Although this mode can be used for standard identiﬁers, it is recommended to use the four or

eight identiﬁer acceptance ﬁlters.

1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.

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Figure 11-40 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3,

CANIDMR0–CANIDMR3) produces a ﬁlter 0 hit. Similarly, the second ﬁlter bank

(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a ﬁlter 1 hit.

• Four identiﬁer acceptance ﬁlters, each to be applied to:

— The 14 most signiﬁcant bits of the extended identiﬁer plus the SRR and IDE bits of CAN 2.0B

messages.

— The 11 bits of the standard identiﬁer, the RTR and IDE bits of CAN 2.0A/B messages.

Figure 11-41 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDA3,

CANIDMR0–3CANIDMR) produces ﬁlter 0 and 1 hits. Similarly, the second ﬁlter bank

(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces ﬁlter 2 and 3 hits.

• Eight identiﬁer acceptance ﬁlters, each to be applied to the ﬁrst 8 bits of the identiﬁer. This mode

implements eight independent ﬁlters for the ﬁrst 8 bits of a CAN 2.0A/B compliant standard

identiﬁer or a CAN 2.0B compliant extended identiﬁer.

Figure 11-42 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3,

CANIDMR0–CANIDMR3) produces ﬁlter 0 to 3 hits. Similarly, the second ﬁlter bank

(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces ﬁlter 4 to 7 hits.

• Closed ﬁlter. No CAN message is copied into the foreground buffer RxFG, and the RXF ﬂag is

never set.

Figure 11-40. 32-bit Maskable Identiﬁer Acceptance Filter

ID28 ID21IDR0

ID10 ID3IDR0

ID20 ID15IDR1

ID2 IDEIDR1

ID14 ID7IDR2

ID10 ID3IDR2

ID6 RTRIDR3

ID10 ID3IDR3

AC7 AC0CANIDAR0

AM7 AM0CANIDMR0

AC7 AC0CANIDAR1

AM7 AM0CANIDMR1

AC7 AC0CANIDAR2

AM7 AM0CANIDMR2

AC7 AC0CANIDAR3

AM7 AM0CANIDMR3

ID Accepted (Filter 0 Hit)

CAN 2.0B

Extended Identiﬁer

CAN 2.0A/B

Standard Identiﬁer

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Figure 11-41. 16-bit Maskable Identiﬁer Acceptance Filters

ID28 ID21IDR0

ID10 ID3IDR0

ID20 ID15IDR1

ID2 IDEIDR1

ID14 ID7IDR2

ID10 ID3IDR2

ID6 RTRIDR3

ID10 ID3IDR3

AC7 AC0CANIDAR0

AM7 AM0CANIDMR0

AC7 AC0CANIDAR1

AM7 AM0CANIDMR1

ID Accepted (Filter 0 Hit)

AC7 AC0CANIDAR2

AM7 AM0CANIDMR2

AC7 AC0CANIDAR3

AM7 AM0CANIDMR3

ID Accepted (Filter 1 Hit)

CAN 2.0B

Extended Identiﬁer

CAN 2.0A/B

Standard Identiﬁer

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Figure 11-42. 8-bit Maskable Identiﬁer Acceptance Filters

CAN 2.0B

Extended Identiﬁer

CAN 2.0A/B

Standard Identiﬁer

AC7 AC0CIDAR3

AM7 AM0CIDMR3

ID Accepted (Filter 3 Hit)

AC7 AC0CIDAR2

AM7 AM0CIDMR2

ID Accepted (Filter 2 Hit)

AC7 AC0CIDAR1

AM7 AM0CIDMR1

ID Accepted (Filter 1 Hit)

ID28 ID21IDR0

ID10 ID3IDR0

ID20 ID15IDR1

ID2 IDEIDR1

ID14 ID7IDR2

ID10 ID3IDR2

ID6 RTRIDR3

ID10 ID3IDR3

AC7 AC0CIDAR0

AM7 AM0CIDMR0

ID Accepted (Filter 0 Hit)

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11.4.3.1 Protocol Violation Protection

The MSCAN protects the user from accidentally violating the CAN protocol through programming errors.

The protection logic implements the following features:

• The receive and transmit error counters cannot be written or otherwise manipulated.

• All registers which control the conﬁguration of the MSCAN cannot be modiﬁedwhile the MSCAN

is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK

handshake bits in the CANCTL0/CANCTL1 registers (see Section 11.3.2.1, “MSCAN Control

— MSCAN control 1 register (CANCTL1)

— MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1)

— MSCAN identiﬁer acceptance control register (CANIDAC)

— MSCAN identiﬁer acceptance registers (CANIDAR0–CANIDAR7)

— MSCAN identiﬁer mask registers (CANIDMR0–CANIDMR7)

• The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power

down mode or initialization mode (see Section 11.4.5.6, “MSCAN Power Down Mode,” and

Section 11.4.4.5, “MSCAN Initialization Mode”).

• The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which

provides further protection against inadvertently disabling the MSCAN.

11.4.3.2 Clock System

Figure 11-43 shows the structure of the MSCAN clock generation circuitry.

Figure 11-43. MSCAN Clocking Scheme

The clock source bit (CLKSRC) in the CANCTL1 register (11.3.2.2/11-303) deﬁnes whether the internal

CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock.

The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the

CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the

clock is required.

If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the

bus clock due to jitter considerations, especially at the faster CAN bus rates.

Bus Clock

Oscillator Clock

MSCAN

CANCLK

CLKSRC

Prescaler

(1 .. 64)

Time quanta clock (Tq)

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For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal

oscillator (oscillator clock).

A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the

atomic unit of time handled by the MSCAN.

Eqn. 11-2

A bit time is subdivided into three segments as described in the Bosch CAN speciﬁcation. (see Figure 11-

44):

• SYNC_SEG: This segment has a ﬁxed length of one time quantum. Signal edges are expected to

happen within this section.

• Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN

standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.

• Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be

programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.

Eqn. 11-3

Figure 11-44. Segments within the Bit Time

Tq fCANCLK

Prescaler value(

)

----------------------------------------------------

Bit Rate fTq

number of Time Quanta()

---------------------------------------------------------------------------------=

SYNC_SEG Time Segment 1 Time Segment 2

1 4 ... 16 2 ... 8

8 ... 25 Time Quanta

= 1 Bit Time

NRZ Signal

Sample Point

(single or triple sampling)

(PROP_SEG + PHASE_SEG1) (PHASE_SEG2)

Transmit Point

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The synchronization jump width (see the Bosch CAN speciﬁcation for details) can be programmed in a

range of 1 to 4 time quanta by setting the SJW parameter.

The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing

registers (CANBTR0, CANBTR1) (see Section 11.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)”

and Section 11.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”).

Table 11-37 gives an overview of the CAN compliant segment settings and the related parameter values.

NOTE

It is the user’s responsibility to ensure the bit time settings are in compliance

with the CAN standard.

11.4.4 Modes of Operation

11.4.4.1 Normal System Operating Modes

The MSCAN module behaves as described within this speciﬁcation in all normal system operating modes.

Write restrictions exist for some registers.

Table 11-36. Time Segment Syntax

Syntax Description

SYNC_SEG System expects transitions to occur on the CAN bus during this

period.

Transmit Point A node in transmit mode transfers a new value to the CAN bus at

this point.

Sample Point A node in receive mode samples the CAN bus at this point. If the

three samples per bit option is selected, then this point marks the

position of the third sample.

Table 11-37. CAN Standard Compliant Bit Time Segment Settings

Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchronization

Jump Width SJW

5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1

4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2

5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3

6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3

7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3

8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3

9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3

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11.4.4.2 Special System Operating Modes

The MSCAN module behaves as described within this speciﬁcation in all special system operating modes.

Write restrictions which exist on speciﬁc registers in normal modes are lifted for test purposes in special

modes.

11.4.4.3 Emulation Modes

In all emulation modes, the MSCAN module behaves just like in normal system operating modes as

described within this speciﬁcation.

11.4.4.4 Listen-Only Mode

In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames

and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a

transmission.

If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload ﬂag, or active error ﬂag), the

bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although the CAN bus

may remain in recessive state externally.

11.4.4.5 MSCAN Initialization Mode

The MSCAN enters initialization mode when it is enabled (CANE=1).

When entering initialization mode during operation, any on-going transmission or reception is

immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol

violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN

immediately drives TXCAN into a recessive state.

NOTE

The user is responsible for ensuring that the MSCAN is not active when

initialization mode is entered. The recommended procedure is to bring the

MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the

INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going

message can cause an error condition and can impact other CAN bus

devices.

In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode

is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ,

CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the

conﬁguration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR,

CANIDMR message ﬁlters. See Section 11.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a

detailed description of the initialization mode.

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Figure 11-45. Initialization Request/Acknowledge Cycle

Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by

using a special handshake mechanism. This handshake causes additional synchronization delay (see

Figure 11-45).

If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus

clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the

INITAK ﬂag is set. The application software must use INITAK as a handshake indication for the request

(INITRQ) to go into initialization mode.

NOTE

The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and

INITAK = 1) is active.

11.4.5 Low-Power Options

If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving.

If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power

consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption

is reduced by stopping all clocks except those to access the registers from the CPU side. In power down

mode, all clocks are stopped and no power is consumed.

Table 11-38 summarizes the combinations of MSCAN and CPU modes. A particular combination of

modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits.

SYNC

Bus Clock Domain CAN Clock Domain

CPU

Init Request

INIT

Flag

INITAK

Flag

INITRQ

sync.

INITAK

sync.

INITRQ

INITAK

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11.4.5.1 Operation in Run Mode

As shown in Table 11-38, only MSCAN sleep mode is available as low power option when the CPU is in

run mode.

11.4.5.2 Operation in Wait Mode

The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set,

additional power can be saved in power down mode because the CPU clocks are stopped. After leaving

this power down mode, the MSCAN restarts and enters normal mode again.

While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts

(registers can be accessed via background debug mode).

11.4.5.3 Operation in Stop Mode

The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the

MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits

(Table 11-38).

11.4.5.4 MSCAN Normal Mode

This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal

mode. In this mode the module can either be in initialization mode or out of initialization mode. See

Section 11.4.4.5, “MSCAN Initialization Mode”.

Table 11-38. CPU vs. MSCAN Operating Modes

CPU Mode

MSCAN Mode

Normal

Reduced Power Consumption

Sleep Power Down Disabled

(CANE=0)

RUN CSWAI = X(1)

SLPRQ = 0

SLPAK = 0

1. ‘X’ means don’t care.

CSWAI = X

SLPRQ = 1

SLPAK = 1

CSWAI = X

SLPRQ = X

SLPAK = X

WAIT CSWAI = 0

SLPRQ = 0

SLPAK = 0

CSWAI = 0

SLPRQ = 1

SLPAK = 1

CSWAI = 1

SLPRQ = X

SLPAK = X

CSWAI = X

SLPRQ = X

SLPAK = X

STOP CSWAI = X

SLPRQ = X

SLPAK = X

CSWAI = X

SLPRQ = X

SLPAK = X

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11.4.5.5 MSCAN Sleep Mode

The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the

CANCTL0 register. The time when the MSCAN enters sleep mode depends on a ﬁxed synchronization

delay and its current activity:

• If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will

continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted

successfully or aborted) and then goes into sleep mode.

• If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN

bus next becomes idle.

• If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.

Figure 11-46. Sleep Request / Acknowledge Cycle

NOTE

The application software must avoid setting up a transmission (by clearing

one or more TXEx ﬂag(s)) and immediately request sleep mode (by setting

SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode

directly depends on the exact sequence of operations.

If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 11-46). The application software must

use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode.

When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks

that allow register accesses from the CPU side continue to run.

If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits

due to the stopped clocks. TXCAN remains in a recessive state. If RXF = 1, the message can be read and

RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does

not take place while in sleep mode.

It is possible to access the transmit buffers and to clear the associated TXE ﬂags. No message abort takes

place while in sleep mode.

SYNC

Bus Clock Domain CAN Clock Domain

MSCAN

in Sleep Mode

CPU

Sleep Request

SLPRQ

Flag

SLPAK

Flag

SLPRQ

sync.

SLPAK

sync.

SLPRQ

SLPAK

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If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN.

RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE

must be set before entering sleep mode to take effect.

The MSCAN is able to leave sleep mode (wake up) only when:

• CAN bus activity occurs and WUPE = 1

• the CPU clears the SLPRQ bit

NOTE

The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and

SLPAK = 1) is active.

After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a

consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.

The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode

was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message

aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it

continues counting the 128 occurrences of 11 consecutive recessive bits.

11.4.5.6 MSCAN Power Down Mode

The MSCAN is in power down mode (Table 11-38) when

• CPU is in stop mode

• CPU is in wait mode and the CSWAI bit is set

When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and

receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal

consequences of violations to the above rule, the MSCAN immediately drives TXCAN into a recessive

state.

NOTE

The user is responsible for ensuring that the MSCAN is not active when

power down mode is entered. The recommended procedure is to bring the

MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI

is set) is executed. Otherwise, the abort of an ongoing message can cause an

error condition and impact other CAN bus devices.

In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in

sleep mode before power down mode became active, the module performs an internal recovery cycle after

powering up. This causes some ﬁxed delay before the module enters normal mode again.

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11.4.5.7 Disabled Mode

The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving,

however the register map can still be accessed as speciﬁed.

11.4.5.8 Programmable Wake-Up Function

The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity

is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing

CAN bus action can be modiﬁed by applying a low-pass ﬁlter function to the RXCAN input line (see

control bit WUPM in Section 11.3.2.2, “MSCAN Control Register 1 (CANCTL1)”).

This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.

Such glitches can result from—for example—electromagnetic interference within noisy environments.

11.4.6 Reset Initialization

The reset state of each individual bit is listed in Section 11.3.2, “Register Descriptions,” which details all

the registers and their bit-ﬁelds.

11.4.7 Interrupts

This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated

ﬂags. Each interrupt is listed and described separately.

11.4.7.1 Description of Interrupt Operation

The MSCAN supports four interrupt vectors (see Table 11-39), any of which can be individually masked

(for details see Section 11.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)” to

Section 11.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”).

Refer to the device overview section to determine the dedicated interrupt vector addresses.

11.4.7.2 Transmit Interrupt

At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message

for transmission. The TXEx ﬂag of the empty message buffer is set.

Table 11-39. Interrupt Vectors

Interrupt Source CCR Mask Local Enable

Wake-Up Interrupt (WUPIF) I bit CANRIER (WUPIE)

Error Interrupts Interrupt (CSCIF, OVRIF) I bit CANRIER (CSCIE, OVRIE)

Receive Interrupt (RXF) I bit CANRIER (RXFIE)

Transmit Interrupts (TXE[2:0]) I bit CANTIER (TXEIE[2:0])

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11.4.7.3 Receive Interrupt

A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.

This interrupt is generated immediately after receiving the EOF symbol. The RXF ﬂag is set. If there are

multiple messages in the receiver FIFO, the RXF ﬂag is set as soon as the next message is shifted to the

foreground buffer.

11.4.7.4 Wake-Up Interrupt

A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN sleep or power-down

mode.

NOTE

This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1

and SLPAK = 1) before entering power down mode, the wake-up option is

enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).

11.4.7.5 Error Interrupt

An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition

occurrs. MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions:

•Overrun — An overrun condition of the receiver FIFO as described in Section 11.4.2.3, “Receive

Structures,” occurred.

•CAN Status Change — The actual value of the transmit and receive error counters control the

CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-

warning, Tx/Rx-error, bus-off) the MSCAN ﬂags an error condition. The status change, which

caused the error condition, is indicated by the TSTAT and RSTAT ﬂags (see Section 11.3.2.5,

“MSCAN Receiver Flag Register (CANRFLG)” and Section 11.3.2.6, “MSCAN Receiver

Interrupt Enable Register (CANRIER)”).

11.4.7.6 Interrupt Acknowledge

Interruptsaredirectly associatedwithone or morestatus ﬂags ineitherthe MSCAN ReceiverFlagRegister

(CANRFLG) or the MSCAN Transmitter Flag Register (CANTFLG). Interrupts are pending as long as

one of the corresponding ﬂags is set. The ﬂags in CANRFLG and CANTFLG must be reset within the

interrupt handler to handshake the interrupt. The ﬂags are reset by writing a 1 to the corresponding bit

position. A ﬂag cannot be cleared if the respective condition prevails.

NOTE

It must be guaranteed that the CPU clears only the bit causing the current

interrupt. For this reason, bit manipulation instructions (BSET) must not be

used to clear interrupt ﬂags. These instructions may cause accidental

clearing of interrupt ﬂags which are set after entering the current interrupt

service routine.

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11.5 Initialization/Application Information

11.5.1 MSCAN initialization

The procedure to initially start up the MSCAN module out of reset is as follows:

1. Assert CANE

2. Write to the conﬁguration registers in initialization mode

3. Clear INITRQ to leave initialization mode

If the conﬁguration of registers which are only writable in initialization mode shall be changed:

1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN

bus becomes idle.

2. Enter initialization mode: assert INITRQ and await INITAK

3. Write to the conﬁguration registers in initialization mode

4. Clear INITRQ to leave initialization mode and continue

11.5.2 Bus-Off Recovery

The bus-off recovery is user conﬁgurable. The bus-off state can either be left automatically or on user

request.

For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this

case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive

recessive bits on the CAN bus (see the Bosch CAN speciﬁcation for details).

If the MSCAN is conﬁgured for user request (BORM set in MSCAN Control Register 1 (CANCTL1)), the

recovery from bus-off starts after both independent events have become true:

• 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored

• BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user

These two events may occur in any order.

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Chapter 12

Periodic Interrupt Timer (S12PIT24B4CV1)

Table 12-1. Revision History

12.1 Introduction

The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules

or raise periodic interrupts. Refer to Figure 12-1 for a simpliﬁed block diagram.

12.1.1 Glossary

12.1.2 Features

The PIT includes these features:

• Four timers implemented as modulus down-counters with independent time-out periods.

• Time-out periods selectable between 1 and 224 bus clock cycles. Time-out equals m*n bus clock

cycles with 1 <= m <= 256 and 1 <= n <= 65536.

• Timers that can be enabled individually.

• Four time-out interrupts.

• Four time-out trigger output signals available to trigger peripheral modules.

• Start of timer channels can be aligned to each other.

12.1.3 Modes of Operation

Refer to the SoC guide for a detailed explanation of the chip modes.

Version

Number Revision

Date Effective

Date Author Description of Changes

01.00 28-Apr-05 28-Apr-05 Initial Release

01.01 05-Jul-05 05-Jul-05 Added application section, removed table 1-1

Acronyms and Abbreviations

PIT Periodic Interrupt Timer

ISR Interrupt Service Routine

CCR Condition Code Register

SoC System on Chip

micro time bases clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit

modulus down-counters.

Periodic Interrupt Timer (S12PIT24B4CV1)

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• Run mode

This is the basic mode of operation.

• Wait mode

PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register.

In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates

like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled.

• Stop mode

In full stop mode or pseudo stop mode, the PIT module is stalled.

• Freeze mode

PIT operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register.

In freeze mode, if the PITFRZ bit is clear, the PIT operates like in run mode. In freeze mode, if the

PITFRZ bit is set, the PIT module is stalled.

12.1.4 Block Diagram

Figure 12-1 shows a block diagram of the PIT module.

Figure 12-1. PIT24B4C Block Diagram

12.2 External Signal Description

The PIT module has no external pins.

Time-Out 0

Time-Out 1

Time-Out 2

Time-Out 3

16-Bit Timer 1

16-Bit Timer 3

16-Bit Timer 0

16-Bit Timer 2

Bus Clock

Micro Time

Base 0

Micro

Time

Base 1

Interrupt 0

Trigger 0

Interface

Interrupt 1

Trigger 1

Interface

Interrupt 2

Trigger 2

Interface

Interrupt 3

Trigger 3

Interface

8-Bit

Micro Timer 0

8-Bit

Micro Timer 1

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 351

12.3 Register Deﬁnition

This section consists of register descriptions in address order of the PIT. Each description includes a

standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow

the register diagrams, in bit order.

Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000

PITCFLMT RPITE PITSWAI PITFRZ 00000

WPFLMT1 PFLMT0

0x0001

PITFLT R00000000

WPFLT3 PFLT2 PFLT1 PFLT0

0x0002

PITCE R0000

PCE3 PCE2 PCE1 PCE0

0x0003

PITMUX R0000

PMUX3 PMUX2 PMUX1 PMUX0

0x0004

PITINTE R0000

PINTE3 PINTE2 PINTE1 PINTE0

0x0005

PITTF R0000

PTF3 PTF2 PTF1 PTF0

0x0006

PITMTLD0 RPMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0

0x0007

PITMTLD1 RPMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0

0x0008

PITLD0 (High) RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8

0x0009

PITLD0 (Low) RPLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

0x000A

PITCNT0 (High) RPCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8

0x000B

PITCNT0 (Low) RPCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0

0x000C

PITLD1 (High) RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8

= Unimplemented or Reserved

Figure 12-2. PIT Register Summary (Sheet 1 of 2)

Periodic Interrupt Timer (S12PIT24B4CV1)

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352 Freescale Semiconductor

0x000D

PITLD1 (Low) RPLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

0x000E

PITCNT1 (High) RPCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8

0x000F

PITCNT1 (Low) RPCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0

0x0010

PITLD2 (High) RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8

0x0011

PITLD2 (Low) RPLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

0x0012

PITCNT2 (High) RPCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8

0x0013

PITCNT2 (Low) RPCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0

0x0014

PITLD3 (High) RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8

0x0015

PITLD3 (Low) RPLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

0x0016

PITCNT3 (High) RPCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8

0x0017

PITCNT3 (Low) RPCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0

0x0018−0x0027

RESERVED R00000000

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 12-2. PIT Register Summary (Sheet 2 of 2)

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 353

12.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Module Base + 0x0000

76543210

RPITE PITSWAI PITFRZ 00000

WPFLMT1 PFLMT0

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 12-3. PIT Control and Force Load Micro Timer Register (PITCFLMT)

Table 12-2. PITCFLMT Field Descriptions

Field Description

PITE PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and

ﬂag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-

counting with the corresponding load register values.

0 PIT disabled (lower power consumption).

1 PIT is enabled.

PITSWAI PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.

0 PIT operates normally in wait mode

1 PIT clock generation stops and freezes the PIT module when in wait mode

PITFRZ PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is

encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ

bit controls the PIT operation while in freeze mode.

0 PIT operates normally in freeze mode

1 PIT counters are stalled when in freeze mode

1:0

PFLMT[1:0] PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is

active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit

micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits

will always return zero.

Note: A micro timer force load affects all timer channels that use the corresponding micro time base.

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

354 Freescale Semiconductor

12.3.0.2 PIT Force Load Timer Register (PITFLT)

Read: Anytime

Write: Anytime

12.3.0.3 PIT Channel Enable Register (PITCE)

Read: Anytime

Write: Anytime

Module Base + 0x0001

76543210

R00000000

WPFLT3 PFLT2 PFLT1 PFLT0

Reset 0 0 0 00000

Figure 12-4. PIT Force Load Timer Register (PITFLT)

Table 12-3. PITFLT Field Descriptions

Field Description

3:0

PFLT[3:0] PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE

set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding

16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will

always return zero.

Module Base + 0x0002

76543210

R0000

PCE3 PCE2 PCE1 PCE0

Reset 0 0 0 00000

Figure 12-5. PIT Channel Enable Register (PITCE)

Table 12-4. PITCE Field Descriptions

Field Description

3:0

PCE[3:0] PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT

channel is disabled and the corresponding ﬂag bit in the PITTF register is cleared. When PCE is set, and if the

PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-

counting.

0 The corresponding PIT channel is disabled.

1 The corresponding PIT channel is enabled.

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 355

12.3.0.4 PIT Multiplex Register (PITMUX)

Read: Anytime

Write: Anytime

12.3.0.5 PIT Interrupt Enable Register (PITINTE)

Read: Anytime

Write: Anytime

Module Base + 0x0003

76543210

R0000

PMUX3 PMUX2 PMUX1 PMUX0

Reset 0 0 0 00000

Figure 12-6. PIT Multiplex Register (PITMUX)

Table 12-5. PITMUX Field Descriptions

Field Description

3:0

PMUX[3:0] PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to

micro time base 1 or 0. If PMUX is modiﬁed, the corresponding 16-bit timer is switched to the other micro time

base immediately.

0 The corresponding 16-bit timer counts with micro time base 0.

1 The corresponding 16-bit timer counts with micro time base 1.

Module Base + 0x0004

76543210

R0000

PINTE3 PINTE2 PINTE1 PINTE0

Reset 0 0 0 00000

Figure 12-7. PIT Interrupt Enable Register (PITINTE)

Table 12-6. PITINTE Field Descriptions

Field Description

3:0

PINTE[3:0] PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request

whenever the time-out ﬂag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)

enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF ﬂag has to be

cleared ﬁrst.

0 Interrupt of the corresponding PIT channel is disabled.

1 Interrupt of the corresponding PIT channel is enabled.

Periodic Interrupt Timer (S12PIT24B4CV1)

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356 Freescale Semiconductor

12.3.0.6 PIT Time-Out Flag Register (PITTF)

Read: Anytime

Write: Anytime (write to clear)

12.3.0.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD0–1)

Read: Anytime

Write: Anytime

Module Base + 0x0005

76543210

R0000

PTF3 PTF2 PTF1 PTF0

Reset 0 0 0 00000

Figure 12-8. PIT Time-Out Flag Register (PITTF)

Table 12-7. PITTF Field Descriptions

Field Description

3:0

PTF[3:0] PIT Time-out Flag Bits for Timer Channel 3:0 — PTF is set when the corresponding 16-bit timer modulus

down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. The ﬂag can be

clearedbywriting aone to the ﬂag bit. Writinga zerohas no effect.If ﬂag clearingbywritinga one and ﬂag setting

happen in the same bus clock cycle, the ﬂag remains set. The ﬂag bits are cleared if the PIT module is disabled

or if the corresponding timer channel is disabled.

0 Time-out of the corresponding PIT channel has not yet occurred.

1 Time-out of the corresponding PIT channel has occurred.

Module Base + 0x0006

76543210

RPMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0

Reset 0 0 0 00000

Figure 12-9. PIT Micro Timer Load Register 0 (PITMTLD0)

Module Base + 0x0007

76543210

RPMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0

Reset 0 0 0 00000

Figure 12-10. PIT Micro Timer Load Register 1 (PITMTLD1)

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 357

Table 12-8. PITMTLD0–1 Field Descriptions

Field Description

7:0

PMTLD[7:0] PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers.

Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down

to zero, the PMTLD register value will be loaded. The PFLMT bits in the PITCFLMT register can be used to

immediately update the count register with the new value if an immediate load is desired.

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

358 Freescale Semiconductor

12.3.0.8 PIT Load Register 0 to 3 (PITLD0–3)

Read: Anytime

Write: Anytime

Module Base + 0x0008, 0x0009

15 14 13 12 11 109876543210

RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 12-11. PIT Load Register 0 (PITLD0)

Module Base + 0x000C, 0x000D

15 14 13 12 11 109876543210

RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 12-12. PIT Load Register 1 (PITLD1)

Module Base + 0x0010, 0x0011

15 14 13 12 11 109876543210

RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 12-13. PIT Load Register 2 (PITLD2)

Module Base + 0x0014, 0x0015

15 14 13 12 11 109876543210

RPLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 12-14. PIT Load Register 3 (PITLD3)

Table 12-9. PITLD0–3 Field Descriptions

Field Description

15:0

PLD[15:0] PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the

PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer

has counted down to zero the PTF time-out ﬂag will be set and the register value will be loaded. The PFLT bits

in the PITFLT register can be used to immediately update the count register with the new value if an immediate

load is desired.

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 359

12.3.0.9 PIT Count Register 0 to 3 (PITCNT0–3)

Read: Anytime

Write: Has no meaning or effect

Module Base + 0x000A, 0x000B

15 14 13 12 11 109876543210

RPCNT

15 PCNT

14 PCNT

13 PCNT

12 PCNT

11 PCNT

10 PCNT

9PCNT

8PCNT

7PCNT

6PCNT

5PCNT

4PCNT

3PCNT

2PCNT

1PCNT

Reset 0000000000000000

Figure 12-15. PIT Count Register 0 (PITCNT0)

Module Base + 0x000E, 0x000F

15 14 13 12 11 109876543210

RPCNT

15 PCNT

14 PCNT

13 PCNT

12 PCNT

11 PCNT

10 PCNT

9PCNT

8PCNT

7PCNT

6PCNT

5PCNT

4PCNT

3PCNT

2PCNT

1PCNT

Reset 0000000000000000

Figure 12-16. PIT Count Register 1 (PITCNT1)

Module Base + 0x0012, 0x0013

15 14 13 12 11 109876543210

RPCNT

15 PCNT

14 PCNT

13 PCNT

12 PCNT

11 PCNT

10 PCNT

9PCNT

8PCNT

7PCNT

6PCNT

5PCNT

4PCNT

3PCNT

2PCNT

1PCNT

Reset 0000000000000000

Figure 12-17. PIT Count Register 2 (PITCNT2)

Module Base + 0x0016, 0x0017

15 14 13 12 11 109876543210

RPCNT

15 PCNT

14 PCNT

13 PCNT

12 PCNT

11 PCNT

10 PCNT

9PCNT

8PCNT

7PCNT

6PCNT

5PCNT

4PCNT

3PCNT

2PCNT

1PCNT

Reset 0000000000000000

Figure 12-18. PIT Count Register 3 (PITCNT3)

Table 12-10. PITCNT0–3 Field Descriptions

Field Description

15:0

PCNT[15:0] PIT Count Bits 15-0 — These bits represent the current 16-bit modulus down-counter value. The read access

for the count register must take place in one clock cycle as a 16-bit access.

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

360 Freescale Semiconductor

12.4 Functional Description

Figure 12-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status,

control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger

interface.

Figure 12-19. PIT24B4C Detailed Block Diagram

12.4.1 Timer

As shown in Figure 12-1 and Figure 12-19, the 24-bit timers are built in a two-stage architecture with four

16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with

two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer

is connected to micro time base 0 or 1 via the PMUX[3:0] bit setting in the PIT Multiplex (PITMUX)

A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer

(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register

is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro

time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter

will load its start value as speciﬁed in the PITMTLD0 or PITMTLD1 register and will start down-counting.

Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the

connected 16-bit modulus down-counters count one cycle.

PITMLD0 Register

8-Bit Micro Timer 0

PITCFLMT Register

PITLD0 Register

PITMLD1 Register

8-Bit Micro Timer 1

PITMUX Register PITCNT0 Register

Timer 0

PMUX0

PFLT0

PITTF Register

PITINTE Register

Interrupt /

Hardware

Trigger

Interrupt

Request

PITLD1 Register

PITCNT1 Register

Timer 1

[1]

PFLT1

PITLD2 Register

PITCNT2 Register

Timer 2

[2]

PFLT2

PITLD3 Register

PITCNT3 Register

Timer 3

PFLT3

time-out 0

PFLMT

[1]

[0]

PMUX

Trigger Interface

Bus

Clock

PIT24B4C

[3]

time-

out 3

time-out 1

PITFLT Register

time-

out 3

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 361

Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the

PITLD register is reloaded and the corresponding time-out ﬂag PTF in the PIT time-out ﬂag (PITTF)

micro timer load (PITMTLD) registers and the bus clock fBUS:

time-out period = (PITMTLD + 1) * (PITLD + 1) / fBUS.

For example, for a 40 MHz bus clock, the maximum time-out period equals:

256 * 65536 * 25 ns = 419.43 ms.

The current 16-bit modulus down-counter value can be read via the PITCNT register. The micro timer

down-counter values cannot be read.

The 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro

timer PFLMT bits in the PIT control and force load micro timer (PITCFLMT) register. The 16-bit timers

can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT

forceload timer (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the

same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant

bits set, as shown in Figure 12-20.

Figure 12-20. PIT Trigger and Flag Signal Timing

12.4.2 Interrupt Interface

Each time-out event can be used to trigger an interrupt service request. For each timer channel, an

individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE

Bus Clock

0210

8-Bit Micro 21021021210

PITCNT Register 0001 000000 0001 0000

8-Bit Force Load

210

PTF Flag1

PITTRIG

16-Bit Force Load

0001 0000 0001

Time-Out Period

Time-Out Period After Restart

Timer Counter

Note 1. The PTF ﬂag clearing depends on the software

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

362 Freescale Semiconductor

is set, an interrupt service is requested whenever the corresponding time-out ﬂag PTF in the PIT time-out

ﬂag (PITTF) register is set. The ﬂag can be cleared by writing a one to the ﬂag bit.

NOTE

Be careful when resetting the PITE, PINTE or PITCE bits in case of pending

PIT interrupt requests, to avoid spurious interrupt requests.

12.4.3 Hardware Trigger

The PIT module contains four hardware trigger signal lines PITTRIG[3:0], one for each timer channel.

These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion

(please refer to the SoC Guide for the mapping of PITTRIG[3:0] signals to peripheral modules).

Whenever a timer channel time-out is reached, the corresponding PTF ﬂag is set and the corresponding

trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of

two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register

values PITLD = 0x0001 and PITMTLD = 0x0002 the ﬂag setting, trigger timing and a restart with force

load is shown in Figure 12-20.

12.5 Initialization

12.5.1 Startup

Set the conﬁguration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the

conﬁguration registers can be written in arbitrary order.

12.5.2 Shutdown

When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are

cleared, the corresponding PIT interrupt ﬂags are cleared. In case of a pending PIT interrupt request, a

spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended:

1. Reset the PIT interrupt ﬂags only in an ISR. When entering the ISR, the I mask bit in the CCR is

set automatically. The I mask bit must not be cleared before the PIT interrupt ﬂags are cleared.

2. After setting the I mask bit with the SEI instruction, the PIT interrupt ﬂags can be cleared. Then

clear the I mask bit with the CLI instruction to re-enable interrupts.

12.5.3 Flag Clearing

A ﬂag is cleared by writing a one to the ﬂag bit. Always use store or move instructions to write a one in

certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET

instructions. “BSET ﬂag_register, #mask” must not be used for ﬂag clearing because BSET is a read-

modify-write instruction which writes back the “bit-wise or” of the ﬂag_register and the mask into the

ﬂag_register. BSET would clear all ﬂag bits that were set, independent from the mask.

For example, to clear ﬂag bit 0 use: MOVB #$01,PITTF.

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 363

12.6 Application Information

To get started quickly with the PIT24B8C module this section provides a small code example how to use

the block. Please note that the example provided is only one speciﬁc case out of the possible conﬁgurations

and implementations.

Functionality: Generate an PIT interrupt on channel 0 every 500 PIT clock cycles.

ORG CODESTART ; place the program into speciﬁc

; range (to be selected)

LDS RAMEND ; load stack pointer to top of RAM

MOVW #CH0_ISR,VEC_PIT_CH0 ; Change value of channel 0 ISR adr

; ******************** Start PIT Initialization *******************************************************

CLR PITCFLMT ; disable PIT

MOVB #$01,PITCE ; enable timer channel 0

CLR PITMUX ; ch0 connected to micro timer 0

MOVB #$63,PITMTLD0 ; micro time base 0 equals 100 clock cycles

MOVW #$0004,PITLD0 ; time base 0 eq. 5 micro time bases 0 =5*100 = 500

MOVB #$01,PITINTE ; enable interupt channel 0

MOVB #$80,PITCFLMT ; enable PIT

CLI ; clear Interupt disable Mask bit

;******************** Main Program *************************************************************

MAIN: BRA * ; loop until interrupt

;******************** Channel 0 Interupt Routine ***************************************************

CH0_ISR: LDAA PITTF ; 8 bit read of PIT time out ﬂags

MOVB #$01,PITTF ; clear PIT channel 0 time out ﬂag

RTI ; return to MAIN

Periodic Interrupt Timer (S12PIT24B4CV1)

S12XS Family Reference Manual, Rev. 1.10

364 Freescale Semiconductor

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 365

Chapter 13

Pulse-Width Modulator (S12PWM8B8CV1)

13.1 Introduction

The PWM deﬁnition is based on the HC12 PWM deﬁnitions. It contains the basic features from the HC11

with some of the enhancements incorporated on the HC12: center aligned output mode and four available

clock sources.The PWM module has eight channels with independent control of left and center aligned

outputs on each channel.

Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A

ﬂexible clock select scheme allows a total of four different clock sources to be used with the counters. Each

of the modulators can create independent continuous waveforms with software-selectable duty rates from

0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.

13.1.1 Features

The PWM block includes these distinctive features:

• Eight independent PWM channels with programmable period and duty cycle

• Dedicated counter for each PWM channel

• Programmable PWM enable/disable for each channel

• Software selection of PWM duty pulse polarity for each channel

• Period and duty cycle are double buffered. Change takes effect when the end of the effective period

is reached (PWM counter reaches zero) or when the channel is disabled.

• Programmable center or left aligned outputs on individual channels

• Eight 8-bit channel or four 16-bit channel PWM resolution

• Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies

• Programmable clock select logic

• Emergency shutdown

Version

Number Revision

Date Effective

Date Author Description of Changes

01.17 08-01-2004 Added clariﬁcation of PWMIF operation in STOP and WAIT mode.

Added notes on minimum pulse width of emergency shutdown

signal.

Pulse-Width Modulator (S12PWM8B8CV1)

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366 Freescale Semiconductor

13.1.2 Modes of Operation

There is a software programmable option for low power consumption in wait mode that disables the input

clock to the prescaler.

In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is

useful for emulation.

13.1.3 Block Diagram

Figure 13-1 shows the block diagram for the 8-bit 8-channel PWM block.

Figure 13-1. PWM Block Diagram

13.2 External Signal Description

The PWM module has a total of 8 external pins.

Period and Duty Counter

Channel 6

Clock Select PWM Clock

Period and Duty Counter

Channel 5

Period and Duty Counter

Channel 4

Period and Duty Counter

Channel 3

Period and Duty Counter

Channel 2

Period and Duty Counter

Channel 1

Alignment

Polarity

Control

PWM8B8C

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

Enable

PWM Channels

Period and Duty Counter

Channel 7

Period and Duty Counter

Channel 0 PWM0

PWM7

Bus Clock

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 367

13.2.1 PWM7 — PWM Channel 7

This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown

feature.

13.2.2 PWM6 — PWM Channel 6

This pin serves as waveform output of PWM channel 6.

13.2.3 PWM5 — PWM Channel 5

This pin serves as waveform output of PWM channel 5.

13.2.4 PWM4 — PWM Channel 4

This pin serves as waveform output of PWM channel 4.

13.2.5 PWM3 — PWM Channel 3

This pin serves as waveform output of PWM channel 3.

13.2.6 PWM3 — PWM Channel 2

This pin serves as waveform output of PWM channel 2.

13.2.7 PWM3 — PWM Channel 1

This pin serves as waveform output of PWM channel 1.

13.2.8 PWM3 — PWM Channel 0

This pin serves as waveform output of PWM channel 0.

13.3 Memory Map and Register Deﬁnition

This section describes in detail all the registers and register bits in the PWM module.

The special-purpose registers and register bit functions that are not normally available to device end users,

such as factory test control registers and reserved registers, are clearly identiﬁed by means of shading the

appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting

access to the registers and functions are also explained in the individual register descriptions.

13.3.1 Module Memory Map

This section describes the content of the registers in the PWM module. The base address of the PWM

module is determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and

begins at the ﬁrst address of the module address offset. The ﬁgure below shows the registers associated

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

368 Freescale Semiconductor

with the PWM and their relative offset from the base address. The register detail description follows the

order they appear in the register map.

Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented

functions are indicated by shading the bit. .

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

13.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the PWM module.

Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000

PWME RPWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0

0x0001

PWMPOL RPPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0

0x0002

PWMCLK RPCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0

0x0003

PWMPRCLK R0 PCKB2 PCKB1 PCKB0 0PCKA2 PCKA1 PCKA0

0x0004

PWMCAE RCAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0

0x0005

PWMCTL RCON67 CON45 CON23 CON01 PSWAI PFRZ 00

0x0006

PWMTST1R00000000

0x0007

PWMPRSC1R00000000

0x0008

PWMSCLA RBit 7 6 5 4 3 2 1 Bit 0

0x0009

PWMSCLB RBit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 13-2. PWM Register Summary (Sheet 1 of 3)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 369

0x000A

PWMSCNTA

R00000000

0x000B

PWMSCNTB

R00000000

0x000C

PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x000D

PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x000E

PWMCNT2 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x000F

PWMCNT3 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x0010

PWMCNT4 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x0011

PWMCNT5 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x0012

PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x0013

PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

0x0014

PWMPER0 RBit 7 6 5 4 3 2 1 Bit 0

0x0015

PWMPER1 RBit 7 6 5 4 3 2 1 Bit 0

0x0016

PWMPER2 RBit 7 6 5 4 3 2 1 Bit 0

0x0017

PWMPER3 RBit 7 6 5 4 3 2 1 Bit 0

0x0018

PWMPER4 RBit 7 6 5 4 3 2 1 Bit 0

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 13-2. PWM Register Summary (Sheet 2 of 3)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

370 Freescale Semiconductor

13.3.2.1 PWM Enable Register (PWME)

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx

bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM

waveform is not available on the associated PWM output until its clock source begins its next cycle due to

the synchronization of PWMEx and the clock source.

0x0019

PWMPER5 RBit 7 6 5 4 3 2 1 Bit 0

0x001A

PWMPER6 RBit 7 6 5 4 3 2 1 Bit 0

0x001B

PWMPER7 RBit 7 6 5 4 3 2 1 Bit 0

0x001C

PWMDTY0 RBit 7 6 5 4 3 2 1 Bit 0

0x001D

PWMDTY1 RBit 7 6 5 4 3 2 1 Bit 0

0x001E

PWMDTY2 RBit 7 6 5 4 3 2 1 Bit 0

0x001F

PWMDTY3 RBit 7 6 5 4 3 2 1 Bit 0

0x0010

PWMDTY4 RBit 7 6 5 4 3 2 1 Bit 0

0x0021

PWMDTY5 RBit 7 6 5 4 3 2 1 Bit 0

0x0022

PWMDTY6 RBit 7 6 5 4 3 2 1 Bit 0

0x0023

PWMDTY7 RBit 7 6 5 4 3 2 1 Bit 0

0x0024

PWMSDN RPWMIF PWMIE 0PWMLVL 0 PWM7IN PWM7INL PWM7ENA

W PWMRSTRT

1Intended for factory test purposes only.

Name Bit 7 6 5 4 3 2 1 Bit 0

= Unimplemented or Reserved

Figure 13-2. PWM Register Summary (Sheet 3 of 3)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 371

NOTE

The ﬁrst PWM cycle after enabling the channel can be irregular.

An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits

set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the

low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their

corresponding PWM output lines are disabled.

While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts

off for power savings.

Read: Anytime

Write: Anytime

Module Base + 0x0000

76543210

RPWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0

Reset 0 0 0 00000

Figure 13-3. PWM Enable Register (PWME)

Table 13-1. PWME Field Descriptions

Field Description

PWME7 Pulse Width Channel 7 Enable

0 Pulse width channel 7 is disabled.

1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when

its clock source begins its next cycle.

PWME6 Pulse Width Channel 6 Enable

0 Pulse width channel 6 is disabled.

1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when

its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.

PWME5 Pulse Width Channel 5 Enable

0 Pulse width channel 5 is disabled.

1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when

its clock source begins its next cycle.

PWME4 Pulse Width Channel 4 Enable

0 Pulse width channel 4 is disabled.

1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when

its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled.

PWME3 Pulse Width Channel 3 Enable

0 Pulse width channel 3 is disabled.

1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when

its clock source begins its next cycle.

PWME2 Pulse Width Channel 2 Enable

0 Pulse width channel 2 is disabled.

1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when

its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled.

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

372 Freescale Semiconductor

13.3.2.2 PWM Polarity Register (PWMPOL)

The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the

PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle

and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts

low and then goes high when the duty count is reached.

Read: Anytime

Write: Anytime

NOTE

PPOLx register bits can be written anytime. If the polarity is changed while

a PWM signal is being generated, a truncated or stretched pulse can occur

during the transition

13.3.2.3 PWM Clock Select Register (PWMCLK)

Each PWM channel has a choice of two clocks to use as the clock source for that channel as described

below.

PWME1 Pulse Width Channel 1 Enable

0 Pulse width channel 1 is disabled.

1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when

its clock source begins its next cycle.

PWME0 Pulse Width Channel 0 Enable

0 Pulse width channel 0 is disabled.

1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when

its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled.

Module Base + 0x0001

76543210

RPPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0

Reset 0 0 0 00000

Figure 13-4. PWM Polarity Register (PWMPOL)

Table 13-2. PWMPOL Field Descriptions

Field Description

7–0

PPOL[7:0] Pulse Width Channel 7–0 Polarity Bits

0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is

reached.

1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is

reached.

Table 13-1. PWME Field Descriptions (continued)

Field Description

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 373

Read: Anytime

Write: Anytime

NOTE

changed while a PWM signal is being generated, a truncated or stretched

pulse can occur during the transition.

13.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)

This register selects the prescale clock source for clocks A and B independently.

Module Base + 0x0002

76543210

RPCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0

Reset 0 0 0 00000

Figure 13-5. PWM Clock Select Register (PWMCLK)

Table 13-3. PWMCLK Field Descriptions

Field Description

PCLK7 Pulse Width Channel 7 Clock Select

0 Clock B is the clock source for PWM channel 7.

1 Clock SB is the clock source for PWM channel 7.

PCLK6 Pulse Width Channel 6 Clock Select

0 Clock B is the clock source for PWM channel 6.

1 Clock SB is the clock source for PWM channel 6.

PCLK5 Pulse Width Channel 5 Clock Select

0 Clock A is the clock source for PWM channel 5.

1 Clock SA is the clock source for PWM channel 5.

PCLK4 Pulse Width Channel 4 Clock Select

0 Clock A is the clock source for PWM channel 4.

1 Clock SA is the clock source for PWM channel 4.

PCLK3 Pulse Width Channel 3 Clock Select

0 Clock B is the clock source for PWM channel 3.

1 Clock SB is the clock source for PWM channel 3.

PCLK2 Pulse Width Channel 2 Clock Select

0 Clock B is the clock source for PWM channel 2.

1 Clock SB is the clock source for PWM channel 2.

PCLK1 Pulse Width Channel 1 Clock Select

0 Clock A is the clock source for PWM channel 1.

1 Clock SA is the clock source for PWM channel 1.

PCLK0 Pulse Width Channel 0 Clock Select

0 Clock A is the clock source for PWM channel 0.

1 Clock SA is the clock source for PWM channel 0.

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

374 Freescale Semiconductor

Read: Anytime

Write: Anytime

NOTE

PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock

pre-scale is changed while a PWM signal is being generated, a truncated or

stretched pulse can occur during the transition.

Module Base + 0x0003

76543210

R0 PCKB2 PCKB1 PCKB0 0PCKA2 PCKA1 PCKA0

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 13-6. PWM Prescale Clock Select Register (PWMPRCLK)

Table 13-4. PWMPRCLK Field Descriptions

Field Description

6–4

PCKB[2:0] Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or

7. These three bits determine the rate of clock B, as shown in Table 13-5.

2–0

PCKA[2:0] Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or

5. These three bits determine the rate of clock A, as shown in Table 13-6.

Table 13-5. Clock B Prescaler Selects

PCKB2 PCKB1 PCKB0 Value of Clock B

0 0 0 Bus clock

0 0 1 Bus clock / 2

0 1 0 Bus clock / 4

0 1 1 Bus clock / 8

1 0 0 Bus clock / 16

1 0 1 Bus clock / 32

1 1 0 Bus clock / 64

1 1 1 Bus clock / 128

Table 13-6. Clock A Prescaler Selects

PCKA2 PCKA1 PCKA0 Value of Clock A

0 0 0 Bus clock

0 0 1 Bus clock / 2

0 1 0 Bus clock / 4

0 1 1 Bus clock / 8

1 0 0 Bus clock / 16

1 0 1 Bus clock / 32

1 1 0 Bus clock / 64

1 1 1 Bus clock / 128

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 375

13.3.2.5 PWM Center Align Enable Register (PWMCAE)

The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned

outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be

center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See

Section 13.4.2.5, “Left Aligned Outputs” and Section 13.4.2.6, “Center Aligned Outputs” for a more

detailed description of the PWM output modes.

Read: Anytime

Write: Anytime

NOTE

Write these bits only when the corresponding channel is disabled.

13.3.2.6 PWM Control Register (PWMCTL)

The PWMCTL register provides for various control of the PWM module.

Read: Anytime

Write: Anytime

There are three control bits for concatenation, each of which is used to concatenate a pair of PWM

channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the

high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers

become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel

Module Base + 0x0004

76543210

RCAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0

Reset 0 0 0 00000

Figure 13-7. PWM Center Align Enable Register (PWMCAE)

Table 13-7. PWMCAE Field Descriptions

Field Description

7–0

CAE[7:0] Center Aligned Output Modes on Channels 7–0

0 Channels 7–0 operate in left aligned output mode.

1 Channels 7–0 operate in center aligned output mode.

Module Base + 0x0005

76543210

RCON67 CON45 CON23 CON01 PSWAI PFRZ 00

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 13-8. PWM Control Register (PWMCTL)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

376 Freescale Semiconductor

2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are

concatenated, channel 0 registers become the high order bytes of the double byte channel.

See Section 13.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM

Function.

NOTE

Change these bits only when both corresponding channels are disabled.

Table 13-8. PWMCTL Field Descriptions

Field Description

CON67 Concatenate Channels 6 and 7

0 Channels 6 and 7 are separate 8-bit PWMs.

1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order

byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit

PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity

bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit

determines the output mode.

CON45 Concatenate Channels 4 and 5

0 Channels 4 and 5 are separate 8-bit PWMs.

1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order

byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit

PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity

bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit

determines the output mode.

CON23 Concatenate Channels 2 and 3

0 Channels 2 and 3 are separate 8-bit PWMs.

1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order

byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit

PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity

bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit

determines the output mode.

CON01 Concatenate Channels 0 and 1

0 Channels 0 and 1 are separate 8-bit PWMs.

1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order

byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit

PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity

bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit

determines the output mode.

PSWAI PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling

the input clock to the prescaler.

0 Allow the clock to the prescaler to continue while in wait mode.

1 Stop the input clock to the prescaler whenever the MCU is in wait mode.

PFREZ PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the

prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode,

the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function

to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal

program ﬂow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can

still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode.

0 Allow PWM to continue while in freeze mode.

1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 377

13.3.2.7 Reserved Register (PWMTST)

This register is reserved for factory testing of the PWM module and is not available in normal modes.

Read: Always read $00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to this register when in special modes can alter the PWM

functionality.

13.3.2.8 Reserved Register (PWMPRSC)

This register is reserved for factory testing of the PWM module and is not available in normal modes.

Read: Always read $00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to this register when in special modes can alter the PWM

functionality.

13.3.2.9 PWM Scale A Register (PWMSCLA)

PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is

generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.

Clock SA = Clock A / (2 * PWMSCLA)

Module Base + 0x0006

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 13-9. Reserved Register (PWMTST)

Module Base + 0x0007

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 13-10. Reserved Register (PWMPRSC)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

378 Freescale Semiconductor

NOTE

When PWMSCLA = $00, PWMSCLA value is considered a full scale value

of 256. Clock A is thus divided by 512.

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).

Read: Anytime

Write: Anytime (causes the scale counter to load the PWMSCLA value)

13.3.2.10 PWM Scale B Register (PWMSCLB)

PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is

generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two.

Clock SB = Clock B / (2 * PWMSCLB)

NOTE

When PWMSCLB = $00, PWMSCLB value is considered a full scale value

of 256. Clock B is thus divided by 512.

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).

Read: Anytime

Write: Anytime (causes the scale counter to load the PWMSCLB value).

13.3.2.11 Reserved Registers (PWMSCNTx)

The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are

not available in normal modes.

Module Base + 0x0008

76543210

RBit 7 6 5 4 3 2 1 Bit 0

Reset 0 0 0 00000

Figure 13-11. PWM Scale A Register (PWMSCLA)

Module Base + 0x0009

76543210

RBit 7 6 5 4 3 2 1 Bit 0

Reset 0 0 0 00000

Figure 13-12. PWM Scale B Register (PWMSCLB)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 379

Read: Always read $00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to these registers when in special modes can alter the PWM

functionality.

13.3.2.12 PWM Channel Counter Registers (PWMCNTx)

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.

The counter can be read at any time without affecting the count or the operation of the PWM channel. In

left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned

output mode, the counter counts from 0 up to the value in the period register and then back down to 0.

Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,

the immediate load of both duty and period registers with values from the buffers, and the output to change

according to the polarity bit. The counter is also cleared at the end of the effective period (see

Section 13.4.2.5, “Left Aligned Outputs” and Section 13.4.2.6, “Center Aligned Outputs” for more

details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a

channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the

PWMCNTx register. For more detailed information on the operation of the counters, see Section 13.4.2.4,

“PWM Timer Counters”.

In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or

high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by

16-bit access to maintain data coherency.

NOTE

Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.

Read: Anytime

Module Base + 0x000A, 0x000B

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 13-13. Reserved Registers (PWMSCNTx)

Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3

Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7

76543210

R Bit 7 6 5 4 3 2 1 Bit 0

W00000000

Reset 0 0 0 00000

Figure 13-14. PWM Channel Counter Registers (PWMCNTx)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

380 Freescale Semiconductor

Write: Anytime (any value written causes PWM counter to be reset to $00).

13.3.2.13 PWM Channel Period Registers (PWMPERx)

There is a dedicated period register for each channel. The value in this register determines the period of

the associated PWM channel.

The period registers for each channel are double buffered so that if they change while the channel is

enabled, the change will NOT take effect until one of the following occurs:

• The effective period ends

• The counter is written (counter resets to $00)

• The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period register will go directly to the

latches as well as the buffer.

NOTE

Reads of this register return the most recent value written. Reads do not

necessarily return the value of the currently active period due to the double

buffering scheme.

See Section 13.4.2.3, “PWM Period and Duty” for more information.

To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,

or SB) and multiply it by the value in the period register for that channel:

• Left aligned output (CAEx = 0)

• PWMxPeriod=ChannelClock Period* PWMPERxCenter AlignedOutput(CAEx=1)

PWMx Period = Channel Clock Period * (2 * PWMPERx)

For boundary case programming values, please refer to Section 13.4.2.8, “PWM Boundary Cases”.

Read: Anytime

Write: Anytime

Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3

Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7

76543210

RBit 7 6 5 4 3 2 1 Bit 0

Reset 1 1 1 11111

Figure 13-15. PWM Channel Period Registers (PWMPERx)

Pulse-Width Modulator (S12PWM8B8CV1)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 381

13.3.2.14 PWM Channel Duty Registers (PWMDTYx)

There is a dedicated duty register for each channel. The value in this register determines the duty of the

associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value

a match occurs and the output changes state.

The duty registers for each channel are double buffered so that if they change while the channel is enabled,

the change will NOT take effect until one of the following occurs:

• The effective period ends

• The counter is written (counter resets to $00)

• The channel is disabled

In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,

not some variation in between. If the channel is not enabled, then writes to the duty register will go directly

to the latches as well as the buffer.

NOTE

Reads of this register return the most recent value written. Reads do not

necessarily return the value of the currently active duty due to the double

buffering scheme.

See Section 13.4.2.3, “PWM Period and Duty” for more information.

NOTE

Depending on the polarity bit, the duty registers will contain the count of

either the high time or the low time. If the polarity bit is one, the output starts

high and then goes low when the duty count is reached, so the duty registers

contain a count of the high time. If the polarity bit is zero, the output starts

low and then goes high when the duty count is reached, so the duty registers

contain a count of the low time.

To calculate the output duty cycle (high time as a% of period) for a particular channel:

• Polarity = 0 (PPOL x =0)

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

• Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

For boundary case programming values, please refer to Section 13.4.2.8, “PWM Boundary Cases”.

Read: Anytime

Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3

Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7

76543210

RBit 7 6 5 4 3 2 1 Bit 0

Reset 1 1 1 11111

Figure 13-16. PWM Channel Duty Registers (PWMDTYx)

Pulse-Width Modulator (S12PWM8B8CV1)

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382 Freescale Semiconductor

Write: Anytime

13.3.2.15 PWM Shutdown Register (PWMSDN)

The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency

cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks.

Read: Anytime

Write: Anytime

Module Base + 0x0024

76543210

RPWMIF PWMIE 0PWMLVL 0 PWM7IN PWM7INL PWM7ENA

W PWMRSTRT

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 13-17. PWM Shutdown Register (PWMSDN)

Table 13-9. PWMSDN Field Descriptions

Field Description

PWMIF PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will

be ﬂagged by setting the PWMIF ﬂag = 1. The ﬂag is cleared by writing a logic 1 to it. Writing a 0 has no effect.

0 No change on PWM7IN input.

1 Change on PWM7IN input

PWMIE PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.

0 PWM interrupt is disabled.

1 PWM interrupt is enabled.

PWMRSTRT PWM Restart — The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic

1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes

next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter

passes $00. The bit is always read as “0”.

PWMLVL PWM Shutdown Output Level If active level as deﬁned by the PWM7IN input, gets asserted all enabled PWM

channels are immediately driven to the level deﬁned by PWMLVL.

0 PWM outputs are forced to 0

1 Outputs are forced to 1.

PWM7IN PWM Channel 7 Input Status — This reﬂects the current status of the PWM7 pin.

PWM7INL PWM Shutdown Active Input Level for Channel 7 — If the emergency shutdown feature is enabled

(PWM7ENA = 1), this bit determines the active level of the PWM7channel.

0 Active level is low

1 Active level is high

PWM7ENA PWM Emergency Shutdown Enable — If this bit is logic 1, the pin associated with channel 7 is forced to input

and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if

PWM7ENA = 1.

0 PWM emergency feature disabled.

1 PWM emergency feature is enabled.

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13.4 Functional Description

13.4.1 PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These

four clocks are based on the bus clock.

Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA

uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B

as an input and divides it further with a reloadable counter. The rates available for clock SA are software

selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are

available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the

pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).

The block diagram in Figure 13-18 shows the four different clocks and how the scaled clocks are created.

13.4.1.1 Prescale

The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze

mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze

mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation

in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are

disabled (PWME7-0 = 0). This is useful for reducing power by disabling the prescale counter.

Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock

A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value

selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The

value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK

13.4.1.2 Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and

then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user

programmable value and then divides this by 2. The rates available for clock SA are software selectable to

be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock

SB.

Pulse-Width Modulator (S12PWM8B8CV1)

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384 Freescale Semiconductor

Figure 13-18. PWM Clock Select Block Diagram

128248163264

PCKB2

PCKB1

PCKB0

Clock A

Clock B

Clock SA

Clock A/2, A/4, A/6,....A/512

Prescale Scale

Divide by

PFRZ

Freeze Mode Signal

Bus Clock

Clock Select

PCLK0

Clock to

PWM Ch 0

PCLK2

Clock to

PWM Ch 2

PCLK1

Clock to

PWM Ch 1

PCLK4

Clock to

PWM Ch 4

PCLK5

Clock to

PWM Ch 5

PCLK6

Clock to

PWM Ch 6

PCLK7

Clock to

PWM Ch 7

PCLK3

Clock to

PWM Ch 3

Load

DIV 2

PWMSCLB Clock SB

Clock B/2, B/4, B/6,....B/512

PCKA2

PCKA1

PCKA0

PWME7-0

Count = 1

Load

DIV 2

PWMSCLA

Count = 1

8-Bit Down

Counter

8-Bit Down

Counter

Prescaler Taps:

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Freescale Semiconductor 385

Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale

value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the

8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater

range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value

in the PWMSCLA register.

NOTE

Clock SA = Clock A / (2 * PWMSCLA)

When PWMSCLA = $00, PWMSCLA value is considered a full scale value

of 256. Clock A is thus divided by 512.

Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock

SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register.

NOTE

Clock SB = Clock B / (2 * PWMSCLB)

When PWMSCLB = $00, PWMSCLB value is considered a full scale value

of 256. Clock B is thus divided by 512.

As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for

this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this

through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value

of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by

8 rate.

Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.

Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper

rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or

PWMSCLB is written prevents this.

NOTE

Writing to the scale registers while channels are operating can cause

irregularities in the PWM outputs.

13.4.1.3 Clock Select

Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock

choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock

selection is done with the PCLKx control bits in the PWMCLK register.

NOTE

Changing clock control bits while channels are operating can cause

irregularities in the PWM outputs.

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386 Freescale Semiconductor

13.4.2 PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period

the period register and the value in the counter. The duty is controlled by a match between the duty register

and the counter value and causes the state of the output to change during the period. The starting polarity

of the output is also selectable on a per channel basis. Shown below in Figure 13-19 is the block diagram

for the PWM timer.

Figure 13-19. PWM Timer Channel Block Diagram

13.4.2.1 PWM Enable

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx

bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual

PWM waveform is not available on the associated PWM output until its clock source begins its next cycle

due to the synchronization of PWMEx and the clock source. An exception to this is when channels are

concatenated. Refer to Section 13.4.2.7, “PWM 16-Bit Functions” for more detail.

NOTE

The ﬁrst PWM cycle after enabling the channel can be irregular.

Clock Source

PPOLx

From Port PWMP

Data Register

PWMEx

To Pin

Driver

Gate

8-bit Compare =

PWMDTYx

8-bit Compare =

PWMPERx

CAEx

8-Bit Counter

PWMCNTx

(Clock Edge

Sync)

Up/Down Reset

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Freescale Semiconductor 387

On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.

There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an

edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.

13.4.2.2 PWM Polarity

Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown

on the block diagram as a mux select of either the Q output or the Q output of the PWM output ﬂip ﬂop.

When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the

beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit

is zero, the output starts low and then goes high when the duty count is reached.

13.4.2.3 PWM Period and Duty

Dedicated period and duty registers exist for each channel and are double buffered so that if they change

while the channel is enabled, the change will NOT take effect until one of the following occurs:

• The effective period ends

• The counter is written (counter resets to $00)

• The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period and duty registers will go

directly to the latches as well as the buffer.

A change in duty or period can be forced into effect “immediately” by writing the new value to the duty

and/or period registers and then writing to the counter. This forces the counter to reset and the new duty

and/or period values to be latched. In addition, since the counter is readable, it is possible to know where

the count is with respect to the duty value and software can be used to make adjustments

NOTE

When forcing a new period or duty into effect immediately, an irregular

PWM cycle can occur.

Depending on the polarity bit, the duty registers will contain the count of

either the high time or the low time.

13.4.2.4 PWM Timer Counters

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see

Section 13.4.1, “PWM Clock Select” for the available clock sources and rates). The counter compares to

two registers, a duty register and a period register as shown in Figure 13-19. When the PWM counter

matches the duty register, the output ﬂip-ﬂop changes state, causing the PWM waveform to also change

state. A match between the PWM counter and the period register behaves differently depending on what

output mode is selected as shown in Figure 13-19 and described in Section 13.4.2.5, “Left Aligned

Outputs” and Section 13.4.2.6, “Center Aligned Outputs”.

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388 Freescale Semiconductor

Each channel counter can be read at anytime without affecting the count or the operation of the PWM

channel.

Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,

the immediate load of both duty and period registers with values from the buffers, and the output to change

according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a

channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the

PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-

enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on

the next selected clock.

NOTE

If the user wants to start a new “clean” PWM waveform without any

“history” from the old waveform, the user must write to channel counter

(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).

Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.

However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is

similar to writing the counter when the channel is disabled, except that the new period is started

immediately with the output set according to the polarity bit.

NOTE

Writing to the counter while the channel is enabled can cause an irregular

PWM cycle to occur.

The counter is cleared at the end of the effective period (see Section 13.4.2.5, “Left Aligned Outputs” and

Section 13.4.2.6, “Center Aligned Outputs” for more details).

13.4.2.5 Left Aligned Outputs

The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are

selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the

corresponding PWM output will be left aligned.

In left aligned output mode, the 8-bit counter is conﬁgured as an up counter only. It compares to two

registers, a duty register and a period register as shown in the block diagram in Figure 13-19. When the

PWM counter matches the duty register the output ﬂip-ﬂop changes state causing the PWM waveform to

also change state. A match between the PWM counter and the period register resets the counter and the

output ﬂip-ﬂop, as shown in Figure 13-19, as well as performing a load from the double buffer period and

duty register to the associated registers, as described in Section 13.4.2.3, “PWM Period and Duty”. The

counter counts from 0 to the value in the period register – 1.

Table 13-10. PWM Timer Counter Conditions

Counter Clears ($00) Counter Counts Counter Stops

When PWMCNTx register written to

any value When PWM channel is enabled

(PWMEx = 1). Counts from last value in

PWMCNTx.

When PWM channel is disabled

(PWMEx = 0)

Effective period ends

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Freescale Semiconductor 389

NOTE

Changing the PWM output mode from left aligned to center aligned output

(or vice versa) while channels are operating can cause irregularities in the

PWM output. It is recommended to program the output mode before

enabling the PWM channel.

Figure 13-20. PWM Left Aligned Output Waveform

To calculate the output frequency in left aligned output mode for a particular channel, take the selected

clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register

for that channel.

• PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx

• PWMx Duty Cycle (high time as a% of period):

— Polarity = 0 (PPOLx = 0)

• Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

— Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

As an example of a left aligned output, consider the following case:

Clock Source = E, where E = 10 MHz (100 ns period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 MHz/4 = 2.5 MHz

PWMx Period = 400 ns

PWMx Duty Cycle = 3/4 *100% = 75%

The output waveform generated is shown in Figure 13-21.

PWMDTYx

Period = PWMPERx

PPOLx = 0

PPOLx = 1

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390 Freescale Semiconductor

Figure 13-21. PWM Left Aligned Output Example Waveform

13.4.2.6 Center Aligned Outputs

For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the

corresponding PWM output will be center aligned.

The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is

equal to $00. The counter compares to two registers, a duty register and a period register as shown in the

block diagram in Figure 13-19. When the PWM counter matches the duty register, the output ﬂip-ﬂop

changes state, causing the PWM waveform to also change state. A match between the PWM counter and

the period register changes the counter direction from an up-count to a down-count. When the PWM

counter decrements and matches the duty register again, the output ﬂip-ﬂop changes state causing the

PWM output to also change state. When the PWM counter decrements and reaches zero, the counter

direction changes from a down-count back to an up-count and a load from the double buffer period and

duty registers to the associated registers is performed, as described in Section 13.4.2.3, “PWM Period and

Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the

effective period is PWMPERx*2.

NOTE

Changing the PWM output mode from left aligned to center aligned output

(or vice versa) while channels are operating can cause irregularities in the

PWM output. It is recommended to program the output mode before

enabling the PWM channel.

Figure 13-22. PWM Center Aligned Output Waveform

Period = 400 ns

E = 100 ns

Duty Cycle = 75%

PPOLx = 0

PPOLx = 1

PWMDTYx PWMDTYx

Period = PWMPERx*2

PWMPERx

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Freescale Semiconductor 391

To calculate the output frequency in center aligned output mode for a particular channel, take the selected

clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period

• PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)

• PWMx Duty Cycle (high time as a% of period):

— Polarity = 0 (PPOLx = 0)

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

— Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

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392 Freescale Semiconductor

As an example of a center aligned output, consider the following case:

Clock Source = E, where E = 10 MHz (100 ns period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 MHz/8 = 1.25 MHz

PWMx Period = 800 ns

PWMx Duty Cycle = 3/4 *100% = 75%

Shown in Figure 13-23 is the output waveform generated.

Figure 13-23. PWM Center Aligned Output Example Waveform

13.4.2.7 PWM 16-Bit Functions

The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater

PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.

The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM

channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and

5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and

channels 0 and 1 are concatenated with the CON01 bit.

NOTE

Change these bits only when both corresponding channels are disabled.

When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double

byte channel, as shown in Figure 13-24. Similarly, when channels 4 and 5 are concatenated, channel 4

registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated,

channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are

concatenated, channel 0 registers become the high order bytes of the double byte channel.

When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel

clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when

channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when

channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order

8-bit channel as also shown in Figure 13-24. The polarity of the resulting PWM output is controlled by the

PPOLx bit of the corresponding low order 8-bit channel as well.

E = 100 ns

DUTY CYCLE = 75%

E = 100 ns

PERIOD = 800 ns

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Freescale Semiconductor 393

Figure 13-24. PWM 16-Bit Mode

Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the

corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order

bytes PWMEx bits have no effect and their corresponding PWM output is disabled.

In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or

high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by

16-bit access to maintain data coherency.

PWMCNT6 PWCNT7

PWM7

Clock Source 7 High Low

Period/Duty Compare

PWMCNT4 PWCNT5

PWM5

Clock Source 5 High Low

Period/Duty Compare

PWMCNT2 PWCNT3

PWM3

Clock Source 3 High Low

Period/Duty Compare

PWMCNT0 PWCNT1

PWM1

Clock Source 1 High Low

Period/Duty Compare

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394 Freescale Semiconductor

Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by

the low order CAEx bit. The high order CAEx bit has no effect.

Table 13-11 is used to summarize which channels are used to set the various control bits when in 16-bit

mode.

13.4.2.8 PWM Boundary Cases

Table 13-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned

or center aligned) and 8-bit (normal) or 16-bit (concatenation).

13.5 Resets

The reset state of each individual bit is listed within the Section 13.3.2, “Register Descriptions” which

details the registers and their bit-ﬁelds. All special functions or modes which are initialized during or just

following reset are described within this section.

• The 8-bit up/down counter is conﬁgured as an up counter out of reset.

• All the channels are disabled and all the counters do not count.

Table 13-11. 16-bit Concatenation Mode Summary

CONxx PWMEx PPOLx PCLKx CAEx PWMx

Output

CON67 PWME7 PPOL7 PCLK7 CAE7 PWM7

CON45 PWME5 PPOL5 PCLK5 CAE5 PWM5

CON23 PWME3 PPOL3 PCLK3 CAE3 PWM3

CON01 PWME1 PPOL1 PCLK1 CAE1 PWM1

Table 13-12. PWM Boundary Cases

PWMDTYx PWMPERx PPOLx PWMx Output

$00

(indicates no duty) >$00 1 Always low

$00

(indicates no duty) >$00 0 Always high

XX $001

(indicates no period)

1Counter = $00 and does not count.

1 Always high

XX $001

(indicates no period) 0 Always low

>= PWMPERx XX 1 Always high

>= PWMPERx XX 0 Always low

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13.6 Interrupts

The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the

corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt ﬂag PWMIF

is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA

is being asserted while the level at PWM7 is active.

In stop mode or wait mode (with the PSWAI bit set), the emergency shutdown feature will drive the PWM

outputs to their shutdown output levels but the PWMIF ﬂag will not be set.

A description of the registers involved and affected due to this interrupt is explained in Section 13.3.2.15,

“PWM Shutdown Register (PWMSDN)”.

The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM

interrupt signal.

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Chapter 14

Serial Communication Interface (S12SCIV5)

14.1 Introduction

This block guide provides an overview of the serial communication interface (SCI) module.

The SCI allows asynchronous serial communications with peripheral devices and other CPUs.

14.1.1 Glossary

IR: InfraRed

IrDA: Infrared Design Associate

IRQ: Interrupt Request

LIN: Local Interconnect Network

LSB: Least Signiﬁcant Bit

MSB: Most Signiﬁcant Bit

NRZ: Non-Return-to-Zero

RZI: Return-to-Zero-Inverted

RXD: Receive Pin

SCI : Serial Communication Interface

TXD: Transmit Pin

Table 14-1. Revision History

Version

Number Revision

Date Effective

Date Author Description of Changes

05.01 04/16/2004 Update OR and PF flag description; Correct baud rate

tolerance in 4.7.5.1 and 4.7.5.2; Clean up classification and

NDA message banners

05.02 10/14/2005 Correct alternative registers address;

Remove unavailable baud rate in Table1-16

05.03 12/25/2008 remove redundancy comments in Figure1-2

05.04 08/05/2009 fix typo, SCIBDL reset value be 0x04, not 0x00

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14.1.2 Features

The SCI includes these distinctive features:

• Full-duplex or single-wire operation

• Standard mark/space non-return-to-zero (NRZ) format

• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• 13-bit baud rate selection

• Programmable 8-bit or 9-bit data format

• Separately enabled transmitter and receiver

• Programmable polarity for transmitter and receiver

• Programmable transmitter output parity

• Two receiver wakeup methods:

— Idle line wakeup

— Address mark wakeup

• Interrupt-driven operation with eight flags:

— Transmitter empty

— Transmission complete

— Receiver full

— Idle receiver input

— Receiver overrun

— Noise error

— Framing error

— Parity error

— Receive wakeup on active edge

— Transmit collision detect supporting LIN

— Break Detect supporting LIN

• Receiver framing error detection

• Hardware parity checking

• 1/16 bit-time noise detection

14.1.3 Modes of Operation

The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait

and stop modes.

• Run mode

• Wait mode

• Stop mode

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14.1.4 Block Diagram

Figure 14-1 is a high level block diagram of the SCI module, showing the interaction of various function

blocks.

Figure 14-1. SCI Block Diagram

SCI Data Register

RXD Data In

Data Out TXD

Receive Shift Register

Infrared

Decoder

Receive & Wakeup

Control

Data Format Control

Transmit Control

Baud Rate

Generator

Bus Clock

1/16

Transmit Shift Register

SCI Data Register

Receive

Interrupt

Generation

Transmit

Interrupt

Generation

Infrared

Encoder

IDLE

RDRF/OR

TDRE

BRKD

BERR

RXEDG

SCI

Interrupt

Request

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14.2 External Signal Description

The SCI module has a total of two external pins.

14.2.1 TXD — Transmit Pin

The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high

impedance anytime the transmitter is disabled.

14.2.2 RXD — Receive Pin

The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is

ignored when the receiver is disabled and should be terminated to a known voltage.

14.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all the SCI registers.

14.3.1 Module Memory Map and Register Deﬁnition

The memory map for the SCI module is given below in Figure 14-2. The address listed for each register is

the address offset. The total address for each register is the sum of the base address for the SCI module and

the address offset for each register.

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14.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Writes to a reserved register locations do not have any effect

and reads of these locations return a zero. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000

SCIBDH1RIREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8

0x0001

SCIBDL1RSBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

0x0002

SCICR11RLOOPS SCISWAI RSRC M WAKE ILT PE PT

0x0000

SCIASR12RRXEDGIF 0000

BERRV BERRIF BKDIF

0x0001

SCIACR12RRXEDGIE 00000

BERRIE BKDIE

0x0002

SCIACR22R00000

BERRM1 BERRM0 BKDFE

0x0003

SCICR2 RTIE TCIE RIE ILIE TE RE RWU SBK

0x0004

SCISR1 R TDRE TC RDRF IDLE OR NF FE PF

0x0005

SCISR2 RAMAP 00

TXPOL RXPOL BRK13 TXDIR RAF

0x0006

SCIDRH RR8 T8 000000

0x0007

SCIDRL RR7R6R5R4R3R2R1R0

WT7T6T5T4T3T2T1T0

1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.

2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.

= Unimplemented or Reserved

Figure 14-2. SCI Register Summary

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402 Freescale Semiconductor

14.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)

Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until

SCIBDL is written to as well, following a write to SCIBDH.

Write: Anytime, if AMAP = 0.

NOTE

Those two registers are only visible in the memory map if AMAP = 0 (reset

condition).

The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared

modulation/demodulation submodule.

Module Base + 0x0000

76543210

RIREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8

Reset 0 0 0 00000

Figure 14-3. SCI Baud Rate Register (SCIBDH)

Module Base + 0x0001

76543210

RSBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

Reset 0 0 0 00100

Figure 14-4. SCI Baud Rate Register (SCIBDL)

Table 14-2. SCIBDH and SCIBDL Field Descriptions

Field Description

IREN Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.

0 IR disabled

1 IR enabled

6:5

TNP[1:0] Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow

pulse. See Table 14-3.

4:0

7:0

SBR[12:0]

SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is

calculated two different ways depending on the state of the IREN bit.

The formulas for calculating the baud rate are:

When IREN = 0 then,

SCI baud rate = SCI bus clock / (16 x SBR[12:0])

When IREN = 1 then,

SCI baud rate = SCI bus clock / (32 x SBR[12:1])

Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the

ﬁrst time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and

IREN = 1).

Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in

a temporary location until SCIBDL is written to.

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14.3.2.2 SCI Control Register 1 (SCICR1)

Read: Anytime, if AMAP = 0.

Write: Anytime, if AMAP = 0.

NOTE

This register is only visible in the memory map if AMAP = 0 (reset

condition).

Table 14-3. IRSCI Transmit Pulse Width

TNP[1:0] Narrow Pulse Width

11 1/4

10 1/32

01 1/16

00 3/16

Module Base + 0x0002

76543210

RLOOPS SCISWAI RSRC M WAKE ILT PE PT

Reset 0 0 0 00000

Figure 14-5. SCI Control Register 1 (SCICR1)

Table 14-4. SCICR1 Field Descriptions

Field Description

LOOPS Loop Select Bit — LOOPS enables loop operation.In loop operation, the RXD pin is disconnected from the SCI

and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must

be enabled to use the loop function.

0 Normal operation enabled

1 Loop operation enabled

The receiver input is determined by the RSRC bit.

SCISWAI SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.

0 SCI enabled in wait mode

1 SCI disabled in wait mode

RSRC Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register

input. See Table 14-5.

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

MData Format Mode Bit — MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

WAKE Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the

most signiﬁcant bit position of a received data character or an idle condition on the RXD pin.

0 Idle line wakeup

1 Address mark wakeup

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ILT Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The

counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of

logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the

stop bit avoids false idle character recognition, but requires properly synchronized transmissions.

0 Idle character bit count begins after start bit

1 Idle character bit count begins after stop bit

PE Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the

most signiﬁcant bit position.

0 Parity function disabled

1 Parity function enabled

PT Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even

parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an

odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.

1 Even parity

1 Odd parity

Table 14-5. Loop Functions

LOOPS RSRC Function

0 x Normal operation

1 0 Loop mode with transmitter output internally connected to receiver input

1 1 Single-wire mode with TXD pin connected to receiver input

Table 14-4. SCICR1 Field Descriptions (continued)

Field Description

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14.3.2.3 SCI Alternative Status Register 1 (SCIASR1)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Module Base + 0x0000

76543210

RRXEDGIF 0 0 0 0 BERRV BERRIF BKDIF

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 14-6. SCI Alternative Status Register 1 (SCIASR1)

Table 14-6. SCIASR1 Field Descriptions

Field Description

RXEDGIF Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,

rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.

0 No active receive on the receive input has occurred

1 An active edge on the receive input has occurred

BERRV Bit Error Value — BERRV reﬂects the state of the RXD input when the bit error detect circuitry is enabled and

a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.

0 A low input was sampled, when a high was expected

1 A high input reassembled, when a low was expected

BERRIF Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value

sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an

interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.

0 No mismatch detected

1 A mismatch has occurred

BKDIF Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is

received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing

a “1” to it.

0 No break signal was received

1 A break signal was received

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14.3.2.4 SCI Alternative Control Register 1 (SCIACR1)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Module Base + 0x0001

76543210

RRXEDGIE 00000

BERRIE BKDIE

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 14-7. SCI Alternative Control Register 1 (SCIACR1)

Table 14-7. SCIACR1 Field Descriptions

Field Description

RSEDGIE Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt ﬂag,

RXEDGIF, to generate interrupt requests.

0 RXEDGIF interrupt requests disabled

1 RXEDGIF interrupt requests enabled

BERRIE Bit Error Interrupt Enable — BERRIE enables the bit error interrupt ﬂag, BERRIF, to generate interrupt

requests.

0 BERRIF interrupt requests disabled

1 BERRIF interrupt requests enabled

BKDIE Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF, to generate interrupt

requests.

0 BKDIF interrupt requests disabled

1 BKDIF interrupt requests enabled

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14.3.2.5 SCI Alternative Control Register 2 (SCIACR2)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Module Base + 0x0002

76543210

R00000

BERRM1 BERRM0 BKDFE

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 14-8. SCI Alternative Control Register 2 (SCIACR2)

Table 14-8. SCIACR2 Field Descriptions

Field Description

2:1

BERRM[1:0] Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 14-9.

BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry.

0 Break detect circuit disabled

1 Break detect circuit enabled

Table 14-9. Bit Error Mode Coding

BERRM1 BERRM0 Function

0 0 Bit error detect circuit is disabled

0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit

(refer to Figure 14-19)

1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit

(refer to Figure 14-19)

1 1 Reserved

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408 Freescale Semiconductor

14.3.2.6 SCI Control Register 2 (SCICR2)

Read: Anytime

Write: Anytime

Module Base + 0x0003

76543210

RTIE TCIE RIE ILIE TE RE RWU SBK

Reset 0 0 0 00000

Figure 14-9. SCI Control Register 2 (SCICR2)

Table 14-10. SCICR2 Field Descriptions

Field Description

TIE Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty ﬂag, TDRE, to generate

interrupt requests.

0 TDRE interrupt requests disabled

1 TDRE interrupt requests enabled

TCIE Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete ﬂag, TC, to generate

interrupt requests.

0 TC interrupt requests disabled

1 TC interrupt requests enabled

RIE Receiver Full Interrupt Enable Bit — RIE enables the receive data register full ﬂag, RDRF, or the overrun ﬂag,

OR, to generate interrupt requests.

0 RDRF and OR interrupt requests disabled

1 RDRF and OR interrupt requests enabled

ILIE Idle Line Interrupt Enable Bit — ILIE enables the idle line ﬂag, IDLE, to generate interrupt requests.

0 IDLE interrupt requests disabled

1 IDLE interrupt requests enabled

TE Transmitter Enable Bit — TE enables the SCI transmitter and conﬁgures the TXD pin as being controlled by

the SCI. The TE bit can be used to queue an idle preamble.

0 Transmitter disabled

1 Transmitter enabled

RE Receiver Enable Bit — RE enables the SCI receiver.

0 Receiver disabled

1 Receiver enabled

RWU Receiver Wakeup Bit — Standby state

0 Normal operation.

1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes

the receiver by automatically clearing RWU.

SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s

if BRK13 is set). Toggling implies clearing the SBK bit before the break character has ﬁnished transmitting. As

long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13

or 14 bits).

0 No break characters

1 Transmit break characters

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14.3.2.7 SCI Status Register 1 (SCISR1)

The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also,

these registers can be polled by the MCU to check the status of these bits. The ﬂag-clearing procedures

require that the status register be read followed by a read or write to the SCI data register.It is permissible

to execute other instructions between the two steps as long as it does not compromise the handling of I/O,

but the order of operations is important for ﬂag clearing.

Read: Anytime

Write: Has no meaning or effect

Module Base + 0x0004

76543210

R TDRE TC RDRF IDLE OR NF FE PF

Reset 1 1 0 00000

= Unimplemented or Reserved

Figure 14-10. SCI Status Register 1 (SCISR1)

Table 14-11. SCISR1 Field Descriptions

Field Description

TDRE Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the

SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value

to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data

0 No byte transferred to transmit shift register

1 Byte transferred to transmit shift register; transmit data register empty

TC Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break

character is loaded. TC is set high when the TDRE ﬂag is set and no data, preamble, or break character is being

transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1

(SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data,

preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of

the TC ﬂag (transmission not complete).

0 Transmission in progress

1 No transmission in progress

RDRF Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI

data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data

0 Data not available in SCI data register

1 Received data available in SCI data register

IDLE Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear

on the receiver input. Once the IDLE ﬂag is cleared, a valid frame must again set the RDRF ﬂag before an idle

condition can set the IDLE ﬂag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then

reading SCI data register low (SCIDRL).

0 Receiver input is either active now or has never become active since the IDLE ﬂag was last cleared

1 Receiver input has become idle

Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag.

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OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the

second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.

Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low

(SCIDRL).

0 No overrun

1 Overrun

Note: OR ﬂag may read back as set when RDRF ﬂag is clear. This may happen if the following sequence of

events occurs:

1. After the ﬁrst frame is received, read status register SCISR1 (returns RDRF set and OR ﬂag clear);

2. Receive second frame without reading the ﬁrst frame in the data register (the second frame is not

received and OR ﬂag is set);

3. Read data register SCIDRL (returns ﬁrst frame and clears RDRF ﬂag in the status register);

4. Read status register SCISR1 (returns RDRF clear and OR set).

Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy

SCIDRL read following event 4 will be required to clear the OR ﬂag if further frames are to be received.

NF Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as

the RDRF ﬂag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1),

and then reading SCI data register low (SCIDRL).

0 No noise

1 Noise

FE Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle

as the RDRF ﬂag but does not get set in the case of an overrun. FE inhibits further data reception until it is

cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register

low (SCIDRL).

0 No framing error

1 Framing error

PF Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not

match the parity type bit (PT). PF bit is set during the same cycle as the RDRF ﬂag but does not get set in the

case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low

(SCIDRL).

0 No parity error

1 Parity error

Table 14-11. SCISR1 Field Descriptions (continued)

Field Description

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Freescale Semiconductor 411

14.3.2.8 SCI Status Register 2 (SCISR2)

Read: Anytime

Write: Anytime

Module Base + 0x0005

76543210

RAMAP 00

TXPOL RXPOL BRK13 TXDIR RAF

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 14-11. SCI Status Register 2 (SCISR2)

Table 14-12. SCISR2 Field Descriptions

Field Description

AMAP Alternative Map —Thisbitcontrols which registers sharing the same address space are accessible. In the reset

condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and

status registers and hides the baud rate and SCI control Register 1.

0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible

1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible

TXPOL Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by

a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA

format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal

polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for

inverted polarity.

0 Normal polarity

1 Inverted polarity

RXPOL Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a

mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA

format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal

polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for

inverted polarity.

0 Normal polarity

1 Inverted polarity

BRK13 Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit

respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.

0 Break character is 10 or 11 bit long

1 Break character is 13 or 14 bit long

TXDIR Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to

be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire

mode of operation.

0 TXD pin to be used as an input in single-wire mode

1 TXD pin to be used as an output in single-wire mode

RAF Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start

bit search. RAF is cleared when the receiver detects an idle character.

0 No reception in progress

1 Reception in progress

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14.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)

Read: Anytime; reading accesses SCI receive data register

Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect

NOTE

If the value of T8 is the same as in the previous transmission, T8 does not

have to be rewritten.The same value is transmitted until T8 is rewritten

In 8-bit data format, only SCI data register low (SCIDRL) needs to be

accessed.

When transmitting in 9-bit data format and using 8-bit write instructions,

write ﬁrst to SCI data register high (SCIDRH), then SCIDRL.

Module Base + 0x0006

76543210

RR8 T8 000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 14-12. SCI Data Registers (SCIDRH)

Module Base + 0x0007

76543210

RR7R6R5R4R3R2R1R0

WT7 T6 T5 T4 T3 T2 T1 T0

Reset 0 0 0 00000

Figure 14-13. SCI Data Registers (SCIDRL)

Table 14-13. SCIDRH and SCIDRL Field Descriptions

Field Description

SCIDRH

Received Bit 8 — R8 is the ninth data bit received when the SCI is conﬁgured for 9-bit data format (M = 1).

SCIDRH

Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is conﬁgured for 9-bit data format (M = 1).

SCIDRL

7:0

R[7:0]

T[7:0]

R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats

T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats

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14.4 Functional Description

This section provides a complete functional description of the SCI block, detailing the operation of the

design from the end user perspective in a number of subsections.

Figure 14-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial

communication between the CPU and remote devices, including other CPUs. The SCI transmitter and

receiver operate independently, although they use the same baud rate generator. The CPU monitors the

status of the SCI, writes the data to be transmitted, and processes received data.

Figure 14-14. Detailed SCI Block Diagram

SCI Data

Receive

Shift Register

SCI Data

Transmit

Shift Register

Baud Rate

Generator

SBR12:SBR0

Bus

Transmit

Control

÷16

Receive

and Wakeup

Data Format

Control

RDRF

IDLE

TIE

TCIE

TDRE

RAF

LOOPS

RWU

ILT

WAKE

Clock

ILIE

RIE

RXD

RSRC

SBK

LOOPS

RSRC

IREN

R16XCLK

Ir_RXD

TXD

Ir_TXD

R16XCLK

R32XCLK

TNP[1:0] IREN

Transmit

Encoder

Receive

Decoder

SCRXD

SCTXD

Infrared

TDRE

RDRF/OR

IDLE

Active Edge

Detect

Break Detect

RXD

BKDFE

BERRM[1:0]

BKDIE

BKDIF

RXEDGIE

RXEDGIF

BERRIE

BERRIF

SCI

Interrupt

Request

LIN Transmit

Collision

Detect

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414 Freescale Semiconductor

14.4.1 Infrared Interface Submodule

This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow

pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer

speciﬁcation deﬁnes a half-duplex infrared communication link for exchange data. The full standard

includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2

Kbits/s.

The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The

SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse

for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be

detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external

from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit

stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be

inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low

pulses.

The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in

the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during

transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK,

which are conﬁgured to generate the narrow pulse width during transmission. The R16XCLK and

R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both

R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the

R16XCLK clock.

14.4.1.1 Infrared Transmit Encoder

The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A

narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle

of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a

zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.

14.4.1.2 Infrared Receive Decoder

The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is

expected for each zero received and no pulse is expected for each one received. A narrow high pulse is

expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when

RXPOL is set. This receive decoder meets the edge jitter requirement as deﬁned by the IrDA serial infrared

physical layer speciﬁcation.

14.4.2 LIN Support

This module provides some basic support for the LIN protocol. At ﬁrst this is a break detect circuitry

making it easier for the LIN software to distinguish a break character from an incoming data stream. As a

further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.

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Freescale Semiconductor 415

14.4.3 Data Format

The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data

format where zeroes are represented by light pulses and ones remain low. See Figure 14-15 below.

Figure 14-15. SCI Data Formats

Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit.

Clearing the M bit in SCI control register 1 conﬁgures the SCI for 8-bit data characters. A frame with eight

data bits has a total of 10 bits. Setting the M bit conﬁgures the SCI for nine-bit data characters. A frame

with nine data bits has a total of 11 bits.

When the SCI is conﬁgured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register

high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it.

A frame with nine data bits has a total of 11 bits.

Table 14-14. Example of 8-Bit Data Formats

Start

Bit Data

Bits Address

Bits Parity

Bits Stop

Bit

18001

17011

17 1

1The address bit identiﬁes the frame as an address

character. See Section 14.4.6.6, “Receiver Wakeup”.

Table 14-15. Example of 9-Bit Data Formats

Start

Bit Data

Bits Address

Bits Parity

Bits Stop

Bit

19001

18011

18 1

101

Bit 5

Start

Bit Bit 0 Bit 1

STOP

Bit

Start

Bit

8-Bit Data Format

(Bit M in SCICR1 Clear)

Start

Bit Bit 0

STOP

Bit

START

Bit

9-Bit Data Format

(Bit M in SCICR1 Set)

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8

Bit 2 Bit 3 Bit 4 Bit 6 Bit 7

POSSIBLE

PARITY

Bit

Possible

Parity

Bit Standard

SCI Data

Infrared

SCI Data

Standard

SCI Data

Infrared

SCI Data

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416 Freescale Semiconductor

14.4.4 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the

transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.

The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is

synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the

transmitter. The receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to one source of error:

• Integer division of the bus clock may not give the exact target frequency.

Table 14-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.

When IREN = 0 then,

SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])

1The address bit identiﬁes the frame as an address

character. See Section 14.4.6.6, “Receiver Wakeup”.

Table 14-16. Baud Rates (Example: Bus Clock = 25 MHz)

Bits

SBR[12:0] Receiver

Clock (Hz) Transmitter

Clock (Hz) Target

Baud Rate Error

(%)

41 609,756.1 38,109.8 38,400 .76

81 308,642.0 19,290.1 19,200 .47

163 153,374.2 9585.9 9,600 .16

326 76,687.1 4792.9 4,800 .15

651 38,402.5 2400.2 2,400 .01

1302 19,201.2 1200.1 1,200 .01

2604 9600.6 600.0 600 .00

5208 4800.0 300.0 300 .00

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Freescale Semiconductor 417

14.4.5 Transmitter

Figure 14-16. Transmitter Block Diagram

14.4.5.1 Transmitter Character Length

The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8

in SCI data register high (SCIDRH) is the ninth bit (bit 8).

14.4.5.2 Character Transmission

To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn

are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through

the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data

registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit

shift register.

H876543210L

11-Bit Transmit Register

Stop

Start

TIE

TDRE

TCIE

SBK

Parity

Generation

MSB

SCI Data Registers

Load from SCIDR

Shift Enable

Preamble (All 1s)

Break (All 0s)

Transmitter Control

Internal Bus

SBR12:SBR0

Baud Divider ÷16

Bus

Clock

SCTXD

TXPOL

LOOPS

LOOP

RSRC

CONTROL To Receiver

Transmit

Collision Detect

TDRE IRQ

TC IRQ

SCTXD

SCRXD

(From Receiver)

TCIE

BERRIF

BER IRQ

BERRM[1:0]

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418 Freescale Semiconductor

The SCI also sets a ﬂag, the transmit data register empty ﬂag (TDRE), every time it transfers data from the

buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this ﬂag by

writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting

out the ﬁrst byte.

To initiate an SCI transmission:

1. Conﬁgure the SCI:

a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud

rate generator. Remember that the baud rate generator is disabled when the baud rate is zero.

Writing to the SCIBDH has no effect without also writing to SCIBDL.

b) Write to SCICR1 to conﬁgure word length, parity, and other conﬁguration bits

(LOOPS,RSRC,M,WAKE,ILT,PE,PT).

c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2

be shifted out of the transmitter shift register.

2. Transmit Procedure for each byte:

a) Poll the TDRE ﬂag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind

that the TDRE bit resets to one.

b) If the TDRE ﬂag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is

written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not

result until the TDRE ﬂag has been cleared.

3. Repeat step 2 for each subsequent transmission.

NOTE

The TDRE ﬂag is set when the shift register is loaded with the next data to

be transmitted from SCIDRH/L, which happens, generally speaking, a little

over half-way through the stop bit of the previous frame. Speciﬁcally, this

transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the

previous frame.

Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic

1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from

the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least

signiﬁcant bit position of the transmit shift register. A logic 1 stop bit goes into the most signiﬁcant bit

position.

Hardware supports odd or even parity. When parity is enabled, the most signiﬁcant bit (MSB) of the data

character is the parity bit.

The transmit data register empty ﬂag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI

data register transfers a byte to the transmit shift register. The TDRE ﬂag indicates that the SCI data

control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request.

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Freescale Semiconductor 419

When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic

1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal

goes low and the transmit signal goes idle.

If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register

continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE

to go high after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between messages:

1. Write the last byte of the ﬁrst message to SCIDRH/L.

2. Wait for the TDRE ﬂag to go high, indicating the transfer of the last frame to the transmit shift

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the ﬁrst byte of the second message to SCIDRH/L.

14.4.5.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift

Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic

1, transmitter logic continuously loads break characters into the transmit shift register. After software

clears the SBK bit, the shift register ﬁnishes transmitting the last break character and then transmits at least

one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit

of the next frame.

The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received.

Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI

registers.

If the break detect feature is disabled (BKDFE = 0):

• Sets the framing error flag, FE

• Sets the receive data register full flag, RDRF

• Clears the SCI data registers (SCIDRH/L)

• May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF

(see 3.4.4 and 3.4.5 SCI Status Register 1 and 2)

If the break detect feature is enabled (BKDFE = 1) there are two scenarios1

The break is detected right from a start bit or is detected during a byte reception.

• Sets the break detect interrupt flag, BLDIF

• Does not change the data register full flag, RDRF or overrun flag OR

• Does not change the framing error flag FE, parity error flag PE.

• Does not clear the SCI data registers (SCIDRH/L)

• May set noise flag NF, or receiver active flag RAF.

1. A Break character in this context are either 10 or 11 consecutive zero received bits

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420 Freescale Semiconductor

Figure 14-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit,

while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there

will be no byte transferred to the receive buffer and the RDRF ﬂag will not be modiﬁed. Also no framing

error or parity error will be ﬂagged from this transfer. In RXD_2 case, however the break signal starts later

during the transmission. At the expected stop bit position the byte received so far will be transferred to the

receive buffer, the receive data register full ﬂag will be set, a framing error and if enabled and appropriate

a parity error will be set. Once the break is detected the BRKDIF ﬂag will be set.

Figure 14-17. Break Detection if BRKDFE = 1 (M = 0)

14.4.5.4 Idle Characters

An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character

length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle

character that begins the ﬁrst transmission initiated after writing the TE bit from 0 to 1.

If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the

transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle

character to be sent after the frame currently being transmitted.

NOTE

When queueing an idle character, return the TE bit to logic 1 before the stop

bit of the current frame shifts out through the TXD pin. Setting TE after the

stop bit appears on TXD causes data previously written to the SCI data

TDRE ﬂag is set and immediately before writing the next byte to the SCI

data register.

If the TE bit is clear and the transmission is complete, the SCI is not the

master of the TXD pin

Start Bit Position Stop Bit Position

BRKDIF = 1

FE = 1 BRKDIF = 1

RXD_1

RXD_2

123 4567 8910

Zero Bit Counter

Zero Bit Counter . . .

. . .

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Freescale Semiconductor 421

14.4.5.5 LIN Transmit Collision Detection

This module allows to check for collisions on the LIN bus.

Figure 14-18. Collision Detect Principle

If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the

transmitted and the received data stream at a point in time and ﬂag any mismatch. The timing checks run

when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received

data is detected the following happens:

• The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)

• The transmission is aborted and the byte in transmit buffer is discarded.

• the transmit data register empty and the transmission complete flag will be set

• The bit error interrupt flag, BERRIF, will be set.

• No further transmissions will take place until the BERRIF is cleared.

Figure 14-19. Timing Diagram Bit Error Detection

If the bit error detect feature is disabled, the bit error interrupt ﬂag is cleared.

NOTE

The RXPOL and TXPOL bit should be set the same when transmission

collision detect feature is enabled, otherwise the bit error interrupt ﬂag may

be set incorrectly.

TXD Pin

RXD Pin

LIN Physical Interface

Synchronizer Stage

Bus Clock

Receive Shift

Transmit Shift

LIN Bus

Compare

Sample

Bit Error

Point

Output Transmit

Shift Register

01234567891011121314150

Input Receive

Shift Register

BERRM[1:0] = 0:1 BERRM[1:0] = 1:1

Compare Sample Points

Sampling Begin

Sampling End

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422 Freescale Semiconductor

14.4.6 Receiver

Figure 14-20. SCI Receiver Block Diagram

14.4.6.1 Receiver Character Length

The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in

SCI data register high (SCIDRH) is the ninth bit (bit 8).

14.4.6.2 Character Reception

During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register

is the read-only buffer between the internal data bus and the receive shift register.

After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the

SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set,

All 1s

WAKE

ILT

H876543210L

11-Bit Receive Shift Register

Stop

Start

Data

Wakeup

Parity

Checking

MSB

SCI Data Register

ILIE

RWU

RDRF

Internal Bus

Bus

SBR12:SBR0

Baud Divider

Clock

IDLE

RAF

Recovery

Logic

RXPOL

LOOPS

Loop

RSRC

Control

SCRXD

From TXD Pin

or Transmitter

Idle IRQ

RDRF/OR

IRQ

Break

Detect Logic

Active Edge

Detect Logic

BRKDFE

BRKDIE

BRKDIF

RXEDGIE

RXEDGIF

Break IRQ

RX Active Edge IRQ

RIE

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Freescale Semiconductor 423

indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control

14.4.6.3 Data Sampling

The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust

for baud rate mismatch, the RT clock (see Figure 14-21) is re-synchronized:

• After every start bit

• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit

samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic

1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

Figure 14-21. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.

Figure 14-17 summarizes the results of the start bit veriﬁcation samples.

If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins.

Table 14-17. Start Bit Veriﬁcation

RT3, RT5, and RT7 Samples Start Bit Veriﬁcation Noise Flag

000 Yes 0

001 Yes 1

010 Yes 1

011 No 0

100 Yes 1

101 No 0

110 No 0

111 No 0

Reset RT Clock

RT1

RT2

RT3

RT4

RT5

RT8

RT7

RT6

RT11

RT10

RT9

RT15

RT14

RT13

RT12

RT16

RT1

RT2

RT3

RT4

Samples

RT Clock

RT CLock Count

Start Bit

RXD

Start Bit

Qualiﬁcation Start Bit Data

Sampling

111111110000000

LSB

Veriﬁcation

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424 Freescale Semiconductor

To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and

RT10. Table 14-18 summarizes the results of the data bit samples.

NOTE

The RT8, RT9, and RT10 samples do not affect start bit veriﬁcation. If any

or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a

successful start bit veriﬁcation, the noise ﬂag (NF) is set and the receiver

assumes that the bit is a start bit (logic 0).

To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-19

summarizes the results of the stop bit samples.

Table 14-18. Data Bit Recovery

RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag

000 0 0

001 0 1

010 0 1

011 1 1

100 0 1

101 1 1

110 1 1

111 1 0

Table 14-19. Stop Bit Recovery

RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag

000 1 0

001 1 1

010 1 1

011 0 1

100 1 1

101 0 1

110 0 1

111 0 0

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Freescale Semiconductor 425

In Figure 14-22 the veriﬁcation samples RT3 and RT5 determine that the ﬁrst low detected was noise and

not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise ﬂag

is not set because the noise occurred before the start bit was found.

Figure 14-22. Start Bit Search Example 1

In Figure 14-23, veriﬁcation sample at RT3 is high. The RT3 sample sets the noise ﬂag. Although the

perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data

recovery is successful.

Figure 14-23. Start Bit Search Example 2

Reset RT Clock

RT1

RT2

RT3

RT4

RT5

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

Samples

RT Clock

RT Clock Count

Start Bit

RXD

110111100000

LSB

0 0

Reset RT Clock

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT11

RT10

RT9

RT14

RT13

RT12

RT2

RT1

RT16

RT15

RT3

RT4

RT5

RT6

RT7

Samples

RT Clock

RT Clock Count

Actual Start Bit

RXD

1111110000

LSB

Perceived Start Bit

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426 Freescale Semiconductor

In Figure 14-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample

at RT5 is high. The RT5 sample sets the noise ﬂag. Although this is a worst-case misalignment of perceived

bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.

Figure 14-24. Start Bit Search Example 3

Figure 14-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper

synchronization with the start bit time, it does set the noise ﬂag.

Figure 14-25. Start Bit Search Example 4

Reset RT Clock

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT13

RT12

RT11

RT16

RT15

RT14

RT4

RT3

RT2

RT1

RT5

RT6

RT7

RT8

RT9

Samples

RT Clock

RT Clock Count

Actual Start Bit

RXD

101110000

LSB

Perceived Start Bit

Reset RT Clock

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

Samples

RT Clock

RT Clock Count

Perceived and Actual Start Bit

RXD

11111001

LSB

11 1 1

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Freescale Semiconductor 427

Figure 14-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample

after the reset is low but is not preceded by three high samples that would qualify as a falling edge.

Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may

set the framing error ﬂag.

Figure 14-26. Start Bit Search Example 5

In Figure 14-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the

noise ﬂag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are

ignored.

Figure 14-27. Start Bit Search Example 6

14.4.6.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it

sets the framing error ﬂag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ﬂag

because a break character has no stop bit. The FE ﬂag is set at the same time that the RDRF ﬂag is set.

Reset RT Clock

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT1

Samples

RT Clock

RT Clock Count

Start Bit

RXD

11111010

LSB

11 1 1 1 0000000 0

No Start Bit Found

Reset RT Clock

RT1

RT2

RT3

RT4

RT7

RT6

RT5

RT10

RT9

RT8

RT14

RT13

RT12

RT11

RT15

RT16

RT1

RT2

RT3

Samples

RT Clock

RT Clock Count

Start Bit

RXD

11111000

LSB

11 1 1 0 110

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428 Freescale Semiconductor

14.4.6.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated

bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside

the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical

values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the

RT8, RT9, and RT10 stop bit samples are a logic zero.

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge

within the frame. Re synchronization within frames will correct a misalignment between transmitter bit

times and receiver bit times.

14.4.6.5.1 Slow Data Tolerance

Figure 14-28 shows how much a slow received frame can be misaligned without causing a noise error or

a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data

samples at RT8, RT9, and RT10.

Figure 14-28. Slow Data

Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles

to start data sampling of the stop bit.

With the misaligned character shown in Figure 14-28, the receiver counts 151 RTr cycles at the point when

the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data

character with no errors is:

((151 – 144) / 151) x 100 = 4.63%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles

to start data sampling of the stop bit.

With the misaligned character shown in Figure 14-28, the receiver counts 167 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit

character with no errors is:

((167 – 160) / 167) X 100 = 4.19%

MSB Stop

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

Data

Samples

Receiver

RT Clock

Serial Communication Interface (S12SCIV5)

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Freescale Semiconductor 429

14.4.6.5.2 Fast Data Tolerance

Figure 14-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10

instead of RT16 but is still sampled at RT8, RT9, and RT10.

Figure 14-29. Fast Data

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles

to ﬁnish data sampling of the stop bit.

With the misaligned character shown in Figure 14-29, the receiver counts 154 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit

character with no errors is:

((160 – 154) / 160) x 100 = 3.75%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles

to ﬁnish data sampling of the stop bit.

With the misaligned character shown in Figure 14-29, the receiver counts 170 RTr cycles at the point when

the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit

character with no errors is:

((176 – 170) /176) x 100 = 3.40%

14.4.6.6 Receiver Wakeup

To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,

the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2

(SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will

still load the receive data into the SCIDRH/L registers, but it will not set the RDRF ﬂag.

The transmitting device can address messages to selected receivers by including addressing information in

the initial frame or frames of each message.

The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby

state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark

wakeup.

Idle or Next FrameStop

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

Data

Samples

Receiver

RT Clock

Serial Communication Interface (S12SCIV5)

S12XS Family Reference Manual, Rev. 1.10

430 Freescale Semiconductor

14.4.6.6.1 Idle Input line Wakeup (WAKE = 0)

In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The

initial frame or frames of every message contain addressing information. All receivers evaluate the

addressing information, and receivers for which the message is addressed process the frames that follow.

Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The

RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD

pin.

Idle line wakeup requires that messages be separated by at least one idle character and that no message

contains idle characters.

The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register

full ﬂag, RDRF.

The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits

after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1).

14.4.6.6.2 Address Mark Wakeup (WAKE = 1)

In this wakeup method, a logic 1 in the most signiﬁcant bit (MSB) position of a frame clears the RWU bit

and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains

addressing information. All receivers evaluate the addressing information, and the receivers for which the

message is addressed process the frames that follow.Any receiver for which a message is not addressed can

set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on

standby until another address frame appears on the RXD pin.

The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets

the RDRF ﬂag.

Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved

for use in address frames.

NOTE

With the WAKE bit clear, setting the RWU bit after the RXD pin has been

idle can cause the receiver to wake up immediately.

14.4.7 Single-Wire Operation

Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is

disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.

Figure 14-30. Single-Wire Operation (LOOPS = 1, RSRC = 1)

RXD

Transmitter

Receiver

TXD

Serial Communication Interface (S12SCIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 431

Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control

the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled

(TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as

an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.

NOTE

In single-wire operation data from the TXD pin is inverted if RXPOL is set.

14.4.8 Loop Operation

In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the

SCI.

Figure 14-31. Loop Operation (LOOPS = 1, RSRC = 0)

Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1

(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC

bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled

(TE = 1 and RE = 1).

NOTE

In loop operation data from the transmitter is not recognized by the receiver

if RXPOL and TXPOL are not the same.

14.5 Initialization/Application Information

14.5.1 Reset Initialization

See Section 14.3.2, “Register Descriptions”.

14.5.2 Modes of Operation

14.5.2.1 Run Mode

Normal mode of operation.

To initialize a SCI transmission, see Section 14.4.5.2, “Character Transmission”.

RXD

Transmitter

Receiver

TXD

Serial Communication Interface (S12SCIV5)

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432 Freescale Semiconductor

14.5.2.2 Wait Mode

SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1

(SCICR1).

• If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.

• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation

state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver

enable bit, RE, or the transmitter enable bit, TE.

If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The

transmission or reception resumes when either an internal or external interrupt brings the CPU out

of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and

resets the SCI.

14.5.2.3 Stop Mode

The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not

affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from

where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset

aborts any transmission or reception in progress and resets the SCI.

The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input

can be used to bring the CPU out of stop mode.

14.5.3 Interrupt Operation

This section describes the interrupt originated by the SCI block.The MCU must service the interrupt

requests. Table 14-20 lists the eight interrupt sources of the SCI.

Table 14-20. SCI Interrupt Sources

Interrupt Source Local Enable Description

TDRE SCISR1[7] TIE Active high level. Indicates that a byte was transferred from SCIDRH/L to the

transmit shift register.

TC SCISR1[6] TCIE Active high level. Indicates that a transmit is complete.

RDRF SCISR1[5] RIE Active high level. The RDRF interrupt indicates that received data is available

in the SCI data register.

OR SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred.

IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle.

RXEDGIF SCIASR1[7] RXEDGIE Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for

RXPOL = 1) was detected.

BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received data

in a single wire application has happened.

BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received.

Serial Communication Interface (S12SCIV5)

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Freescale Semiconductor 433

14.5.3.1 Description of Interrupt Operation

The SCI only originates interrupt requests. The following is a description of how the SCI makes a request

and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are

chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and

all the following interrupts, when generated, are ORed together and issued through that port.

14.5.3.1.1 TDRE Description

The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI

data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a

new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1

with TDRE set and then writing to SCI data register low (SCIDRL).

14.5.3.1.2 TC Description

The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed

when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be

transmitted. No stop bit is transmitted when sending a break character and the TC ﬂag is set (providing

there is no more data queued for transmission) when the break character has been shifted out. A TC

interrupt indicates that there is no transmission in progress. TC is set high when the TDRE ﬂag is set and

no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle

(logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data

be sent.

14.5.3.1.3 RDRF Description

The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A

RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the

byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one

(SCISR1) and then reading SCI data register low (SCIDRL).

14.5.3.1.4 OR Description

The OR interrupt is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data

already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status

14.5.3.1.5 IDLE Description

The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1)

appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF ﬂag before

an idle condition can set the IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE

set and then reading SCI data register low (SCIDRL).

Serial Communication Interface (S12SCIV5)

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434 Freescale Semiconductor

14.5.3.1.6 RXEDGIF Description

The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the

RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.

14.5.3.1.7 BERRIF Description

The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single

wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative

status register 1. This ﬂag is also cleared if the bit error detect feature is disabled.

14.5.3.1.8 BKDIF Description

The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the

SCIASR1 SCI alternative status register 1. This ﬂag is also cleared if break detect feature is disabled.

14.5.4 Recovery from Wait Mode

The SCI interrupt request can be used to bring the CPU out of wait mode.

14.5.5 Recovery from Stop Mode

An active edge on the receive input can be used to bring the CPU out of stop mode.

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 435

Chapter 15

Serial Peripheral Interface (S12SPIV5)

15.1 Introduction

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral

devices. Software can poll the SPI status ﬂags or the SPI operation can be interrupt driven.

15.1.1 Glossary of Terms

15.1.2 Features

The SPI includes these distinctive features:

• Master mode and slave mode

• Selectable 8 or 16-bit transfer width

• Bidirectional mode

• Slave select output

• Mode fault error ﬂag with CPU interrupt capability

• Double-buffered data register

• Serial clock with programmable polarity and phase

• Control of SPI operation during wait mode

15.1.3 Modes of Operation

The SPI functions in three modes: run, wait, and stop.

Table 15-1. Revision History

Revision

Number Revision Date Sections

Affected Description of Changes

V05.00 24 Mar 2005 15.3.2/15-439 - Added 16-bit transfer width feature.

SPI Serial Peripheral Interface

SS Slave Select

SCK Serial Clock

MOSI Master Output, Slave Input

MISO Master Input, Slave Output

MOMI Master Output, Master Input

SISO Slave Input, Slave Output

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

436 Freescale Semiconductor

• Run mode

This is the basic mode of operation.

• Wait mode

SPI operation in wait mode is a conﬁgurable low power mode, controlled by the SPISWAI bit

located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in

run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock

generation turned off. If the SPI is conﬁgured as a master, any transmission in progress stops, but

is resumed after CPU goes into run mode. If the SPI is conﬁgured as a slave, reception and

transmission of data continues, so that the slave stays synchronized to the master.

• Stop mode

The SPI is inactive in stop mode for reduced power consumption. If the SPI is conﬁgured as a

master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI

is conﬁgured as a slave, reception and transmission of data continues, so that the slave stays

synchronized to the master.

For a detailed description of operating modes, please refer to Section 15.4.7, “Low Power Mode Options”.

15.1.4 Block Diagram

Figure 15-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and

data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.

Serial Peripheral Interface (S12SPIV5)

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Freescale Semiconductor 437

Figure 15-1. SPI Block Diagram

15.2 External Signal Description

This section lists the name and description of all ports including inputs and outputs that do, or may, connect

off chip. The SPI module has a total of four external pins.

15.2.1 MOSI — Master Out/Slave In Pin

This pin is used to transmit data out of the SPI module when it is conﬁgured as a master and receive data

when it is conﬁgured as slave.

15.2.2 MISO — Master In/Slave Out Pin

This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data

when it is conﬁgured as master.

SPI Control Register 1

SPI Control Register 2

SPI Baud Rate Register

SPI Status Register

SPI Data Register

Shifter

Port

Control

Logic

MOSI

SCK

Interrupt Control

SPI

MSB LSB

LSBFE=1 LSBFE=0

LSBFE=0 LSBFE=1

Data In

LSBFE=1

LSBFE=0

Data Out

Baud Rate Generator

Prescaler

Bus Clock

Counter

Clock Select

SPPR 33

SPR

Baud Rate

Phase +

Polarity

Control

Master

Slave

SCK In

SCK Out

Master Baud Rate

Slave Baud Rate

Phase +

Polarity

Control

Control CPOL CPHA

BIDIROE

SPC0

Shift Sample

ClockClock

MODF

SPIF SPTEF

SPI

Request

Interrupt

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438 Freescale Semiconductor

15.2.3 SS — Slave Select Pin

This pin is used to output the select signal from the SPI module to another peripheral with which a data

transfer is to take place when it is conﬁgured as a master and it is used as an input to receive the slave select

signal when the SPI is conﬁgured as slave.

15.2.4 SCK — Serial Clock Pin

In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.

15.3 Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the SPI.

15.3.1 Module Memory Map

The memory map for the SPI is given in Figure 15-2. The address listed for each register is the sum of a

base address and an address offset. The base address is deﬁned at the SoC level and the address offset is

deﬁned at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have

no effect.

Name Bit 7 6 5 4 3 2 1 Bit 0

0x0000

SPICR1 RSPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

0x0001

SPICR2 R0 XFRW 0MODFEN BIDIROE 0SPISWAI SPC0

0x0002

SPIBR R0 SPPR2 SPPR1 SPPR0 0SPR2 SPR1 SPR0

0x0003

SPISR R SPIF 0 SPTEF MODF 0 0 0 0

0x0004

SPIDRH R R15 R14 R13 R12 R11 R10 R9 R8

T15 T14 T13 T12 T11 T10 T9 T8W

0x0005

SPIDRL RR7R6R5R4R3R2R1R0

T7 T6 T5 T4 T3 T2 T1 T0W

0x0006

Reserved R

0x0007

Reserved R

= Unimplemented or Reserved

Figure 15-2. SPI Register Summary

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 439

15.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

15.3.2.1 SPI Control Register 1 (SPICR1)

Read: Anytime

Write: Anytime

Module Base +0x0000

76543210

RSPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

Reset 0 0 0 00100

Figure 15-3. SPI Control Register 1 (SPICR1)

Table 15-2. SPICR1 Field Descriptions

Field Description

SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status ﬂag is set.

0 SPI interrupts disabled.

1 SPI interrupts enabled.

SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system

functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.

0 SPI disabled (lower power consumption).

1 SPI enabled, port pins are dedicated to SPI functions.

SPTIE SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF ﬂag is set.

0 SPTEF interrupt disabled.

1 SPTEF interrupt enabled.

MSTR SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.

Switching the SPI from master to slave or vice versa forces the SPI system into idle state.

0 SPI is in slave mode.

1 SPI is in master mode.

CPOL SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI

modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a

transmission in progress and force the SPI system into idle state.

0 Active-high clocks selected. In idle state SCK is low.

1 Active-low clocks selected. In idle state SCK is high.

CPHA SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will

abort a transmission in progress and force the SPI system into idle state.

0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.

1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.

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440 Freescale Semiconductor

15.3.2.2 SPI Control Register 2 (SPICR2)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by

asserting the SSOE as shown in Table 15-3. In master mode, a change of this bit will abort a transmission in

progress and force the SPI system into idle state.

LSBFE LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and

writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit

will abort a transmission in progress and force the SPI system into idle state.

0 Data is transferred most signiﬁcant bit ﬁrst.

1 Data is transferred least signiﬁcant bit ﬁrst.

Table 15-3. SS Input / Output Selection

MODFEN SSOE Master Mode Slave Mode

00 SS not used by SPI SS input

01 SS not used by SPI SS input

10SS input with MODF feature SS input

11 SS is slave select output SS input

Module Base +0x0001

76543210

R0 XFRW 0MODFEN BIDIROE 0SPISWAI SPC0

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 15-4. SPI Control Register 2 (SPICR2)

Table 15-2. SPICR1 Field Descriptions (continued)

Field Description

Serial Peripheral Interface (S12SPIV5)

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Table 15-4. SPICR2 Field Descriptions

Field Description

XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL

becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and

SPIDRL form a 16-bit data register. Please refer to Section 15.3.2.4, “SPI Status Register (SPISR) for

information about transmit/receive data handling and the interrupt ﬂag clearing mechanism. In master mode, a

change of this bit will abort a transmission in progress and force the SPI system into idle state.

0 8-bit Transfer Width (n = 8)1

1 16-bit Transfer Width (n = 16)1

1n is used later in this document as a placeholder for the selected transfer width.

MODFEN Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and

MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an

input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin

conﬁguration, refer to Table 15-3. In master mode, a change of this bit will abort a transmission in progress and

force the SPI system into idle state.

0SS port pin is not used by the SPI.

1SS port pin with MODF feature.

BIDIROE Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer

of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output

buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0

set, a change of this bit will abort a transmission in progress and force the SPI into idle state.

0 Output buffer disabled.

1 Output buffer enabled.

SPISWAI SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.

0 SPI clock operates normally in wait mode.

1 Stop SPI clock generation when in wait mode.

SPC0 Serial Pin Control Bit 0 — This bit enables bidirectional pin conﬁgurations as shown in Table 15-5. In master

mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.

Table 15-5. Bidirectional Pin Conﬁgurations

Pin Mode SPC0 BIDIROE MISO MOSI

Master Mode of Operation

Normal 0 X Master In Master Out

Bidirectional 1 0 MISO not used by SPI Master In

1 Master I/O

Slave Mode of Operation

Normal 0 X Slave Out Slave In

Bidirectional 1 0 Slave In MOSI not used by SPI

1 Slave I/O

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442 Freescale Semiconductor

15.3.2.3 SPI Baud Rate Register (SPIBR)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

The baud rate divisor equation is as follows:

BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 15-1

The baud rate can be calculated with the following equation:

Baud Rate = BusClock / BaudRateDivisor Eqn. 15-2

NOTE

For maximum allowed baud rates, please refer to the SPI Electrical

Speciﬁcation in the Electricals chapter of this data sheet.

Module Base +0x0002

76543210

R0 SPPR2 SPPR1 SPPR0 0SPR2 SPR1 SPR0

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 15-5. SPI Baud Rate Register (SPIBR)

Table 15-6. SPIBR Field Descriptions

Field Description

6–4

SPPR[2:0] SPI Baud Rate Preselection Bits —These bits specify the SPI baud rates as shown in Table 15-7. In master

mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.

2–0

SPR[2:0] SPIBaud Rate SelectionBits—These bitsspecifythe SPIbaudratesasshownin Table 15-7.In master mode,

a change of these bits will abort a transmission in progress and force the SPI system into idle state.

Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3)

SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate

Divisor Baud Rate

0 0 0 0 0 0 2 12.5 Mbit/s

0 0 0 0 0 1 4 6.25 Mbit/s

0 0 0 0 1 0 8 3.125 Mbit/s

0 0 0 0 1 1 16 1.5625 Mbit/s

0 0 0 1 0 0 32 781.25 kbit/s

0 0 0 1 0 1 64 390.63 kbit/s

0 0 0 1 1 0 128 195.31 kbit/s

0 0 0 1 1 1 256 97.66 kbit/s

0 0 1 0 0 0 4 6.25 Mbit/s

0 0 1 0 0 1 8 3.125 Mbit/s

0 0 1 0 1 0 16 1.5625 Mbit/s

0 0 1 0 1 1 32 781.25 kbit/s

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0 0 1 1 0 0 64 390.63 kbit/s

0 0 1 1 0 1 128 195.31 kbit/s

0 0 1 1 1 0 256 97.66 kbit/s

0 0 1 1 1 1 512 48.83 kbit/s

0 1 0 0 0 0 6 4.16667 Mbit/s

0 1 0 0 0 1 12 2.08333 Mbit/s

0 1 0 0 1 0 24 1.04167 Mbit/s

0 1 0 0 1 1 48 520.83 kbit/s

0 1 0 1 0 0 96 260.42 kbit/s

0 1 0 1 0 1 192 130.21 kbit/s

0 1 0 1 1 0 384 65.10 kbit/s

0 1 0 1 1 1 768 32.55 kbit/s

0 1 1 0 0 0 8 3.125 Mbit/s

0 1 1 0 0 1 16 1.5625 Mbit/s

0 1 1 0 1 0 32 781.25 kbit/s

0 1 1 0 1 1 64 390.63 kbit/s

0 1 1 1 0 0 128 195.31 kbit/s

0 1 1 1 0 1 256 97.66 kbit/s

0 1 1 1 1 0 512 48.83 kbit/s

0 1 1 1 1 1 1024 24.41 kbit/s

1 0 0 0 0 0 10 2.5 Mbit/s

1 0 0 0 0 1 20 1.25 Mbit/s

1 0 0 0 1 0 40 625 kbit/s

1 0 0 0 1 1 80 312.5 kbit/s

1 0 0 1 0 0 160 156.25 kbit/s

1 0 0 1 0 1 320 78.13 kbit/s

1 0 0 1 1 0 640 39.06 kbit/s

1 0 0 1 1 1 1280 19.53 kbit/s

1 0 1 0 0 0 12 2.08333 Mbit/s

1 0 1 0 0 1 24 1.04167 Mbit/s

1 0 1 0 1 0 48 520.83 kbit/s

1 0 1 0 1 1 96 260.42 kbit/s

1 0 1 1 0 0 192 130.21 kbit/s

1 0 1 1 0 1 384 65.10 kbit/s

1 0 1 1 1 0 768 32.55 kbit/s

1 0 1 1 1 1 1536 16.28 kbit/s

1 1 0 0 0 0 14 1.78571 Mbit/s

1 1 0 0 0 1 28 892.86 kbit/s

1 1 0 0 1 0 56 446.43 kbit/s

1 1 0 0 1 1 112 223.21 kbit/s

1 1 0 1 0 0 224 111.61 kbit/s

1 1 0 1 0 1 448 55.80 kbit/s

Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3)

SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate

Divisor Baud Rate

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

444 Freescale Semiconductor

15.3.2.4 SPI Status Register (SPISR)

Read: Anytime

Write: Has no effect

1 1 0 1 1 0 896 27.90 kbit/s

1 1 0 1 1 1 1792 13.95 kbit/s

1 1 1 0 0 0 16 1.5625 Mbit/s

1 1 1 0 0 1 32 781.25 kbit/s

1 1 1 0 1 0 64 390.63 kbit/s

1 1 1 0 1 1 128 195.31 kbit/s

1 1 1 1 0 0 256 97.66 kbit/s

1 1 1 1 0 1 512 48.83 kbit/s

1 1 1 1 1 0 1024 24.41 kbit/s

1 1 1 1 1 1 2048 12.21 kbit/s

Module Base +0x0003

76543210

R SPIF 0 SPTEF MODF 0000

Reset 0 0 1 00000

= Unimplemented or Reserved

Figure 15-6. SPI Status Register (SPISR)

Table 15-8. SPISR Field Descriptions

Field Description

SPIF SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For

information about clearing SPIF Flag, please refer to Table 15-9.

0 Transfer not yet complete.

1 New data copied to SPIDR.

SPTEF SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For

information about clearing this bit and placing data into the transmit data register, please refer to Table 15-10.

0 SPI data register not empty.

1 SPI data register empty.

MODF Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is conﬁgured as a master and mode

fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in

Section 15.3.2.2,“SPI Control Register2 (SPICR2)”. Theﬂagis cleared automaticallybyaread oftheSPI status

0 Mode fault has not occurred.

1 Mode fault has occurred.

Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)

SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate

Divisor Baud Rate

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 445

Table 15-9. SPIF Interrupt Flag Clearing Sequence

Table 15-10. SPTEF Interrupt Flag Clearing Sequence

XFRW Bit SPIF Interrupt Flag Clearing Sequence

0 Read SPISR with SPIF == 1 then Read SPIDRL

1 Read SPISR with SPIF == 1

then

Byte Read SPIDRL 1

1Data in SPIDRH is lost in this case.

Byte Read SPIDRH 2

2SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read

of SPIDRL after reading SPISR with SPIF == 1.

Byte Read SPIDRL

Word Read (SPIDRH:SPIDRL)

XFRW Bit SPTEF Interrupt Flag Clearing Sequence

0 Read SPISR with SPTEF == 1 then Write to SPIDRL 1

1Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.

1 Read SPISR with SPTEF == 1

then

Byte Write to SPIDRL 12

2Data in SPIDRH is undeﬁned in this case.

Byte Write to SPIDRH 13

3SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by

writing to SPIDRL after reading SPISR with SPTEF == 1.

Byte Write to SPIDRL 1

Word Write to (SPIDRH:SPIDRL) 1

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

446 Freescale Semiconductor

15.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)

Read: Anytime; read data only valid when SPIF is set

Write: Anytime

The SPI data register is both the input and output register for SPI data. A write to this register

allows data to be queued and transmitted. For an SPI conﬁgured as a master, queued data is

transmitted immediately after the previous transmission has completed. The SPI transmitter empty

ﬂag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.

Received data in the SPIDR is valid when SPIF is set.

If SPIF is cleared and data has been received, the received data is transferred from the receive shift

If SPIF is set and not serviced, and a second data value has been received, the second received data

is kept as valid data in the receive shift register until the start of another transmission. The data in

the SPIDR does not change.

If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of

a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF

remains set (see Figure 15-9).

If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a

third transmission, the data in the receive shift register has become invalid and is not transferred

into the SPIDR (see Figure 15-10).

Module Base +0x0004

76543210

RR15 R14 R13 R12 R11 R10 R9 R8

WT15 T14 T13 T12 T11 T10 T9 T8

Reset 0 0 0 00000

Figure 15-7. SPI Data Register High (SPIDRH)

Module Base +0x0005

76543210

RR7 R6 R5 R4 R3 R2 R1 R0

WT7 T6 T5 T4 T3 T2 T1 T0

Reset 0 0 0 00000

Figure 15-8. SPI Data Register Low (SPIDRL)

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 447

Figure 15-9. Reception with SPIF serviced in Time

Figure 15-10. Reception with SPIF serviced too late

15.4 Functional Description

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral

devices. Software can poll the SPI status ﬂags or SPI operation can be interrupt driven.

The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,

the four associated SPI port pins are dedicated to the SPI function as:

• Slave select (SS)

• Serial clock (SCK)

• Master out/slave in (MOSI)

• Master in/slave out (MISO)

Receive Shift Register

SPIF

SPI Data Register

Data A Data B

Data A

Data A Received Data B Received

Data C

SPIF Serviced

Data C Received

Data B

= Unspeciﬁed = Reception in progress

Receive Shift Register

SPIF

SPI Data Register

Data A Data B

Data A

Data A Received Data B Received

Data C

SPIF Serviced

Data C Received

Data B Lost

= Unspeciﬁed = Reception in progress

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

448 Freescale Semiconductor

The main element of the SPI system is the SPI data register. The n-bit1data register in the master and the

n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1

by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the

master SPI data register becomes the output data for the slave, and data read from the master SPI data

A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register.

When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This

data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes.

A common SPI data register address is shared for reading data from the read data buffer and for writing

data to the transmit data register.

The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1

(SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply

selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally

different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see

Section 15.4.3, “Transmission Formats”).

The SPI can be conﬁgured to operate as a master or as a slave. When the MSTR bit in SPI control register1

is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.

NOTE

A change of CPOL or MSTR bit while there is a received byte pending in

the receive shift register will destroy the received byte and must be avoided.

15.4.1 Master Mode

The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate

transmissions. A transmission begins by writing to the master SPI data register. If the shift register is

empty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under the

control of the serial clock.

• Serial clock

The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and

SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and

determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK

pin, the baud rate generator of the master controls the shift register of the slave peripheral.

• MOSI, MISO pin

In master mode, the function of the serial data output pin (MOSI) and the serial data input pin

(MISO) is determined by the SPC0 and BIDIROE control bits.

•SS pin

If MODFEN and SSOE are set, the SS pin is conﬁgured as slave select output. The SS output

becomes low during each transmission and is high when the SPI is in idle state.

If MODFEN is set and SSOE is cleared, the SS pin is conﬁgured as input for detecting mode fault

error. If the SS input becomes low this indicates a mode fault error where another master tries to

1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 449

drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by

clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional

mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a

transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is

forced into idle state.

This mode fault error also sets the mode fault (MODF) ﬂag in the SPI status register (SPISR). If

the SPI interrupt enable bit (SPIE) is set when the MODF ﬂag becomes set, then an SPI interrupt

sequence is also requested.

When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After

the delay, SCK is started within the master. The rest of the transfer operation differs slightly,

depending on the clock format speciﬁed by the SPI clock phase bit, CPHA, in SPI control register 1

(see Section 15.4.3, “Transmission Formats”).

NOTE

A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN,

SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in

master mode will abort a transmission in progress and force the SPI into idle

state. The remote slave cannot detect this, therefore the master must ensure

that the remote slave is returned to idle state.

15.4.2 Slave Mode

The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.

• Serial clock

In slave mode, SCK is the SPI clock input from the master.

• MISO, MOSI pin

In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI)

is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.

•SS pin

The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI

must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is

forced into idle state.

The SS input also controls the serial data output pin, if SS is high (not selected), the serial data

output pin is high impedance, and, if SS is low, the ﬁrst bit in the SPI data register is driven out of

the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is

ignored and no internal shifting of the SPI shift register occurs.

Although the SPI is capable of duplex operation, some SPI peripherals are capable of only

receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.

NOTE

When peripherals with duplex capability are used, take care not to

simultaneously enable two receivers whose serial outputs drive the same

system slave’s serial data output line.

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

450 Freescale Semiconductor

As long as no more than one slave device drives the system slave’s serial data output line, it is possible for

several slaves to receive the same transmission from a master, although the master would not receive return

information from all of the receiving slaves.

If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at

the serial data input pin to be latched. Even numbered edges cause the value previously latched from the

serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.

If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to

be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift

into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.

When CPHA is set, the ﬁrst edge is used to get the ﬁrst data bit onto the serial data output pin. When CPHA

is clear and the SS input is low (slave selected), the ﬁrst bit of the SPI data is driven out of the serial data

output pin. After the nth1shift, the transfer is considered complete and the received data is transferred into

the SPI data register. To indicate transfer is complete, the SPIF ﬂag in the SPI status register is set.

NOTE

A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or

BIDIROE with SPC0 set in slave mode will corrupt a transmission in

progress and must be avoided.

15.4.3 Transmission Formats

During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially)

simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two

serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that

are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select

line can be used to indicate multiple-master bus contention.

Figure 15-11. Master/Slave Transfer Block Diagram

15.4.3.1 Clock Phase and Polarity Controls

Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase

and polarity.

1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)

SHIFT REGISTER

BAUD RATE

GENERATOR

MASTER SPI SLAVE SPI

MOSI MOSI

MISO MISO

SCK SCK

SS SS

VDD

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 451

The CPOL clock polarity control bit speciﬁes an active high or low clock and has no signiﬁcant effect on

the transmission format.

The CPHA clock phase control bit selects one of two fundamentally different transmission formats.

Clock phase and polarity should be identical for the master SPI device and the communicating slave

device. In some cases, the phase and polarity are changed between transmissions to allow a master device

to communicate with peripheral slaves having different requirements.

15.4.3.2 CPHA = 0 Transfer Format

The ﬁrst edge on the SCK line is used to clock the ﬁrst data bit of the slave into the master and the ﬁrst

data bit of the master into the slave. In some peripherals, the ﬁrst bit of the slave’s data is available at the

slave’s data out pin as soon as the slave is selected. In this format, the ﬁrst SCK edge is issued a half cycle

after SS has become low.

A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value

previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register,

depending on LSBFE bit.

After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of

the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK

line, with data being latched on odd numbered edges and shifted on even numbered edges.

Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and

is transferred to the parallel SPI data register after the last bit is shifted in.

After 2n1 (last) SCK edges:

• Data that was previously in the master SPI data register should now be in the slave data register and

the data that was in the slave data register should be in the master.

• The SPIF ﬂag in the SPI status register is set, indicating that the transfer is complete.

Figure 15-12 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for

CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because

the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal

is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master

must be either high or reconﬁgured as a general-purpose output not affecting the SPI.

1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

452 Freescale Semiconductor

Figure 15-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)

Begin End

SCK (CPOL = 0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL = 1)

MSB ﬁrst (LSBFE = 0):

LSB ﬁrst (LSBFE = 1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHANGE O

SEL SS (I)

MOSI pin

MISO pin

Master only

MOSI/MISO

If next transfer begins here

for tT, tl, tL

Minimum 1/2 SCK

tItL

tL = Minimum leading time before the ﬁrst SCK edge

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transfers (minimum SS high time)

tL, tT, and tI are guaranteed for the master mode and required for the slave mode.

1 234 56 78910111213141516

SCK Edge Number

End of Idle State Begin of Idle State

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 453

Figure 15-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1)

In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the

SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted

for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the

SPI data register is transmitted.

In master mode, with slave select output enabled the SS line is always deasserted and reasserted between

successive transfers for at least minimum idle time.

15.4.3.3 CPHA = 1 Transfer Format

Some peripherals require the ﬁrst SCK edge before the ﬁrst data bit becomes available at the data out pin,

the second edge clocks data into the system. In this format, the ﬁrst SCK edge is issued by setting the

CPHA bit at the beginning of the n1-cycle transfer operation.

The ﬁrst edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This ﬁrst

edge commands the slave to transfer its ﬁrst data bit to the serial data input pin of the master.

A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the

master and slave.

1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)

Begin End

SCK (CPOL = 0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL = 1)

MSB ﬁrst (LSBFE = 0)

LSB ﬁrst (LSBFE = 1) MSB

LSB LSB

MSB

Bit 13

Bit 2

Bit 14

Bit 1 Bit 12

Bit 3 Bit 11

Bit 4 Bit 5

CHANGE O

SEL SS (I)

MOSI pin

MISO pin

Master only

MOSI/MISO

If next transfer begins here

for tT, tl, tL

Minimum 1/2 SCK

tItL

tL = Minimum leading time before the ﬁrst SCK edge

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transfers (minimum SS high time)

tL, tT, and tI are guaranteed for the master mode and required for the slave mode.

12345678910111213141516

SCK Edge Number

End of Idle State Begin of Idle State

17181920212223242526272829303132

Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1

Bit 6Bit 5 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

454 Freescale Semiconductor

When the third edge occurs, the value previously latched from the serial data input pin is shifted into the

LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master

data is coupled out of the serial data output pin of the master to the serial input pin on the slave.

This process continues for a total of n1edges on the SCK line with data being latched on even numbered

edges and shifting taking place on odd numbered edges.

Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and

is transferred to the parallel SPI data register after the last bit is shifted in.

After 2n1 SCK edges:

• Data that was previously in the SPI data register of the master is now in the data register of the

slave, and data that was in the data register of the slave is in the master.

• The SPIF ﬂag bit in SPISR is set indicating that the transfer is complete.

Figure 15-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or

slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master

and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the

master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or

reconﬁgured as a general-purpose output not affecting the SPI.

Figure 15-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0)

tLtT

for tT, tl, tL

Minimum 1/2 SCK

tItL

If next transfer begins here

Begin End

SCK (CPOL = 0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL = 1)

MSB ﬁrst (LSBFE = 0):

LSB ﬁrst (LSBFE = 1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHANGE O

SEL SS (I)

MOSI pin

MISO pin

Master only

MOSI/MISO

tL = Minimum leading time before the ﬁrst SCK edge, not required for back-to-back transfers

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers

1 234 56 78910111213141516SCK Edge Number

End of Idle State Begin of Idle State

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 455

Figure 15-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1)

The SS line can remain active low between successive transfers (can be tied low at all times). This format

is sometimes preferred in systems having a single ﬁxed master and a single slave that drive the MISO data

line.

• Back-to-back transfers in master mode

In master mode, if a transmission has completed and new data is available in the SPI data register,

this data is sent out immediately without a trailing and minimum idle time.

The SPI interrupt request ﬂag (SPIF) is common to both the master and slave modes. SPIF gets set one

half SCK cycle after the last SCK edge.

15.4.4 SPI Baud Rate Generation

Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2,

SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in

the SPI baud rate.

The SPI clock rate is determined by the product of the value in the baud rate preselection bits

(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor

equation is shown in Equation 15-3.

BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 15-3

Begin End

SCK (CPOL = 0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL = 1)

MSB ﬁrst (LSBFE = 0)

LSB ﬁrst (LSBFE = 1) MSB

LSB LSB

MSB

Bit 13

Bit 2

Bit 14

Bit 1 Bit 12

Bit 3 Bit 11

Bit 4 Bit 5

CHANGE O

SEL SS (I)

MOSI pin

MISO pin

Master only

MOSI/MISO

If next transfer begins here

for tT, tl, tL

Minimum 1/2 SCK

tItL

tL = Minimum leading time before the ﬁrst SCK edge, not required for back-to-back transfers

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers

12345678910111213141516

SCK Edge Number

End of Idle State Begin of Idle State

17181920212223242526272829303132

Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1

Bit 6Bit 5 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

456 Freescale Semiconductor

When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection

bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor

becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc.

When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When

the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 15-7 for baud rate calculations

for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided

by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.

The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking

place. In the other cases, the divider is disabled to decrease IDD current.

NOTE

For maximum allowed baud rates, please refer to the SPI Electrical

Speciﬁcation in the Electricals chapter of this data sheet.

15.4.5 Special Features

15.4.5.1 SS Output

The SS output feature automatically drives the SS pin low during transmission to select external devices

and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin

is connected to the SS input pin of the external device.

The SS output is available only in master mode during normal SPI operation by asserting SSOE and

MODFEN bit as shown in Table 15-3.

The mode fault feature is disabled while SS output is enabled.

NOTE

Care must be taken when using the SS output feature in a multimaster

system because the mode fault feature is not available for detecting system

errors between masters.

15.4.5.2 Bidirectional Mode (MOMI or SISO)

The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 15-11). In

this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit

decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and

the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and

MOSI pin in slave mode are not used by the SPI.

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 457

The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is conﬁgured as an output,

serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift

• The SCK is output for the master mode and input for the slave mode.

• The SS is the input or output for the master mode, and it is always the input for the slave mode.

• The bidirectional mode does not affect SCK and SS functions.

NOTE

In bidirectional master mode, with mode fault enabled, both data pins MISO

and MOSI can be occupied by the SPI, though MOSI is normally used for

transmissions in bidirectional mode and MISO is not used by the SPI. If a

mode fault occurs, the SPI is automatically switched to slave mode. In this

case MISO becomes occupied by the SPI and MOSI is not used. This must

be considered, if the MISO pin is used for another purpose.

15.4.6 Error Conditions

The SPI has one error condition:

• Mode fault error

15.4.6.1 Mode Fault Error

If the SS input becomes low while the SPI is conﬁgured as a master, it indicates a system error where more

than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not

permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the

MODFEN bit is set.

In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by

the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case

Table 15-11. Normal Mode and Bidirectional Mode

When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0

Normal Mode

SPC0 = 0

Bidirectional Mode

SPC0 = 1

SPI

MOSI

MISO

Serial Out

Serial In

SPI

MOSI

MISO

Serial In

Serial Out

SPI

MOMI

Serial Out

Serial In

BIDIROE SPI

SISO

Serial In

Serial Out

BIDIROE

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

458 Freescale Semiconductor

the SPI system is conﬁgured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur

in slave mode.

If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output

buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any

possibility of conﬂict with another output driver. A transmission in progress is aborted and the SPI is

forced into idle state.

If the mode fault error occurs in the bidirectional mode for a SPI system conﬁgured in master mode, output

enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in

the bidirectional mode for SPI system conﬁgured in slave mode.

The mode fault ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed

by a write to SPI control register 1. If the mode fault ﬂag is cleared, the SPI becomes a normal master or

slave again.

NOTE

If a mode fault error occurs and a received data byte is pending in the receive

shift register, this data byte will be lost.

15.4.7 Low Power Mode Options

15.4.7.1 SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a

low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are

disabled.

15.4.7.2 SPI in Wait Mode

SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.

• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode

• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation

state when the CPU is in wait mode.

– If SPISWAI is set and the SPI is configured for master, any transmission and reception in

progress stops at wait mode entry. The transmission and reception resumes when the SPI exits

wait mode.

– If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in

progress continues if the SCK continues to be driven from the master. This keeps the slave

synchronized to the master and the SCK.

If the master transmits several bytes while the slave is in wait mode, the slave will continue to

send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is

currently sending its SPIDR to the master, it will continue to send the same byte. Else if the

slave is currently sending the last received byte from the master, it will continue to send each

previous master byte).

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 459

NOTE

Care must be taken when expecting data from a master while the slave is in

wait or stop mode. Even though the shift register will continue to operate,

the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated

until exiting stop or wait mode). Also, the byte from the shift register will

not be copied into the SPIDR register until after the slave SPI has exited wait

or stop mode. In slave mode, a received byte pending in the receive shift

SPIDR copy is generated only if wait mode is entered or exited during a

tranmission. If the slave enters wait mode in idle mode and exits wait mode

in idle mode, neither a SPIF nor a SPIDR copy will occur.

15.4.7.3 SPI in Stop Mode

Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held

high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the

transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is

exchanged correctly. In slave mode, the SPI will stay synchronized with the master.

The stop mode is not dependent on the SPISWAI bit.

15.4.7.4 Reset

The reset values of registers and signals are described in Section 15.3, “Memory Map and Register

Deﬁnition”, which details the registers and their bit ﬁelds.

• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit

garbage, or the data last received from the master before the reset.

• Reading from the SPIDR after reset will always read zeros.

15.4.7.5 Interrupts

The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is

a description of how the SPI makes a request and how the MCU should acknowledge that request. The

interrupt vector offset and interrupt priority are chip dependent.

The interrupt ﬂags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.

15.4.7.5.1 MODF

MODF occurs when the master detects an error on the SS pin. The master SPI must be conﬁgured for the

MODF feature (see Table 15-3). After MODF is set, the current transfer is aborted and the following bit is

changed:

• MSTR = 0, The master bit in SPICR1 resets.

The MODF interrupt is reﬂected in the status register MODF ﬂag. Clearing the ﬂag will also clear the

interrupt. This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing

process which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”.

Serial Peripheral Interface (S12SPIV5)

S12XS Family Reference Manual, Rev. 1.10

460 Freescale Semiconductor

15.4.7.5.2 SPIF

SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does

not clear until it is serviced. SPIF has an automatic clearing process, which is described in

Section 15.3.2.4, “SPI Status Register (SPISR)”.

15.4.7.5.3 SPTEF

SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear

until it is serviced. SPTEF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI

Status Register (SPISR)”.

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Freescale Semiconductor 461

Chapter 16

Timer Module (TIM16B8CV2)

16.1 Introduction

The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable

prescaler.

This timer can be used for many purposes, including input waveform measurements while simultaneously

generating an output waveform. Pulse widths can vary from microseconds to many seconds.

This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The

input capture function is used to detect a selected transition edge and record the time. The output compare

function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator

is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares

timer channel 7 when in event mode.

A full access for the counter registers or the input capture/output compare registers should take place in

one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the

same result as accessing them in one word.

16.1.1 Features

The TIM16B8CV2 includes these distinctive features:

Table 16-1. Revision History

Revision

Number Revision Date Sections Affected Description of Changes

V02.05 9 Jul 2009 16.3.2.12/16-477

16.3.2.13/16-477

16.3.2.15/16-479

16.3.2.16/16-480

16.3.2.19/16-482

16.4.2/16-485

16.4.3/16-485

- Revised ﬂag clearing procedure, whereby TEN or PAEN bit must be set

when clearing ﬂags.

- Add fomula to describe prescaler

V02.06 26 Aug 2009 16.1.2/16-462

16.3.2.15/16-479

16.3.2.2/16-468

16.3.2.3/16-469

16.3.2.4/16-470

16.4.3/16-485

- Correct typo: TSCR ->TSCR1

- Correct reference: Figure 1-25 -> Figure 1-31

- Add description, “a counter overﬂow when TTOV[7] is set”, to be the

condition of channel 7 override event.

- Phrase the description of OC7M to make it more explicit

V02.07 04 May 2010 16.3.2.8/16-473

16.3.2.11/16-476

16.4.3/16-485

- Add Table 16-10

- in TCRE bit description part,add Note

- Add Figure 16-31

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

462 Freescale Semiconductor

• Eight input capture/output compare channels.

• Clock prescaling.

• 16-bit counter.

• 16-bit pulse accumulator.

16.1.2 Modes of Operation

Stop: Timer is off because clocks are stopped.

Freeze: Timer counter keep on running, unless TSFRZ in TSCR1 (0x0006) is set to 1.

Wait: Counters keep on running, unless TSWAI in TSCR1 (0x0006) is set to 1.

Normal: Timer counter keep on running, unless TEN in TSCR1 (0x0006) is cleared to 0.

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 463

16.1.3 Block Diagrams

Figure 16-1. TIM16B8CV2 Block Diagram

Prescaler

16-bit Counter

Input capture

Output compare

16-bit

Pulse accumulator

IOC0

IOC2

IOC1

IOC5

IOC3

IOC4

IOC6

IOC7

PA input

interrupt

PA overflow

interrupt

Timer overflow

interrupt

Timer channel 0

interrupt

Timer channel 7

interrupt

Registers

Bus clock

Input capture

Output compare

Input capture

Output compare

Input capture

Output compare

Input capture

Output compare

Input capture

Output compare

Input capture

Output compare

Input capture

Output compare

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

464 Freescale Semiconductor

Figure 16-2. 16-Bit Pulse Accumulator Block Diagram

Figure 16-3. Interrupt Flag Setting

Edge detector

Intermodule Bus

PT7

M clock

Divide by 64

Clock select

CLK0

CLK1 4:1 MUX

TIMCLK

PACL K

PACLK / 256

PACLK / 65536

Prescaled clock

(PCLK)

(Timer clock)

Interrupt

MUX

(PAMOD)

PACNT

PTn

Edge detector

16-bit Main Timer

TCn Input Capture Reg.

Set CnF Interrupt

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 465

Figure 16-4. Channel 7 Output Compare/Pulse Accumulator Logic

16.2 External Signal Description

The TIM16B8CV2 module has a total of eight external pins.

16.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin

This pin serves as input capture or output compare for channel 7. This can also be conﬁgured as pulse

accumulator input.

16.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin

This pin serves as input capture or output compare for channel 6.

16.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin

This pin serves as input capture or output compare for channel 5.

16.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin

This pin serves as input capture or output compare for channel 4. Pin

16.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin

This pin serves as input capture or output compare for channel 3.

16.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin

This pin serves as input capture or output compare for channel 2.

PULSE

ACCUMULATOR PAD

TEN

CHANNEL 7 OUTPUT COMPARE

OCPD

TIOS7

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

466 Freescale Semiconductor

16.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin

This pin serves as input capture or output compare for channel 1.

16.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin

This pin serves as input capture or output compare for channel 0.

NOTE

For the description of interrupts see Section 16.6, “Interrupts”.

16.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all memory and registers.

16.3.1 Module Memory Map

The memory map for the TIM16B8CV2 module is given below in Figure 16-5. The address listed for each

TIM16B8CV2 module and the address offset for each register.

16.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard

Name Bit 7 654321Bit 0

0x0000

TIOS RIOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0

0x0001

CFORC R00000000

W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

0x0002

OC7M ROC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

0x0003

OC7D ROC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0

0x0004

TCNTH RTCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8

0x0005

TCNTL RTCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0

= Unimplemented or Reserved

Figure 16-5. TIM16B8CV2 Register Summary (Sheet 1 of 3)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 467

0x0006

TSCR1 RTEN TSWAI TSFRZ TFFCA PRNT 000

0x0007

TTOV RTOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0

0x0008

TCTL1 ROM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4

0x0009

TCTL2 ROM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

0x000A

TCTL3 REDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

0x000B

TCTL4 REDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A

0x000C

TIE RC7I C6I C5I C4I C3I C2I C1I C0I

0x000D

TSCR2 RTOI 000

TCRE PR2 PR1 PR0

0x000E

TFLG1 RC7F C6F C5F C4F C3F C2F C1F C0F

0x000F

TFLG2 RTOF 0000000

0x0010–0x001F

TCxH–TCxL

RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x0020

PACTL R0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

0x0021

PAFLG R000000

PAOVF PAIF

0x0022

PACNTH RPACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8

0x0023

PACNTL RPACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0

0x0024–0x002B

Reserved R

Name Bit 7 654321Bit 0

= Unimplemented or Reserved

Figure 16-5. TIM16B8CV2 Register Summary (Sheet 2 of 3)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

468 Freescale Semiconductor

16.3.2.1 Timer Input Capture/Output Compare Select (TIOS)

Read: Anytime

Write: Anytime

16.3.2.2 Timer Compare Force Register (CFORC)

0x002C

OCPD ROCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0

0x002D R

0x002E

PTPSR RPTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0

0x002F

Reserved R

Module Base + 0x0000

76543210

RIOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0

Reset 00000000

Figure 16-6. Timer Input Capture/Output Compare Select (TIOS)

Table 16-2. TIOS Field Descriptions

Field Description

7:0

IOS[7:0] Input Capture or Output Compare Channel Conﬁguration

0 The corresponding channel acts as an input capture.

1 The corresponding channel acts as an output compare.

Module Base + 0x0001

76543210

R00000000

W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

Reset 00000000

Figure 16-7. Timer Compare Force Register (CFORC)

Name Bit 7 654321Bit 0

= Unimplemented or Reserved

Figure 16-5. TIM16B8CV2 Register Summary (Sheet 3 of 3)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 469

Read: Anytime but will always return 0x0000 (1 state is transient)

Write: Anytime

16.3.2.3 Output Compare 7 Mask Register (OC7M)

Read: Anytime

Write: Anytime

Table 16-3. CFORC Field Descriptions

Field Description

7:0

FOC[7:0] Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set

causes the action which is programmed for output compare “x” to occur immediately. The action taken is the

same as if a successful comparison had just taken place with the TCx register except the interrupt ﬂag does not

get set.

Note: A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare

on channel 7, overrides any channel 6:0 compares. If forced output compare on any channel occurs at the

same time as the successful output compare then forced output compare action will take precedence and

interrupt ﬂag won’t get set.

Module Base + 0x0002

76543210

ROC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

Reset 00000000

Figure 16-8. Output Compare 7 Mask Register (OC7M)

Table 16-4. OC7M Field Descriptions

Field Description

7:0

OC7M[7:0] Output Compare 7 Mask — A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a

successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,

the output compare action reﬂects the corresponding OC7D bit.

0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on

a channel 7 event, even if the corresponding pin is setup for output compare.

1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a

channel 7 event.

Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to

be transferred from the output compare 7 data register to the timer port.

Timer Module (TIM16B8CV2)

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470 Freescale Semiconductor

16.3.2.4 Output Compare 7 Data Register (OC7D)

Read: Anytime

Write: Anytime

16.3.2.5 Timer Count Register (TCNT)

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle. A separate read/write for high

byte and low byte will give a different result than accessing them as a word.

Read: Anytime

Module Base + 0x0003

76543210

ROC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0

Reset 00000000

Figure 16-9. Output Compare 7 Data Register (OC7D)

Table 16-5. OC7D Field Descriptions

Field Description

7:0

OC7D[7:0] Output Compare 7 Data — A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a

successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the

timer port data register depending on the output compare 7 mask register.

Module Base + 0x0004

15 14 13 12 11 10 9 9

RTCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8

Reset 00000000

Figure 16-10. Timer Count Register High (TCNTH)

Module Base + 0x0005

76543210

RTCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0

Reset 00000000

Figure 16-11. Timer Count Register Low (TCNTL)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 471

Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).

The period of the ﬁrst count after a write to the TCNT registers may be a different size because the write

is not synchronized with the prescaler clock.

16.3.2.6 Timer System Control Register 1 (TSCR1)

Read: Anytime

Write: Anytime

Module Base + 0x0006

76543210

RTEN TSWAI TSFRZ TFFCA PRNT 000

Reset 00000000

= Unimplemented or Reserved

Figure 16-12. Timer System Control Register 1 (TSCR1)

Table 16-6. TSCR1 Field Descriptions

Field Description

TEN Timer Enable

0 Disables the main timer, including the counter. Can be used for reducing power consumption.

1 Allows the timer to function normally.

If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is

generated by the timer prescaler.

TSWAI Timer Module Stops While in Wait

0 Allows the timer module to continue running during wait.

1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU

out of wait.

TSWAI also affects pulse accumulator.

TSFRZ Timer Stops While in Freeze Mode

0 Allows the timer counter to continue running while in freeze mode.

1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.

TSFRZ does not stop the pulse accumulator.

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472 Freescale Semiconductor

16.3.2.7 Timer Toggle On Overﬂow Register 1 (TTOV)

Read: Anytime

Write: Anytime

TFFCA Timer Fast Flag Clear All

0 Allows the timer ﬂag clearing to function normally.

1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)

causes the corresponding channel ﬂag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT

the PAOVF and PAIF ﬂags in the PAFLG register (0x0021). This has the advantage of eliminating software

overhead in a separate clear sequence. Extra care is required to avoid accidental ﬂag clearing due to

unintended accesses.

PRNT Precision Timer

0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler

selection.

1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and

all bits.

This bit is writable only once out of reset.

Module Base + 0x0007

76543210

RTOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0

Reset 00000000

Figure 16-13. Timer Toggle On Overﬂow Register 1 (TTOV)

Table 16-7. TTOV Field Descriptions

Field Description

7:0

TOV[7:0] Toggle On Overﬂow Bits — TOVx toggles output compare pin on overﬂow. This feature only takes effect when

in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override

events.

0 Toggle output compare pin on overﬂow feature disabled.

1 Toggle output compare pin on overﬂow feature enabled.

Table 16-6. TSCR1 Field Descriptions (continued)

Field Description

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 473

16.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

Read: Anytime

Write: Anytime

Module Base + 0x0008

76543210

ROM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4

Reset 00000000

Figure 16-14. Timer Control Register 1 (TCTL1)

Module Base + 0x0009

76543210

ROM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

Reset 00000000

Figure 16-15. Timer Control Register 2 (TCTL2)

Table 16-8. TCTL1/TCTL2 Field Descriptions

Field Description

7:0

OMx Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result

of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output

tied to OCx.

Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For

an output line to be driven by an OCx the OCPDx must be cleared.

7:0

OLx Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result

of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output

tied to OCx.

Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For

an output line to be driven by an OCx the OCPDx must be cleared.

Table 16-9. Compare Result Output Action

OMx OLx Action

0 0 No output compare

action on the timer output signal

0 1 Toggle OCx output line

1 0 Clear OCx output line to zero

1 1 Set OCx output line to one

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

474 Freescale Semiconductor

To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0

respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the

OC7M register must also be cleared.

To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in

the OC7M register must also be cleared. The settings for these bits can be seen in Table 16-10

Table 16-10. The OC7 and OCx event priority

Note: in Table 16-10, the IOS7 and IOSx should be set to 1

IOSx is the register TIOS bit x,

OC7Mx is the register OC7M bit x,

TCx is timer Input Capture/Output Compare register,

IOCx is channel x,

OMx/OLx is the register TCTL1/TCTL2,

OC7Dx is the register OC7D bit x.

IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value.

16.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

OC7M7=0 OC7M7=1

OC7Mx=1 OC7Mx=0 OC7Mx=1 OC7Mx=0

TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx

IOCx=OC7Dx

IOC7=OM7/O

IOCx=OC7Dx

+OMx/OLx

IOC7=OM7/O

IOCx=OMx/OLx

IOC7=OM7/OL7 IOCx=OC7Dx

IOC7=OC7D7 IOCx=OC7Dx

+OMx/OLx

IOC7=OC7D7

IOCx=OMx/OLx

IOC7=OC7D7

Module Base + 0x000A

76543210

REDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

Reset 00000000

Figure 16-16. Timer Control Register 3 (TCTL3)

Module Base + 0x000B

76543210

REDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A

Reset 00000000

Figure 16-17. Timer Control Register 4 (TCTL4)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 475

Read: Anytime

Write: Anytime.

16.3.2.10 Timer Interrupt Enable Register (TIE)

Read: Anytime

Write: Anytime.

Table 16-11. TCTL3/TCTL4 Field Descriptions

Field Description

7:0

EDGnB

EDGnA

Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector

circuits.

Table 16-12. Edge Detector Circuit Conﬁguration

EDGnB EDGnA Conﬁguration

0 0 Capture disabled

0 1 Capture on rising edges only

1 0 Capture on falling edges only

1 1 Capture on any edge (rising or falling)

Module Base + 0x000C

76543210

RC7I C6I C5I C4I C3I C2I C1I C0I

Reset 00000000

Figure 16-18. Timer Interrupt Enable Register (TIE)

Table 16-13. TIE Field Descriptions

Field Description

7:0

C7I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in

the TFLG1 status register. If cleared, the corresponding ﬂag is disabled from causing a hardware interrupt. If set,

the corresponding ﬂag is enabled to cause a interrupt.

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

476 Freescale Semiconductor

16.3.2.11 Timer System Control Register 2 (TSCR2)

Read: Anytime

Write: Anytime.

Module Base + 0x000D

76543210

RTOI 000

TCRE PR2 PR1 PR0

Reset 00000000

= Unimplemented or Reserved

Figure 16-19. Timer System Control Register 2 (TSCR2)

Table 16-14. TSCR2 Field Descriptions

Field Description

TOI Timer Overﬂow Interrupt Enable

0 Interrupt inhibited.

1 Hardware interrupt requested when TOF ﬂag set.

TCRE Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7

event. This mode of operation is similar to an up-counting modulus counter.

0 Counter reset inhibited and counter free runs.

1 Counter reset by a successful output compare 7.

Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1,

TOF will never be set when TCNT is reset from 0xFFFF to 0x0000.

Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for

a more detail explanation please refer to Section 16.4.3, “Output Compare

PR[2:0] Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the

Bus Clock as shown in Table 16-15.

Table 16-15. Timer Clock Selection

PR2 PR1 PR0 Timer Clock

0 0 0 Bus Clock / 1

0 0 1 Bus Clock / 2

0 1 0 Bus Clock / 4

0 1 1 Bus Clock / 8

1 0 0 Bus Clock / 16

1 0 1 Bus Clock / 32

1 1 0 Bus Clock / 64

1 1 1 Bus Clock / 128

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 477

NOTE

The newly selected prescale factor will not take effect until the next

synchronized edge where all prescale counter stages equal zero.

16.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime

Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero

will not affect current status of the bit.

16.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)

TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the ﬂag register, write the bit

to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.

Read: Anytime

Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.

Module Base + 0x000E

76543210

RC7F C6F C5F C4F C3F C2F C1F C0F

Reset 00000000

Figure 16-20. Main Timer Interrupt Flag 1 (TFLG1)

Table 16-16. TRLG1 Field Descriptions

Field Description

7:0

C[7:0]F Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output

compare event occurs. Clearing requires writing a one to the corresponding ﬂag bit while TEN or PAEN is set to

one.

When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel

(0x0010–0x001F) will cause the corresponding channel ﬂag CxF to be cleared.

Module Base + 0x000F

76543210

RTOF 0000000

Reset 00000000

Unimplemented or Reserved

Figure 16-21. Main Timer Interrupt Flag 2 (TFLG2)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

478 Freescale Semiconductor

16.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7

(TCxH and TCxL)

Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the

free-running counter when a deﬁned transition is sensed by the corresponding input capture edge detector

or to trigger an output action for output compare.

Read: Anytime

Write: Anytime for output compare function.Writes to these registers have no meaning or effect during

input capture. All timer input capture/output compare registers are reset to 0x0000.

NOTE

Read/Write access in byte mode for high byte should takes place before low

byte otherwise it will give a different result.

Table 16-17. TRLG2 Field Descriptions

Field Description

TOF Timer Overﬂow Flag — Set when 16-bit free-running timer overﬂows from 0xFFFF to 0x0000. Clearing this bit

requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one

(See also TCRE control bit explanation.)

Module Base + 0x0010 = TC0H

0x0012 = TC1H

0x0014 = TC2H

0x0016 = TC3H

0x0018 = TC4H

0x001A = TC5H

0x001C = TC6H

0x001E = TC7H

15 14 13 12 11 10 9 0

RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Reset 00000000

Figure 16-22. Timer Input Capture/Output Compare Register x High (TCxH)

Module Base + 0x0011 = TC0L

0x0013 = TC1L

0x0015 = TC2L

0x0017 = TC3L

0x0019 = TC4L

0x001B = TC5L

0x001D = TC6L

0x001F = TC7L

76543210

RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset 00000000

Figure 16-23. Timer Input Capture/Output Compare Register x Low (TCxL)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 479

16.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)

When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.

Read: Any time

Write: Any time

Module Base + 0x0020

76543210

R0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

Reset 00000000

Unimplemented or Reserved

Figure 16-24. 16-Bit Pulse Accumulator Control Register (PACTL)

Table 16-18. PACTL Field Descriptions

Field Description

PAEN Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse

accumulator can function unless pulse accumulator is disabled.

0 16-Bit Pulse Accumulator system disabled.

1 Pulse Accumulator system enabled.

PAMOD Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See

Table 16-19.

0 Event counter mode.

1 Gated time accumulation mode.

PEDGE Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).

For PAMOD bit = 0 (event counter mode). See Table 16-19.

0 Falling edges on IOC7 pin cause the count to be incremented.

1 Rising edges on IOC7 pin cause the count to be incremented.

For PAMOD bit = 1 (gated time accumulation mode).

0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling

edge on IOC7 sets the PAIF ﬂag.

1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge

on IOC7 sets the PAIF ﬂag.

3:2

CLK[1:0] Clock Select Bits — Refer to Table 16-20.

PAOVI Pulse Accumulator Overﬂow Interrupt Enable

0 Interrupt inhibited.

1 Interrupt requested if PAOVF is set.

PAI Pulse Accumulator Input Interrupt Enable

0 Interrupt inhibited.

1 Interrupt requested if PAIF is set.

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

480 Freescale Semiconductor

NOTE

If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64

because the ÷64 clock is generated by the timer prescaler.

For the description of PACLK please refer Figure 16-30.

If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an

input clock to the timer counter. The change from one selected clock to the other happens immediately

after these bits are written.

16.3.2.16 Pulse Accumulator Flag Register (PAFLG)

Read: Anytime

Write: Anytime

When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the ﬂags

in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while

clearing these bits.

Table 16-19. Pin Action

PAMOD PEDGE Pin Action

0 0 Falling edge

0 1 Rising edge

1 0 Div. by 64 clock enabled with pin high level

1 1 Div. by 64 clock enabled with pin low level

Table 16-20. Timer Clock Selection

CLK1 CLK0 Timer Clock

0 0 Use timer prescaler clock as timer counter clock

0 1 Use PACLK as input to timer counter clock

1 0 Use PACLK/256 as timer counter clock frequency

1 1 Use PACLK/65536 as timer counter clock frequency

Module Base + 0x0021

76543210

R000000

PAOVF PAIF

Reset 00000000

Unimplemented or Reserved

Figure 16-25. Pulse Accumulator Flag Register (PAFLG)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 481

16.3.2.17 Pulse Accumulators Count Registers (PACNT)

Read: Anytime

Write: Anytime

These registers contain the number of active input edges on its input pin since the last reset.

When PACNT overﬂows from 0xFFFF to 0x0000, the Interrupt ﬂag PAOVF in PAFLG (0x0021) is set.

Full count register access should take place in one clock cycle. A separate read/write for high byte and low

byte will give a different result than accessing them as a word.

NOTE

Reading the pulse accumulator counter registers immediately after an

active edge on the pulse accumulator input pin may miss the last count

because the input has to be synchronized with the bus clock ﬁrst.

Table 16-21. PAFLG Field Descriptions

Field Description

PAOVF Pulse Accumulator Overﬂow Flag — Set when the 16-bit pulse accumulator overﬂows from 0xFFFF to 0x0000.

Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of

PACTL register is set to one.

PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event

mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at

the IOC7 input pin triggers PAIF.

Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of

PACTL register is set to one. Any access to the PACNT register will clear all the ﬂags in this register when TFFCA

bit in register TSCR(0x0006) is set.

Module Base + 0x0022

15 14 13 12 11 10 9 0

RPACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8

Reset 00000000

Figure 16-26. Pulse Accumulator Count Register High (PACNTH)

Module Base + 0x0023

76543210

RPACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0

Reset 00000000

Figure 16-27. Pulse Accumulator Count Register Low (PACNTL)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

482 Freescale Semiconductor

16.3.2.18 Output Compare Pin Disconnect Register(OCPD)

Read: Anytime

Write: Anytime

All bits reset to zero.

16.3.2.19 Precision Timer Prescaler Select Register (PTPSR)

Read: Anytime

Write: Anytime

All bits reset to zero.

Module Base + 0x002C

76543210

ROCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0

Reset 00000000

Figure 16-28. Ouput Compare Pin Disconnect Register (OCPD)

Table 16-22. OCPD Field Description

Field Description

OCPD[7:0} Output Compare Pin Disconnect Bits

0 Enables the timer channel port. Ouptut Compare action will occur on the channel pin. These bits do not affect

the input capture or pulse accumulator functions

1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output

compare ﬂag still become set .

Module Base + 0x002E

76543210

RPTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0

Reset 00000000

Figure 16-29. Precision Timer Prescaler Select Register (PTPSR)

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 483

The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:

PRNT = 1 : Prescaler = PTPS[7:0] + 1

Table 16-24. Precision Timer Prescaler Selection Examples when PRNT = 1

16.4 Functional Description

This section provides a complete functional description of the timer TIM16B8CV2 block. Please refer to

the detailed timer block diagram in Figure 16-30 as necessary.

Table 16-23. PTPSR Field Descriptions

Field Description

7:0

PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.

These are effective only when the PRNT bit of TSCR1 is set to 1. Table 16-24 shows some selection examples

in this case.

Thenewlyselected prescale factorwillnot takeeffectuntil thenextsynchronizededgewhereall prescale counter

stages equal zero.

PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale

Factor

00000000 1

00000001 2

00000010 3

00000011 4

00000100 5

00000101 6

00000110 7

00000111 8

00001111 16

00011111 32

00111111 64

01111111128

11111111256

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

484 Freescale Semiconductor

Figure 16-30. Detailed Timer Block Diagram

16.4.1 Prescaler

The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select

the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).

PRESCALER

CHANNEL 0

IOC0 PIN

16-BIT COUNTER

LOGIC

PR[2:1:0]

DIVIDE-BY-64

TC0

EDGE

DETECT

PACNT(hi):PACNT(lo)

PAOVF PEDGE

PAOVI

TEN

PAE

16-BIT COMPARATOR

TCNT(hi):TCNT(lo)

CHANNEL 1

TC1

16-BIT COMPARATOR

16-BIT COUNTER

INTERRUPT

LOGIC

TOF

TOI

C0F

C1F

EDGE

DETECT

IOC1 PIN

LOGIC

EDGE

DETECT

CxF

CHANNEL7

TC7

16-BIT COMPARATOR C7F

IOC7 PIN

LOGIC

EDGE

DETECT

OM:OL0

TOV0

OM:OL1

TOV1

OM:OL7

TOV7

EDG1A EDG1B

EDG7A

EDG7B

EDG0B

TCRE

PAIF

CLEAR COUNTER

PAIF

PAI

INTERRUPT

LOGIC

CxI

INTERRUPT

REQUEST

PAOVF

CH. 7 COMPARE

CH.7 CAPTURE

CH. 1 CAPTURE

MUX

CLK[1:0]

PACLK

PACLK/256

PACLK/65536

IOC1 PIN

IOC0 PIN

IOC7 PIN

PACLK

PACLK/256

PACLK/65536

CH. 1 COMPARE

CH. 0COMPARE

CH. 0 CAPTURE

PA INPUT

CHANNEL2

EDG0A

channel 7 output

compare

IOC0

IOC1

IOC7

Bus Clock

PAOVF

PAOVI

TOF

C0F

C1F

C7F

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 485

The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system

control register 2 (TSCR2) are set to deﬁne a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,

64 and 128 when the PRNT bit in TSCR1 is disabled.

By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this

case, it is possible to set additional prescaler settings for the main timer counter in the present timer by

using PTPSR[7:0] bits of PTPSR register.

16.4.2 Input Capture

Clearing the I/O (input/output) select bit, IOSx, conﬁgures channel x as an input capture channel. The

input capture function captures the time at which an external event occurs. When an active edge occurs on

the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel

registers, TCx.

The minimum pulse width for the input capture input is greater than two bus clocks.

An input capture on channel x sets the CxF ﬂag. The CxI bit enables the CxF ﬂag to generate interrupt

requests. Timer module or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of

PACTL regsiter must be set to one) while clearing CxF (writing one to CxF).

16.4.3 Output Compare

Setting the I/O select bit, IOSx, conﬁgures channel x as an output compare channel. The output compare

function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the

timer counter reaches the value in the channel registers of an output compare channel, the timer can set,

clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on

channel x sets the CxF ﬂag. The CxI bit enables the CxF ﬂag to generate interrupt requests. Timer module

or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of PACTL regsiter must be set

to one) while clearing CxF (writing one to CxF).

The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both

OMx and OLx results in no output compare action on the output compare channel pin.

Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output

compare does not set the channel ﬂag.

A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare

on channel 7, overrides output compares on all other output compare channels. The output compare 7 mask

enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the

timer counter even if the IOC7 pin is being used as the pulse accumulator input.

Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is

stored in an internal latch. When the pin becomes available for general-purpose output, the last value

written to the bit appears at the pin.

When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches

TC7 value, it will last only one bus cycle then reset to 0.

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

486 Freescale Semiconductor

Note: in Figure 16-31,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock

Figure 16-31. The TCNT cycle diagram under TCRE=1 condition

16.4.3.1 OC Channel Initialization

Internal register whose output drives OCx can be programmed before timer drives OCx. The desired state

can be programmed to this Internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN

bits set to one. Setting OCPDx to zero allows Interal register to drive the programmed state to OCx. This

allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set

to zero.

16.4.4 Pulse Accumulator

The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes:

Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI.

Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the

mode of operation.

The minimum pulse width for the PAI input is greater than two bus clocks.

16.4.5 Event Counter Mode

Clearing the PAMOD bit conﬁgures the PACNT for event counter operation. An active edge on the IOC7

pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to

increment the count.

NOTE

The PACNT input and timer channel 7 use the same pin IOC7. To use the

IOC7, disconnect it from the output logic by clearing the channel 7 output

mode and output level bits, OM7 and OL7. Also clear the channel 7 output

compare 7 mask bit, OC7M7.

The Pulse Accumulator counter register reﬂect the number of active input edges on the PACNT input pin

since the last reset.

The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator

overﬂow interrupt enable bit, PAOVI, enables the PAOVF ﬂag to generate interrupt requests.

TC7 01----- TC7-1 TC7 0

TC7 event TC7 event

prescaler

counter 1 bus

clock

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual Rev. 1.10

Freescale Semiconductor 487

NOTE

The pulse accumulator counter can operate in event counter mode even

when the timer enable bit, TEN, is clear.

16.4.6 Gated Time Accumulation Mode

Setting the PAMOD bit conﬁgures the pulse accumulator for gated time accumulation operation. An active

level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE

bit selects low levels or high levels to enable the divided-by-64 clock.

The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF ﬂag to

generate interrupt requests.

The pulse accumulator counter register reﬂect the number of pulses from the divided-by-64 clock since the

last reset.

NOTE

The timer prescaler generates the divided-by-64 clock. If the timer is not

active, there is no divided-by-64 clock.

16.5 Resets

The reset state of each individual bit is listed within Section 16.3, “Memory Map and Register Deﬁnition”

which details the registers and their bit ﬁelds.

16.6 Interrupts

This section describes interrupts originated by the TIM16B8CV2 block. Table 16-25 lists the interrupts

generated by the TIM16B8CV2 to communicate with the MCU.

The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers

are chip dependent.

Table 16-25. TIM16B8CV1 Interrupts

Interrupt Offset1

1Chip Dependent.

Vector1Priority1Source Description

C[7:0]F — — — Timer Channel 7–0 Active high timer channel interrupts 7–0

PAOVI — — — Pulse Accumulator

Input Active high pulse accumulator input interrupt

PAOVF — — — Pulse Accumulator

Overﬂow Pulse accumulator overﬂow interrupt

TOF — — — Timer Overﬂow Timer Overﬂow interrupt

Timer Module (TIM16B8CV2)

S12XS Family Reference Manual, Rev. 1.10

488 Freescale Semiconductor

16.6.1 Channel [7:0] Interrupt (C[7:0]F)

This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be

serviced by the system controller.

16.6.2 Pulse Accumulator Input Interrupt (PAOVI)

This active high output will be asserted by the module to request a timer pulse accumulator input interrupt

to be serviced by the system controller.

16.6.3 Pulse Accumulator Overﬂow Interrupt (PAOVF)

This active high output will be asserted by the module to request a timer pulse accumulator overﬂow

interrupt to be serviced by the system controller.

16.6.4 Timer Overﬂow Interrupt (TOF)

This active high output will be asserted by the module to request a timer overﬂow interrupt to be serviced

by the system controller.

S12XS Family Reference Manual, Rev. 1.10

Freescale Semiconductor 489

Chapter 17

Voltage Regulator (S12VREGL3V3V1)

Table 17-1. Revision History Table

17.1 Introduction

Module VREG_3V3 is a tri output voltage regulator that provides two separate 1.84V (typical) supplies

differing in the amount of current that can be sourced and a 2.82V (typical) supply. The regulator input

voltage range is from 3.3V up to 5V (typical).

17.1.1 Features

Module VREG_3V3 includes these distinctive features:

• Three parallel, linear voltage regulators with bandgap reference

• Low-voltage detect (LVD) with low-voltage interrupt (LVI)

• Power-on reset (POR)

• Low-voltage reset (LVR)

• High Temperature Detect (HTD) with High Temperature Interrupt (HTI)

• Autonomous periodical interrupt (API)

17.1.2 Modes of Operation

There are three modes VREG_3V3 can operate in:

1. Full performance mode (FPM) (MCU is not in stop mode)

The regulator is active, providing the nominal supply voltages with full current sourcing capability.

Features LVD (low-voltage detect), LVR (low-voltage reset), and POR (power-on reset) and HTD

(High Temperature Detect) are available. The API is available.

2. Reduced power mode (RPM) (MCU is in stop mode)

The purpose is to reduce power consumption of the device. The output voltage may degrade to a

lower value than in full performance mode, additionally the current sourcing capability is

substantially reduced. Only the POR is available in this mode, LVD, LVR and HTD are disabled.

The API is available.

Rev. No.

(Item No.) Date

(Submitted By) Sections

Affected Substantial Change(s)

V01.02 09 Sep 2005 Updates for API external access and LVR ﬂags.

V01.03 23 Sep 2005 VAE reset value is 1.

V01.04 08 Jun 2007 Added temperature sensor to customer information

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3. Shutdown mode

Controlled by VREGEN (see device level speciﬁcation for connectivity of VREGEN).

This mode is characterized by minimum power consumption. The regulator outputs are in a high-

impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API

internal RC oscillator clock is not available.

This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the

VREG_3V3 to use external supplies.

17.1.3 Block Diagram

Figure 17-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core

REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output

voltages.

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Figure 17-1. VREG_3V3 Block Diagram

LVR

LVD POR

VDDR

VDD

LVI

POR

LVR

CTRL

VSS

VDDPLL

VSSPLL

VREGEN

REG

VDDA

REG: Regulator Core

CTRL: Regulator Control

LVD: Low Voltage Detect

LVR: Low Voltage Reset

POR: Power-on Reset

HTD: High Temperature Detect

HTI

HTD

API

API: Auto. Periodical Interrupt

API

Rate

Select

Bus Clock

REG2

REG1

REG3

VDDF

VSSA

VDDX

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17.2 External Signal Description

Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply

voltages, most signals are power supply signals connected to pads.

Table 17-2 shows all signals of VREG_3V3 associated with pins.

NOTE

Check device level speciﬁcation for connectivity of the signals.

17.2.1 VDDR — Regulator Power Input Pins

Signal VDDR is the power input of VREG_3V3. All currents sourced into the regulator loads ﬂow through

this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR

(if VSSR is not available VSS) can smooth ripple on VDDR.

For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without VREGEN pin.

17.2.2 VDDA, VSSA — Regulator Reference Supply Pins

Signals VDDA/VSSA,which are supposed to be relatively quiet, are used to supply the analog parts of the

regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling

capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of

this supply.

17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins

Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic.

These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).

Table 17-2. Signal Properties

Name Function Reset State Pull Up

VDDR Power input (positive supply) — —

VDDA Quiet input (positive supply) — —

VSSA Quiet input (ground) — —

VDDX Power input (positive supply) — —

VDD Primary output (positive supply) — —

VSS Primary output (ground) — —

VDDF Secondary output (positive supply) — —

VDDPLL Tertiary output (positive supply) — —

VSSPLL Tertiary output (ground) — —

VREGEN (optional) Optional Regulator Enable — —

VREG_API

(optional) VREG Autonomous Periodical

Interrupt output ——

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In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator.

17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins

Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM

logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R

ceramic).

In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator.

17.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins

Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for

the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors

(100 nF...220 nF, X7R ceramic).

In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.

17.2.6 VDDX — Power Input Pin

Signals VDDX/VSS are monitored by VREG_3V3 with the LVR feature.

17.2.7 VREGEN — Optional Regulator Enable Pin

This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL

must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high,

the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.

For the connectivity of VREGEN, see device speciﬁcation.

NOTE

Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa

is not supported while MCU is powered.

17.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin

This pin provides the signal selected via APIEA if system is set accordingly. See 17.3.2.3, “Autonomous

Periodical Interrupt Control Register (VREGAPICL) and 17.4.8, “Autonomous Periodical Interrupt (API)

for details.

For the connectivity of VREG_API, see device speciﬁcation.

17.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in VREG_3V3.

If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within

it’s memory slice. See device level speciﬁcation for details.

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17.3.1 Module Memory Map

A summary of the registers associated with the VREG_3V3 sub-block is shown in Table 17-3. Detailed

descriptions of the registers and bits are given in the subsections that follow

Address Name Bit 7 6 54321Bit 0

0x02F0 VREGHTCL R0 0 VSEL VAE HTEN HTDS HTIE HTIF

0x02F1 VREGCTRL R00000LVDS

LVIE LVIF

0x02F2 VREGAPIC

LRAPICLK 00

APIFES APIEA APIFE APIE APIF

0x02F3 VREGAPIT

RRAPITR5 APITR4 APITR3 APITR2 APITR1 APITR0 00

0x02F4 VREGAPIR

HRAPIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8

0x02F5 VREGAPIR

LRAPIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0

0x02F6 Reserved

06 R00000000

0x02F7 VREGHTTR RHTOEN 000

HTTR3 HTTR2 HTTR1 HTTR0

Table 17-3. Register Summary

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17.3.2 Register Descriptions

This section describes all the VREG_3V3 registers and their individual bits.

17.3.2.1 High Temperature Control Register (VREGHTCL)

The VREGHTCL register allows to conﬁgure the VREG temperature sense features.

0x02F0

76543210

R0 0 VSEL VAE HTEN HTDS HTIE HTIF

Reset 0 0 0 10000

= Unimplemented or Reserved

Table 17-4. VREGHTCL Field Descriptions

Field Description

7, 6

Reserved These reserved bits are used for test purposes and writable only in special modes.

They must remain clear for correct temperature sensor operation.

VSEL Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e.

multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabledby bit VAE.

See device level speciﬁcation for connectivity.

0 An internal temperature proportional voltage VHT can be accessed internally if VAE is set.

1 Bandgap reference voltage VBG can be accessed internally if VAE is set.

VAE Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.

multiplexed to an internal Analog to Digital Converter channel). See device level speciﬁcation for connectivity.

0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog

to Digital Converter channel).

1 Voltage selected by VSEL can be accessed internally.

HTEN High Temperature Enable Bit — If set the temperature sense is enabled.

0 The temperature sense is disabled.

1 The temperature sense is enabled.

HTDS High Temperature Detect Status Bit —

This read-only status bit reﬂects the temperature status. Writes have no effect.

0 Temperature TDIE is below level THTID or RPM or Shutdown Mode.

1 Temperature TDIE is above level THTIA and FPM.

HTIE High Temperature Interrupt Enable Bit

0 Interrupt request is disabled.

1 Interrupt will be requested whenever HTIF is set.

HTIF High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag

HTIF is set to 1 when HTDS status bit changes. This ﬂag can only be cleared by writing a 1.}Writing a 0 has no

effect. If enabled (HTIE=1), HTIF causes an interrupt request.

0 No change in HTDS bit.

1 HTDS bit has changed.

Note: On entering the reduced power mode the HTIF is not cleared by the VREG.

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17.3.2.2 Control Register (VREGCTRL)

The VREGCTRL register allows the conﬁguration of the VREG_3V3 low-voltage detect features.

0x02F1

76543210

R00000LVDS

LVIE LVIF

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 17-2. Control Register (VREGCTRL)

Table 17-5. VREGCTRL Field Descriptions

Field Description

LVDS Low-Voltage Detect Status Bit — This read-only status bit reﬂects the input voltage. Writes have no effect.

0 Input voltage VDDA is above level VLVID or RPM or shutdown mode.

1 Input voltage VDDA is below level VLVIA and FPM.

LVIE Low-Voltage Interrupt Enable Bit

0 Interrupt request is disabled.

1 Interrupt will be requested whenever LVIF is set.

LVIF Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This ﬂag can only be cleared by

writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.

0 No change in LVDS bit.

1 LVDS bit has changed.

Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.

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17.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL)

The VREGAPICL register allows the conﬁguration of the VREG_3V3 autonomous periodical interrupt

features.

0x02F2

76543210

RAPICLK 00

APIES APIEA APIFE APIE APIF

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 17-3. Autonomous Periodical Interrupt Control Register (VREGAPICL)

Table 17-6. VREGAPICL Field Descriptions

Field Description

APICLK Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if

APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.

0 Autonomous periodical interrupt clock used as source.

1 Bus clock used as source.

APIES Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin.If set, at the

external pin a clock is visible with 2 times the selected API Period (Table 17-10). If not set, at the external pin will

be a high pulse at the end of every selected period with the size of half of the min period (Table 17-10). See

device level speciﬁcation for connectivity.

0 At the external periodic high pulses are visible, if APIEA and APIFE is set.

1 At the external pin a clock is visible, if APIEA and APIFE is set.

APIEA Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES

can be accessed externally. See device level speciﬁcation for connectivity.

0 Waveform selected by APIES can not be accessed externally.

1 Waveform selected by APIES can be accessed externally, if APIFE is set.

APIFE Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer

when set.

0 Autonomous periodical interrupt is disabled.

1 Autonomous periodical interrupt is enabled and timer starts running.

APIE Autonomous Periodical Interrupt Enable Bit

0 API interrupt request is disabled.

1 API interrupt will be requested whenever APIF is set.

APIF Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API conﬁgured time has elapsed.

This ﬂag can only be cleared by writing a 1 to it. Clearing of the ﬂag has precedence over setting.

Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.

0 API timeout has not yet occurred.

1 API timeout has occurred.

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17.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

The VREGAPITR register allows to trim the API timeout period.

0x02F3

76543210

RAPITR5 APITR4 APITR3 APITR2 APITR1 APITR0 00

Reset 01010101010100

1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.

= Unimplemented or Reserved

Figure 17-4. Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

Table 17-7. VREGAPITR Field Descriptions

Field Description

7–2

APITR[5:0] Autonomous Periodical Interrupt Period Trimming Bits — See Table 17-8 for trimming effects.

Table 17-8. Trimming Effect of APIT

Bit Trimming Effect

APITR[5] Increases period

APITR[4] Decreases period less than APITR[5] increased it

APITR[3] Decreases period less than APITR[4]

APITR[2] Decreases period less than APITR[3]

APITR[1] Decreases period less than APITR[2]

APITR[0] Decreases period less than APITR[1]

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17.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register

(VREGAPIRH / VREGAPIRL)

The VREGAPIRH and VREGAPIRL register allows the conﬁguration of the VREG_3V3 autonomous

periodical interrupt rate.

0x02F4

76543210

RAPIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 17-5. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)

0x02F5

76543210

RAPIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0

Reset 0 0 0 00000

Figure 17-6. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)

Table 17-9. VREGAPIRH / VREGAPIRL Field Descriptions

Field Description

15-0

APIR[15:0] Autonomous Periodical Interrupt Rate Bits — These bits deﬁne the timeout period of the API. See Table 17-

10 for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of

VREGAPICL register.

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The period can be calculated as follows depending of APICLK:

Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period

Table 17-10. Selectable Autonomous Periodical Interrupt Periods

APICLK APIR[15:0] Selected Period

0 0000 0.2 ms1

1When trimmed within speciﬁed accuracy. See electrical speciﬁcations for details.

0 0001 0.4 ms1

0 0002 0.6 ms1

0 0003 0.8 ms1

0 0004 1.0 ms1

0 0005 1.2 ms1

0 ..... .....

0 FFFD 13106.8 ms1

0 FFFE 13107.0 ms1

0 FFFF 13107.2 ms1

1 0000 2 * bus clock period

1 0001 4 * bus clock period

1 0002 6 * bus clock period

1 0003 8 * bus clock period

1 0004 10 * bus clock period

1 0005 12 * bus clock period

1 ..... .....

1 FFFD 131068 * bus clock period

1 FFFE 131070 * bus clock period

1 FFFF 131072 * bus clock period

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17.3.2.6 Reserved 06

The Reserved 06 is reserved for test purposes.

17.3.2.7 High Temperature Trimming Register (VREGHTTR)

The VREGHTTR register allows to trim the VREG temperature sense.

Fiption

Table 17-12. Trimming Effect

0x02F6

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 17-7. Reserved 06

0x02F7

76543210

RHTOEN 000

HTTR3 HTTR2 HTTR1 HTTR0

Reset 0 0 0 0 01010101

1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.

= Unimplemented or Reserved

Figure 17-8. VREGHTTR

Table 17-11. VREGHTTR ﬁeld descriptions

Field Description

HTOEN High Temperature Offset Enable Bit — If set the temperature sense offset is enabled

0 The temperature sense offset is disabled

1 The temperature sense offset is enabled

3–0

HTTR[3:0] High Temperature Trimming Bits — See Table 23-16 for trimming effects.

Bit Trimming Effect

HTTR[3] Increases VHT twice of HTTR[2]

HTTR[2] Increases VHT twice of HTTR[1]

HTTR[1] Increases VHT twice of HTTR[0]

HTTR[0] Increases VHT (to compensate Temperature Offset)

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17.4 Functional Description

17.4.1 General

Module VREG_3V3 is a voltage regulator, as depicted in Figure 17-1. The regulator functional elements

are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on

reset module (POR), and a low-voltage reset module (LVR)and a high temperature sensor (HTD).

17.4.2 Regulator Core (REG)

Respectively its regulator core has three parallel, independent regulation loops (REG1,REG2 and REG3).

REG1 and REG3 differ only in the amount of current that can be delivered.

The regulators are linear regulator with a bandgap reference when operated in Full Performance Mode.

They act as a voltage clamp in Reduced Power Mode. All load currents ﬂow from input VDDR to VSS or

VSSPLL. The reference circuits are supplied by VDDA and VSSA.

17.4.2.1 Full Performance Mode

In Full Performance Mode, the output voltage is compared with a reference voltage by an operational

ampliﬁer. The ampliﬁed input voltage difference drives the gate of an output transistor.

17.4.2.2 Reduced Power Mode

In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to

reduce power consumption. Mode switching from reduced power to full performance requires a transition

time of tvup, if the voltage regulator is enabled.

17.4.3 Low-Voltage Detect (LVD)

Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input

voltage (VDDA–VSSA) and continuously updates the status ﬂag LVDS. Interrupt ﬂag LVIF is set whenever

status ﬂag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode

or Shutdown Mode.

17.4.4 Power-On Reset (POR)

This functional block monitors VDD. If VDD is below VPORD, POR is asserted; if VDD exceeds VPORD,

the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-

on sequence.

17.4.5 Low-Voltage Reset (LVR)

Block LVR monitors the supplies VDD, VDDX and VDDF. If one (or more) drops below it’s

corresponding assertion level, signal LVR asserts; if all VDD,VDDX and VDDF supplies are above their

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corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full

Performance Mode.

17.4.6 HTD - High Temperature Detect

Subblock HTD is responsible for generating the high temperature interrupt (HTI). HTD monitors the die

temperature TDIE and continuously updates the status ﬂag HTDS.

Interrupt ﬂag HTIF is set whenever status ﬂag HTDS changes its value.

The HTD is available in FPM and is inactive in Reduced Power Mode and Shutdown Mode.

The HT Trimming bits HTTR[3:0] can be set so that the temperature offset is zero, if accurate temperature

measurement is desired.

See Table 23-16 for the trimming effect of APITR.

17.4.7 Regulator Control (CTRL)

This part contains the register block of VREG_3V3 and further digital functionality needed to control the

operating modes. CTRL also represents the interface to the digital core logic.

17.4.8 Autonomous Periodical Interrupt (API)

Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable

the timer, the bit APIFE needs to be set.

The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation

will freeze when MCU clock source is selected and bus clock is turned off. See CRG speciﬁcation for

details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is

not set.

The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is

cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When

the conﬁgured time has elapsed, the ﬂag APIF is set. An interrupt, indicated by ﬂag APIF = 1, is triggered

if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.

The procedure to change APICLK or APIR[15:0] is ﬁrst to clear APIFE, then write to APICLK or

APIR[15:0], and afterwards set APIFE.

The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency

is desired.

See Table 17-8 for the trimming effect of APITR.

NOTE

The ﬁrst period after enabling the counter by APIFE might be reduced by

API start up delay tsdel. The API internal RC oscillator clock is not available

if VREG_3V3 is in Shutdown Mode.

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It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE

and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If

APIES is set, then at the external pin a clock is visible with 2 times the selected API Period (Table 17-10).

If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the

size of half of the min period (Table 17-10). See device level speciﬁcation for connectivity.

17.4.9 Resets

This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and

signals are provided in Section 17.3, “Memory Map and Register Deﬁnition”. Possible reset sources are

listed in Table 17-13.

17.4.10 Description of Reset Operation

17.4.10.1 Power-On Reset (POR)

During chip power-up the digital core may not work if its supply voltage VDD is below the POR

deassertion level (VPORD). Therefore, signal POR, which forces the other blocks of the device into reset,

is kept high until VDD exceeds VPORD. The MCU will run the start-up sequence after POR deassertion.

The power-on reset is active in all operation modes of VREG_3V3.

17.4.10.2 Low-Voltage Reset (LVR)

For details on low-voltage reset, see Section 17.4.5, “Low-Voltage Reset (LVR)”.

17.4.11 Interrupts

This section describes all interrupts originated by VREG_3V3.

The interrupt vectors requested by VREG_3V3 are listed in Table 17-14. Vector addresses and interrupt

priorities are deﬁned at MCU level.

Table 17-13. Reset Sources

Reset Source Local Enable

Power-on reset Always active

Low-voltage reset Available only in Full Performance Mode

Table 17-14. Interrupt Vectors

Interrupt Source Local Enable

Low-voltage interrupt (LVI) LVIE = 1; available only in Full Performance

Mode

High Temperature Interrupt (HTI) HTIE=1;

available only in Full Performance Mode

Autonomous periodical interrupt (API) APIE = 1

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17.4.11.1 Low-Voltage Interrupt (LVI)

In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the

status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID.An

interrupt, indicated by ﬂag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable

bit LVIE = 1.

NOTE

On entering the Reduced Power Mode, the LVIF is not cleared by the

VREG_3V3.

17.4.11.2 HTI - High Temperature Interrupt

In FPM VREG monitors the die temperature TDIE. Whenever TDIE exceeds level THTIA the status bit

HTDS is set to 1. Vice versa, HTDS is reset to 0 when TDIE get below level THTID. An interrupt, indicated

by ﬂag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.

NOTE

On entering the Reduced Power Mode the HTIF is not cleared by the VREG.

17.4.11.3 Autonomous Periodical Interrupt (API)

As soon as the conﬁgured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated

by ﬂag APIF = 1, is triggered if interrupt enable bit APIE = 1.

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Chapter 18

256 KByte Flash Module (S12XFTMR256K1V1)

18.1 Introduction

The FTMR256K1 module implements the following:

• 256 Kbytes of P-Flash (Program Flash) memory

• 8 Kbytes of D-Flash (Data Flash) memory

The Flash memory is ideal for single-supply applications allowing for ﬁeld reprogramming without

requiring external high voltage sources for program or erase operations. The Flash module includes a

memory controller that executes commands to modify Flash memory contents. The user interface to the

memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is

written to with the command, global address, data, and any required command parameters. The memory

controller must complete the execution of a command before the FCCOB register can be written to with a

new command.

Table 18-1. Revision History

Revision

Number Revision

Date Sections

Affected Description of Changes

V01.04 03 Jan 2008 - Cosmetic changes

V01.05 19 Dec 2008 18.1/18-507

18.4.2.4/18-542

18.4.2.6/18-544

18.4.2.11/18-54

- Clarify single bit fault correction for P-Flash phrase

- Add statement concerning code runaway when executing Read Once,

Program Once, and Verify Backdoor Access Key commands from Flash block

containing associated ﬁelds

- Relate Key 0 to associated Backdoor Comparison Key address

- Change “power down reset” to “reset” in Section 18.4.2.11

V01.06 25 Sep 2009

18.3.2/18-514

18.3.2.1/18-516

18.4.1.2/18-536

18.6/18-556

The following changes were made to clarify module behavior related to Flash

- Add caution concerning register writes while command is active

- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear

- Add caution concerning register writes while command is active

- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during

reset sequence

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CAUTION

A Flash word or phrase must be in the erased state before being

programmed. Cumulative programming of bits within a Flash word or

phrase is not allowed.

The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus

cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased

bit reads 1 and a programmed bit reads 0.

It is not possible to read from a Flash block while any command is executing on that speciﬁc Flash block.

It is possible to read from a Flash block while a command is executing on a different Flash block.

Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve

single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that

programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read

by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.

18.1.1 Glossary

Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including

program and erase) on the Flash memory.

D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data.

D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.

The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.

NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters

required for Flash command execution.

Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight

ECC bits for single bit fault correction and double bit fault detection within the phrase.

P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.

P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.

Each P-Flash sector contains 1024 bytes.

Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device

ID, Version ID, and the Program Once ﬁeld. The Program IFR is visible in the global memory map by

setting the PGMIFRON bit in the MMCCTL1 register.

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18.1.2 Features

18.1.2.1 P-Flash Features

• 256 Kbytes of P-Flash memory composed of one 256 Kbyte Flash block divided into 256 sectors

of 1024 bytes

• Single bit fault correction and double bit fault detection within a 64-bit phrase during read

operations

• Automated program and erase algorithm with verify and generation of ECC parity bits

• Fast sector erase and phrase program operation

• Flexible protection scheme to prevent accidental program or erase of P-Flash memory

18.1.2.2 D-Flash Features

• 8 Kbytes of D-Flash memory composed of one 8 Kbyte Flash block divided into 32 sectors of 256

bytes

• Single bit fault correction and double bit fault detection within a word during read operations

• Automated program and erase algorithm with verify and generation of ECC parity bits

• Fast sector erase and word program operation

• Protection scheme to prevent accidental program or erase of D-Flash memory

• Ability to program up to four words in a burst sequence

18.1.2.3 Other Flash Module Features

• No external high-voltage power supply required for Flash memory program and erase operations

• Interrupt generation on Flash command completion and Flash error detection

• Security mechanism to prevent unauthorized access to the Flash memory

18.1.3 Block Diagram

The block diagram of the Flash module is shown in Figure 18-1.

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Figure 18-1. FTMR256K1 Block Diagram

18.2 External Signal Description

The Flash module contains no signals that connect off-chip.

18.3 Memory Map and Registers

This section describes the memory map and registers for the Flash module. Read data from unimplemented

memory space in the Flash module is undeﬁned. Write access to unimplemented or reserved memory space

in the Flash module will be ignored by the Flash module.

Oscillator

Clock

Divider

Clock (XTAL)

Command

Interrupt

Request

FCLK

Protection

Security

Registers

Flash

Interface

P-Flash

32Kx72

sector 0

sector 1

sector 127

sector 0

sector 1

sector 127

16bit

internal

bus 16Kx72 16Kx72

Error

Interrupt

Request

CPU

Memory

Controller

D-Flash

4Kx22

sector 0

sector 1

sector 31

Scratch RAM

384x16

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18.3.1 Module Memory Map

The S12X architecture places the P-Flash memory between global addresses 0x7C_0000 and 0x7F_FFFF

as shown in Table 18-2. The P-Flash memory map is shown in Figure 18-2.

The FPROT register, described in Section 18.3.2.9, can be set to protect regions in the Flash memory from

accidental program or erase. Three separate memory regions, one growing upward from global address

0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address

0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash

memory, can be activated for protection. The Flash memory addresses covered by these protectable regions

are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader

code since it covers the vector space. Default protection settings as well as security information that allows

the MCU to restrict access to the Flash module are stored in the Flash conﬁguration ﬁeld as described in

Table 18-3.

Table 18-2. P-Flash Memory Addressing

Global Address Size

(Bytes) Description

0x7C_0000 – 0x7F_FFFF 256 K P-Flash Block 0

Contains Flash Conﬁguration Field

(see Table 18-3)

Table 18-3. Flash Conﬁguration Field1

1Older versions may have swapped protection byte addresses

Global Address Size

(Bytes) Description

0x7F_FF00 – 0x7F_FF07 8 Backdoor Comparison Key

Refer to Section 18.4.2.11, “Verify Backdoor Access Key Command,” and

Section 18.5.1, “Unsecuring the MCU using Backdoor Key Access”

0x7F_FF08 – 0x7F_FF0B2

20x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in

the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF.

4 Reserved

0x7F_FF0C21P-Flash Protection byte.

Refer to Section 18.3.2.9, “P-Flash Protection Register (FPROT)”

0x7F_FF0D21D-Flash Protection byte.

Refer to Section 18.3.2.10, “D-Flash Protection Register (DFPROT)”

0x7F_FF0E21Flash Nonvolatile byte

Refer to Section 18.3.2.15, “Flash Option Register (FOPT)”

0x7F_FF0F21Flash Security byte

Refer to Section 18.3.2.2, “Flash Security Register (FSEC)”

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Figure 18-2. P-Flash Memory Map

Flash Conﬁguration Field

0x7F_C000

Flash Protected/Unprotected Lower Region

1, 2, 4, 8 Kbytes

0x7F_8000

0x7F_9000

0x7F_8400

0x7F_8800

0x7F_A000

P-Flash END = 0x7F_FFFF

0x7F_F800

0x7F_F000

0x7F_E000 Flash Protected/Unprotected Higher Region

2, 4, 8, 16 Kbytes

Flash Protected/Unprotected Region

8 Kbytes (up to 29 Kbytes)

16 bytes (0x7F_FF00 - 0x7F_FF0F)

Flash Protected/Unprotected Region

224 Kbytes

P-Flash START = 0x7C_0000

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Table 18-4. Program IFR Fields

Global Address

(PGMIFRON) Size

(Bytes) Field Description

0x40_0000 – 0x40_0007 8 Device ID

0x40_0008 – 0x40_00E7 224 Reserved

0x40_00E8 – 0x40_00E9 2 Version ID

0x40_00EA – 0x40_00FF 22 Reserved

0x40_0100 – 0x40_013F 64 Program Once Field

Refer to Section 18.4.2.6, “Program Once Command”

0x40_0140 – 0x40_01FF 192 Reserved

Table 18-5. D-Flash and Memory Controller Resource Fields

Global Address Size

(Bytes) Description

0x10_0000 – 0x10_1FFF 8,192 D-Flash Memory

0x10_2000 – 0x11_FFFF 122,880 Reserved

0x12_0000 – 0x12_007F 128 D-Flash Nonvolatile Information Register (DFIFRON1 = 1)

1MMCCTL1 register bit

0x12_0080 – 0x12_0FFF 3,968 Reserved

0x12_1000 – 0x12_1FFF 4,096 Reserved

0x12_2000 – 0x12_3CFF 7,242 Reserved

0x12_3D00 – 0x12_3FFF 768 Memory Controller Scratch RAM (MGRAMON1 = 1)

0x12_4000 – 0x12_E7FF 43,008 Reserved

0x12_E800 – 0x12_FFFF 6,144 Reserved

0x13_0000 – 0x13_FFFF 65,536 Reserved

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Figure 18-3. D-Flash and Memory Controller Resource Memory Map

18.3.2 Register Descriptions

The Flash module contains a set of 20 control and status registers located between Flash module base +

0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 18-4 with detailed

descriptions in the following subsections.

CAUTION

Writes to any Flash register must be avoided while a Flash command is

active (CCIF=0) to prevent corruption of Flash register contents and

Memory Controller behavior.

Address

& Name 76543210

0x0000

FCLKDIV R FDIVLD FDIV6 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0

0x0001

FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0

Figure 18-4. FTMR256K1 Register Summary

0x12_FFFF

0x12_4000

0x12_1000

Memory Controller Scratch RAM (MGRAMON)

768 bytes

D-Flash Nonvolatile Information Register (DFIFRON)

128 bytes

D-Flash Memory

8 Kbytes

D-Flash START = 0x10_0000

0x12_0000

0x12_2000

0x12_E800

D-Flash END = 0x10_1FFF

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0x0002

FCCOBIX R0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0

0x0003

FECCRIX R0 0 0 0 0 ECCRIX2 ECCRIX1 ECCRIX0

0x0004

FCNFG RCCIE 00

IGNSF 00

FDFD FSFD

0x0005

FERCNFG R0DFDIE SFDIE

0x0006

FSTAT RCCIF 0ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0

0x0007

FERSTAT R0 0 0 0 0 0 DFDIF SFDIF

0x0008

FPROT RFPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0

0x0009

DFPROT RDPOPEN 00

DPS4 DPS3 DPS2 DPS1 DPS0

0x000A

FCCOBHI RCCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8

0x000B

FCCOBLO RCCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0

0x000C

FRSV0 R00000000

0x000D

FRSV1 R00000000

0x000E

FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8

0x000F

FECCRLO R ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0

Address

& Name 76543210

Figure 18-4. FTMR256K1 Register Summary (continued)

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18.3.2.1 Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms.

All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.

0x0010

FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0

0x0011

FRSV2 R00000000

0x0012

FRSV3 R00000000

0x0013

FRSV4 R00000000

= Unimplemented or Reserved

Offset Module Base + 0x0000

76543210

R FDIVLD FDIV[6:0]

Reset 00000000

= Unimplemented or Reserved

Figure 18-5. Flash Clock Divider Register (FCLKDIV)

Table 18-6. FCLKDIV Field Descriptions

Field Description

FDIVLD Clock Divider Loaded

0 FCLKDIV register has not been written

1 FCLKDIV register has been written since the last reset

6–0

FDIV[6:0] Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash

clock,FCLK,witha target frequency of 1MHzforusebytheFlash module to control timedevents during program

and erase algorithms. Table 18-7 shows recommended values for FDIV[6:0] based on OSCCLK frequency.

Please refer to Section 18.4.1, “Flash Command Operations,” for more information.

Address

& Name 76543210

Figure 18-4. FTMR256K1 Register Summary (continued)

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CAUTION

The FCLKDIV register should never be written while a Flash command is

executing (CCIF=0). The FCLKDIV register is writable during the Flash

reset sequence even though CCIF is clear.

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Table 18-7. FDIV vs OSCCLK Frequency

OSCCLK Frequency

(MHz) FDIV[6:0]

OSCCLK Frequency

(MHz) FDIV[6:0]

MIN1

1FDIV shown generates an FCLK frequency of >0.8 MHz

MAX2

2FDIV shown generates an FCLK frequency of 1.05 MHz

MIN1MAX2

1.60 2.10 0x01 33.60 34.65 0x20

2.40 3.15 0x02 34.65 35.70 0x21

3.20 4.20 0x03 35.70 36.75 0x22

4.20 5.25 0x04 36.75 37.80 0x23

5.25 6.30 0x05 37.80 38.85 0x24

6.30 7.35 0x06 38.85 39.90 0x25

7.35 8.40 0x07 39.90 40.95 0x26

8.40 9.45 0x08 40.95 42.00 0x27

9.45 10.50 0x09 42.00 43.05 0x28

10.50 11.55 0x0A 43.05 44.10 0x29

11.55 12.60 0x0B 44.10 45.15 0x2A

12.60 13.65 0x0C 45.15 46.20 0x2B

13.65 14.70 0x0D 46.20 47.25 0x2C

14.70 15.75 0x0E 47.25 48.30 0x2D

15.75 16.80 0x0F 48.30 49.35 0x2E

16.80 17.85 0x10 49.35 50.40 0x2F

17.85 18.90 0x11

18.90 19.95 0x12

19.95 21.00 0x13

21.00 22.05 0x14

22.05 23.10 0x15

23.10 24.15 0x16

24.15 25.20 0x17

25.20 26.25 0x18

26.25 27.30 0x19

27.30 28.35 0x1A

28.35 29.40 0x1B

29.40 30.45 0x1C

30.45 31.50 0x1D

31.50 32.55 0x1E

32.55 33.60 0x1F

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18.3.2.2 Flash Security Register (FSEC)

The FSEC register holds all bits associated with the security of the MCU and Flash module.

All bits in the FSEC register are readable but not writable.

During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the

Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 18-3) as

indicated by reset condition F in Figure 18-6. If a double bit fault is detected while reading the P-Flash

phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be

set to leave the Flash module in a secured state with backdoor key access disabled.

Offset Module Base + 0x0001

76543210

R KEYEN[1:0] RNV[5:2] SEC[1:0]

Reset F F FFFFFF

= Unimplemented or Reserved

Figure 18-6. Flash Security Register (FSEC)

Table 18-8. FSEC Field Descriptions

Field Description

7–6

KEYEN[1:0] Backdoor Key Security Enable Bits — The KEYEN[1:0] bits deﬁne the enabling of backdoor key access to the

Flash module as shown in Table 18-9.

5–2

RNV[5:2} Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.

1–0

SEC[1:0] Flash Security Bits — The SEC[1:0] bits deﬁne the security state of the MCU as shown in Table 18-10. If the

Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.

Table 18-9. Flash KEYEN States

KEYEN[1:0] Status of Backdoor Key Access

00 DISABLED

01 DISABLED1

1Preferred KEYEN state to disable backdoor key access.

10 ENABLED

11 DISABLED

Table 18-10. Flash Security States

SEC[1:0] Status of Security

00 SECURED

01 SECURED1

10 UNSECURED

11 SECURED

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The security function in the Flash module is described in Section 18.5.

18.3.2.3 Flash CCOB Index Register (FCCOBIX)

The FCCOBIX register is used to index the FCCOB register for Flash memory operations.

CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.

18.3.2.4 Flash ECCR Index Register (FECCRIX)

The FECCRIX register is used to index the FECCR register for ECC fault reporting.

ECCRIX bits are readable and writable while remaining bits read 0 and are not writable.

1Preferred SEC state to set MCU to secured state.

Offset Module Base + 0x0002

76543210

R00000 CCOBIX[2:0]

Reset 00000000

= Unimplemented or Reserved

Figure 18-7. FCCOB Index Register (FCCOBIX)

Table 18-11. FCCOBIX Field Descriptions

Field Description

2–0

CCOBIX[1:0] Common Command Register Index—TheCCOBIX bitsareused to selectwhich wordof the FCCOBregister

array is being read or written to. See Section 18.3.2.11, “Flash Common Command Object Register (FCCOB),”

for more details.

Offset Module Base + 0x0003

76543210

R00000 ECCRIX[2:0]

Reset 00000000

= Unimplemented or Reserved

Figure 18-8. FECCR Index Register (FECCRIX)

Table 18-12. FECCRIX Field Descriptions

Field Description

2-0

ECCRIX[2:0] ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is

being read. See Section 18.3.2.14, “Flash ECC Error Results Register (FECCR),” for more details.

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18.3.2.5 Flash Conﬁguration Register (FCNFG)

The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array

read access from the CPU or XGATE.

CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not

writable.

18.3.2.6 Flash Error Conﬁguration Register (FERCNFG)

The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.

Offset Module Base + 0x0004

76543210

RCCIE 00

IGNSF 00

FDFD FSFD

Reset 00000000

= Unimplemented or Reserved

Figure 18-9. Flash Conﬁguration Register (FCNFG)

Table 18-13. FCNFG Field Descriptions

Field Description

CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command

has completed.

0 Command complete interrupt disabled

1 An interrupt will be requested whenever the CCIF ﬂag in the FSTAT register is set (see Section 18.3.2.7)

IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see

Section 18.3.2.8).

0 All single bit faults detected during array reads are reported

1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be

generated

FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array

read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The

FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual

double bit fault is detected.

0 Flash array read operations will set the DFDIF ﬂag in the FERSTAT register only if a double bit fault is detected

1 Any Flash array read operation will force the DFDIF ﬂag in the FERSTAT register to be set (see

Section 18.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG

FSFD Force Single Bit Fault Detect —The FSFD bit allows the user to simulate a single bit fault during Flash array

read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The

FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single

bit fault is detected.

0 Flash array read operations will set the SFDIF ﬂag in the FERSTAT register only if a single bit fault is detected

1 Flash array read operation will force the SFDIF ﬂag in the FERSTAT register to be set (see Section 18.3.2.7)

and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see

Section 18.3.2.6)

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All assigned bits in the FERCNFG register are readable and writable.

18.3.2.7 Flash Status Register (FSTAT)

The FSTAT register reports the operational status of the Flash module.

CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable

but not writable, while remaining bits read 0 and are not writable.

Offset Module Base + 0x0005

76543210

R 0 DFDIE SFDIE

Reset 00000000

= Unimplemented or Reserved

Figure 18-10. Flash Error Conﬁguration Register (FERCNFG)

Table 18-14. FERCNFG Field Descriptions

Field Description

DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault

is detected during a Flash block read operation.

0 DFDIF interrupt disabled

1 An interrupt will be requested whenever the DFDIF ﬂag is set (see Section 18.3.2.8)

SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault

is detected during a Flash block read operation.

0 SFDIF interrupt disabled whenever the SFDIF ﬂag is set (see Section 18.3.2.8)

1 An interrupt will be requested whenever the SFDIF ﬂag is set (see Section 18.3.2.8)

Offset Module Base + 0x0006

76543210

RCCIF 0ACCERR FPVIOL MGBUSY RSVD MGSTAT[1:0]

Reset 1000000

1Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 18.6).

= Unimplemented or Reserved

Figure 18-11. Flash Status Register (FSTAT)

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18.3.2.8 Flash Error Status Register (FERSTAT)

The FERSTAT register reﬂects the error status of internal Flash operations.

All ﬂags in the FERSTAT register are readable and only writable to clear the ﬂag.

Table 18-15. FSTAT Field Descriptions

Field Description

CCIF Command Complete Interrupt Flag — The CCIF ﬂag indicates that a Flash command has completed. The

CCIF ﬂag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command

completion or command violation.

0 Flash command in progress

1 Flash command has completed

ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory

caused by either a violation of the command write sequence (see Section 18.4.1.2) or issuing an illegal Flash

command. While ACCERR is set, the CCIF ﬂag cannot be cleared to launch a command. The ACCERR bit is

cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.

0 No access error detected

1 Access error detected

FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an

address in a protected area of P-Flash or D-Flash memory during a command write sequence. The FPVIOL

bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL

is set, it is not possible to launch a command or start a command write sequence.

0 No protection violation detected

1 Protection violation detected

MGBUSY Memory Controller Busy Flag — The MGBUSY ﬂag reﬂects the active state of the Memory Controller.

0 Memory Controller is idle

1 Memory Controller is busy executing a Flash command (CCIF = 0)

RSVD Reserved Bit — This bit is reserved and always reads 0.

1–0

MGSTAT[1:0] Memory Controller Command Completion Status Flag — One or more MGSTAT ﬂag bits are set if an error

is detected during execution of a Flash command or during the Flash reset sequence. See Section 18.4.2,

“Flash Command Description,” and Section 18.6, “Initialization” for details.

Offset Module Base + 0x0007

76543210

R000000

DFDIF SFDIF

Reset 00000000

= Unimplemented or Reserved

Figure 18-12. Flash Error Status Register (FERSTAT)

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18.3.2.9 P-Flash Protection Register (FPROT)

The FPROT register defines which P-Flash sectors are protected against program and erase operations.

The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected

region can only be increased (see Section 18.3.2.9.1, “P-Flash Protection Restrictions,” and Table 18-21).

During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte

in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see Table 18-3)

as indicated by reset condition ‘F’ in Figure 18-13. To change the P-Flash protection that will be loaded

during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash

protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase

containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and

remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.

Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error

and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible

if any of the P-Flash sectors contained in the same P-Flash block are protected.

Table 18-16. FERSTAT Field Descriptions

Field Description

DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF ﬂag indicates that a double bit fault was

detectedinthestoredparity and data bits duringaFlasharray read operation or that a Flash arrayread operation

was attempted on a Flash block that was under a Flash command operation. The DFDIF ﬂag is cleared by writing

a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.

0 No double bit fault detected

1 Double bit fault detected or an invalid Flash array read operation attempted

SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF ﬂag

indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation

or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.

The SFDIF ﬂag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.

0 No single bit fault detected

1 Single bit fault detected and corrected or an invalid Flash array read operation attempted

Offset Module Base + 0x0008

76543210

RFPOPEN RNV6 FPHDIS FPHS[1:0] FPLDIS FPLS[1:0]

Reset F F FFFFFF

= Unimplemented or Reserved

Figure 18-13. Flash Protection Register (FPROT)

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Table 18-17. FPROT Field Descriptions

Field Description

FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or

erase operations as shown in Table 18-18 for the P-Flash block.

0 When FPOPEN is clear, the FPHDIS and FPLDIS bits deﬁne unprotected address ranges as speciﬁed by the

corresponding FPHS and FPLS bits

1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range speciﬁed by the

corresponding FPHS and FPLS bits

RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.

FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a

protected/unprotected area in a speciﬁc region of the P-Flash memory ending with global address 0x7F_FFFF.

0 Protection/Unprotection enabled

1 Protection/Unprotection disabled

4–3

FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area

in P-Flash memory as shown inTable 18-19. The FPHS bits can only be written to while the FPHDIS bit is set.

FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a

protected/unprotected area in a speciﬁc region of the P-Flash memory beginning with global address

0x7F_8000.

0 Protection/Unprotection enabled

1 Protection/Unprotection disabled

1–0

FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area

in P-Flash memory as shown in Table 18-20. The FPLS bits can only be written to while the FPLDIS bit is set.

Table 18-18. P-Flash Protection Function

FPOPEN FPHDIS FPLDIS Function1

1For range sizes, refer to Table 18-19 and Table 18-20.

1 1 1 No P-Flash Protection

1 1 0 Protected Low Range

1 0 1 Protected High Range

1 0 0 Protected High and Low Ranges

0 1 1 Full P-Flash Memory Protected

0 1 0 Unprotected Low Range

0 0 1 Unprotected High Range

0 0 0 Unprotected High and Low Ranges

Table 18-19. P-Flash Protection Higher Address Range

FPHS[1:0] Global Address Range Protected Size

00 0x7F_F800–0x7F_FFFF 2 Kbytes

01 0x7F_F000–0x7F_FFFF 4 Kbytes

10 0x7F_E000–0x7F_FFFF 8 Kbytes

11 0x7F_C000–0x7F_FFFF 16 Kbytes

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526 Freescale Semiconductor

All possible P-Flash protection scenarios are shown in Figure 18-14. Although the protection scheme is

loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed

by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single

chip mode while providing as much protection as possible if reprogramming is not required.

Table 18-20. P-Flash Protection Lower Address Range

FPLS[1:0] Global Address Range Protected Size

00 0x7F_8000–0x7F_83FF 1 Kbyte

01 0x7F_8000–0x7F_87FF 2 Kbytes

10 0x7F_8000–0x7F_8FFF 4 Kbytes

11 0x7F_8000–0x7F_9FFF 8 Kbytes

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Figure 18-14. P-Flash Protection Scenarios

7654

FPHS[1:0] FPLS[1:0]

3210

FPHS[1:0] FPLS[1:0]

FPHDIS = 1

FPLDIS = 1

FPHDIS = 1

FPLDIS = 0

FPHDIS = 0

FPLDIS = 1

FPHDIS = 0

FPLDIS = 0

Scenario

Unprotected region Protected region with size

Protected region Protected region with size

defined by FPLS

defined by FPHSnot defined by FPLS, FPHS

0x7F_8000

0x7F_FFFF

0x7F_8000

0x7F_FFFF

FLASH START

FPOPEN = 1FPOPEN = 0

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18.3.2.9.1 P-Flash Protection Restrictions

The general guideline is that P-Flash protection can only be added and not removed. Table 18-21 specifies

all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the

FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.

See the FPHS and FPLS bit descriptions for additional restrictions.

18.3.2.10 D-Flash Protection Register (DFPROT)

The DFPROT register deﬁnes which D-Flash sectors are protected against program and erase operations.

The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added

but not removed. Writes must increase the DPS value and the DPOEN bit can only be written from 1

(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is

irrelevant.

During the reset sequence, the DFPROT register is loaded with the contents of the D-Flash protection byte

in the Flash configuration field at global address 0x7F_FF0D located in P-Flash memory (see Table 18-3)

as indicated by reset condition F in Figure 18-15. To change the D-Flash protection that will be loaded

during the reset sequence, the P-Flash sector containing the D-Flash protection byte must be unprotected,

then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the

Table 18-21. P-Flash Protection Scenario Transitions

From

Protection

Scenario

To Protection Scenario1

1Allowed transitions marked with X, see Figure 18-14 for a deﬁnition of the scenarios.

01234567

0XXXX

1XX

2XX

4XX

5XXXX

6XXXX

7XXXXXXXX

Offset Module Base + 0x0009

76543210

RDPOPEN 00 DPS[4:0]

Reset F 0 0 FFFFF

= Unimplemented or Reserved

Figure 18-15. D-Flash Protection Register (DFPROT)

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P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be

cleared and DPS bits will be set to leave the D-Flash memory fully protected.

Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error

and the FPVIOL bit will be set in the FSTAT register. Block erase of the D-Flash memory is not possible

if any of the D-Flash sectors are protected.

Table 18-22. DFPROT Field Descriptions

Field Description

DPOPEN D-Flash Protection Control

0 Enables D-Flash memory protection from program and erase with protected address range deﬁned by DPS

bits

1 Disables D-Flash memory protection from program and erase

4–0

DPS[4:0] D-Flash Protection Size — The DPS[4:0] bits determine the size of the protected area in the D-Flash memory

as shown in Table 18-23.

Table 18-23. D-Flash Protection Address Range

DPS[4:0] Global Address Range Protected Size

0_0000 0x10_0000 – 0x10_00FF 256 bytes

0_0001 0x10_0000 – 0x10_01FF 512 bytes

0_0010 0x10_0000 – 0x10_02FF 768 bytes

0_0011 0x10_0000 – 0x10_03FF 1024 bytes

0_0100 0x10_0000 – 0x10_04FF 1280 bytes

0_0101 0x10_0000 – 0x10_05FF 1536 bytes

0_0110 0x10_0000 – 0x10_06FF 1792 bytes

0_0111 0x10_0000 – 0x10_07FF 2048 bytes

0_1000 0x10_0000 – 0x10_08FF 2304 bytes

0_1001 0x10_0000 – 0x10_09FF 2560 bytes

0_1010 0x10_0000 – 0x10_0AFF 2816 bytes

0_1011 0x10_0000 – 0x10_0BFF 3072 bytes

0_1100 0x10_0000 – 0x10_0CFF 3328 bytes

0_1101 0x10_0000 – 0x10_0DFF 3584 bytes

0_1110 0x10_0000 – 0x10_0EFF 3840 bytes

0_1111 0x10_0000 – 0x10_0FFF 4096 bytes

1_0000 0x10_0000 – 0x10_10FF 4352 bytes

1_0001 0x10_0000 – 0x10_11FF 4608 bytes

1_0010 0x10_0000 – 0x10_12FF 4864 bytes

1_0011 0x10_0000 – 0x10_13FF 5120 bytes

1_0100 0x10_0000 – 0x10_14FF 5376 bytes

1_0101 0x10_0000 – 0x10_15FF 5632 bytes

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530 Freescale Semiconductor

18.3.2.11 Flash Common Command Object Register (FCCOB)

The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.

Byte wide reads and writes are allowed to the FCCOB register.

18.3.2.11.1 FCCOB - NVM Command Mode

NVM command mode uses the indexed FCCOB register to provide a command code and its relevant

parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates

the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user

clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register

all FCCOB parameter fields are locked and cannot be changed by the user until the command completes

1_0110 0x10_0000 – 0x10_16FF 5888 bytes

1_0111 0x10_0000 – 0x10_17FF 6144 bytes

1_1000 0x10_0000 – 0x10_18FF 6400 bytes

1_1001 0x10_0000 – 0x10_19FF 6656 bytes

1_1010 0x10_0000 – 0x10_1AFF 6912 bytes

1_1011 0x10_0000 – 0x10_1BFF 7168 bytes

1_1100 0x10_0000 – 0x10_1CFF 7424 bytes

1_1101 0x10_0000 – 0x10_1DFF 7680 bytes

1_1110 0x10_0000 – 0x10_1EFF 7936 bytes

1_1111 0x10_0000 – 0x10_1FFF 8192 bytes

Offset Module Base + 0x000A

76543210

RCCOB[15:8]

Reset 00000000

Figure 18-16. Flash Common Command Object High Register (FCCOBHI)

Offset Module Base + 0x000B

76543210

RCCOB[7:0]

Reset 00000000

Figure 18-17. Flash Common Command Object Low Register (FCCOBLO)

Table 18-23. D-Flash Protection Address Range

DPS[4:0] Global Address Range Protected Size

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(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the

FCCOB register array.

The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 18-24.

The return values are available for reading after the CCIF flag in the FSTAT register has been returned to

1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX

= 111) are ignored with reads from these fields returning 0x0000.

Table 18-24 shows the generic Flash command format. The high byte of the first word in the CCOB array

contains the command code, followed by the parameters for this specific Flash command. For details on

the FCCOB settings required by each command, see the Flash command descriptions in Section 18.4.2.

18.3.2.12 Flash Reserved0 Register (FRSV0)

This Flash register is reserved for factory testing.

All bits in the FRSV0 register read 0 and are not writable.

Table 18-24. FCCOB - NVM Command Mode (Typical Usage)

CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode)

000 HI FCMD[7:0] deﬁning Flash command

LO 0, Global address [22:16]

001 HI Global address [15:8]

LO Global address [7:0]

010 HI Data 0 [15:8]

LO Data 0 [7:0]

011 HI Data 1 [15:8]

LO Data 1 [7:0]

100 HI Data 2 [15:8]

LO Data 2 [7:0]

101 HI Data 3 [15:8]

LO Data 3 [7:0]

Offset Module Base + 0x000C

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 18-18. Flash Reserved0 Register (FRSV0)

256 KByte Flash Module (S12XFTMR256K1V1)

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532 Freescale Semiconductor

18.3.2.13 Flash Reserved1 Register (FRSV1)

This Flash register is reserved for factory testing.

All bits in the FRSV1 register read 0 and are not writable.

18.3.2.14 Flash ECC Error Results Register (FECCR)

The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.

The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits

in the FECCRIX register (see Section 18.3.2.4). Once ECC fault information has been stored, no other

fault information will be recorded until the specific ECC fault flag has been cleared. In the event of

simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.

All FECCR bits are readable but not writable.

Offset Module Base + 0x000D

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 18-19. Flash Reserved1 Register (FRSV1)

Offset Module Base + 0x000E

76543210

R ECCR[15:8]

Reset 00000000

= Unimplemented or Reserved

Figure 18-20. Flash ECC Error Results High Register (FECCRHI)

Offset Module Base + 0x000F

76543210

R ECCR[7:0]

Reset 00000000

= Unimplemented or Reserved

Figure 18-21. Flash ECC Error Results Low Register (FECCRLO)

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The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The

following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four

data words and the parity byte are the uncorrected data read from the P-Flash block.

The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The

uncorrected 16-bit data word is addressed by ECCRIX = 010.

18.3.2.15 Flash Option Register (FOPT)

The FOPT register is the Flash option register.

All bits in the FOPT register are readable but are not writable.

Table 18-25. FECCR Index Settings

ECCRIX[2:0] FECCR Register Content

Bits [15:8] Bit[7] Bits[6:0]

000 Parity bits read from

Flash block 0Global address

[22:16]

001 Global address [15:0]

010 Data 0 [15:0]

011 Data 1 [15:0] (P-Flash only)

100 Data 2 [15:0] (P-Flash only)

101 Data 3 [15:0] (P-Flash only)

110 Not used, returns 0x0000 when read

111 Not used, returns 0x0000 when read

Table 18-26. FECCR Index=000 Bit Descriptions

Field Description

15:8

PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,

allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.

6–0

GADDR[22:16] Global Address — The GADDR[22:16] ﬁeld contains the upper seven bits of the global address having

caused the error.

Offset Module Base + 0x0010

76543210

R NV[7:0]

Reset F F FFFFFF

= Unimplemented or Reserved

Figure 18-22. Flash Option Register (FOPT)

256 KByte Flash Module (S12XFTMR256K1V1)

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534 Freescale Semiconductor

During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash

configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 18-3) as indicated

by reset condition F in Figure 18-22. If a double bit fault is detected while reading the P-Flash phrase

containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.

18.3.2.16 Flash Reserved2 Register (FRSV2)

This Flash register is reserved for factory testing.

All bits in the FRSV2 register read 0 and are not writable.

18.3.2.17 Flash Reserved3 Register (FRSV3)

This Flash register is reserved for factory testing.

All bits in the FRSV3 register read 0 and are not writable.

18.3.2.18 Flash Reserved4 Register (FRSV4)

This Flash register is reserved for factory testing.

Table 18-27. FOPT Field Descriptions

Field Description

7–0

NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper

use of the NV bits.

Offset Module Base + 0x0011

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 18-23. Flash Reserved2 Register (FRSV2)

Offset Module Base + 0x0012

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 18-24. Flash Reserved3 Register (FRSV3)

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All bits in the FRSV4 register read 0 and are not writable.

18.4 Functional Description

18.4.1 Flash Command Operations

Flash command operations are used to modify Flash memory contents.

The next sections describe:

• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from

OSCCLK for Flash program and erase command operations

• The command write sequence used to set Flash command parameters and launch execution

• Valid Flash commands available for execution

18.4.1.1 Writing the FCLKDIV Register

Prior to issuing any Flash program or erase command after a reset, the user is required to write the

FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 18-7 shows recommended

values for the FDIV ﬁeld based on OSCCLK frequency.

NOTE

Programming or erasing the Flash memory cannot be performed if the bus

clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash

memory due to overstress. Setting FDIV too low can result in incomplete

programming or erasure of the Flash memory cells.

When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the

FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,

any Flash program or erase command loaded during a command write sequence will not execute and the

ACCERR bit in the FSTAT register will set.

Offset Module Base + 0x0013

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 18-25. Flash Reserved4 Register (FRSV4)

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18.4.1.2 Command Write Sequence

The Memory Controller will launch all valid Flash commands entered using a command write sequence.

Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see

Section 18.3.2.7) and the CCIF flag should be tested to determine the status of the current command write

sequence. If CCIF is 0, the previous command write sequence is still active, a new command write

sequence cannot be started, and all writes to the FCCOB register are ignored.

CAUTION

Writes to any Flash register must be avoided while a Flash command is

active (CCIF=0) to prevent corruption of Flash register contents and

Memory Controller behavior.

18.4.1.2.1 Deﬁne FCCOB Contents

The FCCOB parameter ﬁelds must be loaded with all required parameters for the Flash command being

executed. Access to the FCCOB parameter ﬁelds is controlled via the CCOBIX bits in the FCCOBIX

The contents of the FCCOB parameter ﬁelds are transferred to the Memory Controller when the user clears

the CCIF command completion ﬂag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF ﬂag

will remain clear until the Flash command has completed. Upon completion, the Memory Controller will

return CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic

command write sequence is shown in Figure 18-26.

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Figure 18-26. Generic Flash Command Write Sequence Flowchart

Write to FCCOBIX register

Write: FSTAT register (to launch command)

Clear CCIF 0x80

Clear ACCERR/FPVIOL 0x30

Write: FSTAT register

yes

Access Error and

Protection Violation

Read: FSTAT register

START

yes

Check

CCIF

Set?

FCCOB

ACCERR/

FPVIOL

Set?

EXIT

Write: FCLKDIV register

Read: FCLKDIV register

yes

Clock Register

Written

Check

FDIVLD

Set?

Bit Polling for

Command Completion

Check

yes

CCIF Set?

to identify speciﬁc command

parameter to load.

Write to FCCOB register

to load required command parameter.

yes

Parameters?

Availability Check

Results from previous Command

Note: FCLKDIV must be set after

each reset

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18.4.1.3 Valid Flash Module Commands

18.4.1.4 P-Flash Commands

Table 18-29 summarizes the valid P-Flash commands along with the effects of the commands on the

P-Flash block and other resources within the Flash module.

Table 18-28. Flash Commands by Mode

FCMD Command Unsecured Secured

NS1

1Unsecured Normal Single Chip mode.

NX2

2Unsecured Normal Expanded mode.

SS3

3Unsecured Special Single Chip mode.

ST4

4Unsecured Special Mode.

NS5

5Secured Normal Single Chip mode.

NX6

6Secured Normal Expanded mode.

SS7

7Secured Special Single Chip mode.

ST8

8Secured Special Mode.

0x01 Erase Verify All Blocks ∗∗∗∗∗∗∗∗

0x02 Erase Verify Block ∗∗∗∗∗∗∗∗

0x03 Erase Verify P-Flash Section ∗∗∗∗∗

0x04 Read Once ∗∗∗∗∗

0x06 Program P-Flash ∗∗∗∗∗

0x07 Program Once ∗∗∗∗∗

0x08 Erase All Blocks ∗∗ ∗∗

0x09 Erase Flash Block ∗∗∗∗∗

0x0A Erase P-Flash Sector ∗∗∗∗∗

0x0B Unsecure Flash ∗∗ ∗∗

0x0C Verify Backdoor Access Key ∗∗

0x0D Set User Margin Level ∗∗∗∗∗

0x0E Set Field Margin Level ∗∗

0x10 Erase Verify D-Flash Section ∗∗∗∗∗

0x11 Program D-Flash ∗∗∗∗∗

0x12 Erase D-Flash Sector ∗∗∗∗∗

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18.4.1.5 D-Flash Commands

Table 18-30 summarizes the valid D-Flash commands along with the effects of the commands on the

D-Flash block.

Table 18-29. P-Flash Commands

FCMD Command Function on P-Flash Memory

0x01 Erase Verify All

Blocks Verify that all P-Flash (and D-Flash) blocks are erased.

0x02 Erase Verify Block Verify that a P-Flash block is erased.

0x03 Erase Verify

P-Flash Section Verify that a given number of words starting at the address provided are erased.

0x04 Read Once Read a dedicated 64 byte ﬁeld in the nonvolatile information register in P-Flash block 0

that was previously programmed using the Program Once command.

0x06 Program P-Flash Program a phrase in a P-Flash block.

0x07 Program Once Program a dedicated 64 byte ﬁeld in the nonvolatile information register in P-Flash block

0 that is allowed to be programmed only once.

0x08 Erase All Blocks

Erase all P-Flash (and D-Flash) blocks.

An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN

bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to

launching the command.

0x09 Erase Flash Block Erase a P-Flash (or D-Flash) block.

An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN

bits in the FPROT register are set prior to launching the command.

0x0A Erase P-Flash

Sector Erase all bytes in a P-Flash sector.

0x0B Unsecure Flash Supports amethod ofreleasingMCU security byerasingallP-Flash (andD-Flash)blocks

and verifying that all P-Flash (and D-Flash) blocks are erased.

0x0C Verify Backdoor

Access Key Supports a method of releasing MCU security by verifying a set of security keys.

0x0D Set User Margin

Level Speciﬁes a user margin read level for all P-Flash blocks.

0x0E Set Field Margin

Level Speciﬁes a ﬁeld margin read level for all P-Flash blocks (special modes only).

Table 18-30. D-Flash Commands

FCMD Command Function on D-Flash Memory

0x01 Erase Verify All

Blocks Verify that all D-Flash (and P-Flash) blocks are erased.

0x02 Erase Verify Block Verify that the D-Flash block is erased.

0x08 Erase All Blocks

Erase all D-Flash (and P-Flash) blocks.

An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN

bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to

launching the command.

0x09 Erase Flash Block Erase a D-Flash (or P-Flash) block.

An erase of the full D-Flash block is only possible when DPOPEN bit in the DFPROT

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18.4.2 Flash Command Description

This section provides details of all available Flash commands launched by a command write sequence. The

ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following

illegal steps are performed, causing the command not to be processed by the Memory Controller:

• Starting any command write sequence that programs or erases Flash memory before initializing the

FCLKDIV register

• Writing an invalid command as part of the command write sequence

• For additional possible errors, refer to the error handling table provided for each command

If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation

will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read

operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded

with the global address used in the invalid read operation with the data and parity fields set to all 0.

If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting

any command write sequence (see Section 18.3.2.7).

CAUTION

A Flash word or phrase must be in the erased state before being

programmed. Cumulative programming of bits within a Flash word or

phrase is not allowed.

18.4.2.1 Erase Verify All Blocks Command

The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.

0x0B Unsecure Flash Supportsamethodof releasingMCU security byerasingallD-Flash(andP-Flash)blocks

and verifying that all D-Flash (and P-Flash) blocks are erased.

0x0D Set User Margin

Level Speciﬁes a user margin read level for the D-Flash block.

0x0E Set Field Margin

Level Speciﬁes a ﬁeld margin read level for the D-Flash block (special modes only).

0x10 Erase Verify

D-Flash Section Verify that a given number of words starting at the address provided are erased.

0x11 Program D-Flash Program up to four words in the D-Flash block.

0x12 Erase D-Flash

Sector Erase all bytes in a sector of the D-Flash block.

Table 18-31. Erase Verify All Blocks Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x01 Not required

Table 18-30. D-Flash Commands

FCMD Command Function on D-Flash Memory

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Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify

that the entire Flash memory space is erased. The CCIF ﬂag will set after the Erase Verify All Blocks

operation has completed.

18.4.2.2 Erase Verify Block Command

The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been

erased. The FCCOB upper global address bits determine which block must be veriﬁed.

Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that

the selected P-Flash or D-Flash block is erased. The CCIF ﬂag will set after the Erase Verify Block

operation has completed.

18.4.2.3 Erase Verify P-Flash Section Command

The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is

erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and

the number of phrases. The section to be verified cannot cross a 256 Kbyte boundary in the P-Flash

memory space.

Table 18-32. Erase Verify All Blocks Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 18-33. Erase Verify Block Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x02 Global address [22:16] of the

Flash block to be veriﬁed.

Table 18-34. Erase Verify Block Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

Set if an invalid global address [22:16] is supplied

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

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Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will

verify the selected section of Flash memory is erased. The CCIF ﬂag will set after the Erase Verify P-Flash

Section operation has completed.

18.4.2.4 Read Once Command

The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the

nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the

Program Once command described in Section 18.4.2.6. The Read Once command must not be executed

from the Flash block containing the Program Once reserved field to avoid code runaway.

Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the

FCCOB indexed register. The CCIF ﬂag will set after the Read Once operation has completed. Valid

Table 18-35. Erase Verify P-Flash Section Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x03 Global address [22:16] of

a P-Flash block

001 Global address [15:0] of the ﬁrst phrase to be veriﬁed

010 Number of phrases to be veriﬁed

Table 18-36. Erase Verify P-Flash Section Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 010 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned phrase address is supplied (global address [2:0] != 000)

Set if the requested section crosses a 256 Kbyte boundary

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 18-37. Read Once Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x04 Not Required

001 Read Once phrase index (0x0000 - 0x0007)

010 Read Once word 0 value

011 Read Once word 1 value

100 Read Once word 2 value

101 Read Once word 3 value

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phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the

Read Once command, any attempt to read addresses within P-Flash block will return invalid data.

18.4.2.5 Program P-Flash Command

The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an

embedded algorithm.

CAUTION

A P-Flash phrase must be in the erased state before being programmed.

Cumulative programming of bits within a Flash phrase is not allowed.

Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the

data words to the supplied global address and will then proceed to verify the data words read back as

expected. The CCIF ﬂag will set after the Program P-Flash operation has completed.

Table 18-38. Read Once Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid phrase index is supplied

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 18-39. Program P-Flash Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x06 Global address [22:16] to

identify P-Flash block

001 Global address [15:0] of phrase location to be programmed1

1Global address [2:0] must be 000

010 Word 0 program value

011 Word 1 program value

100 Word 2 program value

101 Word 3 program value

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18.4.2.6 Program Once Command

The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the

nonvolatile information register located in P-Flash block 0. The Program Once reserved field can be read

using the Read Once command as described in Section 18.4.2.4. The Program Once command must only

be issued once since the nonvolatile information register in P-Flash block 0 cannot be erased. The Program

Once command must not be executed from the Flash block containing the Program Once reserved field to

avoid code runaway.

Upon clearing CCIF to launch the Program Once command, the Memory Controller ﬁrst veriﬁes that the

selected phrase is erased. If erased, then the selected phrase will be programmed and then veriﬁed with

read back. The CCIF ﬂag will remain clear, setting only after the Program Once operation has completed.

The reserved nonvolatile information register accessed by the Program Once command cannot be erased

and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index

values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program

Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.

Table 18-40. Program P-Flash Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 101 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned phrase address is supplied (global address [2:0] != 000)

FPVIOL Set if the global address [22:0] points to a protected area

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 18-41. Program Once Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x07 Not Required

001 Program Once phrase index (0x0000 - 0x0007)

010 Program Once word 0 value

011 Program Once word 1 value

100 Program Once word 2 value

101 Program Once word 3 value

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18.4.2.7 Erase All Blocks Command

The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space.

Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire

Flash memory space and verify that it is erased. If the Memory Controller veriﬁes that the entire Flash

memory space was properly erased, security will be released. During the execution of this command

(CCIF=0) the user must not write to any Flash module register. The CCIF ﬂag will set after the Erase All

Blocks operation has completed.

18.4.2.8 Erase Flash Block Command

The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block.

Table 18-42. Program Once Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 101 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid phrase index is supplied

Set if the requested phrase has already been programmed1

1If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will

be allowed to execute again on that same phrase.

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 18-43. Erase All Blocks Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x08 Not required

Table 18-44. Erase All Blocks Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

Set if command not available in current mode (see Table 18-28)

FPVIOL Set if any area of the P-Flash or D-Flash memory is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

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Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the

selected Flash block and verify that it is erased. The CCIF ﬂag will set after the Erase Flash Block

operation has completed.

18.4.2.9 Erase P-Flash Sector Command

The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.

Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the

selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash

Sector operation has completed.

Table 18-45. Erase Flash Block Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x09 Global address [22:16] to

identify Flash block

001 Global address [15:0] in Flash block to be erased

Table 18-46. Erase Flash Block Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:16] is supplied

Set if the supplied P-Flash address is not phrase-aligned or if the D-Flash

address is not word-aligned

FPVIOL Set if an area of the selected Flash block is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 18-47. Erase P-Flash Sector Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0A Global address [22:16] to identify

P-Flash block to be erased

001 Global address [15:0] anywhere within the sector to be erased.

Refer to Section 18.1.2.1 for the P-Flash sector size.

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18.4.2.10 Unsecure Flash Command

The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is

successful, will release security.

Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire

P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller veriﬁes that the

entire Flash memory space was properly erased, security will be released. If the erase verify is not

successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security

state. During the execution of this command (CCIF=0) the user must not write to any Flash module

18.4.2.11 Verify Backdoor Access Key Command

The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the

FSEC register (see Table 18-9). The Verify Backdoor Access Key command releases security if

user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see

Table 18-48. Erase P-Flash Sector Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:16] is supplied

Set if a misaligned phrase address is supplied (global address [2:0] != 000)

FPVIOL Set if the selected P-Flash sector is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 18-49. Unsecure Flash Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0B Not required

Table 18-50. Unsecure Flash Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

Set if command not available in current mode (see Table 18-28)

FPVIOL Set if any area of the P-Flash or D-Flash memory is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

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Table 18-3). The Verify Backdoor Access Key command must not be executed from the Flash block

containing the backdoor comparison key to avoid code runaway.

Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will

check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory

Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the

Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash

conﬁguration ﬁeld with Key 0 compared to 0x7F_FF00, etc. If the backdoor keys match, security will be

released. If the backdoor keys do not match, security is not released and all future attempts to execute the

Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is

set after the Verify Backdoor Access Key operation has completed.

18.4.2.12 Set User Margin Level Command

The Set User Margin Level command causes the Memory Controller to set the margin level for future read

operations of a specific P-Flash or D-Flash block.

Table 18-51. Verify Backdoor Access Key Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0C Not required

001 Key 0

010 Key 1

011 Key 2

100 Key 3

Table 18-52. Verify Backdoor Access Key Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 100 at command launch

Set if an incorrect backdoor key is supplied

Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see

Section 18.3.2.2)

Set if the backdoor key has mismatched since the last reset

FPVIOL None

MGSTAT1 None

MGSTAT0 None

Table 18-53. Set User Margin Level Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0D Global address [22:16] to identify the

Flash block

001 Margin level setting

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Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the

user margin level for the targeted block and then set the CCIF ﬂag.

Valid margin level settings for the Set User Margin Level command are deﬁned in Table 18-54.

NOTE

User margin levels can be used to check that Flash memory contents have

adequate margin for normal level read operations. If unexpected results are

encountered when checking Flash memory contents at user margin levels, a

potential loss of information has been detected.

18.4.2.13 Set Field Margin Level Command

The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set

the margin level specified for future read operations of a specific P-Flash or D-Flash block.

Table 18-54. Valid Set User Margin Level Settings

CCOB

(CCOBIX=001) Level Description

0x0000 Return to Normal Level

0x0001 User Margin-1 Level1

1Read margin to the erased state

0x0002 User Margin-0 Level2

2Read margin to the programmed state

Table 18-55. Set User Margin Level Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:16] is supplied

Set if an invalid margin level setting is supplied

FPVIOL None

MGSTAT1 None

MGSTAT0 None

Table 18-56. Set Field Margin Level Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0E Global address [22:16] to identify the Flash

block

001 Margin level setting

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Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the

ﬁeld margin level for the targeted block and then set the CCIF ﬂag. Valid margin level settings for the Set

Field Margin Level command are deﬁned in Table 18-57.

CAUTION

Field margin levels must only be used during verify of the initial factory

programming.

NOTE

Field margin levels can be used to check that Flash memory contents have

adequate margin for data retention at the normal level setting. If unexpected

results are encountered when checking Flash memory contents at ﬁeld

margin levels, the Flash memory contents should be erased and

reprogrammed.

18.4.2.14 Erase Verify D-Flash Section Command

The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased. The

Erase Verify D-Flash Section command defines the starting point of the data to be verified and the number

of words.

Table 18-57. Valid Set Field Margin Level Settings

CCOB

(CCOBIX=001) Level Description

0x0000 Return to Normal Level

0x0001 User Margin-1 Level1

1Read margin to the erased state

0x0002 User Margin-0 Level2

2Read margin to the programmed state

0x0003 Field Margin-1 Level1

0x0004 Field Margin-0 Level2

Table 18-58. Set Field Margin Level Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:16] is supplied

Set if an invalid margin level setting is supplied

FPVIOL None

MGSTAT1 None

MGSTAT0 None

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Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will

verify the selected section of D-Flash memory is erased. The CCIF ﬂag will set after the Erase Verify

D-Flash Section operation has completed.

18.4.2.15 Program D-Flash Command

The Program D-Flash operation programs one to four previously erased words in the D-Flash block. The

Program D-Flash operation will confirm that the targeted location(s) were successfully programmed upon

completion.

CAUTION

A Flash word must be in the erased state before being programmed.

Cumulative programming of bits within a Flash word is not allowed.

Table 18-59. Erase Verify D-Flash Section Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x10 Global address [22:16] to

identify the D-Flash block

001 Global address [15:0] of the ﬁrst word to be veriﬁed

010 Number of words to be veriﬁed

Table 18-60. Erase Verify D-Flash Section Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 010 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned word address is supplied (global address [0] != 0)

Set if the requested section breaches the end of the D-Flash block

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 18-61. Program D-Flash Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x11 Global address [22:16] to

identify the D-Flash block

001 Global address [15:0] of word to be programmed

010 Word 0 program value

011 Word 1 program value, if desired

100 Word 2 program value, if desired

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Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred

to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at

Program D-Flash command launch determines how many words will be programmed in the D-Flash block.

The CCIF ﬂag is set when the operation has completed.

18.4.2.16 Erase D-Flash Sector Command

The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash block.

Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the

selected Flash sector and verify that it is erased. The CCIF ﬂag will set after the Erase D-Flash Sector

operation has completed.

101 Word 3 program value, if desired

Table 18-62. Program D-Flash Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] < 010 at command launch

Set if CCOBIX[2:0] > 101 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned word address is supplied (global address [0] != 0)

Set if the requested group of words breaches the end of the D-Flash block

FPVIOL Set if the selected area of the D-Flash memory is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 18-63. Erase D-Flash Sector Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x12 Global address [22:16] to identify

D-Flash block

001 Global address [15:0] anywhere within the sector to be erased.

See Section 18.1.2.2 for D-Flash sector size.

Table 18-61. Program D-Flash Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

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18.4.3 Interrupts

The Flash module can generate an interrupt when a Flash command operation has completed or when a

Flash command operation has detected an ECC fault.

NOTE

Vector addresses and their relative interrupt priority are determined at the

MCU level.

18.4.3.1 Description of Flash Interrupt Operation

The Flash module uses the CCIF ﬂag in combination with the CCIE interrupt enable bit to generate the

Flash command interrupt request. The Flash module uses the DFDIF and SFDIF ﬂags in combination with

the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed

description of the register bits involved, refer to Section 18.3.2.5, “Flash Configuration Register

(FCNFG)”, Section 18.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 18.3.2.7, “Flash

Status Register (FSTAT)”, and Section 18.3.2.8, “Flash Error Status Register (FERSTAT)”.

The logic used for generating the Flash module interrupts is shown in Figure 18-27.

Table 18-64. Erase D-Flash Sector Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 18-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned word address is supplied (global address [0] != 0)

FPVIOL Set if the selected area of the D-Flash memory is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 18-65. Flash Interrupt Sources

Interrupt Source Interrupt Flag Local Enable Global (CCR)

Mask

Flash Command Complete CCIF

(FSTAT register) CCIE

(FCNFG register) I Bit

ECC Double Bit Fault on Flash Read DFDIF

(FERSTAT register) DFDIE

(FERCNFG register) I Bit

ECC Single Bit Fault on Flash Read SFDIF

(FERSTAT register) SFDIE

(FERCNFG register) I Bit

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Figure 18-27. Flash Module Interrupts Implementation

18.4.4 Wait Mode

The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU

from wait via the CCIF interrupt (see Section 18.4.3, “Interrupts”).

18.4.5 Stop Mode

If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation

will be completed before the CPU is allowed to enter stop mode.

18.5 Security

The Flash module provides security information to the MCU. The Flash security state is deﬁned by the

SEC bits of the FSEC register (see Table 18-10). During reset, the Flash module initializes the FSEC

0x7F_FF0F.

The security state out of reset can be permanently changed by programming the security byte of the Flash

conﬁguration ﬁeld. This assumes that you are starting from a mode where the necessary P-Flash erase and

program commands are available and that the upper region of the P-Flash is unprotected. If the Flash

security byte is successfully programmed, its new value will take affect after the next MCU reset.

The following subsections describe these security-related subjects:

• Unsecuring the MCU using Backdoor Key Access

• Unsecuring the MCU in Special Single Chip Mode using BDM

• Mode and Security Effects on Flash Command Availability

18.5.1 Unsecuring the MCU using Backdoor Key Access

The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the

contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If

the KEYEN[1:0] bits are in the enabled state (see Section 18.3.2.2), the Verify Backdoor Access Key

command (see Section 18.4.2.11) allows the user to present four prospective keys for comparison to the

Flash Error Interrupt Request

CCIF

CCIE

DFDIF

DFDIE

SFDIF

SFDIE

Flash Command Interrupt Request

256 KByte Flash Module (S12XFTMR256K1V1)

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keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor

Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC

not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash block

0 will not be available for read access and will return invalid data.

The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an

external stimulus. This external stimulus would typically be through one of the on-chip serial ports.

If the KEYEN[1:0] bits are in the enabled state (see Section 18.3.2.2), the MCU can be unsecured by the

backdoor key access sequence described below:

1. Follow the command sequence for the Verify Backdoor Access Key command as explained in

Section 18.4.2.11

2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the

SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10

The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will

prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method

to re-enable the Verify Backdoor Access Key command.

After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is

unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be

reprogrammed to the unsecure state, if desired.

In the unsecure state, the user has full control of the contents of the backdoor keys by programming

addresses 0x7F_FF00–0x7F_FF07 in the Flash conﬁguration ﬁeld.

The security as deﬁned in the Flash security byte (0x7F_FF0F) is not changed by using the Verify

Backdoor Access Key command sequence. The backdoor keys stored in addresses

0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the

next reset of the MCU, the security state of the Flash module is determined by the Flash security byte

(0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and

erase protections deﬁned in the Flash protection register, FPROT.

18.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

The MCU can be unsecured in special single chip mode by erasing the P-Flash and D-Flash memory by

one of the following methods:

• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM,

send BDM commands to disable protection in the P-Flash and D-Flash memory, and execute the

Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory.

• Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash

memory and run code from external memory to execute the Erase All Blocks command write

sequence to erase the P-Flash and D-Flash memory.

After the CCIF ﬂag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into

special single chip mode. The BDM will execute the Erase Verify All Blocks command write sequence to

verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as

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erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may

be programmed to the unsecure state by the following method:

• Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash

security byte to the unsecured state and reset the MCU.

18.5.3 Mode and Security Effects on Flash Command Availability

The availability of Flash module commands depends on the MCU operating mode and security state as

shown in Table 18-28.

18.6 Initialization

On each system reset the Flash module executes a reset sequence which establishes initial values for the

Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and

FSEC registers. The Flash module reverts to built-in default values that leave the module in a fully

protected and secured state if errors are encountered during execution of the reset sequence. If a double bit

fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.

CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the

initial portion of the reset sequence. While Flash reads are possible when the hold is removed, writes to

the FCCOBIX, FCCOBHI, and FCCOBLO registers are ignored to prevent command activity while the

Memory Controller remains busy. Completion of the reset sequence is marked by setting CCIF high which

enables writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash

command.

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The

state of the word being programmed or the sector/block being erased is not guaranteed.

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Preliminary

Chapter 19

128 KByte Flash Module (S12XFTMR128K1V1)

19.1 Introduction

The FTMR128K1 module implements the following:

• 128 Kbytes of P-Flash (Program Flash) memory

• 8 Kbytes of D-Flash (Data Flash) memory

The Flash memory is ideal for single-supply applications allowing for ﬁeld reprogramming without

requiring external high voltage sources for program or erase operations. The Flash module includes a

memory controller that executes commands to modify Flash memory contents. The user interface to the

memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is

written to with the command, global address, data, and any required command parameters. The memory

controller must complete the execution of a command before the FCCOB register can be written to with a

new command.

Table 19-1. Revision History

Revision

Number Revision

Date Sections

Affected Description of Changes

V01.04 03 Jan 2008 - Cosmetic changes

V01.05 19 Dec 2008 19.1/19-557

19.4.2.4/19-592

19.4.2.6/19-594

19.4.2.11/19-59

- Clarify single bit fault correction for P-Flash phrase

- Add statement concerning code runaway when executing Read Once,

Program Once, and Verify Backdoor Access Key commands from Flash block

containing associated ﬁelds

- Relate Key 0 to associated Backdoor Comparison Key address

- Change “power down reset” to “reset” in Section 19.4.2.11

V01.06 25 Sep 2009

19.3.2/19-564

19.3.2.1/19-566

19.4.1.2/19-586

19.6/19-606

The following changes were made to clarify module behavior related to Flash

- Add caution concerning register writes while command is active

- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear

- Add caution concerning register writes while command is active

- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during

reset sequence

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Preliminary

CAUTION

A Flash word or phrase must be in the erased state before being

programmed. Cumulative programming of bits within a Flash word or

phrase is not allowed.

The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus

cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased

bit reads 1 and a programmed bit reads 0.

It is not possible to read from a Flash block while any command is executing on that speciﬁc Flash block.

It is possible to read from a Flash block while a command is executing on a different Flash block.

Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve

single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that

programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read

by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.

19.1.1 Glossary

Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including

program and erase) on the Flash memory.

D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data.

D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.

The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.

NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters

required for Flash command execution.

Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight

ECC bits for single bit fault correction and double bit fault detection within the phrase.

P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.

P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.

Each P-Flash sector contains 1024 bytes.

Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device

ID, Version ID, and the Program Once ﬁeld. The Program IFR is visible in the global memory map by

setting the PGMIFRON bit in the MMCCTL1 register.

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19.1.2 Features

19.1.2.1 P-Flash Features

• 128 Kbytes of P-Flash memory composed of one 128 Kbyte Flash block divided into 128 sectors

of 1024 bytes

• Single bit fault correction and double bit fault detection within a 64-bit phrase during read

operations

• Automated program and erase algorithm with verify and generation of ECC parity bits

• Fast sector erase and phrase program operation

• Flexible protection scheme to prevent accidental program or erase of P-Flash memory

19.1.2.2 D-Flash Features

• 8 Kbytes of D-Flash memory composed of one 8 Kbyte Flash block divided into 32 sectors of 256

bytes

• Single bit fault correction and double bit fault detection within a word during read operations

• Automated program and erase algorithm with verify and generation of ECC parity bits

• Fast sector erase and word program operation

• Protection scheme to prevent accidental program or erase of D-Flash memory

• Ability to program up to four words in a burst sequence

19.1.2.3 Other Flash Module Features

• No external high-voltage power supply required for Flash memory program and erase operations

• Interrupt generation on Flash command completion and Flash error detection

• Security mechanism to prevent unauthorized access to the Flash memory

19.1.3 Block Diagram

The block diagram of the Flash module is shown in Figure 19-1.

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Figure 19-1. FTMR128K1 Block Diagram

19.2 External Signal Description

The Flash module contains no signals that connect off-chip.

19.3 Memory Map and Registers

This section describes the memory map and registers for the Flash module. Read data from unimplemented

memory space in the Flash module is undeﬁned. Write access to unimplemented or reserved memory space

in the Flash module will be ignored by the Flash module.

Oscillator

Clock

Divider

Clock (XTAL)

Command

Interrupt

Request

FCLK

Protection

Security

Registers

Flash

Interface

16bit

internal

bus

sector 0

sector 1

sector 127

16Kx72

P-Flash

Error

Interrupt

Request

CPU

D-Flash

4Kx22

sector 0

sector 1

sector 31

Scratch RAM

384x16bits

Memory

Controller

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19.3.1 Module Memory Map

The S12X architecture places the P-Flash memory between global addresses 0x7E_0000 and 0x7F_FFFF

as shown in Table 19-2. The P-Flash memory map is shown in Figure 19-2.

The FPROT register, described in Section 19.3.2.9, can be set to protect regions in the Flash memory from

accidental program or erase. Three separate memory regions, one growing upward from global address

0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address

0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash

memory, can be activated for protection. The Flash memory addresses covered by these protectable regions

are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader

code since it covers the vector space. Default protection settings as well as security information that allows

the MCU to restrict access to the Flash module are stored in the Flash conﬁguration ﬁeld as described in

Table 19-3.

Table 19-2. P-Flash Memory Addressing

Global Address Size

(Bytes) Description

0x7E_0000 – 0x7F_FFFF 128 K P-Flash Block 0

Contains Flash Conﬁguration Field

(see Table 19-3)

Table 19-3. Flash Conﬁguration Field1

1Older versions may have swapped protection byte addresses

Global Address Size

(Bytes) Description

0x7F_FF00 – 0x7F_FF07 8 Backdoor Comparison Key

Refer to Section 19.4.2.11, “Verify Backdoor Access Key Command,” and

Section 19.5.1, “Unsecuring the MCU using Backdoor Key Access”

0x7F_FF08 – 0x7F_FF0B2

20x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in

the 0x7F_FF08 - 0x7F_FF0B reserved ﬁeld should be programmed to 0xFF.

4 Reserved

0x7F_FF0C21P-Flash Protection byte.

Refer to Section 19.3.2.9, “P-Flash Protection Register (FPROT)”

0x7F_FF0D21D-Flash Protection byte.

Refer to Section 19.3.2.10, “D-Flash Protection Register (DFPROT)”

0x7F_FF0E21Flash Nonvolatile byte

Refer to Section 19.3.2.15, “Flash Option Register (FOPT)”

0x7F_FF0F21Flash Security byte

Refer to Section 19.3.2.2, “Flash Security Register (FSEC)”

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Figure 19-2. P-Flash Memory Map

Flash Conﬁguration Field

0x7F_C000

Flash Protected/Unprotected Lower Region

1, 2, 4, 8 Kbytes

0x7F_8000

0x7F_9000

0x7F_8400

0x7F_8800

0x7F_A000

P-Flash END = 0x7F_FFFF

0x7F_F800

0x7F_F000

0x7F_E000 Flash Protected/Unprotected Higher Region

2, 4, 8, 16 Kbytes

Flash Protected/Unprotected Region

8 Kbytes (up to 29 Kbytes)

16 bytes (0x7F_FF00 - 0x7F_FF0F)

Flash Protected/Unprotected Region

96 Kbytes

P-Flash START = 0x7E_0000

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Table 19-4. Program IFR Fields

Global Address

(PGMIFRON) Size

(Bytes) Field Description

0x40_0000 – 0x40_0007 8 Device ID

0x40_0008 – 0x40_00E7 224 Reserved

0x40_00E8 – 0x40_00E9 2 Version ID

0x40_00EA – 0x40_00FF 22 Reserved

0x40_0100 – 0x40_013F 64 Program Once Field

Refer to Section 19.4.2.6, “Program Once Command”

0x40_0140 – 0x40_01FF 192 Reserved

Table 19-5. D-Flash and Memory Controller Resource Fields

Global Address Size

(Bytes) Description

0x10_0000 – 0x10_1FFF 8,192 D-Flash Memory

0x10_2000 – 0x11_FFFF 122,880 Reserved

0x12_0000 – 0x12_007F 128 D-Flash Nonvolatile Information Register (DFIFRON1 = 1)

1MMCCTL1 register bit

0x12_0080 – 0x12_0FFF 3,968 Reserved

0x12_1000 – 0x12_1FFF 4,096 Reserved

0x12_2000 – 0x12_3CFF 7,242 Reserved

0x12_3D00 – 0x12_3FFF 768 Memory Controller Scratch RAM (MGRAMON1 = 1)

0x12_4000 – 0x12_E7FF 43,008 Reserved

0x12_E800 – 0x12_FFFF 6,144 Reserved

0x13_0000 – 0x13_FFFF 65,536 Reserved

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Figure 19-3. D-Flash and Memory Controller Resource Memory Map

19.3.2 Register Descriptions

The Flash module contains a set of 20 control and status registers located between Flash module base +

0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 19-4 with detailed

descriptions in the following subsections.

CAUTION

Writes to any Flash register must be avoided while a Flash command is

active (CCIF=0) to prevent corruption of Flash register contents and

Memory Controller behavior.

Address

& Name 76543210

0x0000

FCLKDIV R FDIVLD FDIV6 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0

0x0001

FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0

Figure 19-4. FTMR128K1 Register Summary

0x12_FFFF

0x12_4000

0x12_1000

Memory Controller Scratch RAM (MGRAMON)

768 bytes

D-Flash Nonvolatile Information Register (DFIFRON)

128 bytes

D-Flash Memory

8 Kbytes

D-Flash START = 0x10_0000

0x12_0000

0x12_2000

0x12_E800

D-Flash END = 0x10_1FFF

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0x0002

FCCOBIX R0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0

0x0003

FECCRIX R0 0 0 0 0 ECCRIX2 ECCRIX1 ECCRIX0

0x0004

FCNFG RCCIE 00

IGNSF 00

FDFD FSFD

0x0005

FERCNFG R0DFDIE SFDIE

0x0006

FSTAT RCCIF 0ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0

0x0007

FERSTAT R0 0 0 0 0 0 DFDIF SFDIF

0x0008

FPROT RFPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0

0x0009

DFPROT RDPOPEN 00

DPS4 DPS3 DPS2 DPS1 DPS0

0x000A

FCCOBHI RCCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8

0x000B

FCCOBLO RCCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0

0x000C

FRSV0 R00000000

0x000D

FRSV1 R00000000

0x000E

FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8

0x000F

FECCRLO R ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0

Address

& Name 76543210

Figure 19-4. FTMR128K1 Register Summary (continued)

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19.3.2.1 Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms.

All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.

0x0010

FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0

0x0011

FRSV2 R00000000

0x0012

FRSV3 R00000000

0x0013

FRSV4 R00000000

= Unimplemented or Reserved

Offset Module Base + 0x0000

76543210

R FDIVLD FDIV[6:0]

Reset 00000000

= Unimplemented or Reserved

Figure 19-5. Flash Clock Divider Register (FCLKDIV)

Table 19-6. FCLKDIV Field Descriptions

Field Description

FDIVLD Clock Divider Loaded

0 FCLKDIV register has not been written

1 FCLKDIV register has been written since the last reset

6–0

FDIV[6:0] Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash

clock,FCLK,witha target frequency of 1MHzforusebytheFlash module to control timedevents during program

and erase algorithms. Table 19-7 shows recommended values for FDIV[6:0] based on OSCCLK frequency.

Please refer to Section 19.4.1, “Flash Command Operations,” for more information.

Address

& Name 76543210

Figure 19-4. FTMR128K1 Register Summary (continued)

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CAUTION

The FCLKDIV register should never be written while a Flash command is

executing (CCIF=0). The FCLKDIV register is writable during the Flash

reset sequence even though CCIF is clear.

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Table 19-7. FDIV vs OSCCLK Frequency

OSCCLK Frequency

(MHz) FDIV[6:0]

OSCCLK Frequency

(MHz) FDIV[6:0]

MIN1

1FDIV shown generates an FCLK frequency of >0.8 MHz

MAX2

2FDIV shown generates an FCLK frequency of 1.05 MHz

MIN1MAX2

1.60 2.10 0x01 33.60 34.65 0x20

2.40 3.15 0x02 34.65 35.70 0x21

3.20 4.20 0x03 35.70 36.75 0x22

4.20 5.25 0x04 36.75 37.80 0x23

5.25 6.30 0x05 37.80 38.85 0x24

6.30 7.35 0x06 38.85 39.90 0x25

7.35 8.40 0x07 39.90 40.95 0x26

8.40 9.45 0x08 40.95 42.00 0x27

9.45 10.50 0x09 42.00 43.05 0x28

10.50 11.55 0x0A 43.05 44.10 0x29

11.55 12.60 0x0B 44.10 45.15 0x2A

12.60 13.65 0x0C 45.15 46.20 0x2B

13.65 14.70 0x0D 46.20 47.25 0x2C

14.70 15.75 0x0E 47.25 48.30 0x2D

15.75 16.80 0x0F 48.30 49.35 0x2E

16.80 17.85 0x10 49.35 50.40 0x2F

17.85 18.90 0x11

18.90 19.95 0x12

19.95 21.00 0x13

21.00 22.05 0x14

22.05 23.10 0x15

23.10 24.15 0x16

24.15 25.20 0x17

25.20 26.25 0x18

26.25 27.30 0x19

27.30 28.35 0x1A

28.35 29.40 0x1B

29.40 30.45 0x1C

30.45 31.50 0x1D

31.50 32.55 0x1E

32.55 33.60 0x1F

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19.3.2.2 Flash Security Register (FSEC)

The FSEC register holds all bits associated with the security of the MCU and Flash module.

All bits in the FSEC register are readable but not writable.

During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the

Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 19-3) as

indicated by reset condition F in Figure 19-6. If a double bit fault is detected while reading the P-Flash

phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be

set to leave the Flash module in a secured state with backdoor key access disabled.

Offset Module Base + 0x0001

76543210

R KEYEN[1:0] RNV[5:2] SEC[1:0]

Reset F F FFFFFF

= Unimplemented or Reserved

Figure 19-6. Flash Security Register (FSEC)

Table 19-8. FSEC Field Descriptions

Field Description

7–6

KEYEN[1:0] Backdoor Key Security Enable Bits — The KEYEN[1:0] bits deﬁne the enabling of backdoor key access to the

Flash module as shown in Table 19-9.

5–2

RNV[5:2} Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.

1–0

SEC[1:0] Flash Security Bits — The SEC[1:0] bits deﬁne the security state of the MCU as shown in Table 19-10. If the

Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.

Table 19-9. Flash KEYEN States

KEYEN[1:0] Status of Backdoor Key Access

00 DISABLED

01 DISABLED1

1Preferred KEYEN state to disable backdoor key access.

10 ENABLED

11 DISABLED

Table 19-10. Flash Security States

SEC[1:0] Status of Security

00 SECURED

01 SECURED1

10 UNSECURED

11 SECURED

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The security function in the Flash module is described in Section 19.5.

19.3.2.3 Flash CCOB Index Register (FCCOBIX)

The FCCOBIX register is used to index the FCCOB register for Flash memory operations.

CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.

19.3.2.4 Flash ECCR Index Register (FECCRIX)

The FECCRIX register is used to index the FECCR register for ECC fault reporting.

ECCRIX bits are readable and writable while remaining bits read 0 and are not writable.

1Preferred SEC state to set MCU to secured state.

Offset Module Base + 0x0002

76543210

R00000 CCOBIX[2:0]

Reset 00000000

= Unimplemented or Reserved

Figure 19-7. FCCOB Index Register (FCCOBIX)

Table 19-11. FCCOBIX Field Descriptions

Field Description

2–0

CCOBIX[1:0] Common Command Register Index—TheCCOBIX bitsareused to selectwhich wordof the FCCOBregister

array is being read or written to. See Section 19.3.2.11, “Flash Common Command Object Register (FCCOB),”

for more details.

Offset Module Base + 0x0003

76543210

R00000 ECCRIX[2:0]

Reset 00000000

= Unimplemented or Reserved

Figure 19-8. FECCR Index Register (FECCRIX)

Table 19-12. FECCRIX Field Descriptions

Field Description

2-0

ECCRIX[2:0] ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is

being read. See Section 19.3.2.14, “Flash ECC Error Results Register (FECCR),” for more details.

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19.3.2.5 Flash Conﬁguration Register (FCNFG)

The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array

read access from the CPU or XGATE.

CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not

writable.

19.3.2.6 Flash Error Conﬁguration Register (FERCNFG)

The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.

Offset Module Base + 0x0004

76543210

RCCIE 00

IGNSF 00

FDFD FSFD

Reset 00000000

= Unimplemented or Reserved

Figure 19-9. Flash Conﬁguration Register (FCNFG)

Table 19-13. FCNFG Field Descriptions

Field Description

CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command

has completed.

0 Command complete interrupt disabled

1 An interrupt will be requested whenever the CCIF ﬂag in the FSTAT register is set (see Section 19.3.2.7)

IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see

Section 19.3.2.8).

0 All single bit faults detected during array reads are reported

1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be

generated

FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array

read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The

FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual

double bit fault is detected.

0 Flash array read operations will set the DFDIF ﬂag in the FERSTAT register only if a double bit fault is detected

1 Any Flash array read operation will force the DFDIF ﬂag in the FERSTAT register to be set (see

Section 19.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG

FSFD Force Single Bit Fault Detect —The FSFD bit allows the user to simulate a single bit fault during Flash array

read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The

FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single

bit fault is detected.

0 Flash array read operations will set the SFDIF ﬂag in the FERSTAT register only if a single bit fault is detected

1 Flash array read operation will force the SFDIF ﬂag in the FERSTAT register to be set (see Section 19.3.2.7)

and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see

Section 19.3.2.6)

128 KByte Flash Module (S12XFTMR128K1V1)

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All assigned bits in the FERCNFG register are readable and writable.

19.3.2.7 Flash Status Register (FSTAT)

The FSTAT register reports the operational status of the Flash module.

CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable

but not writable, while remaining bits read 0 and are not writable.

Offset Module Base + 0x0005

76543210

R 0 DFDIE SFDIE

Reset 00000000

= Unimplemented or Reserved

Figure 19-10. Flash Error Conﬁguration Register (FERCNFG)

Table 19-14. FERCNFG Field Descriptions

Field Description

DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault

is detected during a Flash block read operation.

0 DFDIF interrupt disabled

1 An interrupt will be requested whenever the DFDIF ﬂag is set (see Section 19.3.2.8)

SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault

is detected during a Flash block read operation.

0 SFDIF interrupt disabled whenever the SFDIF ﬂag is set (see Section 19.3.2.8)

1 An interrupt will be requested whenever the SFDIF ﬂag is set (see Section 19.3.2.8)

Offset Module Base + 0x0006

76543210

RCCIF 0ACCERR FPVIOL MGBUSY RSVD MGSTAT[1:0]

Reset 1000000

1Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 19.6).

= Unimplemented or Reserved

Figure 19-11. Flash Status Register (FSTAT)

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19.3.2.8 Flash Error Status Register (FERSTAT)

The FERSTAT register reﬂects the error status of internal Flash operations.

All ﬂags in the FERSTAT register are readable and only writable to clear the ﬂag.

Table 19-15. FSTAT Field Descriptions

Field Description

CCIF Command Complete Interrupt Flag — The CCIF ﬂag indicates that a Flash command has completed. The

CCIF ﬂag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command

completion or command violation.

0 Flash command in progress

1 Flash command has completed

ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory

caused by either a violation of the command write sequence (see Section 19.4.1.2) or issuing an illegal Flash

command. While ACCERR is set, the CCIF ﬂag cannot be cleared to launch a command. The ACCERR bit is

cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.

0 No access error detected

1 Access error detected

FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an

address in a protected area of P-Flash or D-Flash memory during a command write sequence. The FPVIOL

bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL

is set, it is not possible to launch a command or start a command write sequence.

0 No protection violation detected

1 Protection violation detected

MGBUSY Memory Controller Busy Flag — The MGBUSY ﬂag reﬂects the active state of the Memory Controller.

0 Memory Controller is idle

1 Memory Controller is busy executing a Flash command (CCIF = 0)

RSVD Reserved Bit — This bit is reserved and always reads 0.

1–0

MGSTAT[1:0] Memory Controller Command Completion Status Flag — One or more MGSTAT ﬂag bits are set if an error

is detected during execution of a Flash command or during the Flash reset sequence. See Section 19.4.2,

“Flash Command Description,” and Section 19.6, “Initialization” for details.

Offset Module Base + 0x0007

76543210

R000000

DFDIF SFDIF

Reset 00000000

= Unimplemented or Reserved

Figure 19-12. Flash Error Status Register (FERSTAT)

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19.3.2.9 P-Flash Protection Register (FPROT)

The FPROT register defines which P-Flash sectors are protected against program and erase operations.

The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected

region can only be increased (see Section 19.3.2.9.1, “P-Flash Protection Restrictions,” and Table 19-21).

During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte

in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see Table 19-3)

as indicated by reset condition ‘F’ in Figure 19-13. To change the P-Flash protection that will be loaded

during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash

protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase

containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and

remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.

Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error

and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible

if any of the P-Flash sectors contained in the same P-Flash block are protected.

Table 19-16. FERSTAT Field Descriptions

Field Description

DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF ﬂag indicates that a double bit fault was

detectedinthestoredparity and data bits duringaFlasharray read operation or that a Flash arrayread operation

was attempted on a Flash block that was under a Flash command operation. The DFDIF ﬂag is cleared by writing

a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.

0 No double bit fault detected

1 Double bit fault detected or an invalid Flash array read operation attempted

SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF ﬂag

indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation

or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.

The SFDIF ﬂag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.

0 No single bit fault detected

1 Single bit fault detected and corrected or an invalid Flash array read operation attempted

Offset Module Base + 0x0008

76543210

RFPOPEN RNV6 FPHDIS FPHS[1:0] FPLDIS FPLS[1:0]

Reset F F FFFFFF

= Unimplemented or Reserved

Figure 19-13. Flash Protection Register (FPROT)

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Table 19-17. FPROT Field Descriptions

Field Description

FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or

erase operations as shown in Table 19-18 for the P-Flash block.

0 When FPOPEN is clear, the FPHDIS and FPLDIS bits deﬁne unprotected address ranges as speciﬁed by the

corresponding FPHS and FPLS bits

1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range speciﬁed by the

corresponding FPHS and FPLS bits

RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.

FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a

protected/unprotected area in a speciﬁc region of the P-Flash memory ending with global address 0x7F_FFFF.

0 Protection/Unprotection enabled

1 Protection/Unprotection disabled

4–3

FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area

in P-Flash memory as shown inTable 19-19. The FPHS bits can only be written to while the FPHDIS bit is set.

FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a

protected/unprotected area in a speciﬁc region of the P-Flash memory beginning with global address

0x7F_8000.

0 Protection/Unprotection enabled

1 Protection/Unprotection disabled

1–0

FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area

in P-Flash memory as shown in Table 19-20. The FPLS bits can only be written to while the FPLDIS bit is set.

Table 19-18. P-Flash Protection Function

FPOPEN FPHDIS FPLDIS Function1

1For range sizes, refer to Table 19-19 and Table 19-20.

1 1 1 No P-Flash Protection

1 1 0 Protected Low Range

1 0 1 Protected High Range

1 0 0 Protected High and Low Ranges

0 1 1 Full P-Flash Memory Protected

0 1 0 Unprotected Low Range

0 0 1 Unprotected High Range

0 0 0 Unprotected High and Low Ranges

Table 19-19. P-Flash Protection Higher Address Range

FPHS[1:0] Global Address Range Protected Size

00 0x7F_F800–0x7F_FFFF 2 Kbytes

01 0x7F_F000–0x7F_FFFF 4 Kbytes

10 0x7F_E000–0x7F_FFFF 8 Kbytes

11 0x7F_C000–0x7F_FFFF 16 Kbytes

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576 Freescale Semiconductor

All possible P-Flash protection scenarios are shown in Figure 19-14. Although the protection scheme is

loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed

by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single

chip mode while providing as much protection as possible if reprogramming is not required.

Table 19-20. P-Flash Protection Lower Address Range

FPLS[1:0] Global Address Range Protected Size

00 0x7F_8000–0x7F_83FF 1 Kbyte

01 0x7F_8000–0x7F_87FF 2 Kbytes

10 0x7F_8000–0x7F_8FFF 4 Kbytes

11 0x7F_8000–0x7F_9FFF 8 Kbytes

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Figure 19-14. P-Flash Protection Scenarios

7654

FPHS[1:0] FPLS[1:0]

3210

FPHS[1:0] FPLS[1:0]

FPHDIS = 1

FPLDIS = 1

FPHDIS = 1

FPLDIS = 0

FPHDIS = 0

FPLDIS = 1

FPHDIS = 0

FPLDIS = 0

Scenario

Unprotected region Protected region with size

Protected region Protected region with size

defined by FPLS

defined by FPHSnot defined by FPLS, FPHS

0x7F_8000

0x7F_FFFF

0x7F_8000

0x7F_FFFF

FLASH START

FPOPEN = 1FPOPEN = 0

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578 Freescale Semiconductor

19.3.2.9.1 P-Flash Protection Restrictions

The general guideline is that P-Flash protection can only be added and not removed. Table 19-21 specifies

all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the

FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.

See the FPHS and FPLS bit descriptions for additional restrictions.

19.3.2.10 D-Flash Protection Register (DFPROT)

The DFPROT register deﬁnes which D-Flash sectors are protected against program and erase operations.

The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added

but not removed. Writes must increase the DPS value and the DPOEN bit can only be written from 1

(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is

irrelevant.

During the reset sequence, the DFPROT register is loaded with the contents of the D-Flash protection byte

in the Flash configuration field at global address 0x7F_FF0D located in P-Flash memory (see Table 19-3)

as indicated by reset condition F in Figure 19-15. To change the D-Flash protection that will be loaded

during the reset sequence, the P-Flash sector containing the D-Flash protection byte must be unprotected,

then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the

Table 19-21. P-Flash Protection Scenario Transitions

From

Protection

Scenario

To Protection Scenario1

1Allowed transitions marked with X, see Figure 19-14 for a deﬁnition of the scenarios.

01234567

0XXXX

1XX

2XX

4XX

5XXXX

6XXXX

7XXXXXXXX

Offset Module Base + 0x0009

76543210

RDPOPEN 00 DPS[4:0]

Reset F 0 0 FFFFF

= Unimplemented or Reserved

Figure 19-15. D-Flash Protection Register (DFPROT)

128 KByte Flash Module (S12XFTMR128K1V1)

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P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be

cleared and DPS bits will be set to leave the D-Flash memory fully protected.

Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error

and the FPVIOL bit will be set in the FSTAT register. Block erase of the D-Flash memory is not possible

if any of the D-Flash sectors are protected.

Table 19-22. DFPROT Field Descriptions

Field Description

DPOPEN D-Flash Protection Control

0 Enables D-Flash memory protection from program and erase with protected address range deﬁned by DPS

bits

1 Disables D-Flash memory protection from program and erase

4–0

DPS[4:0] D-Flash Protection Size — The DPS[4:0] bits determine the size of the protected area in the D-Flash memory

as shown in Table 19-23.

Table 19-23. D-Flash Protection Address Range

DPS[4:0] Global Address Range Protected Size

0_0000 0x10_0000 – 0x10_00FF 256 bytes

0_0001 0x10_0000 – 0x10_01FF 512 bytes

0_0010 0x10_0000 – 0x10_02FF 768 bytes

0_0011 0x10_0000 – 0x10_03FF 1024 bytes

0_0100 0x10_0000 – 0x10_04FF 1280 bytes

0_0101 0x10_0000 – 0x10_05FF 1536 bytes

0_0110 0x10_0000 – 0x10_06FF 1792 bytes

0_0111 0x10_0000 – 0x10_07FF 2048 bytes

0_1000 0x10_0000 – 0x10_08FF 2304 bytes

0_1001 0x10_0000 – 0x10_09FF 2560 bytes

0_1010 0x10_0000 – 0x10_0AFF 2816 bytes

0_1011 0x10_0000 – 0x10_0BFF 3072 bytes

0_1100 0x10_0000 – 0x10_0CFF 3328 bytes

0_1101 0x10_0000 – 0x10_0DFF 3584 bytes

0_1110 0x10_0000 – 0x10_0EFF 3840 bytes

0_1111 0x10_0000 – 0x10_0FFF 4096 bytes

1_0000 0x10_0000 – 0x10_10FF 4352 bytes

1_0001 0x10_0000 – 0x10_11FF 4608 bytes

1_0010 0x10_0000 – 0x10_12FF 4864 bytes

1_0011 0x10_0000 – 0x10_13FF 5120 bytes

1_0100 0x10_0000 – 0x10_14FF 5376 bytes

1_0101 0x10_0000 – 0x10_15FF 5632 bytes

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580 Freescale Semiconductor

19.3.2.11 Flash Common Command Object Register (FCCOB)

The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.

Byte wide reads and writes are allowed to the FCCOB register.

19.3.2.11.1 FCCOB - NVM Command Mode

NVM command mode uses the indexed FCCOB register to provide a command code and its relevant

parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates

the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user

clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register

all FCCOB parameter fields are locked and cannot be changed by the user until the command completes

1_0110 0x10_0000 – 0x10_16FF 5888 bytes

1_0111 0x10_0000 – 0x10_17FF 6144 bytes

1_1000 0x10_0000 – 0x10_18FF 6400 bytes

1_1001 0x10_0000 – 0x10_19FF 6656 bytes

1_1010 0x10_0000 – 0x10_1AFF 6912 bytes

1_1011 0x10_0000 – 0x10_1BFF 7168 bytes

1_1100 0x10_0000 – 0x10_1CFF 7424 bytes

1_1101 0x10_0000 – 0x10_1DFF 7680 bytes

1_1110 0x10_0000 – 0x10_1EFF 7936 bytes

1_1111 0x10_0000 – 0x10_1FFF 8192 bytes

Offset Module Base + 0x000A

76543210

RCCOB[15:8]

Reset 00000000

Figure 19-16. Flash Common Command Object High Register (FCCOBHI)

Offset Module Base + 0x000B

76543210

RCCOB[7:0]

Reset 00000000

Figure 19-17. Flash Common Command Object Low Register (FCCOBLO)

Table 19-23. D-Flash Protection Address Range

DPS[4:0] Global Address Range Protected Size

128 KByte Flash Module (S12XFTMR128K1V1)

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(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the

FCCOB register array.

The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 19-24.

The return values are available for reading after the CCIF flag in the FSTAT register has been returned to

1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX

= 111) are ignored with reads from these fields returning 0x0000.

Table 19-24 shows the generic Flash command format. The high byte of the first word in the CCOB array

contains the command code, followed by the parameters for this specific Flash command. For details on

the FCCOB settings required by each command, see the Flash command descriptions in Section 19.4.2.

19.3.2.12 Flash Reserved0 Register (FRSV0)

This Flash register is reserved for factory testing.

All bits in the FRSV0 register read 0 and are not writable.

Table 19-24. FCCOB - NVM Command Mode (Typical Usage)

CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode)

000 HI FCMD[7:0] deﬁning Flash command

LO 0, Global address [22:16]

001 HI Global address [15:8]

LO Global address [7:0]

010 HI Data 0 [15:8]

LO Data 0 [7:0]

011 HI Data 1 [15:8]

LO Data 1 [7:0]

100 HI Data 2 [15:8]

LO Data 2 [7:0]

101 HI Data 3 [15:8]

LO Data 3 [7:0]

Offset Module Base + 0x000C

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 19-18. Flash Reserved0 Register (FRSV0)

128 KByte Flash Module (S12XFTMR128K1V1)

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582 Freescale Semiconductor

19.3.2.13 Flash Reserved1 Register (FRSV1)

This Flash register is reserved for factory testing.

All bits in the FRSV1 register read 0 and are not writable.

19.3.2.14 Flash ECC Error Results Register (FECCR)

The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.

The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits

in the FECCRIX register (see Section 19.3.2.4). Once ECC fault information has been stored, no other

fault information will be recorded until the specific ECC fault flag has been cleared. In the event of

simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.

All FECCR bits are readable but not writable.

Offset Module Base + 0x000D

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 19-19. Flash Reserved1 Register (FRSV1)

Offset Module Base + 0x000E

76543210

R ECCR[15:8]

Reset 00000000

= Unimplemented or Reserved

Figure 19-20. Flash ECC Error Results High Register (FECCRHI)

Offset Module Base + 0x000F

76543210

R ECCR[7:0]

Reset 00000000

= Unimplemented or Reserved

Figure 19-21. Flash ECC Error Results Low Register (FECCRLO)

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The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The

following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four

data words and the parity byte are the uncorrected data read from the P-Flash block.

The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The

uncorrected 16-bit data word is addressed by ECCRIX = 010.

19.3.2.15 Flash Option Register (FOPT)

The FOPT register is the Flash option register.

All bits in the FOPT register are readable but are not writable.

Table 19-25. FECCR Index Settings

ECCRIX[2:0] FECCR Register Content

Bits [15:8] Bit[7] Bits[6:0]

000 Parity bits read from

Flash block 0Global address

[22:16]

001 Global address [15:0]

010 Data 0 [15:0]

011 Data 1 [15:0] (P-Flash only)

100 Data 2 [15:0] (P-Flash only)

101 Data 3 [15:0] (P-Flash only)

110 Not used, returns 0x0000 when read

111 Not used, returns 0x0000 when read

Table 19-26. FECCR Index=000 Bit Descriptions

Field Description

15:8

PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,

allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.

6–0

GADDR[22:16] Global Address — The GADDR[22:16] ﬁeld contains the upper seven bits of the global address having

caused the error.

Offset Module Base + 0x0010

76543210

R NV[7:0]

Reset F F FFFFFF

= Unimplemented or Reserved

Figure 19-22. Flash Option Register (FOPT)

128 KByte Flash Module (S12XFTMR128K1V1)

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During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash

configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 19-3) as indicated

by reset condition F in Figure 19-22. If a double bit fault is detected while reading the P-Flash phrase

containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.

19.3.2.16 Flash Reserved2 Register (FRSV2)

This Flash register is reserved for factory testing.

All bits in the FRSV2 register read 0 and are not writable.

19.3.2.17 Flash Reserved3 Register (FRSV3)

This Flash register is reserved for factory testing.

All bits in the FRSV3 register read 0 and are not writable.

19.3.2.18 Flash Reserved4 Register (FRSV4)

This Flash register is reserved for factory testing.

Table 19-27. FOPT Field Descriptions

Field Description

7–0

NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper

use of the NV bits.

Offset Module Base + 0x0011

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 19-23. Flash Reserved2 Register (FRSV2)

Offset Module Base + 0x0012

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 19-24. Flash Reserved3 Register (FRSV3)

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All bits in the FRSV4 register read 0 and are not writable.

19.4 Functional Description

19.4.1 Flash Command Operations

Flash command operations are used to modify Flash memory contents.

The next sections describe:

• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from

OSCCLK for Flash program and erase command operations

• The command write sequence used to set Flash command parameters and launch execution

• Valid Flash commands available for execution

19.4.1.1 Writing the FCLKDIV Register

Prior to issuing any Flash program or erase command after a reset, the user is required to write the

FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 19-7 shows recommended

values for the FDIV ﬁeld based on OSCCLK frequency.

NOTE

Programming or erasing the Flash memory cannot be performed if the bus

clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash

memory due to overstress. Setting FDIV too low can result in incomplete

programming or erasure of the Flash memory cells.

When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the

FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,

any Flash program or erase command loaded during a command write sequence will not execute and the

ACCERR bit in the FSTAT register will set.

Offset Module Base + 0x0013

76543210

R00000000

Reset 00000000

= Unimplemented or Reserved

Figure 19-25. Flash Reserved4 Register (FRSV4)

128 KByte Flash Module (S12XFTMR128K1V1)

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586 Freescale Semiconductor

19.4.1.2 Command Write Sequence

The Memory Controller will launch all valid Flash commands entered using a command write sequence.

Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see

Section 19.3.2.7) and the CCIF flag should be tested to determine the status of the current command write

sequence. If CCIF is 0, the previous command write sequence is still active, a new command write

sequence cannot be started, and all writes to the FCCOB register are ignored.

CAUTION

Writes to any Flash register must be avoided while a Flash command is

active (CCIF=0) to prevent corruption of Flash register contents and

Memory Controller behavior.

19.4.1.2.1 Deﬁne FCCOB Contents

The FCCOB parameter ﬁelds must be loaded with all required parameters for the Flash command being

executed. Access to the FCCOB parameter ﬁelds is controlled via the CCOBIX bits in the FCCOBIX

The contents of the FCCOB parameter ﬁelds are transferred to the Memory Controller when the user clears

the CCIF command completion ﬂag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF ﬂag

will remain clear until the Flash command has completed. Upon completion, the Memory Controller will

return CCIF to 1 and the FCCOB register will be used to communicate any results. The ﬂow for a generic

command write sequence is shown in Figure 19-26.

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Figure 19-26. Generic Flash Command Write Sequence Flowchart

Write to FCCOBIX register

Write: FSTAT register (to launch command)

Clear CCIF 0x80

Clear ACCERR/FPVIOL 0x30

Write: FSTAT register

yes

Access Error and

Protection Violation

Read: FSTAT register

START

yes

Check

CCIF

Set?

FCCOB

ACCERR/

FPVIOL

Set?

EXIT

Write: FCLKDIV register

Read: FCLKDIV register

yes

Clock Register

Written

Check

FDIVLD

Set?

Bit Polling for

Command Completion

Check

yes

CCIF Set?

to identify speciﬁc command

parameter to load.

Write to FCCOB register

to load required command parameter.

yes

Parameters?

Availability Check

Results from previous Command

Note: FCLKDIV must be set after

each reset

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19.4.1.3 Valid Flash Module Commands

19.4.1.4 P-Flash Commands

Table 19-29 summarizes the valid P-Flash commands along with the effects of the commands on the

P-Flash block and other resources within the Flash module.

Table 19-28. Flash Commands by Mode

FCMD Command Unsecured Secured

NS1

1Unsecured Normal Single Chip mode.

NX2

2Unsecured Normal Expanded mode.

SS3

3Unsecured Special Single Chip mode.

ST4

4Unsecured Special Mode.

NS5

5Secured Normal Single Chip mode.

NX6

6Secured Normal Expanded mode.

SS7

7Secured Special Single Chip mode.

ST8

8Secured Special Mode.

0x01 Erase Verify All Blocks ∗∗∗∗∗∗∗∗

0x02 Erase Verify Block ∗∗∗∗∗∗∗∗

0x03 Erase Verify P-Flash Section ∗∗∗∗∗

0x04 Read Once ∗∗∗∗∗

0x06 Program P-Flash ∗∗∗∗∗

0x07 Program Once ∗∗∗∗∗

0x08 Erase All Blocks ∗∗ ∗∗

0x09 Erase Flash Block ∗∗∗∗∗

0x0A Erase P-Flash Sector ∗∗∗∗∗

0x0B Unsecure Flash ∗∗ ∗∗

0x0C Verify Backdoor Access Key ∗∗

0x0D Set User Margin Level ∗∗∗∗∗

0x0E Set Field Margin Level ∗∗

0x10 Erase Verify D-Flash Section ∗∗∗∗∗

0x11 Program D-Flash ∗∗∗∗∗

0x12 Erase D-Flash Sector ∗∗∗∗∗

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19.4.1.5 D-Flash Commands

Table 19-30 summarizes the valid D-Flash commands along with the effects of the commands on the

D-Flash block.

Table 19-29. P-Flash Commands

FCMD Command Function on P-Flash Memory

0x01 Erase Verify All

Blocks Verify that all P-Flash (and D-Flash) blocks are erased.

0x02 Erase Verify Block Verify that a P-Flash block is erased.

0x03 Erase Verify

P-Flash Section Verify that a given number of words starting at the address provided are erased.

0x04 Read Once Read a dedicated 64 byte ﬁeld in the nonvolatile information register in P-Flash block 0

that was previously programmed using the Program Once command.

0x06 Program P-Flash Program a phrase in a P-Flash block.

0x07 Program Once Program a dedicated 64 byte ﬁeld in the nonvolatile information register in P-Flash block

0 that is allowed to be programmed only once.

0x08 Erase All Blocks

Erase all P-Flash (and D-Flash) blocks.

An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN

bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to

launching the command.

0x09 Erase Flash Block Erase a P-Flash (or D-Flash) block.

An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN

bits in the FPROT register are set prior to launching the command.

0x0A Erase P-Flash

Sector Erase all bytes in a P-Flash sector.

0x0B Unsecure Flash Supports amethod ofreleasingMCU security byerasingallP-Flash (andD-Flash)blocks

and verifying that all P-Flash (and D-Flash) blocks are erased.

0x0C Verify Backdoor

Access Key Supports a method of releasing MCU security by verifying a set of security keys.

0x0D Set User Margin

Level Speciﬁes a user margin read level for all P-Flash blocks.

0x0E Set Field Margin

Level Speciﬁes a ﬁeld margin read level for all P-Flash blocks (special modes only).

Table 19-30. D-Flash Commands

FCMD Command Function on D-Flash Memory

0x01 Erase Verify All

Blocks Verify that all D-Flash (and P-Flash) blocks are erased.

0x02 Erase Verify Block Verify that the D-Flash block is erased.

0x08 Erase All Blocks

Erase all D-Flash (and P-Flash) blocks.

An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN

bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to

launching the command.

0x09 Erase Flash Block Erase a D-Flash (or P-Flash) block.

An erase of the full D-Flash block is only possible when DPOPEN bit in the DFPROT

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19.4.2 Flash Command Description

This section provides details of all available Flash commands launched by a command write sequence. The

ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following

illegal steps are performed, causing the command not to be processed by the Memory Controller:

• Starting any command write sequence that programs or erases Flash memory before initializing the

FCLKDIV register

• Writing an invalid command as part of the command write sequence

• For additional possible errors, refer to the error handling table provided for each command

If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation

will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read

operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded

with the global address used in the invalid read operation with the data and parity fields set to all 0.

If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting

any command write sequence (see Section 19.3.2.7).

CAUTION

A Flash word or phrase must be in the erased state before being

programmed. Cumulative programming of bits within a Flash word or

phrase is not allowed.

19.4.2.1 Erase Verify All Blocks Command

The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.

0x0B Unsecure Flash Supportsamethodof releasingMCU security byerasingallD-Flash(andP-Flash)blocks

and verifying that all D-Flash (and P-Flash) blocks are erased.

0x0D Set User Margin

Level Speciﬁes a user margin read level for the D-Flash block.

0x0E Set Field Margin

Level Speciﬁes a ﬁeld margin read level for the D-Flash block (special modes only).

0x10 Erase Verify

D-Flash Section Verify that a given number of words starting at the address provided are erased.

0x11 Program D-Flash Program up to four words in the D-Flash block.

0x12 Erase D-Flash

Sector Erase all bytes in a sector of the D-Flash block.

Table 19-31. Erase Verify All Blocks Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x01 Not required

Table 19-30. D-Flash Commands

FCMD Command Function on D-Flash Memory

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Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify

that the entire Flash memory space is erased. The CCIF ﬂag will set after the Erase Verify All Blocks

operation has completed.

19.4.2.2 Erase Verify Block Command

The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been

erased. The FCCOB upper global address bits determine which block must be veriﬁed.

Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that

the selected P-Flash or D-Flash block is erased. The CCIF ﬂag will set after the Erase Verify Block

operation has completed.

19.4.2.3 Erase Verify P-Flash Section Command

The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is

erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and

the number of phrases. The section to be verified cannot cross a 128 Kbyte boundary in the P-Flash

memory space.

Table 19-32. Erase Verify All Blocks Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 19-33. Erase Verify Block Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x02 Global address [22:16] of the

Flash block to be veriﬁed.

Table 19-34. Erase Verify Block Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

Set if an invalid global address [22:16] is supplied

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

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Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will

verify the selected section of Flash memory is erased. The CCIF ﬂag will set after the Erase Verify P-Flash

Section operation has completed.

19.4.2.4 Read Once Command

The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the

nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the

Program Once command described in Section 19.4.2.6. The Read Once command must not be executed

from the Flash block containing the Program Once reserved field to avoid code runaway.

Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the

FCCOB indexed register. The CCIF ﬂag will set after the Read Once operation has completed. Valid

Table 19-35. Erase Verify P-Flash Section Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x03 Global address [22:16] of

a P-Flash block

001 Global address [15:0] of the ﬁrst phrase to be veriﬁed

010 Number of phrases to be veriﬁed

Table 19-36. Erase Verify P-Flash Section Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 010 at command launch

Set if command not available in current mode (see Table 19-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned phrase address is supplied (global address [2:0] != 000)

Set if the requested section crosses a 128 Kbyte boundary

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 19-37. Read Once Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x04 Not Required

001 Read Once phrase index (0x0000 - 0x0007)

010 Read Once word 0 value

011 Read Once word 1 value

100 Read Once word 2 value

101 Read Once word 3 value

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phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the

Read Once command, any attempt to read addresses within P-Flash block will return invalid data.

19.4.2.5 Program P-Flash Command

The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an

embedded algorithm.

CAUTION

A P-Flash phrase must be in the erased state before being programmed.

Cumulative programming of bits within a Flash phrase is not allowed.

Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the

data words to the supplied global address and will then proceed to verify the data words read back as

expected. The CCIF ﬂag will set after the Program P-Flash operation has completed.

Table 19-38. Read Once Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 19-28)

Set if an invalid phrase index is supplied

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the read

MGSTAT0 Set if any non-correctable errors have been encountered during the read

Table 19-39. Program P-Flash Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x06 Global address [22:16] to

identify P-Flash block

001 Global address [15:0] of phrase location to be programmed1

1Global address [2:0] must be 000

010 Word 0 program value

011 Word 1 program value

100 Word 2 program value

101 Word 3 program value

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19.4.2.6 Program Once Command

The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the

nonvolatile information register located in P-Flash block 0. The Program Once reserved field can be read

using the Read Once command as described in Section 19.4.2.4. The Program Once command must only

be issued once since the nonvolatile information register in P-Flash block 0 cannot be erased. The Program

Once command must not be executed from the Flash block containing the Program Once reserved field to

avoid code runaway.

Upon clearing CCIF to launch the Program Once command, the Memory Controller ﬁrst veriﬁes that the

selected phrase is erased. If erased, then the selected phrase will be programmed and then veriﬁed with

read back. The CCIF ﬂag will remain clear, setting only after the Program Once operation has completed.

The reserved nonvolatile information register accessed by the Program Once command cannot be erased

and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index

values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program

Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.

Table 19-40. Program P-Flash Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 101 at command launch

Set if command not available in current mode (see Table 19-28)

Set if an invalid global address [22:0] is supplied

Set if a misaligned phrase address is supplied (global address [2:0] != 000)

FPVIOL Set if the global address [22:0] points to a protected area

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 19-41. Program Once Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x07 Not Required

001 Program Once phrase index (0x0000 - 0x0007)

010 Program Once word 0 value

011 Program Once word 1 value

100 Program Once word 2 value

101 Program Once word 3 value

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19.4.2.7 Erase All Blocks Command

The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space.

Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire

Flash memory space and verify that it is erased. If the Memory Controller veriﬁes that the entire Flash

memory space was properly erased, security will be released. During the execution of this command

(CCIF=0) the user must not write to any Flash module register. The CCIF ﬂag will set after the Erase All

Blocks operation has completed.

19.4.2.8 Erase Flash Block Command

The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block.

Table 19-42. Program Once Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 101 at command launch

Set if command not available in current mode (see Table 19-28)

Set if an invalid phrase index is supplied

Set if the requested phrase has already been programmed1

1If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will

be allowed to execute again on that same phrase.

FPVIOL None

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 19-43. Erase All Blocks Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x08 Not required

Table 19-44. Erase All Blocks Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

Set if command not available in current mode (see Table 19-28)

FPVIOL Set if any area of the P-Flash or D-Flash memory is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

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Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the

selected Flash block and verify that it is erased. The CCIF ﬂag will set after the Erase Flash Block

operation has completed.

19.4.2.9 Erase P-Flash Sector Command

The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.

Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the

selected Flash sector and then verify that it is erased. The CCIF ﬂag will be set after the Erase P-Flash

Sector operation has completed.

Table 19-45. Erase Flash Block Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x09 Global address [22:16] to

identify Flash block

001 Global address [15:0] in Flash block to be erased

Table 19-46. Erase Flash Block Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 19-28)

Set if an invalid global address [22:16] is supplied

Set if the supplied P-Flash address is not phrase-aligned or if the D-Flash

address is not word-aligned

FPVIOL Set if an area of the selected Flash block is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 19-47. Erase P-Flash Sector Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0A Global address [22:16] to identify

P-Flash block to be erased

001 Global address [15:0] anywhere within the sector to be erased.

Refer to Section 19.1.2.1 for the P-Flash sector size.

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19.4.2.10 Unsecure Flash Command

The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is

successful, will release security.

Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire

P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller veriﬁes that the

entire Flash memory space was properly erased, security will be released. If the erase verify is not

successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security

state. During the execution of this command (CCIF=0) the user must not write to any Flash module

19.4.2.11 Verify Backdoor Access Key Command

The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the

FSEC register (see Table 19-9). The Verify Backdoor Access Key command releases security if

user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see

Table 19-48. Erase P-Flash Sector Command Error Handling

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see Table 19-28)

Set if an invalid global address [22:16] is supplied

Set if a misaligned phrase address is supplied (global address [2:0] != 000)

FPVIOL Set if the selected P-Flash sector is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

Table 19-49. Unsecure Flash Command FCCOB Requirements

CCOBIX[2:0] FCCOB Parameters

000 0x0B Not required

Table 19-50. Unsecure Flash Command Error Handling

FSTAT

ACCERR Set if CCOBIX[2:0] != 000 at command launch

Set if command not available in current mode (see Table 19-28)

FPVIOL Set if any area of the P-Flash or D-Flash memory is protected

MGSTAT1 Set if any errors have been encountered during the verify operation

MGSTAT0 Set if any non-correctable errors have been encountered during the verify

operation

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Table 19-3). The Verify Backdoor Access Key command must not be executed from the Flash block