PH7530CL,115 - NXP SEMICONDUCTORS

PH7030AL

N-channel TrenchMOS logic level FET

Rev. 03 — 12 January 2010 Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing and consumer applications.

1.2 Features and benefits

High efficiency due to low switching

and conduction losses

Suitable for logic level gate drive

sources

1.3 Applications

Consumer applications

Desktop Voltage Regulator Module

(VRM)

Notebook Voltage Regulator Module

(VRM)

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤175 °C - - 30 V

IDdrain current Tmb =25°C; V

GS =10V;

see Figure 1 --76A

Ptot total power

dissipation Tmb = 25 °C; see Figure 2 --51W

Dynamic characteristics

QGD gate-drain charge VGS = 4.5 V; ID=10A;

VDS = 12 V; see Figure 14

and 15

-2.9-nC

QG(tot) total gate charge - 10 - nC

Static characteristics

RDSon drain-source

on-state resistance VGS =10V; I

D=15A;

Tj=25°C -4.97mΩ

Product data sheet Rev. 03 — 12 January 2010 2 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

2. Pinning information

3. Ordering information

4. Limiting values

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S source

SOT669 (LFPAK)

2S source

3S source

4G gate

mb D mounting base; connected to

drain

1234

bb076

Table 3. Orderi ng informatio n

Type number Package

Name Description Version

PH7030AL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

Table 4. Limiting values

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤175 °C - 30 V

VDGR drain-gate voltage Tj≥25 °C; Tj≤175 °C; RGS =20kΩ-30V

VGS gate-source voltage -20 20 V

IDdrain current VGS =10V; T

mb = 100 °C; see Figure 1 -53A

VGS =10V; T

mb =25°C; see Figure 1 -76A

IDM peak drain current tp≤10 µs; pulsed; Tmb =25°C; see Figure 3 -260A

Ptot total power dissipation Tmb =25°C; see Figure 2 -51W

Tstg storage temperature -55 175 °C

Tjjunction temperature -55 175 °C

Source-drain diode

ISsource current Tmb =25°C - 65 A

ISM peak source current tp≤10 µs; pulsed; Tmb =25°C - 260 A

Avalanche rugg edness

EDS(AL)S non-repetitive

drain-source avalanche

energy

VGS =10V; T

j(init) =25°C; I

D=65A; V

sup ≤30 V;

RGS =50Ω; unclamped -21mJ

Product data sheet Rev. 03 — 12 January 2010 3 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

Fig 1. Continuous drain current as a function of

mounting base temperature Fig 2. Normalized total power dissipation as a

function of mounting base temperature

Fig 3. Safe operating area; continuous and pe ak drain currents as a function of drain -s ou rce voltage

003aac720

100

0 50 100 150 200

(°C)

(A)

Tmb (°C)

0 20015050 100

03aa16

120

Pder

(%)

003aac732

-1

1 10 10

(V)

(A)

Limit R

DSon

= V

/ I

100 ms

10 ms

1 ms

100 μs

10 μs

Product data sheet Rev. 03 — 12 January 2010 4 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to

mounting base see Figure 4 - 1.4 2.45 K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

003aac721

single shot

0.2

0.1

0.05

0.02

-2

-1

-6

-5

-4

-3

-2

-1

(s)

th(j-mb)

(K/W)

δ = 0.5

δ =

Product data sheet Rev. 03 — 12 January 2010 5 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source

breakdown voltage ID=20A; V

GS =0V; T

j=25°C; t

av = 100 ns 35 - - V

ID=250µA; V

GS =0V; T

j=25°C 30 - - V

ID=250µA; V

GS =0V; T

j=-55°C 27 - - V

VGS(th) gate-source threshold

voltage ID=1mA; V

DS = VGS; Tj=25°C;

see Figure 11 and 12 1.3 1.7 2.15 V

ID=1mA; V

DS = VGS; Tj= 150 °C;

see Figure 12 0.65 - - V

ID=1mA; V

DS = VGS; Tj=-55°C;

see Figure 12 --2.45V

IDSS drain leakage current VDS =30V; V

GS =0V; T

j=25°C --1µA

VDS =30V; V

GS =0V; T

j= 150 °C - - 100 µA

IGSS gate leakage current VGS =16V; V

DS =0V; T

j= 25 °C - - 100 nA

VGS =-16V; V

DS =0V; T

j= 25 °C - - 100 nA

RDSon drain-source on-state

resistance VGS =4.5V; I

D=15A; T

j= 25 °C - 6.97 9.1 mΩ

VGS =10V; I

D=15A; T

j= 150 °C;

see Figure 13 --12.2mΩ

VGS =10V; I

D=15A; T

j=25°C - 4.9 7 mΩ

RGgate resistance f = 1 MHz - 0.6 1.5 Ω

Dynamic character i stics

QG(tot) total gate charge ID=10A; V

DS =12V; V

GS =4.5V;

see Figure 14 and 15 -10-nC

ID=0A; V

DS =0V; V

GS =10V - 20 - nC

ID=10A; V

DS =12V; V

GS =10V;

see Figure 14 and 15 -22-nC

QGS gate-source charge ID=10A; V

DS =12V; V

GS =4.5V;

see Figure 14 and 15 -3.7-nC

QGS(th) pre-threshold

gate-source charge -2.1-nC

QGS(th-pl) post-threshold

gate-source charge -1.6-nC

QGD gate-drain charge - 2.9 - nC

VGS(pl) gate-source plateau

voltage VDS =12V; see Figure 14 and 15 -2.6-V

Ciss input capacitance VDS =12V; V

GS =0V; f=1MHz; T

j=25°C;

see Figure 16 - 1270 - pF

Coss output capacitance - 255 - pF

Crss reverse transfer

capacitance - 145 - pF

td(on) turn-on delay time VDS =12V; R

L=0.5Ω; VGS =4.5V;

RG(ext) =4.7Ω

-24-ns

trrise time - 39 - ns

td(off) turn-off delay time - 30 - ns

tffall time - 11 - ns

Product data sheet Rev. 03 — 12 January 2010 6 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

[1] Tested to JEDEC standards where applicable.

Source-drain diode

VSD source-drain voltage IS=25A; V

GS =0V; T

j=25°C;

see Figure 17 - 0.88 1.2 V

trr reverse recovery time IS=20A; dI

S/dt = -100 A/µs; VGS =0V;

VDS =20V -30-ns

Qrrecovered charge - 22 - nC

Table 6. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit

Fig 5. Tran sfer characteristics: drain current as a

function of gate-source voltage; typical values Fig 6. Forward transconductance as a function of

drain current; typical values

Fig 7. Outp ut characteristics: drain current as a

function of drain-source voltage; typical values Fig 8. Input and reverse transfer capacitances as a

function of gate-source vo ltage; typical values

003aac729

01234

(V)

(A)

= 150 °C

25 °C

003aac728

010203040

(A)

(S)

003aac726

100

0246810

(V)

(A) V

(V) = 4.5

3.2

2.8

2.6

2.4

2.2

003aac724

500

1000

1500

2000

2500

0246810

(V)

(pF) C

iss

rss

Product data sheet Rev. 03 — 12 January 2010 7 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values Fig 10. Drain-source on-state resistance as a function

of gate-source voltage; typical values

Fig 11. Sub-threshold drain cu rrent as a function of

gate-source voltage Fig 12. Gate-source threshold voltage as a function of

junction temperature

003aac722

0 20406080100

(A)

DSon

(mΩ)

(V) = 4.5

3.2

003aac727

246810

(V)

DSon

(mΩ)

003aab271

10-6

10-5

10-4

10-3

10-2

10-1

0123

VGS (V)

(A)

maxtypmin

003aac337

-60 0 60 120 180

Tj (°C)

VGS(th)

(V)

max

typ

min

Product data sheet Rev. 03 — 12 January 2010 8 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

Fig 13. Normalized drain-source on-state resistance

factor as a function of junction temperature Fig 14. Gate charge wa ve form definitions

Fig 15. Gate-source voltage as a function of gate

charge; typical values Fig 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

03aa27

0.5

1.5

−60 0 60 120 180

Tj (°C)

003aaa508

VGS

VGS(th)

QGS1 QGS2

QGD

VDS

QG(tot)

QGS

VGS(pl)

003aac725

0 5 10 15 20 25

(nC)

(V)

= 19 (V)

= 12 (V)

003aac723

400

800

1200

1600

-1

1 10 10

(V)

(pF)

iss

oss

rss

Product data sheet Rev. 03 — 12 January 2010 9 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

Fig 17. Source ( dio de forwa r d) current as a functio n of source-drain (diode forward) voltage; typical values

003aac730

0.0 0.2 0.4 0.6 0.8 1.0

(V)

(A)

= 150 °C

25 °C

Product data sheet Rev. 03 — 12 January 2010 10 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

7. Package outline

Fig 18. Package outline SOT669 (LFPAK)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT669 MO-235 04-10-13

06-03-16

0 2.5 5 mm

scale

A2bcA e

UNIT

DIMENSIONS (mm are the original dimensions)

mm 1.10

0.95

0.15

0.00

1.20

1.01

0.50

0.35

4.41

3.62

2.2

2.0

0.9

0.7

0.25

0.19

0.30

0.24

4.10

3.80

6.2

5.8

1.3

0.8

0.85

0.40

1.3

0.8

8°

0°

D(1)

5.0

4.8

E(1)

3.3

3.1

E1(1)

D1(1)

max

0.25 4.20 1.27 0.25 0.1

1234

mounting

base

lastic single-ended surface-mounted package (LFPAK); 4 leads SOT66

1/2 e

(A )

detail X

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

Product data sheet Rev. 03 — 12 January 2010 11 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PH7030AL_3 20100112 Product data sheet - PH7030AL_2

Modifications: •Various changes to content.

PH7030AL_2 20090121 Product data sheet - PH7030AL_1

PH7030AL_1 20080819 Preliminary data sheet - -

Product data sheet Rev. 03 — 12 January 2010 12 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest pro duct

status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specifica t io n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

9.3 Disclaimers

Limited warranty and liability — Information in this document is be lieved to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applicati ons where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application /use or t he application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary

testing for the Application in order to avoid a def ault of the Applicat ion and the

product. NXP Semiconductors does not accept any liability in this respect.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property right s.

Document status [1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 03 — 12 January 2010 13 of 14

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

Export control — This document as well as the item(s) descri bed herein may

be subject to export control regulat i ons. Export might require a prior

authorization from national authorities.

Non-automotive qualified products — Unless the data sheet of an NXP

Semiconductors product expressly states that the product is automotive

qualified, the product is not suitable for automotive use. It is neither qualified

nor tested in accordan ce with a uto moti ve t estin g or ap plicat ion requiremen ts.

NXP Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in auto motive equipment or applications. In

the event that cust omer uses the product for design-in and use in automot ive

applications to automotive specifica tions and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive application s beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use of

the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

9.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PH7030AL

N-channel TrenchMOS logic level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 January 2010

Document identifier: PH7030AL_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

10 Contact information. . . . . . . . . . . . . . . . . . . . . .13