SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoStarand NanoFreePackages
D1.65-V to 5.5-V VCC Operation
DHigh On-Off Output Voltage Ratio
DHigh Degree of Linearity
DHigh Speed, Typically 0.5 ns (VCC = 3 V,
CL = 50 pF)
DLow On-State Resistance, Typically ≈6.5 Ω
(VCC = 4.5 V)
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G53 can handle both analog and digital signals. The device permits signals with amplitudes of
up to 5.5 V (peak) to be transmitted in either direction.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing f o r
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA SN74LVC2G53YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
SN74LVC2G53YZAR
_ _ _C4_
−40
°
C to 85
°
C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000 SN74LVC2G53YEPR _ _ _C4_
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free) SN74LVC2G53YZPR
SSOP − DCT Reel of 3000 SN74LVC2G53DCTR C53_ _ _
VSSOP − DCU
Reel of 3000 SN74LVC2G53DCUR
C53_
VSSOP − DCU
Reel of 250 SN74LVC2G53DCUT
C53_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, •= Pb-free).
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1
%$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (2, (,%&) $# ,3') ")(%+&,"()
)('"0'%0 4'%%'"(51 %$0+*(!$" -%$*,))!"6 0$,) "$( ",*,))'%!/5 !"*/+0,
(,)(!"6 $# '// -'%'&,(,%)1
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
COM
INH
GND
GND
VCC
Y1
Y2
A
4
3
2
1
5
6
7
8
GND
GND
INH
COM
A
Y2
Y1
VCC
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
NanoStar and NanoFree are trademarks of Texas Instruments.
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
CONTROL
INPUTS ON
CHANNEL
INH A
CHANNEL
L L Y1
LHY2
H X None
logic diagram (positive logic)
Y2
A
INH
Y1
COM
5
2
7
6
1
SW
SW
NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals can
be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.
simplified schematic, each switch (SW)
COM Y
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Notes 1 and 2) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state switch current, IT (VI/O = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 4): DCT package 220°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCU package 227°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA/YZA package 140°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 102°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 5)
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VI/O I/O port voltage 0 VCC V
VCC = 1.65 V to 1.95 V VCC × 0.65
VIH
High-level input voltage, control input
VCC = 2.3 V to 2.7 V VCC × 0.7
V
VIH High-level input voltage, control input VCC = 3 V to 3.6 V VCC × 0.7 V
VCC = 4.5 V to 5.5 V VCC × 0.7
VCC = 1.65 V to 1.95 V VCC ×0.35
VIL
Low-level input voltage, control input
VCC = 2.3 V to 2.7 V VCC ×0.3
V
VIL Low-level input voltage, control input VCC = 3 V to 3.6 V VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3
VIControl input voltage 0 5.5 V
VCC = 1.65 V to 1.95 V 20
∆t/∆v
Input transition rise/fall time
VCC = 2.3 V to 2.7 V 20
ns/V
∆t/∆vInput transition rise/fall time VCC = 3 V to 3.6 V 10 ns/V
VCC = 4.5 V to 5.5 V 10
TAOperating free-air temperature −40 85 °C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
V = V or GND,
IS = 4 mA 1.65 V 13 30
ron
On-state switch resistance
VI = VCC or GND,
VINH = VIL
IS = 8 mA 2.3 V 10 20
Ω
ron On-state switch resistance
ICC
V
INH
= V
IL
(see Figures 1 and 2)
IS = 24 mA 3 V 8.5 17 Ω
(see Figures 1 and 2)
IS = 32 mA 4.5 V 6.5 13
V = V to GND,
IS = 4 mA 1.65 V 86.5 120
ron(p)
Peak on-state resistance
VI = VCC to GND,
VINH = VIL
IS = 8 mA 2.3 V 23 30
Ω
ron(p) Peak on-state resistance
ICC
V
INH
= V
IL
(see Figures 1 and 2)
IS = 24 mA 3 V 13 20 Ω
(see Figures 1 and 2)
IS = 32 mA 4.5 V 8 15
V = V to GND,
IS = 4 mA 1.65 V 7
∆ron
Difference of on-state resistance
VI = VCC to GND,
VC = VIH
IS = 8 mA 2.3 V 5
Ω
∆ron
Difference of on-state resistance
between switches
ICC
V
C
= V
IH
(see Figures 1 and 2)
IS = 24 mA 3 V 3Ω
between switches
(see Figures 1 and 2)
IS = 32 mA 4.5 V 2
IS(off)
Off-state switch leakage current
VI = VCC and VO = GND or
VI = GND and VO = VCC,
5.5 V
±1
A
IS(off) Off-state switch leakage current
ICC O
V
I
= GND and V
O
= V
CC
,
VINH = VIH (see Figure 3) 5.5 V ±0.1†µA
IS(on)
On-state switch leakage current
VI = VCC or GND, VINH = VIL,
5.5 V
±1
A
IS(on) On-state switch leakage current
VI = VCC or GND, VINH = VIL,
VO = Open (see Figure 4) 5.5 V ±0.1†µA
II
Control input current
VC = VCC or GND
5.5 V
±1µA
IIControl input current VC = VCC or GND 5.5 V ±0.1†µA
ICC Supply current VC = VCC or GND 5.5 V 1µA
∆ICC Supply-current change VC = VCC − 0.6 V 5.5 V 500 µA
Cic Control input capacitance 5 V 3.5 pF
Cio(off)
Switch input/output capacitance
Y
5 V
6.5
pF
Cio(off) Switch input/output capacitance COM 5 V 10 pF
Cio(on) Switch input/output capacitance 5 V 19.5 pF
†TA = 25°C
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
±0.15 V VCC = 2.5 V
±0.2 V VCC = 3.3 V
±0.3 V VCC = 5 V
±0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd‡COM or Y Y or COM 2 1.2 0.8 0.6 ns
ten§
INH
COM or Y
3.3 9 2.5 6.1 2.2 5.4 1.8 4.5
ns
tdis¶
INH
COM or Y
3.2 10.9 2.3 8.3 2.3 8.1 1.6 8
ns
ten§
A
COM or Y
2.9 10.3 2.1 7.2 1.9 5.8 1.3 5.4
ns
tdis¶
A
COM or Y
2.1 9.4 1.4 7.9 1.1 7.2 1 5
ns
‡tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
§tPZL and tPZH are the same as ten.
¶tPLZ and tPHZ are the same as tdis.
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analog switch characteristics, TA = 25°C
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS VCC TYP UNIT
1.65 V 35
CL = 50 pF, RL = 600 Ω,
fin = sine wave
2.3 V 120
LL
fin = sine wave
(see Figure 6)
3 V 190
Frequency response
†
COM or Y
Y or COM
(see Figure 6)
4.5 V 215
MHz
Frequency response†
(switch on) COM or Y Y or COM 1.65 V >300 MHz
(switch on)
CL = 5 pF, RL = 50 Ω,
fin = sine wave
2.3 V >300
LL
fin = sine wave
(see Figure 6)
3 V >300
(see Figure 6)
4.5 V >300
1.65 V −58
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
2.3 V −58
LL
fin = 1 MHz (sine wave)
(see Figure 7)
3 V −58
Crosstalk
‡
COM or Y
Y or COM
(see Figure 7)
4.5 V −58
dB
Crosstalk‡
(between switches) COM or Y Y or COM 1.65 V −42 dB
(between switches)
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
2.3 V −42
LL
fin = 1 MHz (sine wave)
(see Figure 7)
3 V −42
(see Figure 7)
4.5 V −42
1.65 V 35
Crosstalk
INH
COM or Y
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
2.3 V 50
mV
Crosstalk
(control input to signal output) INH COM or Y
LL
fin = 1 MHz (square wave)
(see Figure 8)
3 V 70 mV
(control input to signal output)
(see Figure 8)
4.5 V 100
1.65 V −60
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
2.3 V −60
LL
fin = 1 MHz (sine wave)
(see Figure 9)
3 V −60
Feed-through attenuation
‡
COM or Y
Y or COM
(see Figure 9)
4.5 V −60
dB
Feed-through attenuation‡
(switch off) COM or Y Y or COM 1.65 V −50 dB
(switch off)
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
2.3 V −50
LL
fin = 1 MHz (sine wave)
(see Figure 9)
3 V −50
(see Figure 9)
4.5 V −50
C = 50 pF, R = 10 k ,
1.65 V 0.1
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
2.3 V 0.025
LL
f
in
= 1 kHz (sine wave)
(see Figure 10)
3 V 0.015
Sine-wave distortion
COM or Y
Y or COM
(see Figure 10)
4.5 V 0.01
%
Sine-wave distortion
COM or Y
Y or COM
C = 50 pF, R = 10 k ,
1.65 V 0.15
%
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
2.3 V 0.025
LL
f
in
= 10 kHz (sine wave)
(see Figure 10)
3 V 0.015
(see Figure 10)
4.5 V 0.01
†Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads −3 dB.
‡Adjust fin voltage to obtain 0 dBm at input.
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
TEST CONDITIONS
TYP TYP TYP TYP
UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 9 10 10 12 pF
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC or GND
VO
ron +VI*VO
IS
W
VI − VO
GND
V
Y1
IS
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
Figure 1. On-State Resistance Test Circuit
100
10
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VI − V
ron −Ω
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VI
VO
GND
Y1
(Off)
VCC
VIH
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
A
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VI
VO
GND
Y1
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
A
VI = VCC or GND
VO = Open
Figure 4. On-State Switch Leakage-Current Test Circuit
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V∆
VOH − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
VCC
VCC
VI
VCC/2
VCC/2
VCC/2
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 5. Load Circuit and Voltage Waveforms
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VO
GND
Y1
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
50 Ω
0.1 µF
fin
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
RLCL
VCC/2
Figure 6. Frequency Response (Switch On)
VCC
VO1
GND
Y1
VCC
VIL
Y2
VIL or VIH
50 Ω
0.1 µF
fin
CL
50 pF
VCC/2
Rin
600 Ω
RL
600 Ω
VO2
CL
50 pF
VCC/2
RL
600 Ω
VA
VIL
VIH
TEST CONDITION
20log10(VO2/VI)
20log10(VO1/VI)
A
VA
VINH
INH
COM
Figure 7. Crosstalk (Between Switches)
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VO
GND
Y1
(On)
VCC
Y2
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
50 Ω
VCC/2
Rin
600 Ω
VCC/2
CL
50 pF
RL
600 Ω
A
VA
VINH
INH
COM
Figure 8. Crosstalk (Control Input, Switch Output)
VCC
VO
GND
Y1
(Off)
VCC
VIL
Y2
VIL or VIH
S
1
2
50 Ω
0.1 µF
fin
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
RLCL
VCC/2
RL
VCC/2
A
VA
VINH
INH
COM
S
1
2
VA
VIL
VIH
Figure 9. Feed Through (Switch Off)
SCES324K − JULY 2001 − REVISED SEPTEMBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
VO
GND
Y1
(On)
VCC
VIL
Y2
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
600 Ω
10 µF
fin
RL
10 kΩ
CL
50 pF
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.30 V, VI = 2.0 VP-P
VCC = 3.00 V, VI = 2.5 VP-P
V
CC
= 4.50 V, V
I
= 4.0 V
P-P
10 µF
A
VA
VINH
INH
COM
Figure 10. Sine-Wave Distortion
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
0,60
0,20
0,25
0°– 8°
0,15 NOM
Gage Plane
4188781/C 09/02
4,25
5
0,30
0,15
2,90 3,75
2,70
8
4
3,15
2,75
1
0,10
0,00
1,30 MAX
Seating Plane
0,10
M
0,13
0,65
PIN 1
INDEX AREA
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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Products Applications
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DSP dsp.ti.com Broadband www.ti.com/broadband
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Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
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