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1
www.fairchildsemi.com
FDMF6704V Rev.C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
August 2009
FDMF6704V - XS
TM
DrMOS
The Xtra Small, High Performance, High Frequency DrMOS Module with LDO
Benefits
Single 12 V power supply operation.
Ultra compact size - 6 mm x 6 mm MLP, 44 % space
saving compared to conventional MLP 8 mm x 8 mm
DrMOS packages.
Ultra compact thermally enhanced 6 mm x 6 mm MLP
package 84 % smaller than conventional discrete solutions.
Fully optimized system efficiency.
Clean voltage waveforms with reduced ringing.
High frequency operation.
Compatible with a wide variety of PWM controllers in the
market.
Single input voltage operation.
Features
Internal 12 V to 5 V regulator.
Synchronous driver plus FET multichip module.
High current handling of 35 A.
Over 93 % peak efficiency.
Tri-State PWM input.
Fairchild's PowerTrench® 5 technology MOSFETs for clean
voltage waveforms and reduced ringing.
Optimized for high switching frequencies of up to 1 MHz.
Skip mode SMOD [low side gate turn off] input.
Fairchild SyncFETTM [integrated Schottky diode] technology
in the low side MOSFET.
Integrated bootstrap Schottky diode.
Adaptive gate drive timing for shoot-through protection.
Driver output disable function [DISB# pin].
Undervoltage lockout (UVLO).
Fairchild Green Packaging and RoHS
compliant. Low profile SMD package.
General Description
The XSTM DrMOS family is Fairchild’s next-generation fully-
optimized, ultra-compact, integrated MOSFET plus driver power
stage solutions for high current, high frequency synchronous
buck DC-DC applications. The FDMF6704V XSTM DrMOS
integrates a driver IC, two power MOSFETs and a bootstrap
Schottky diode along with an integrated 5 V gate drive LDO
regulator into a thermally enhanced, ultra compact 6 mm x 6
mm MLP package. With an integrated approach, the complete
switching power stage is optimized with regards to driver and
MOSFET dynamic performance, system inductance and
R
DS(ON)
. This greatly reduces the package parasitics and layout
challenges associated with conventional discrete solutions.
XS
TM
DrMOS uses Fairchild's high performance
PowerTrench
TM
5 MOSFET technology, which dramatically
reduces ringing in synchronous buck converter applications.
PowerTrench
TM
5 can eliminate the need for a snubber circuit in
buck converter applications. The driver IC incorporates
advanced features such as SMOD for improved light load
efficiency and a Tri-State PWM input for compatibility with a
wide range of PWM controllers. A 5 V gate drive and an
improved PCB interface, optimized for a maximum low side FET
exposed pad area, ensure higher performance. This product is
compatible with the new Intel 6 mm x 6 mm DrMOS
specification.
Applications
Compact blade servers V-core, non V-core and VTT DC-DC
converters.
Desktop computers V-core, non V-core and VTT DC-DC
converters.
Workstations V-core, non V-core and VTT DC-DC
converters.
Gaming Motherboards V-core, non V-core and VTT DC-DC
converters.
Gaming consoles.
High-current DC-DC Point of Load (POL) converters.
Networking and telecom microprocessor voltage regulators.
Power Train Application Circuit
Figure 1. Power Train Application Circuit
DISB#
PWM
CGND PGND
VDRV VIN
BOOT
VSWH
DISB#
PWM Input
C
VIN
C
BOOT
C
OUT
OUTPUT
C
VCIN
VCIN
C
VDRV
SMOD#
ON
OFF PHASE
Ordering Information
Order Number Marking Temperature Range Device Package Packing Method Quantity
FDMF6704V FDMF6704V_1 -55 °C to 150 °C 40 Pin, 3 DAP, MLP 6x6 mm Tape and Reel 3000
V
DRV
V
IN
L
OUT
R
BOOT
2
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Functional Block Diagram
Pin Configuration
Figure 2. Functional Block Diagram
CGND PGND
VSWH
VIN
BOOT
VCIN
VCIN
GH
GL
VDRV
PWM
DISB# Overlap
Control
SMOD#
Q1
Q2
5 V
Reg
CGND
VIN
VSWH
Figure 3. 6mm x 6mm, 40L MLP
CGND VIN
VSWH
PWM
SMOD#
DISB#
NC
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
VCIN
VDRV
BOOT
CGND
GH
NC
VIN
VIN
VIN
VIN
VIN
VIN
VSWH
PGND
VSWH
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PHASE
PGND
PGND
PGND
PGND
PGND
Bottom View Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
SMOD#
VCIN
VDRV
BOOT
CGND
GH
NC
VIN
VIN
PHASE
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PWM
DISB#
NC
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
41
42
43
41 42
43
3
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Pin Description
Absolute Maximum Rating
* I
O(AV)
and I
O(peak)
are measured in FCS evaluation board. These ratings can be changed with different application setting.
Recommended Operating Range
* May be operated at lower input voltage. See figure 10.
Pin Name Function
1 SMOD#
When SMOD# = HI, low side driver is inverse of PWM input. When SMOD# = Low, low
side driver is disabled. This pin has no internal pullup or pulldown. It should not be left
floating. Do not add noise filter cap.
2 VCIN Regulator 5 V Output. Power for gate drives and logic. A minimum 4.7 F X7R ceramic
capacitor is required to be connected from this pin to CGND.
3 VDRV Regulator Input Voltage. A minimum 4.7 F X7R ceramic capacitor is required to be
connected from this pin to CGND.
4 BOOT Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor from this pin to PHASE.
5, 37, 41 CGND IC Ground. Ground return for driver IC.
6 GH For manufacturing test only. This pin must be floated. Must not be connected to any pin.
7 PHASE Switch node pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin.
8, 38 NC Not Connected Internally.
9-14, 42 VIN Power input. Output stage supply voltage.
15, 29-35, 43 VSWH Switch Node Output. Provides return for high-side bootstrapped driver and acts as a
sense point for the adaptive shoot-thru protection.
16-28 PGND Power Ground. Output stage ground. Source pin of low side MOSFET(s).
36 GL For manufacturing test only. This pin must be floated. Must not be connected to any pin.
39 DISB#
Output disable. When low, this pin disable FET switching (GH and GL are held low). This
pin has no internal pullup or pulldown. It should not be left floating. Do not add noise filter
cap.
40 PWM PWM Signal Input. This pin accepts a Tri-state logic-level PWM signal from the controller.
Do not add noise filter cap.
Parameter Min Max Units
VCIN, DISB#, PWM, SMOD#, GL to CGND 6 V
VIN to PGND, CGND 27 V
VDRV to PGND, CGND 16 V
BOOT, GH to VSWH, PHASE 6 V
BOOT, VSWH, PHASE, GH to GND 27 V
BOOT to VCIN 22 V
I
O(AV)
* V
IN
= 12 V, V
O
= 1.3 V f
SW
= 350 kHz 35 A
f
SW
= 1 MHz 32 A
I
O(peak)
* 80 A
R
θJB
Thermal Resistance Junction to Board 3.75 °C/W
Operating and Storage Junction Temperature Range -55 150 °C
Parameter Min Typ Max Units
V
DRV
Vgate and Logic Supply Voltage 8 12 14 V
V
IN
Output FET Supply Voltage 3* 12 14 V
4
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Electrical Characteristics
V
IN
= 12 V, V
DRV
= 12 V, T
A
= 25 °C unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units
Operating Quiescent Current IQ PWM = GND 2 mA
PWM = V
CIN
2
Internal 5V Regulator
Input Voltage V
DRV
8 14 V
Input Current I
VDRV
8V < V
IN
< 14V, 1MHz 36 mA
Output voltage V
CIN
V
DRV
= 8V, I
Load
= 5mA 4.8 5 5.2 V
Power Dissipation P
VDRV
V
DRV
= 12V, 1MHz 250 mW
VCIN Capacitor C
VCIN
X7R Ceramic 4.7 10 F
Line Regulation 8V < V
DRV
< 14V, I
Load
= 5mA 20 mV
Load Regulation V
DRV
= 8V, 5mA < I
Load
< 100mA 75 mV
Short Circuit Current Limit 200 mA
UVLO Threshold 7.5 V
UVLO COMP Hysteresis 0.5 V
PWM Input
Sink Impedance PWM to GND 10 k
Source Impedance PWM to V
CIN
10 k
Tri-State Rising Threshold 3.2 3.4 3.6 V
Tri-State Rising Hysteresis 100 mV
Tri-State Falling Threshold 1.2 1.4 1.6 V
Tri-State Falling Hysteresis 100 mV
Tri-State Pin Open 2.5 V
Tri-State Shut Off Time 100 ns
SMOD# and DISB# Input
High Level Input Voltage 2 V
Low Level Input Voltage 0.8 V
Input Bias Current -2 2 A
Propagation Delay Time
PWM = GND, delay between SMOD#
or DISB# from HI to LO to GL from HI
to LO.
15 ns
High Side Driver
Rise Time 10 % to 90 % 25 ns
Fall Time 90 % to 10 % 20 ns
Deadband Time t
DTHH
GL going LO to GH going HI, 10 % to
10 % 25 ns
Propagation Delay t
PDHL
PMW going LO to GH going LO 10 ns
Low Side Driver
Rise Time 10 % to 90 % 25 ns
Fall Time 90 % to 10 % 20 ns
Deadband Time t
DTLH
VSWH going LO to GL going HI, 10
% to 10 % 20 ns
Propagation Delay t
PDLL
PWM going HI to GL going LO 10 ns
250 ns Time Out Circuit
250 ns Time Delay Delay between GH from HI to LO and
GL from LO to HI if VSWH is high. 250 ns
5
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Description of Operation
Circuit Description
The FDMF6704V is a driver plus FET module incorporating an
internal 12 V to 5 V regulator that is optimized for synchronous
buck converter topology. A single PWM input signal is all that is
required to properly drive the high-side and the low-side
MOSFETs at speeds up to 1 MHz.
PWM
When the PWM input goes high, the high side MOSFET turns
on. When it goes low, the low side MOSFET turns on. When it is
open, both the low side and high side MOFET will turn off. The
individual PWM signals from the controller will be used to
dynamically enable or disable individual phases.
DISB#
The DISB# input is combined with the PWM signal to control the
driver output. In a typical multiphase design, DISB# will be a
common signal used to turn on all phases.
Gate Low
The low-side driver (GL) is designed to drive a ground
referenced low RDS
(ON)
N-channel MOSFET. The bias for GL is
internally connected between VCIN and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB# = 0 V), GL
is held low turning the low side FET off.
Gate High
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal BOOT diode and an external bootstrap capacitor
(C
BOOT
). During start-up, VSWH is held at PGND, allowing
C
BOOT
to charge to V
CIN
through the internal diode. When the
PWM input goes high, GH will begin to charge the high-side
MOSFET's gate (Q1). During this transition, charge is removed
from C
BOOT
and delivered to Q1's gate. As Q1 turns on, VSWH
rises to V
IN
, forcing the BOOT pin to V
IN
+V
C(BOOT)
, which
provides sufficient V
GS
enhancement for Q1. To complete the
switching cycle, Q1 is turned off by pulling GH to VSWH. C
BOOT
is then recharged to VCIN when VSWH falls to PGND. GH
output is in phase with the PWM input. When the driver is
disabled, the high-side FET is turned off.
VDRV and VCIN
The FDMF6704V incorporates an internal 12 V to 5 V regulator
to allow it to be used in single 12 V supply applications.
The regulator’s 5V output (VCIN) is connected to pin 2 and used
internally to supply power to the gate drives and to the internal
logic. A 4.7F X7R ceramic capacitor must be connected
between VCIN and ground. This capacitor is part of the
regulator’s loop compensation so a high X7R type is required.
The regulator’s input VDRV is connected to pin 3.
SMOD#
The SMOD (Skip Mode) function allows for higher converter
efficiency under light load conditions. During SMOD, the LS
FET is disabled and it prevents discharging of output caps.
When the SMOD# pin is pulled high, the sync buck converter
will work in synchronous mode. When the SMOD# pin is pulled
low, the LS FET is turned off. The SMOD function does not have
internal current sensing. This SMOD# pin is connected to a
PWM controller which enables or disables the SMOD
automatically when the controller detects light load condition.
This pin is Active Low.
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 4 for the
relevant timing waveforms.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the GL pin. When the PWM signal goes HIGH, Q2 will begin
to turn OFF after some propagation delay (t
PDLL
). Once the GL
pin is discharged below 1 V, Q1 begins to turn ON after adaptive
delay t
DTHH
.
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the
VSWH pin. When the PWM signal goes LOW, Q1 will begin to
turn OFF after some propagation delay (t
PDHL
). Once the
VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive
delay t
DTLH
.
Additionally, V
GS
of Q1 is monitored. When V
GS(Q1)
is
discharged low, a secondary adaptive delay is initiated, which
results in Q2 being driven ON after 250 ns, regardless of VSWH
state. This function is implemented to ensure C
BOOT
is
recharged each switching cycle, particularly for cases where the
power converter is sinking current and VSWH voltage does not
fall below the 1 V adaptive threshold. The 250 ns secondary
delay is longer than t
DTLH
.
6
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Timing Diagrams
Switch Node Ringing Suppression
Fairchild's DrMOS products have proprietary feature* that minimizes the peak overshoot and ringing voltage on the switch node
(VSWH) output, without the need of external snubbers. The following pictures show the waveforms of an FDMF6704 DrMOS part and
a competitor's part tested without snubbing. The tests were done in the same test circuit, under the same operating conditions.
* Patent Pending
Figure 4. Timing Diagram
PWM
t
PDLL
GH to VSWH t
DTLH
GL
VSWH
t
PDHL
Timeout
t
DTHH
tri-state shutoff
Figure 5. FDMF6704 Figure 6. Competitor Part
7
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Typical Characteristics
V
IN
= 12V, V
DRV
= 12V, T
A
= 25°C unless otherwise noted.
Figure 9. Normalized Power Loss vs. Switching Frequency Figure 10. Normalized Power Loss vs. Input Voltage
Figure 11. Normalized Power Loss vs. Output Voltage Figure 12. Normalized Power Loss vs. Output Inductance
Figure 7. Safe Operating Area Figure 8. Module Power Loss vs. Output Current
(Note: For total power loss, add 5 V regulator loss shown in
Figure 18 on page 8.
0
5
10
15
20
25
30
35
0 25 50 75 100 125 150
PCB Temperature,
o
C
I
LOAD
, A
V
IN
= 12 V
V
OUT
= 1.3 V
f
SW
= 1 MHz
L = 440 nH
0
2
4
6
8
10
12
0 5 10 15 20 25 30 35
I
LOAD
, A
P
LOSS
, W
f
SW
= 1 MHz
f
SW
= 350 kHz
V
IN
= 12 V
V
OUT
= 1.3 V
L = 440 nH
0.98
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
6 8 10 12 14 16
Input Voltage, V
P
LOSS (NORMALIZED)
V
OUT
= 1.3 V
I
OUT
= 30 A
L = 440 nH
f
SW
= 350 kHz
0.80
0.90
1.00
1.10
1.20
1.30
1.40
0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2
Output Voltage, V
P
LOSS (NORMALIZED)
V
IN
= 12 V
I
OUT
= 30 A
L = 440 nH
f
SW
= 350 kHz
0.80
0.90
1.00
1.10
1.20
1.30
1.40
200 300 400 500 600 700 800 900 1000
f
SW
, kHz
P
LOSS (NORMALIZED)
V
IN
= 12 V
V
OUT
= 1.3 V
I
OUT
= 30 A
L = 440 nH
0.995
1.000
1.005
1.010
1.015
1.020
1.025
1.030
1.035
1.040
1.045
220 275 330 385 440
Output Inductance, nH
P
LOSS (NORMALIZED)
V
IN
= 12 V
V
OUT
= 1.3 V
I
OUT
= 30 A
f
SW
= 350 kHz
8
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
1.0
1.2
1.4
1.6
1.8
2.0
2.2
-50 -25 0 25 50 75 100 125 150
Temperature,
o
C
DISB# Threshold Voltage, V
V
IH
V
IL
VRIN = 12 V
Typical Characteristics
V
IN
= 12V, V
DRV
= 12V, T
A
= 25°C unless otherwise noted.
Figure 15. PWM Tri-state Threshold Voltage vs. Temperature
Figure 18. Internal 5 V Regulator Power Dissipation vs.
Frequency and VDRV Voltage
Figure 17. DISB# Threshold Voltage vs. Temperature
Figure 13. Driver Supply Current vs. Frequency Figure 14. Driver Supply Current vs. Temperature
Figure 16. SMOD# Threshold Voltage vs. Temperature
1.0
1.2
1.4
1.6
1.8
2.0
2.2
-50 -25 0 25 50 75 100 125 150
Temperature,
o
C
SMOD# Threshold Voltage, V
V
IH
V
IL
VRIN = 12 V
40
41
42
43
44
45
46
47
48
49
50
-50 -25 0 25 50 75 100 125 150
Temperature,
o
C
Driver Supply Current, mA
VRIN = 12 V
f
SW
= 1 MHz
0
5
10
15
20
25
30
35
40
45
200 300 400 500 600 700 800 900 1000
f
SW
, kHz
Driver Supply Current, mA
VRIN = 12 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-40 25 85 125 150
Temperature,
o
C
PWM Tri-state Threshold Voltage, V
ON STATE
OFF STATE
TRI STATE
VRIN = 12 V
0
80
160
240
320
400
200 300 400 500 600 700 800 900 1000
Switching Frequency, kHz
Power Dissipation, mW
16V
12V
8V
V
DRV
= 12 V
V
DRV
= 12 V
V
DRV
= 12 V
V
DRV
= 12 V
f
SW
= 1 MHz
V
DRV
= 12 V
9
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Supply Capacitor Selection
For the supply input (VIN) of the FDMF6704V, a local ceramic
bypass capacitor is recommended to reduce the noise and to
supply the peak current. Use at least a 4.7F, X7R or X5R
capacitor. Keep this capacitor close to the FDMF6704V VIN and
PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (C
BOOT
),
as shown in Figure 19. A bootstrap capacitance of 100nF, X7R
capacitor is adequate. A series bootstrap resistor would be
needed for specific application in order to improve switching
noise immunity.
Signal
V
IN
12V
PWM3
PWM1
PWM2
CGND
PWM
Controller
EN
PWM4
GND Power
GND
VOUT
Typical Application
Note: For operation with V
IN
<8V, a separate >8V supply is required for VDRV.
Figure 19. Typical Application
SMOD#
FDMF6704V
DISB#
PWM
CGND PGND
VCIN
VIN
BOOT
VSWH
C
BOOT
VDRV
SMOD# PHASE
FDMF6704V
DISB#
PWM
CGND PGND
VCIN
VIN VSWH
VDRV
SMOD# PHASE
FDMF6704V
DISB#
PWM
CGND PGND
VIN
VIN VSWH
VDRV
SMOD# PHASE
FDMF6704V
DISB#
PWM
CGND PGND
VCIN
VIN VSWH
VDRV
SMOD# PHASE
BOOT
C
BOOT
BOOT
C
BOOT
BOOT
C
BOOT
Application Information
R
BOOT
R
BOOT
R
BOOT
R
BOOT
10
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 20 for power loss testing method. Power loss
calculation are as follows:
(a) P
IN
= (V
IN
x I
IN
) + (V
DRV
x I
VDRV
) (W)
(b) P
SW
= V
SW
x I
OUT
(W)
(c) P
OUT
= V
OUT
x I
OUT
(W)
(d) P
LOSS_MODULE
= P
IN
- P
SW
(W)
(e) P
LOSS_BOARD
= P
IN
- P
OUT
(W)
(f) EFF
MODULE
= 100 x P
SW
/P
IN
(%)
(g) EFF
BOARD
= 100 x P
OUT
/P
IN
(%)
PCB Layout Guideline
Figure 21 shows a proper layout example of FDMF6704V and
critical parts. All of high current flow path, such as VIN, VSWH,
V
OUT
and GND copper, should be short and wide for better and
stable current flow, heat radiation and system performance.
Following is a guideline which the PCB designer should
consider:
1. Input ceramic bypass capacitors must be close to VIN and
PGND pin of FDMF6704V to help reduce the input current ripple
component induced by switching operation.
2. The VSWH copper trace serves two purposes. In addition to
being the high frequency current path from the DrMOS package
to the output inductor, it also serves as heatsink for the lower
FET in the DrMOS package. The trace should be short and wide
enough to present a low impedance path for the high frequency,
high current flow between the DrMOS and inductor in order to
minimize losses and temperature rise. Please note that the
VSWH node is a high voltage and high frequency switching
node with high noise potential. Care should be taken to
minimize coupling to adjacent traces. Additionally, since this
copper trace also acts as heatsink for the lower FET, tradeoff
must be made to use the largest area possible to improve
DrMOS cooling while maintaining acceptable noise emission.
3. Output inductor location should be as close as possible to the
FDMF6704V to minimize lower power loss due to copper trace.
Care should be taken so that inductor dissipation does not heat
the DrMOS.
4. The PowerTrench® 5 MOSFETs used in the output stage are
very effective at minimizing ringing. In most cases, no snubber
will be required. If a snubber is used, it should be placed near
the FDMF6704V. The resistor and capacitor need to be of
proper size for the power dissipation.
5. Place ceramic bypass capacitor and BOOT capacitor as
close as possible to the VCIN and BOOT pins of the
FDMF6704V to ensure clean and stable power. Routing width
and length should be considered as well.
6. Include a trace from PHASE to VSWH in order to improve
noise margin. Keep the trace as short as possible.
7. The layout should include the option to insert a small value
series boot resistor between boot cap and BOOT pin. The boot
loop size, including R
BOOT
and C
BOOT
, should be as small as
possible. The boot resistor is normally not required, but is
effective at improving noise operating margin in multi phase
designs that may have noise issues due to ground bounce and
high negative VSWH ringing. The VIN and PGND pins handle
large current transients with frequency components above
100 MHz. If possible, these package pins should be connected
directly to the VIN and board GND planes. The use of thermal
relief traces in series with these pins is discouraged since this
will add inductance to the power path. This added inductance in
series with the PGND pin will degrade system noise immunity
by increasing negative VSWH ringing.
8. CGND pad and PGND pins should be connected by plane
GND copper with multiple vias for stable grounding. Poor
grounding can create a noise transient offset voltage level
between CGND and PGND. This could lead to fault operation of
gate driver and MOSFET.
9. Ringing at the BOOT pin is most effectively controlled by
close placement of the boot capacitor. Do not add an additional
BOOT to PGND capacitor. This may lead to excess current flow
through the BOOT diode.
10. SMOD#, DISB# and PWM pins don’t have internal pull up or
pull down resistors. They should not be left floating. These pins
should not have any noise filter caps.
11. Use multiple vias on each copper area to interconnect top,
inner and bottom layers to help smooth current flow and heat
conduction. Vias should be relatively large and of reasonable
inductance. Critical high frequency components such as R
BOOT
,
C
BOOT
, the RC snubber and bypass caps should be located
close to the DrMOS module and on the same side of the PCB
as the module. If not feasible, they should be connected from
the backside via a network of low inductance vias.
Figure 20. Power Loss Measurement Block Diagram
DISB#
PWM
CGND PGND
VCIN VIN
BOOT
VSWH
DISB#
PWM Input
C
VIN
C
BOOT
C
OUT
C
VDRV
VDRV
C
VCIN
SMOD#
PHASE
AV
IN
I
IN
AV
OUT
I
OUT
VV
SW
SMOD#
A
I
VDRV
L
OUT
V
DRV
R
BOOT
11
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Figure 21. Typical PCB Layout Example
TOP VIEW BOTTOM VIEW
12
www.fairchildsemi.com
FDMF6704V Rev. C
FDMF6704V - XS
TM
DrMOS with Internal 5V Regulator
Dimensional Outline and Pad layout
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
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