82430FX PCIset DATASHEET 82437FX SYSTEM CONTROLLER (TSC) AND 82438FX DATA PATH UNIT (TDP) Y Supports all 3V PentiumE Processors Y Integrated Second Level Cache Controller Direct Mapped Organization Write-Back Cache Policy Cacheless, 256-Kbyte, and 512-Kbyte Standard Burst and Pipelined Burst SRAMs Cache Hit Read/Write Cycle Timings at 3-1-1-1 with Burst or Pipelined Burst SRAMs Back-to-Back Read Cycles at 3-1-1-11-1-1-1 with Burst or Pipelined Burst SRAMs Integrated Tag/Valid Status Bits for Cost Savings and Performance Supports 5V SRAMs for Tag Address Y Integrated DRAM Controller 64-Bit Data Path to Memory 4 Mbytes to 128 Mbytes Main Memory EDO/Hyper Page Mode DRAM (x-2-2-2 Reads) or Standard Page Mode DRAMs 5 RAS Lines 4 Qword Deep Buffer for 3-1-1-1 Posted Write Cycles Symmetrical and Asymmetrical DRAMs 3V or 5V DRAMs Y EDO DRAM Support Highest Performance with Burst or Pipelined Burst SRAMs Superior Cacheless Designs Y Fully Synchronous 25/30/33 MHz PCI Bus Interface 100 MB/s Instant Access Enables Native Signal Processing (NSP) on Pentium Processors Synchronized CPU-to-PCI Interface for High Performance Graphics PCI Bus Arbiter: PIIX and Four PCI Bus Masters Supported CPU-to-PCI Memory Write Posting with 4 Dword Deep Buffers Converts Back-to-Back Sequential CPU to PCI Memory Writes to PCI Burst Writes PCI-to-DRAM Posting of 12 Dwords PCI-to-DRAM up to 120 Mbytes/Sec Bandwidth Utilizing Snoop Ahead Feature Y NAND Tree for Board-Level ATE Testing Y 208 Pin QFP for the 82437FX System Controller (TSC); 100 Pin QFP for Each 82438FX Data Path (TDP) Y Supported Kits 82437FX ISA Kit (TSC, TDPs, PIIX) The 82430FX PCIset consists of the 82437FX System Controller (TSC), two 82438FX Data Paths (TDP), and the 82371FB PCI ISA IDE Xcelerator (PIIX). The PCIset forms a Host-to-PCI bridge and provides the second level cache control and a full function 64-bit data path to main memory. The TSC integrates the cache and main memory DRAM control functions and provides bus control for transfers between the CPU, cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a write-back cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory can be implemented with either standard, burst, or pipelined burst SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. For the TSC's DRAM controller, five rows are supported for up to 128 Mbytes of main memory. The TSC's optimized PCI interface allows the CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop ahead feature, the TSC allows PCI masters to achieve full PCI bandwidth. The TDPs provide the data paths between the CPU/cache, main memory, and PCI. For increased system performance, the TDPs contain read prefetch and posted write buffers. November 1996 Order Number: 290518-002 82437FX TSC AND 82438FX TDP 290518 - 1 82437FX TSC Simplified Block Diagram 290518 - 2 82438FX TDP Simplified Block Diagram 2 82430FX PCIset DATASHEET 82437FX SYSTEM CONTROLLER (TSC) AND 82438FX DATA PATH UNIT (TDP) CONTENTS PAGE 1.0 ARCHITECTURE OVERVIEW OF TSC/TDP AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 5 2.0 SIGNAL DESCRIPTION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 6 2.1 TSC Signals AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 7 2.1.1 HOST INTERFACE (TSC) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 7 2.1.2 DRAM INTERFACE (TSC) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 8 2.1.3 SECONDARY CACHE INTERFACE (TSC) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 9 2.1.4 PCI INTERFACE (TSC) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 10 2.1.5 TDP INTERFACE (TSC) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 11 2.1.6 CLOCKS (TSC) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 11 2.2 TDP Signals AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 12 2.2.1 DATA INTERFACE SIGNALS (TDP) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 12 2.2.2 TSC INTERFACE SIGNALS (TDP) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 12 2.2.3 CLOCK SIGNAL (TDP) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 12 2.3 Signal State During Reset AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 13 3.0 REGISTER DESCRIPTION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 14 3.1 Control Registers AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 14 3.1.1 CONFADDCONFIGURATION ADDRESS REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAA 15 3.1.2 CONFDATACONFIGURATION DATA REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 15 3.2 PCI Configuration Registers AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 16 3.2.1 VIDVENDOR IDENTIFICATION REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 18 3.2.2 DIDDEVICE IDENTIFICATION REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 18 3.2.3 PCICMDPCI COMMAND REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 18 3.2.4 PCISTSPCI STATUS REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 19 3.2.5 RIDREVISION IDENTIFICATION REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 19 3.2.6 SUBCSUB-CLASS CODE REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 20 3.2.7 BCCBASE CLASS CODE REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 20 3.2.8 MLTMASTER LATENCY TIMER REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 20 3.2.9 BISTBIST REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 21 3.2.10 PCONPCI CONTROL REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 21 3.2.11 CCCACHE CONTROL REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 22 3.2.12 DRAMCDRAM CONTROL REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 23 3.2.13 DRAMTDRAM TIMING REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 24 3.2.14 PAMPROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM [6:0] ) AAAAAAAAAAA 26 3.2.15 DRBDRAM ROW BOUNDARY REGISTERS AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 29 3 CONTENTS PAGE 3.2.16 DRTDRAM ROW TYPE REGISTER AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 31 3.2.17 SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER AAAAAAAAAAAAAAAA 32 4.0 FUNCTIONAL DESCRIPTION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 34 4.1 Host Interface AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 34 4.2 PCI Interface AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 34 4.3 Secondary Cache Interface AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 34 4.3.1 CLOCK LATENCIES AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 35 4.3.2 SNOOP CYCLES AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 35 4.3.3 CACHE ORGANIZATION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 35 4.3.4 CLARIFICATION ON HOW TO FLUSH THE L2 CACHE AAAAAAAAAAAAAAAAAAAAAAAAAAA 36 4.4 DRAM Interface AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 41 4.4.1 DRAM ORGANIZATION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 41 4.4.2 MAIN MEMORY ADDRESS MAP AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 42 4.4.3 DRAM ADDRESS TRANSLATION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 42 4.4.4 DRAM PAGE MODE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 44 4.4.5 EDO MODE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 45 4.4.6 DRAM PERFORMANCE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 46 4.4.7 DRAM REFRESH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 46 4.4.8 SYSTEM MANAGEMENT RAM AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 46 4.5 82438FX Data Path (TDP) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 46 4.6 PCI Bus Arbitration AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 47 4.6.1 PRIORITY SCHEME AND BUS GRANT AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 47 4.6.2 CPU POLICIES AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 48 4.7 Clock Generation and Distribution AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 48 4.7.1 RESET SEQUENCING AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 48 5.0 PINOUT AND PACKAGE INFORMATION AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 49 5.1 82437FX Pinout AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 49 5.2 82438FX Pinout AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 53 5.3 82437FX Package Dimensions AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 55 5.4 82438FX Package Dimensions AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 57 6.0 82437FX TSC TESTABILITY AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 58 6.1 Test Mode Description AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 58 6.2 NAND Tree Mode AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 58 7.0 82438FX TDP TESTABILITY AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 64 7.1 Test Mode Description AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 64 7.2 NAND Tree Mode AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 64 4 82437FX TSC AND 82438FX TDP 1.0 ARCHITECTURE OVERVIEW OF TSC/TDP The 82430FX PCIset (Figure 1) consists of the 82437FX System Controller (TSC), two 82438FX Data Path (TDP) units, and the 82371FB PCI IDE ISA Xcelerator (PIIX). The TSC and two TDPs form a Host-to-PCI bridge. The PIIX is a multi-function PCI device providing a PCI-to-ISA bridge and a fast IDE interface. The PIIX also provides power management and has a plug and play port. The two TDPs provide a 64-bit data path to the host and to main memory and provide a 16-bit data path (PLINK) between the TSC and TDP. PLINK provides the data path for CPU to PCI accesses and for PCI to main memory accesses. The TSC and TDP bus interfaces are designed for 3V and 5V busses. The TSC/TDP connect directly to the PentiumE processor 3V host bus; The TSC/TDP connect directly to 5V or 3V main memory DRAMs; and the TSC connects directly to the 5V PCI Bus. 290518 - 3 Figure 1. 82430FX PCIset System 5 82437FX TSC AND 82438FX TDP DRAM Interface System Clocking The DRAM interface is a 64-bit data path that supports both standard page mode and Extended Data Out (EDO) (also known as Hyper Page Mode) memory. The DRAM interface supports 4 Mbytes to 128 Mbytes with five RAS lines available and also supports symmetrical and asymmetrical addressing for 512K, 1M, 2M, and 4M deep DRAMs. The processor, second level cache, main memory subsystem, and PLINK bus all run synchronous to the host clock. The PCI clock runs synchronously at half the host clock frequency. The TSC and TDP's have a host clock input and the TSC has a PCI clock input. These clocks are derived from an external source and have a maximum clock skew requirement with respect to each other. Second Level Cache The TSC supports a write-back cache policy providing all necessary snoop functions and inquire cycles. The second level cache is direct mapped and supports both a 256-Kbyte or 512-Kbyte SRAM configuration using either burst, pipelined burst, or standard SRAMs. The burst 256-Kbyte configuration performance is 3-1-1-1 for read/write cycles; pipelined backto-back reads can maintain a 3-1-1-1-1-1-1-1 transfer rate. TDP Two TDPs create a 64-bit CPU and main memory data path. The TDP's also interface to the TSC's 16-bit PLINK inter-chip bus for PCI transactions. The combination of the 64-bit memory path and the 16-bit PLINK bus make the TDP's a cost effective solution, providing optimal CPU-to-main memory performance while maintaining a small package footprint (100 pins each). PCI Interface The PCI interface is 2.0 compliant and supports up to 4 PCI bus masters in addition to the PIIX bus master requests. While the TSC and TDP's together provide the interface between PCI and main memory, only the TSC connects to the PCI Bus. Buffers The TSC and TDP's together contain buffers for optimizing data flow. A four Qword deep buffer is provided for CPU-to-main memory writes, second level cache write back cycles, and PCI-to-main memory transfers. This buffer is used to achieve 3-1-1-1 posted writes to main memory. A four Dword buffer is used for CPU-to-PCI writes. In addition, a four Dword PCI Write Buffer is provided which is combined with the DRAM Write Buffer to supply a 12 Dword deep buffering for PCI to main memory writes. 6 2.0 SIGNAL DESCRIPTION This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The ``Y'' symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When ``Y'' is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used extensively. This is done to avoid confusion when working with a mixture of ``active-low'' and ``active-high'' signals. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive. The following notations are used to describe the signal type. I Input is a standard input-only signal. O Totem pole output is a standard active driver. o/d Open drain. Tri-State is a bi-directional, tri-state input/output pin. s/t/s Sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. A new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tristates it. An external pull-up is required to sustain the inactive state until another agent drives it and must be provided by the central resource. t/s 82437FX TSC AND 82438FX TDP 2.1 TSC Signals 2.1.1 HOST INTERFACE (TSC) Signal Name Type Description A[31:3] I/O 3V ADDRESS BUS: A[31:3] connect to the address bus of the CPU. During CPU cycles A [31:3] are inputs. These signals are driven by the TSC during cache snoop operations. Note that A [31:28] provide poweron/reset strapping options for the second level cache. BE [7:0] Y I 3V BYTE ENABLES: The CPU byte enables indicate which byte lane the current CPU cycle is accessing. All eight byte lanes are provided to the CPU if the cycle is a cacheable read regardless of the state of BE [7:0] Y. ADSY I 3V ADDRESS STATUS: The CPU asserts ADSY to indicate that a new bus cycle is being driven. BRDYY O 3V BUS READY: The TSC asserts BRDYY to indicate to the CPU that data is available on reads or has been received on writes. NAY O 3V NEXT ADDRESS: When burst SRAMs are used in the second level cache or the second level cache is disabled, the TSC asserts NAY in T2 during CPU write cycles and with the first assertion of BRDYY during CPU linefills. NAY is never asserted if the second level cache is enabled with asynchronous SRAMs. NAY on the TSC must be connected to the CPU NAY pin for all configurations. AHOLD O 3V ADDRESS HOLD: The TSC asserts AHOLD when a PCI master is accessing main memory. AHOLD is held for the duration of the PCI burst transfer. The TSC negates AHOLD when the PCI to main memory read/write cycles complete and during PCI peer transfers. EADSY O 3V EXTERNAL ADDRESS STROBE: Asserted by the TSC to inquire the first level cache when servicing PCI master accesses to main memory. BOFFY O 3V BACK OFF: Asserted by the TSC when required to terminate a CPU cycle that was in progress. HITMY I 3V HIT MODIFIED: Asserted by the CPU to indicate that the address presented with the last assertion of EADSY is modified in the first level cache and needs to be written back. M/IOY, D/CY, W/RY I 3V MEMORY/IO; DATA/CONTROL; WRITE/READ: Asserted by the CPU with ADSY to indicate the type of cycle on the host bus. HLOCKY I 3V HOST LOCK: All CPU cycles sampled with the assertion of HLOCKY and ADSY, until the negation of HLOCKY must be atomic (i.e., no PCI activity to main memory is allowed). CACHEY I 3V CACHEABLE: Asserted by the CPU during a read cycle to indicate the CPU can perform a burst line fill. Asserted by the CPU during a write cycle to indicate that the CPU will perform a burst write-back cycle. If CACHEY is asserted to indicate cacheability, the TSC asserts KENY either with the first BRDYY, or with NAY, if NAY is asserted before the first BRDYY. 7 82437FX TSC AND 82438FX TDP Signal Name Type Description KENY/INV O 3V CACHE ENABLE/INVALIDATE: KENY/INV functions as both the KENY signal during CPU read cycles and the INV signal during first level cache snoop cycles. During CPU cycles, KENY/INV is normally low. The TSC drives KENY high during the first BRDYY or NAY assertion of a non-cacheable (in first level cache) CPU read cycle. The TSC drives INV high during the EADSY assertion of a PCI master DRAM write snoop cycle and low during the EADSY assertion of a PCI master DRAM read snoop cycle. SMIACTY I 3V SYSTEM MANAGEMENT INTERRUPT ACTIVE: The CPU asserts SMIACTY when it is in system management mode as a result of an SMI. After SMM space (located at A0000h) is loaded and locked by BIOS, this signal must be sampled active with ADSY for the processor to access the SMM space of DRAM. 2.1.2 DRAM INTERFACE (TSC) Signal Name Type RAS [4:0] Y O 3V ROW ADDRESS STROBE: These pins select the DRAM row. CAS [7:0] Y O 3V COLUMN ADDRESS STROBE: These pins always select which bytes are affected by a DRAM cycle. MA [11:2] O 3V MEMORY ADDRESS: This is the row and column address for DRAM. MAA [1:0] O 3V MEMORY ADDRESS COPY A: One copy of the MAs that change during a burst read or write of DRAM. MAB [1:0] O 3V MEMORY ADDRESS COPY B: A second copy of the MAs that change during a burst read or write of DRAM. 8 Description 82437FX TSC AND 82438FX TDP 2.1.3 SECONDARY CACHE INTERFACE (TSC) Signal Name CADVY/ CAA4 Type O 3V Description CACHE ADVANCE/CACHE ADDRESS 4 (COPY A): This pin has two modes of operation depending on the type of SRAMs selected via hardware strapping options or programming the CC Register. The CAA4 mode is used when the L2 cache consists of asynchronous SRAMs. CAA4 is used to sequence through the Qwords in a cache line during a burst operation. CADVY mode is used when the L2 cache consists of burst SRAMs. In this mode, assertion causes the burst SRAM in the L2 cache to advance to the next Qword in the cache line. CADSY/CAA3 O 3V CACHE ADDRESS STROBE/CACHE ADDRESS 3 (COPY A): This pin has two modes of operation depending on the type of SRAMs selected via hardware strapping options or programming the CC Register. The CAA3 mode is used when the L2 cache consists of asynchronous SRAMs. CAA3 is used to sequence through the Qwords in a cache line during a burst operation. CADSY mode is used when the L2 cache consists of burst SRAMs. In this mode assertion causes the burst SRAM in the L2 cache to load the BSRAM address register from the BSRAM address pins. CAB3 O 3V CACHE ADDRESS 3 (COPY B): CAB3 is used when the L2 cache consists of asynchronous SRAMs. CAB3 is used to sequence through the Qwords in a cache line during a burst operation CCSY/CAB4 O 3V CACHE CHIP SELECT/CACHE ADDRESS (COPY B): This pin has two modes of operation depending on the type of SRAMs selected via hardware strapping options or programming the CC Register. The CAB4 mode is used when the L2 cache consists of asynchronous SRAMs. CAB4 is used to sequence through the Qwords in a cache line during a burst operation. A L2 cache consisting of burst SRAMs will power up, if necessary, and perform an access if CCSY is asserted when CADSY is asserted. A L2 cache consisting of burst SRAMs will power down if CCSY is negated when CADSY is asserted. When CCSY is negated, a L2 cache consisting of burst SRAMs ignores ADSY. If CCSY is asserted when ADSY is asserted, a L2 cache consisting of burst SRAMs will power up, if necessary, and perform an access. COEY O 3V CACHE OUTPUT ENABLE: The secondary cache data RAMs drive the CPU's data bus when COEY is asserted. CWE [7:0] Y O 3V CACHE WRITE ENABLE: Each CWEY corresponds to one byte lane. Assertion causes the byte lane to be written into the secondary cache data RAMs if they are powered up. TIO [7:0] I/O 5V TAG ADDRESS: These are inputs during CPU accesses and outputs during L2 cache line fills and L2 cache line invalidates due to inquire cycles. TIO [7:0] contain the L2 tag address for 256-Kbyte L2 caches. TIO [6:0] contains the L2 tag address and TIO7 contains the L2 cache valid bit for 512-Kbyte caches. TWEY O 5V TAG WRITE ENABLE: When asserted, new state and tag addresses are written into the external tag. 9 82437FX TSC AND 82438FX TDP 2.1.4 PCI INTERFACE (TSC) Signal Name Type Description AD [31:0] I/O 5V ADDRESS DATA BUS: The standard PCI address and data lines. The address is driven with FRAMEY assertion and data is driven or received in following clocks. C/BE[3:0] Y I/O 5V COMMAND, BYTE ENABLE: The command is driven with FRAMEY assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. FRAMEY I/O 5V FRAME: Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. DEVSELY I/O 5V DEVICE SELECT: The TSC drvies DEVSELY when a PCI initiator attempts to access main memory. DEVSELY is asserted at medium decode time. IRDYY I/O 5V INITIATOR READY: Asserted when the initiator is ready for a data transfer. TRDYY I/O 5V TARGET READY: Asserted when the target is ready for a data transfer. STOPY I/O 5V STOP: Asserted by the target to request the master to stop the current transaction. LOCKY I/O 5V LOCK: Used to establish, maintain, and release resource locks on PCI. REQ [3:0] Y I 5V REQUEST: PCI master requests for PCI. GNT [3:0] Y O 5V GRANT: Permission is given to the master to use PCI. PHLDY I 5V PCI HOLD: This signal comes from the PIIX. PHLDY is the PIIX request for the PCI Bus. The TSC flushes the DRAM Write Buffers and acquires the host bus before granting PIIX via PHLDAY. This ensures that the guaranteed access time is met for ISA masters. PHLDAY O 5V PCI HOLD ACKNOWLEDGE: This signal is driven by the TSC to grant PCI to the PIIX. PAR I/O 5V PARITY: A single parity bit is provided over AD [31:0] and C/BE [3:0] . RSTY I 5V RESET: When asserted, RSTY resets the TSC and sets all register bits to the default value. 10 82437FX TSC AND 82438FX TDP 2.1.5 TDP INTERFACE (TSC) Signal Name Type PLINK [15:0] I/O 3V PCI LINK: These signals are connected to the PLINK data bus on the TDP. This is the data path between the TSC and TDP. Each TDP connects to one byte of the 16-bit bus. MSTBY O 3V MEMORY STROBE: Assertion causes data to be posted in the DRAM Write Buffer. MADVY O 3V MEMORY ADVANCE: For memory write cycles, assertion causes a Qword to be drained from the DRAM Write Buffer and the next data to be made available to the MD pins of the TDPs. For memory read cycles, assertion causes a Qword to be latched in the DRAM Input Register. PCMD [1:0] O 3V PLINK COMMAND: This field controls how data is loaded into the PLINK input and output registers. HOEY O 3V HOST OUTPUT ENABLE: This signal is used as the output enable for the Host Data Bus. MOEY O 3V MEMORY OUTPUT ENABLE: This signal is used as the output enable for the memory data bus. A buffered copy of MOEY also serves as a WEY select for the DRAM array. POEY O 3V PLINK OUTPUT ENABLE: This signal is used as the output enable for the PLINK Data Bus. Description 2.1.6 CLOCKS (TSC) Signal Name Type Description HCLKIN I 5V HOST CLOCK IN: This pin receives a buffered host clock. This clock is used by all of the TSC logic that is in the Host clock domain. This should be the same clock net that is delivered to the CPU. The net should tee and have equal lengths from the tee to the CPU and the TSC. PCLKIN I 5V PCI CLOCK IN: This pin receives a buffered divide-by-2 host clock. This clock is used by all of the TSC logic that is in the PCI clock domain. 11 82437FX TSC AND 82438FX TDP 2.2 TDP Signals 2.2.1 DATA INTERFACE SIGNALS (TDP) Signal Name Type Description HD[31:0] I/O 3V HOST DATA: These signals are connected to the CPU data bus. The CPU data bus is interleaved between the two TDPs for every byte, effectively creating an even and an odd TDP. MD [31:0] I/O 3V/5V MEMORY DATA: These signals are connected to the DRAM data bus. The DRAM data bus is interleaved between the two TDPs for every byte, effectively creating an even and an odd TDP. PLINK [7:0] I/O 3V PCI LINK: These signals are connected to the PLINK data bus on the TSC. This is the data path between the TSC and TDP. Each TDP connects to one byte of the 16-bit bus. 2.2.2 TSC INTERFACE SIGNALS (TDP) Signal Name Type Description MSTBY I 3V MEMORY STROBE: Assertion causes data to be posted in the DRAM Write Buffer. MADVY I 3V MEMORY ADVANCE: For memory write cycles, assertion causes a Qword to be flushed from the DRAM Write Buffer and the next data to be made available to the MD pins of the TDPs. For memory read cycles, assertion causes a Qword to be latched in the DRAM Input register. PCMD [1:0] I 3V PLINK COMMAND: This field controls how data is loaded into the PLINK input and output registers. HOEY I 3V HOST OUTPUT ENABLE: This signal is used as the output enable for the Host Data Bus. MOEY I 3V MEMORY OUTPUT ENABLE: This signal is used as the output enable for the Memory Data Bus. POEY I 3V PLINK OUTPUT ENABLE: This signal is used as the output enable for the PLINK Data Bus. 2.2.3 CLOCK SIGNAL (TDP) Signal Name Type HCLK I 5V 12 Description HOST CLOCK: Primary clock input used to drive the part. 82437FX TSC AND 82438FX TDP 2.3 Signal State During Reset Table 1 shows the state of all TSC and TDP output and bi-directional signals during a hard reset (RSTY asserted). The TSC samples the strapping options on the A [31:28] signal lines on the rising edge of RSTY. When RSTY is asserted, the TSC enables the TDP outputs via the HOEY, MOEY, and POEY TSC/TDP interface signals. When RSTY is negated, the TSC resets the TDP logic by driving HOEY, MOEY, and POEY inactive for two HCLKs. Table 1. Output and I/O Signal States During Hard Reset Signal State TSC Signal State Signal State CCSY/CAB4 High PAR Low A [31:28] Input CAB3 High PLINK [15:0] Low A [27:3] Low COEY High MSTBY High BRDYY High CWE [7:0] Y High MADVY High NAY High TIO [7:0] Y Tri-state PCMD [1:0] High AHOLD High TWEY High HOEY High EADSY High AD [31:0] Low MOEY Low BOFFY High C/BE [3:0] Y Low POEY KENY/INV Low FRAMEY Tri-state RAS [4:0] Y Low DEVSELY Tri-state HD [31:0] Low CAS [7:0] Y Low IRDYY Tri-state MD [31:1] Low MA [11:2] Low TRDYY Tri-state MD0 MAA [1:0] Low STOPY Tri-state NAND Tree Output MAB [1:0] Low LOCKY Tri-state PLINK [7:0] Low CADVY/CAA4 High GNT [3:0] Y Tri-state High PHLDAY Tri-state CADSY/CAA3 Low TDP 13 82437FX TSC AND 82438FX TDP 3.0 REGISTER DESCRIPTION The TSC contains two sets of software accessible registers (Control and Configuration registers), accessed via the Host CPU I/O address space. Control Registers control access to PCI configuration space. Configuration Registers reside in PCI configuration space and specify PCI configuration, DRAM configuration, cache configuration, operating parameters, and optional system features. The TSC internal registers (both I/O Mapped and Configuration registers) are only accessible by the Host CPU and cannot be accessed by PCI masters. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFADD which can only be accessed as a Dword. All multi-byte numeric fields use ``little-endian'' ordering (i.e., lower addresses contain the least significant parts of the field). The following nomenclature is used for access attributes. RO Read Only. If a register is read only, writes to this register have no effect. R/W Read/Write. A register with this attribute can be read and written. R/WC Read/Write Clear. A register bit with this attribute can be read and written. However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. Some of the TSC registers described in this section contain reserved bits. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That 14 is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. In addition to reserved bits within a register, the TSC contains address locations in the PCI configuration space that are marked ``Reserved'' (Table 2). The TSC responds to accesses to these address locations by completing the Host cycle. Software should not write to reserved TSC configuration locations in the device-specific region (above address offset 3Fh). During a hard reset (RSTY asserted), the TSC sets its internal configuration registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, cache configuration, operating parameters and optional system features that are applicable, and to program the TSC registers accordingly. 3.1 Control Registers The TSC contains two registers that reside in the CPU I/O address spacethe Configuration Address (CONFADD) Register and the Configuration Data (CONFDATA) Register. These registers can not reside in PCI configuration space because of the special functions they perform. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. 82437FX TSC AND 82438FX TDP 3.1.1 CONFADDCONFIGURATION ADDRESS REGISTER I/O Address: Default Value: 0CF8h (Dword access only) 00000000h Access: Read/Write CONFADD is a 32-bit register accessed only when referenced as a Dword. A Byte or Word reference will ``pass through'' the Configuration Address Register to the PCI Bus. The CONFADD Register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. Bit Descriptions 31 Configuration Enable (CONE): 1 e Enable; 0 e Disable. 30:24 Reserved. 23:16 Bus Number (BUSNUM): When BUSNUM is programmed to 00h, the target of the configuration cycle is either the TSC or the PCI Bus that is directly connected to the TSC, depending on the Device Number field. If the Bus Number is programmed to 00h and the TSC is not the target, a type 0 configuration cycle is generated on PCI. If the Bus Number is non-zero, a type 1 configuration cycle is generated on PCI with the Bus Number mapped to AD [23:16] during the address phase. 15:11 Device Number (DEVNUM): This field selects one agent on the PCI Bus selected by the Bus Number. During a Type 1 Configuration cycle, this field is mapped to AD [15:11] . During a Type 0 configuration cycle, this field is decoded and one of AD [31:11] is driven to 1. The TSC is always Device Number 0. 10:8 Function Number (FUNCNUM): This field is mapped to AD [10:8] during PCI configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed. The TSC responds to configuration cycles with a function number of 000b; all other function number values attempting access to the TSC (Device Number e 0, Bus Number e 0) generate a type 0 configuration cycle on the PCI Bus with no IDSEL asserted, which results in a master abort. 7:2 Register Number (REGNUM): This field selects one register within a particular bus, device, and function as specified by the other fields in the Configuration Address Register. This field is mapped to AD [7:2] during PCI configuration cycles. 1:0 Reserved. 3.1.2 CONFDATACONFIGURATION DATA REGISTER I/O Address: Default Value: CFCh 00000000h Access: Read/Write CONFDATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFDATA is determined by the contents of CONFADD. Bit 31:0 Descriptions Configuration Data Window (CDW): If bit 31 of CONFADD is 1, any I/O reference in the CONFDATA I/O space is mapped to configuration space using the contents of CONFADD. 15 82437FX TSC AND 82438FX TDP 3.2 PCI Configuration Registers The PCI Bus defines a slot based ``configuration space'' that allows each device to contain up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration spaceConfiguration Read and Configuration Write. While memory and I/O spaces are supported by the Pentium microprocessor, configuration space is not supported. The PCI specification defines two mechanisms to access configuration space, Mechanism Y1 and Mechanism Y2. The TSC only supports Mechanism Y1. Table 2 shows the TSC configuration space. The configuration access mechanism makes use of the CONFADD Register and CONFDATA Register. To reference a configuration register, a Dword I/O write cycle is used to place a value into CONFADD that specifies the PCI Bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFADD [31] must be 1 to enable a configuration cycle. Then, CONFDATA becomes a window onto four bytes of configuration space speci- 16 fied by the contents of CONFADD. Read/write accesses to CONFDATA generates a PCI configuration cycle to the address specified by CONFADD. Type 0 Access If the Bus Number field of CONFADD is 0, a type 0 configuration cycle is generated on PCI. CONFADD [10:2] is mapped directly to AD [10:2] . The Device Number field of CONFADD is decoded onto AD [31:11] . The TSC is Device Y0 and does not pass its configuration cycles to PCI. Thus, AD11 is never asserted. (For accesses to device Y1, AD12 is asserted, etc., to Device Y20 which asserts AD31.) Only one AD line is asserted at a time. All device numbers higher than 20 cause a type 0 configuration access with no IDSEL asserted, which results in a master abort. Type 1 Access If the Bus Number field of CONFADD is non-zero, a type 1 configuration cycle is generated on PCI. CONFADD [23:2] are mapped directly to AD [23:2] . AD [1:0] are driven to 01 to indicate a Type 1 Configuration cycle. All other lines are driven to 0. 82437FX TSC AND 82438FX TDP Table 2. TSC Configuration Space Address Offset Symbol Register Name VID 02-03h DID Device Identification RO 04-05h PCICMD Command Register R/W 06-07h PCISTS Status Register 08h RID Revision Identification 09h Vendor Identification Access 00-01h RO RO, R/WC RO Reserved 0Ah SUBC Sub-Class Code RO 0Bh BCC Base Class Code RO 0Ch 0Dh Reserved MLT 0Eh 0Fh BIST 10-49h 50h PCON BIST Register R/W PCI Control Register R/W Reserved CC 53-56h 57h R/W Reserved 51h 52h Master Latency Timer Reserved Cache Control R/W Reserved DRAMC DRAM Control R/W 58h DRAMT DRAM Timing R/W 59-5Fh PAM [6:0] Programmable Attribute Map (7 registers) R/W 60-64h DRB [4:0] DRAM Row Boundary (5 registers) R/W 65-67h 68h Reserved DRT 69-71h 72h 73-FFh DRAM Row Type R/W Reserved SMRAM System Management RAM Control R/W Reserved 17 82437FX TSC AND 82438FX TDP 3.2.1 VIDVENDOR IDENTIFICATION REGISTER Address Offset: 00-01h Default Value: 8086h Attribute: Read Only The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Description Vendor Identification Number: This is a 16-bit value assigned to Intel. 3.2.2 DIDDEVICE IDENTIFICATION REGISTER Address Offset: 02-03h Default Value: 122Dh Attribute: Read Only This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Description Device Identification Number. This is a 16-bit value assigned to the TSC. 3.2.3 PCICMDPCI COMMAND REGISTER Address Offset: 04-05h Default: 06h Access: Read/Write This register controls the TSC's ability to respond to PCI cycles. Bit Descriptions 15:10 Reserved. 9 Fast Back-to-Back: (Not Implemented) This bit is hardwired to 0. 8 SERRY Enable (SERRE): (Not Implemented) This bit is hardwired to 0. 7 Address/Data Stepping: (Not Implemented) This bit is hardwired to 0. 6 Parity Error Enable (PERRE): (Not Implemented) This bit is hardwired to 0. 5:3 Reserved: These bits are hardwired to 0. 2 Bus Master Enable (BME): (Not Implemented) The TSC does not support disabling of its bus master capability on the PCI Bus. This bit is hardwired to 1. 1 Memory Access Enable (MAE): 1 e Enable PCI master access to main memory, if the PCI address selects enabled DRAM space; 0 e Disable (TSC does not respond to main memory accesses). 0 I/O Access Enable (IOAE): (Not Implemented) This bit is hardwired to 0. The TSC does not respond to PCI I/O cycles. 18 82437FX TSC AND 82438FX TDP 3.2.4 PCISTSPCI STATUS REGISTER Address Offset: 06-07h Default Value: 0200h Access: Read Only, Read/Write Clear PCISTS reports the occurrence of a PCI master abort and PCI target abort. PCISTS also indicates the DEVSELY timing that has been set by the TSC hardware. Bit Descriptions 15 Detected Parity Error (DPE): (Not Implemented) This bit is hardwired to 0. 14 Signaled System Error (SSE)R/WC: This bit is hardwired to 0. 13 Received Master Abort Status (RMAS)R/WC: When the TSC terminates a Host-to-PCI transaction (TSC is a PCI master) with an unexpected master abort, this bit is set to 1. NOTE: Master abort is the normal and expected termination of PCI special cycles. Software sets this bit to 0 by writing 1 to it. 12 Received Target Abort Status (RTAS)R/WC: When a TSC-initiated PCI transaction is terminated with a target abort, RTAS is set to 1. Software sets RTAS to 0 by writing 1 to it. 11 Signaled Target Abort Status (STAS): This bit is hardwired to 0. The TSC never terminates a PCI cycle with a target abort. 10:9 DEVSELY Timing (DEVT)RO: This 2-bit field indicates the timing of the DEVSELY signal when the TSC responds as a target, and is hard-wired to the value 01b (medium) to indicate the slowest time that DEVSELY is generated. 8 Data Parity Detected (DPD)R/WC: This bit is hardwired to 0 7 Fast Back-to-Back (FB2B): (Not Implemented) This bit is hardwired to 0. 6:0 Reserved. 3.2.5 RIDREVISION IDENTIFICATION REGISTER Address Offset: 08h Default Value: See stepping information document Access: Read Only This register contains the revision number of the TSC. Bit 7:0 Description Revision Identification Number: This is an 8-bit value that indicates the revision identification number for the TSC. 19 82437FX TSC AND 82438FX TDP 3.2.6 SUBCSUB-CLASS CODE REGISTER Address Offset: 0Ah Default Value: 00h Access: Read Only This register indicates the function sub-class in relation to the Base Class Code. Bit 7:0 Description Sub-Class Code (SUBC): 00h e Host bridge. 3.2.7 BCCBASE CLASS CODE REGISTER Address Offset: 0Bh Default Value: 06h Access: Read Only This register contains the Base Class Code of the TSC. Bit 7:0 Description Base Class Code (BASEC): 06h e Bridge device. 3.2.8 MLTMASTER LATENCY TIMER REGISTER Address Offset: 0Dh Default Value: 00h Access: Read/Write MLT is an 8-bit register that controls the amount of time the TSC, as a bus master, can burst data on the PCI Bus. The Count Value is an 8-bit quantity. However, MLT [2:0] are hardwired to 0. MLT is also used to guarantee the host CPU a minimum amount of the system resources as described in the PCI Bus Arbitration section. Bit Description 7:3 Master Latency Timer Count Value: The number of clocks programmed in the MLT represents the minimum guaranteed time slice (measured in PCI clocks) allotted to the TSC, after which it must surrender the bus as soon as other PCI masters are granted the bus. The default value of MLT is 00h or 0 PCI clocks. The MLT should always be programmed to a non-zero value. 2:0 Reserved: Hardwired to 0. 20 82437FX TSC AND 82438FX TDP 3.2.9 BISTBIST REGISTER Address Offset: 0Fh Default: 00h Access: Read/Write The Built In Self Test (BIST) function is not supported by the TSC. Writes to this register have no affect. Bit Descriptions 7 BIST SupportedRO: 00h e Disable BIST function. 6 Start BIST: This function is not supported and writes have no affect. 5:4 Reserved. 3:0 Completion CodeRO: This field always returns 0 when read and writes have no affect. 3.2.10 PCONPCI CONTROL REGISTER Address Offset: 50h Default: 00h Access: Read/Write The PCON Register enables and disables features related to the PCI unit operation not already covered in the PCI required configuration space. Bit 7:5 Descriptions CPU Inactivity Timer Bits: This field selects the value used in the CPU Inactivity Timer. This timer counts CPU inactivity in PCI clocks. The inactivity window is defined as the last BRDYY to the next ADSY. When active, the CPU is default owner of the PCI Bus. If the CPU is inactive, PHOLD and the REQxY lines are given priority. Bits [7:5] PCI Clocks 000 001 010 011 100 101 110 111 1 2 3* 4 5* 6 7 8 * Recommended settings 4 Reserved. 3 Peer Concurrency Enable Bit (PCE): 1 e Peer Concurrency enabled. 0 e Peer Concurrency disabled. This bit is normally programmed to 1. 2 CPU-to-PCI Write Bursting Disable Bit: 0 e CPU-to-PCI Write bursting enabled. 1 e CPU-to-PCI Write bursting disabled. 1 PCI Streaming Bit: 0 e PCI streaming enabled. 1 e PCI streaming disabled. 0 Bus Concurrency Disable Bit: 0 e Bus concurrency enabled. 1 e Bus concurrency disabled. 21 82437FX TSC AND 82438FX TDP 3.2.11 CCCACHE CONTROL REGISTER Address Offset: 52h Default: SSSS0010 (S e Strapping option) Access: Read/Write The CC Register selects the secondary cache operations. This register enables/disables the L2 cache, adjusts cache size, defines the cache SRAM type, and controls tag initialization. After a hard reset, CC [7:4] reflect the inverted signal levels on the host address lines A [31:28] . Bit 7:6 Description Secondary Cache Size (SCS): This field reflects the inverted signal level on the A [31:30] pins at the rising edge of the RESET signal (default). The default values can be overwritten with subsequent writes to the CC Register. The options for this field are: Bits [7:6] Secondary Cache Size 0 0 1 1 Cache not populated 256 Kbytes 512 Kbytes Reserved 0 1 0 1 NOTE: 1. When SCS e 00, the L2 cache is disabled and the cache tag state is frozen. 2. To enable the L2 cache, SCS must be non-zero and the FLCE bit must be 1. 5:4 SRAM Type (SRAMT): This field reflects the inverted signal level on the A [29:28] pins at the rising edge of the RESET signal (default). The default values can be overwritten with subsequent writes to the CC Register. The options for this field are: Bits [5:4] 0 0 0 1 1 0 1 1 3 SRAM Type Pipelined Burst Burst Asynchronous Pipelined Burst for 512K/Dual-bank inplementations. Selects 3-1-1-1-2-1-1-1 instead of 3-1-1-1-1-1-1-1 back-to-back burst timings with NAY enabled. An extra clock is inserted for bank turnaround. SCS must be set to 10. NAY Disable Bit: 0 e NAY will be asserted as appropriate by the TSC (default). 1 e TCS's NAY signal is never asserted. This bit should be configured as desired before either the L1 or L2 caches are enabled. The NAY signal can be connected or disconnected from the processor as long as the NAY Disable bit is set to 1. Default is not set. 2 Reserved. 1 Secondary Cache Force Miss or Invalidate (SCFMI): When SCFMI e 1, the L2 hit/miss detection is disabled, and all tag lookups result in a miss. If the L2 is enabled, the cycle is processed as a miss. If the L2 is populated but disabled (FLCE e 0) and SCFMI e 1, any CPU read cycle invalidates the selected tag entry. When SCFMI e 0, normal L2 cache hit/miss detection and cycle processing occurs. Software can flush the cache (cause all modified lines to be written back to main memory) by setting SCFMI to 1 with the L2 cache enabled (SCS i 00 and FLCE e 1), and reading all L2 cache tag address locations. 22 82437FX TSC AND 82438FX TDP Bit 0 Description First Level Cache Enable (FLCE): FLCE enables/disables the first level cache. When FLCE e 1, the TSC responds to CPU cycles with KENY asserted for cacheable memory cycles. When FLCE e 0, KENY is always negated and line fills to either the first level or L2 cache are prevented. Note that, when FLCE e 1 and SCFMI e 1, writes to the cache are also forced as misses. Thus, it is possible to create incoherent data between main memory and the L2 cache. A summary of FLCE/SCFMI bit interactions is as follows: FLCE SCFMI 0 0 1 1 0 1 0 1 L2 Cache Result Disabled Disabled; tag invalidate on reads Normal L2 cache operation (dependent on SCS) Enabled; miss forced on reads/writes 3.2.12 DRAMCDRAM CONTROL REGISTER Address Offset: 57h Default Value: 01h Access: Read/Write This 8-bit register controls main memory DRAM operating modes and features. Bit Description 7:6 Hole Enable (HEN): This field enables a memory hole in main memory space. CPU cycles matching an enabled hole are passed on to PCI. PCI cycles matching an enabled hole are ignored by the TSC (no DEVSELY). Note that a selected hole is not remapped. Note that this field should not be changed while the L2 cache is enabled. Bits [7:6] 00 01 10 11 Hole Enabled None 512 Kbytes -640 Kbytes 15 Mbytes -16 Mbytes Reserved 5:4 Reserved. 3 EDO Detect Mode Enable (EDME): This bit, if set to 1, enables a special timing mode for BIOS to detect EDO DRAM type on a bank-by-bank basis. Once all DRAM row banks have been tested for EDO, the EDME bit should be set to 0. Otherwise, performance will be seriously impacted. An algorithm for using the EDME bit 3 follows the table. 2:0 DRAM Refresh Rate (DRR): The DRAM refresh rate is adjusted according to the frequency selected by this field. Note that refresh is also disabled via this field, and that disabling refresh results in the eventual loss of DRAM data. Bits [2:0] 000 001 010 011 1XX Host Bus Frequency Refresh Disabled 50 MHz 60 MHz 66 MHz Reserved 23 82437FX TSC AND 82438FX TDP DRAM Type Detection The EDO Detect Mode Enable field (bit 3) provides a special timing mode that allows BIOS to determine the DRAM type in each of the banks of main memory DRAM. To exploit the performance improvements from EDO DRAMs, the BIOS should provide for dynamic detection of any EDO DRAMs in the DRAM rows. 3.2.13 DRAMTDRAM TIMING REGISTER Address Offset: 58h Default Value: 00h Access: Read/Write This 8-bit register controls main memory DRAM timings. While most system designs will be able to use one of the faster burst mode timings, slower rates may be required in certain system designs to support layouts with longer trace lengths or slower DRAMs. Bit Description 7 Reserved. 6:5 DRAM Read Burst Timing (DRBT): The DRAM read burst timings are controlled by the DRBT field. The timing used depends on the type of DRAM on a per-bank basis, as indicated by the DRT register. DRBT EDO Burst Rate Standard Page Mode Rate 00 01 10 11 x444 x333 x222 Reserved x444 x444 x333 Reserved This field is typically set to ``01'' or ``10'' depending on the system configuration. 4:3 DRAM Write Burst Timing (DWBT): The DRAM write burst timings are controlled by the DWBT field. Slower rates may be required in certain system designs to support layouts with longer trace lengths or slower DRAMs. Most system designs will be able to use one of the faster burst mode timings. DWBT 00 01 10 11 Standard Page Mode Rate x444 x333 x222 (see notes 1 and 2) Reserved NOTES: 1. Minimum 3-Clock CASY Cycle Time for Single Writes. The DWBT field controls the minimum CASY cycle time for single and burst write cycles, except for the x222 programming case in which the minimum cycle time for single writes is limited to 3-clocks. 2. Two clock writes should not be programmed at 66 MHz. 2 RAS to CAS Delay (RCD): RCD controls the DRAM page miss and row miss leadoff timings. When RCD e 1, the RAS active to CAS active delay is 2 clocks. When RCD e 0, the timing is 3 clocks. Note that RCD timing adjustments are independent to DLT timing adjustments. RCD 0 1 24 RAS to CAS Delay 3 2 82437FX TSC AND 82438FX TDP Bit 1:0 Description DRAM Leadoff Timing (DLT): The DRAM leadoff timings for page/row miss cycles are controlled by the DLT bits. DLT controls the MA setup to the first CASY assertion. The DLT bits do not effect page hit cycles. DLT Read Leadoff Write Leadoff RASY Precharge 00 01 10 11 8 7 8 7 6 5 6 5 3 3 4 4 Note that the DLT field and RCD bit have cumulative affects (i.e., setting DLT0 e 0 and RCD e 0 results in two additional clocks betwwen RASY assertion and CASY assertion). 25 82437FX TSC AND 82438FX TDP 3.2.14 PAMPROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) Address Offset: PAM0 (59h)PAM6 (5Fh) Default Value: 00h Attribute: Read/Write The TSC allows programmable memory and cacheability attributes on 14 memory segments of various sizes in the 640-Kbyte to 1-Mbyte address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Three bits are used to specify L1 cacheability and memory attributes for each memory segment. These attributes are: RE Read Enable. When RE e 1, the CPU read accesses to the corresponding memory segment are directed to main memory. Conversely, when RE e 0, the CPU read accesses are directed to PCI. WE Write Enable. When WE e 1, the CPU write accesses to the corresponding memory segment are directed to main memory. Conversely, when WE e 0, the CPU write accesses are directed to PCI. CE Cache Enable. When CE e 1, the corresponding memory segment is L1 cacheable. CE must not be set to 1 when RE e 0 for any particular memory segment. When CE e 1 and WE e 0, the corresponding memory segment is cached in the first level cache only on CPU code read cycles. The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled (Table 3.). For example, if a memory segment has RE e 1 and WE e 0, the segment is Read Only. Table 3. Attribute Definition Read/Write Attribute Definition Read Only Read cycles: CPU cycles are serviced by the main memory or second level cache in a normal manner. Write cycles: CPU initiated write cycles are ignored by the DRAM interface as well as the second level cache. Instead, the cycles are passed to PCI for termination. Areas marked as read only are L1 cacheable for code accesses only. These regions are not cached in the second level cache. Write Only Read cycles: All read cycles are ignored by main memory as well as the second level cache. CPU-initiated read cycles are passed onto PCI for termination. The write only state can be used while copying the contents of a ROM, accessible on PCI, to main memory for shadowing, as in the case of BIOS shadowing. Write cycles: CPU write cycles are serviced by main memory and L2 cache in a normal manner. Read/Write This is the normal operating mode of main memory. Both read and write cycles from the CPU and PCI are serviced by main memory and L2 cache interface. Disabled All read and write cycles to this area are ignored by the main memory and cache interface. These cycles are forwarded to PCI for termination. 26 82437FX TSC AND 82438FX TDP Each PAM Register controls two regions, typically 16-Kbyte in size. Each of these regions has a 4-bit field. The four bits that control each region have the same encoding and are defined in Table 4. If the PAM programming indicates a region is readable, PCI master reads are accepted. If a PCI write to a non-writeable main memory region or a PCI read of a non-readable main memory region occurs, the TSC does not accept the cycle (DEVSELY is not asserted). PCI master accesses to enabled memory hole regions are not accepted by the TSC. PCI master access to main memory space is also controlled by the PAM Registers. If the PAM programming indicates a region is writeable, then PCI master writes are accepted (DEVSELY generated). Table 4. Attribute Bit Assignment Bits [7,3] Reserved Bits [6,2] Cache Enable Bits [5,1] Write Enable Bits [4,0] Read Enable x x 0 0 Main memory disabled; accesses directed to PCI x 0 0 1 Read only; main memory write protected; non-cacheable. Read-modify-write cycles to this space is not supported. x 1 0 1 Read only; main memory write protected; L1 cacheable for code accesses only x 0 1 0 Write only x 0 1 1 Read/write; non-cacheable x 1 1 1 Read/write; cacheable Description 27 82437FX TSC AND 82438FX TDP As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process, BIOS can be shadowed in main memory to increase the system performance. To shadow BIOS, the attributes for that address range should be set to write only. BIOS is shadowed by first performing a read of that address. This read is forwarded to the expansion bus. The CPU then performs a write of the same address, which is directed to main memory. After BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Table 5. PAM Registers and Associated Memory Segments PAM Reg Attribute Bits Memory Segment Comments Offset PAM0 [3:0] Reserved PAM0[7:4] R CE WE RE 0F0000 - 0FFFFFh BIOS Area 59h PAM1 [3:0] R CE WE RE 0C0000 - 0C3FFFh ISA Add-on BIOS 5Ah PAM1 [7:4] R CE WE RE 0C4000 - 0C7FFFh ISA Add-on BIOS 5Ah PAM2 [3:0] R CE WE RE 0C8000 - 0CBFFFh ISA Add-on BIOS 5Bh PAM2 [7:4] R CE WE RE 0CC000 - 0CFFFFh ISA Add-on BIOS 5Bh PAM3 [3:0] R CE WE RE 0D0000 - 0D3FFFh ISA Add-on BIOS 5Ch PAM3 [7:4] R CE WE RE 0D4000 - 0D7FFFh ISA Add-on BIOS 5Ch PAM4 [3:0] R CE WE RE 0D8000 - 0DBFFFh ISA Add-on BIOS 5Dh PAM4 [7:4] R CE WE RE 0DC000 - 0DFFFFh ISA Add-on BIOS 5Dh PAM5 [3:0] R CE WE RE 0E0000 - 0E3FFFh BIOS Extension 5Eh PAM5 [7:4] R CE WE RE 0E4000 - 0E7FFFh BIOS Extension 5Eh PAM6 [3:0] R CE WE RE 0E8000 - 0EBFFFh BIOS Extension 5Fh PAM6 [7:4] R CE WE RE 0EC000 - 0EFFFFh BIOS Extension 5Fh 59h NOTE: The CE bit should not be changed while the L2 cache is enabled. DOS Application Area (00000-9FFFh) Expansion Area (C0000 - DFFFFh) Read, write, and cacheability attributes are always enabled and are not programmable for the 0- 640Kbyte DOS application region. This 128-Kbyte area is divided into eight 16-Kbyte segments. Each segment can be assigned one of four read/write states: read-only, write-only, read/ write, or disabled memory that is disabled is not remapped. Cacheability status can also be specified for each segment. Video Buffer Area (A0000-BFFFFh) This 128-Kbyte area is not controlled by attribute bits. CPU-initiated cycles in this region are always forwarded to PCI for termination. This area is not cacheable. See section 3.2.16 for details on the use of this range as SMRAM. 28 Extended System BIOS Area (E0000 - EFFFFh) This 64-Kbyte area is divided into four 16-Kbyte segments. Each segment can be assigned independent cacheability, read, and write attributes. Memory segments that are disabled are not remapped elsewhere. 82437FX TSC AND 82438FX TDP System BIOS Area (F0000-FFFFFh) This area is a single 64-Kbyte segment. This segment can be assigned cacheability, read, and write attributes. When disabled, this segment is not remapped. Extended Memory Area (100000-FFFFFFFFh) The extended memory area can be split into several parts; # Flash BIOS area from 4 Gbyte to 4 Gbyte 512 Kbyte (aliased on ISA at 16 Mbyte 15.5 Mbyte) On power-up or reset the CPU vectors to the Flash BIOS area, mapped in the range of 4 Gbyte to 4 Gbyte - 512 Kbyte. This area is physically mapped on the expansion bus. Since these addresses are in the upper 4 Gbyte range, the request is directed to PCI. The main memory space can occupy extended memory from a minimum of 1 Mbyte up to 128 Mbytes. This memory is cacheable. PCI memory space from the top of main memory to 4Gbytes is always non-cacheable. # Main Memory from 1 Mbyte to a maximum of 128 Mbytes # PCI Memory space from the top of main memory to 4 Gbyte - 512 Kbyte 3.2.15 DRBDRAM ROW BOUNDARY REGISTERS Address Offset: 60h(DRB0)64h(DRB4) Default Value: Access: 02h Read/Write The TSC supports 5 rows of DRAM. Each row is 64 bits wide. The DRAM Row Boundary Registers define upper and lower addresses for each DRAM row. Contents of these 8-bit registers represent the boundary addresses in 4-Mbyte granularity. Note that bit 0 of each DRB must always be programmed to 0 for proper operation. DRB0 e Total amount of memory in row 0 (in 4 Mbytes) DRB1 e Total amount of memory in row 0 a row 1 (in 4 Mbytes) DRB2 e Total amount of memory in row 0 a row 1 a row 2 (in 4 Mbytes) DRB3 e Total amount of memory in row 0 a row 1 a row 2 a row 3 (in 4 Mbytes) DRB4 e Total amount of memory in row 0 a row 1 a row 2 a row 3 a row4 (in 4 Mbytes) The DRAM array can be configured with 512Kx32, 1Mx32, 2Mx32, and 4Mx32 SIMMs. Each register defines an address range that causes a particular RASY line to be asserted (e.g., if the first DRAM row is 8 Mbytes in size then accesses within the 0 to 8-Mbyte range causes RAS0Y to be asserted). Bit Description 7:6 Reserved. 5:0 Row Boundary Address: This 6-bit field is compared against address lines A [27:22] to determine the upper address limit of a particular row (i.e., DRB minus previous DRB e row size). 29 82437FX TSC AND 82438FX TDP Row Boundary Address These 6-bit values represent the upper address limits of the 5 rows (i.e., this row minus previous row e row size). Unpopulated rows have a value equal to the previous row (row size e 0). DRB4 reflects the maximum amount of DRAM in the system. The top of memory is determined by the value written into DRB4. If DRB4 is greater than 128 Mbytes, then 128 Mbytes of DRAM are available. As an example of a general purpose configuration where 4 physical rows are configured for either single-sided or double-sided SIMMs, the memory array would be configured like the one shown Figure 2. In this configuration, the TSC drives two RASY signals directly to the SIMM rows. If single-sided SIMMs are populated, the even RASY signal is used and the odd RASY is not connected. If double-sided SIMMs are used, both RASY signals are used. 290518 - 4 Figure 2. SIMMs and Corresponding DRB Registers 30 82437FX TSC AND 82438FX TDP The following 2 examples describe how the DRB Registers are programmed for cases of single-sided and double-sided SIMMs on a motherboard having a total of four 8-byte or eight 4-byte SIMM sockets. Example Y1 The memory array is populated with four single-sided 1MB x 32 SIMMs, a total of 16 Mbytes of DRAM. Two SIMMs are required for each populated row making each populated row 8 Mbytes in size. DRB0 e 02h populated (2 SIMMs, 8 Mbyte this row) DRB1 e 04h populated (2 SIMMs, 8 Mbyte this row) empty row empty row DRB2 e 04h DRB3 e 04h DRB4 e 04h Example Y2 The memory array is populated with two 2-Mbyte x 32 double-sided SIMMs (one row), and four 4-Mbyte x 32 single-sided SIMMs (two rows), yielding a total of 96 Mbytes of DRAM. The DRB Registers are programmed as follows: DRB0 e 04h DRB1 e 08h DRB2 e 10h DRB3 e 18h DRB4 e 18h populated with 16 Mbytes, (/2 of double-sided SIMMs the other 16 Mbytes of the double-sided SIMMs populated with 32 Mbytes, one of the sided SIMMs the other 32 Mbytes of single-sided SIMMs empty row empty row 3.2.16 DRTDRAM ROW TYPE REGISTER Address Offset: 68h Default Value: 00h Access: Read/Write This 8-bit register identifies the type of DRAM (EDO or page mode) used in each row, and should be programmed by BIOS for optimum performance if EDO DRAMs are used. The TSC uses these bits to determine the correct cycle timing on DRAM cycles. Bit Description 7:5 Reserved. 4:0 DRAM Row Type (DRT [4:0] ): Each bit in this field corresponds to the DRAM row identified by the corresponding DRB Register. Thus, DRT0 corresponds to row 0, DRT1 to row 1, etc. When DRTx e 0, page mode DRAM timings are used for that bank. When DRTx e 1, EDO DRAM timings are used for that bank. 31 82437FX TSC AND 82438FX TDP 3.2.17 SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER Address Offset: 72h Default Value: 02h Access: Read/Write The System Management RAM Control Register controls how accesses to this space are treated. The Open, Close, and Lock SMRAM Space bits function only when the SMRAM enable bit is set to 1. Also, the OPEN bit (DOPEN) should be set to 0 before the LOCK bit (DLCK) is set to 1. Bit Description 7 Reserved. 6 SMM Space Open (DOPEN): When DOPEN e 1 and DLCK e 0, SMM space DRAM is made visible, even when SMIACTY is negated. This is intended to help BIOS initialize SMM space. Software should ensure that DOPEN e 1 is mutually exclusive with DCLS e 1. When DLCK is set to 1, DOPEN is set to 0 and becomes read only. 5 SMM Space Closed (DCLS): When DCLS e 1, SMM space DRAM is not accessible to data references, even if SMIACTY is asserted. Code references may still access SMM space DRAM. This allows SMM software to reference ``through'' SMM space to update the display, even when SMM space is mapped over the VGA range. Software should ensure that DOPEN e 1 is mutually exclusive with DCLS e 1. 4 SMM Space Locked (DLCK): When DLCK is set to 1, the TSC sets DOPEN to 0 and both DLCK and DOPEN become read only. DLCK can be set to 1 via a normal configuration space write but can only be cleared by a power-on reset. The combination of DLCK and DOPEN provide convenience with security. The BIOS can use the DOPEN function to initialize SMM space and then use DLCK to ``lock down'' SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the DOPEN function. 3 SMRAM Enable (SMRAME): When SMRAME e 1, the SMRAM function is enabled, providing 128 Kbytes of DRAM accessible at the A0000h address while in SMM (ADSY with SMIACTY). 2:0 SMM Space Base Segment (DBASESEG): This field selects the location of SMM space. ``SMM DRAM'' is not remapped. It is simply ``made visible'' if the conditions are right to access SMM space. Otherwise, the access is forwarded to PCI. DBASESEG e 010 is the only allowable setting and selects the SMM space as A0000-BFFFFh. All other values are reserved. PCI masters are not allowed access to SMM space. 32 82437FX TSC AND 82438FX TDP Table 6 summarizes the operation of SMRAM space cycles targeting SMI space addresses (A and B segments): Table 6. SMRAM Space Cycles SMRAME DLCK DCLS DOPEN SMIACTY Code Fetch Data Reference 0 X X X X PCI PCI 1 0 0 0 0 DRAM DRAM 1 0 X 0 1 PCI PCI 1 0 0 1 X DRAM DRAM 1 0 1 0 0 DRAM PCI 1 0 1 1 X INVALID INVALID 1 1 0 X 0 DRAM DRAM 1 1 X X 1 PCI PCI 1 1 1 X 0 DRAM PCI 33 82437FX TSC AND 82438FX TDP 4.0 FUNCTIONAL DESCRIPTION This section provides a functional description of the TSC and TDP. Read prefetch and write posting buffers in the TSC/ TDPs enable PCI masters to access main memory at up to 120 MB/second. The TSC incorporates a snoop-ahead feature which allows PCI masters to continue bursting on both reads and writes even as the bursts cross cache line boundaries. 4.1 Host Interface The Host Interface of the TSC is designed to support the Pentium processor. The host interface of the TSC supports 50 MHz, 60 MHz, and 66 MHz bus speeds. The 82430FX PCIset supports the Pentium processor with a full 64-bit data bus, 32-bit address bus, and associated internal write-back cache logic. Host bus addresses are decoded by the TSC for accesses to main memory, PCI memory, and PCI I/ O. The TSC also supports the pipelined addressing capability of the Pentium processor. 4.2 PCI Interface The 82437FX integrates a high performance interface to the PCI local bus taking full advantage of the high bandwidth and low latency of PCI. Five PCI masters are supported by the integrated arbiter including a PCI-to-ISA bridge and four general PCI masters. The TSC acts as a PCI master for CPU accesses to PCI. The PCI Bus is clocked at one half the frequency of the CPU clock. This divided synchronous interface minimizes latency for CPU-to-PCI cycles and PCI-to-main memory cycles. The TSC/TDPs integrate posted write buffers for CPU memory writes to PCI. Back-to-back sequential memory writes to PCI are converted to burst writes on PCI. This feature allows the CPU to continue posting dword writes at the maximum bandwidth for the Pentium processor for the highest possible transfer rates to the graphics frame buffer. 4.3 Secondary Cache Interface The TSC integrates a high performance second level cache controller using internal/external tags and provides a full first level and second level cache coherency mechanism. The second level cache is direct mapped, non-sectored, and supports a writeback cache policy. Cache lines are allocated on read misses (no write allocate). The second level cache can be configured for either 256-Kbyte or 512-Kbyte cache sizes using either synchronous burst or pipelined burst SRAMs, or standard asynchronous SRAMs. For the 256-Kbyte configurations, an 8kx8 standard SRAM is used to store the tags. For the 512-Kbyte configurations, a 16kx8 standard SRAM is used to store the tags and the valid bits. A 5V SRAM is used for the Tag. A second level cache line is 32 bytes wide. In the 256-Kbyte configurations, the second level cache contains 8K lines, while the 512-Kbyte configurations contain 16K lines. Valid and modified status bits are kept on a per-line basis. Cacheability of the entire memory space in the first level cache is supported. For the second level cache, only the lower 64 Mbytes of main memory are cacheable (only main memory controlled by the TSC DRAM interface is cached). PCI memory is not cached. Table 7 shows the different standard SRAM access time requirements for different host clock frequencies. Table 7. SRAM Access Time Requirements 34 Standard Burst Tag RAM Access Time (ns) Tag RAM Access Time (ns) 13.5 30 20 10 20 15 8.5 15 15 Host Clock Frequency (MHz) Standard SRAM Access Time (ns) Burst SRAM Clock-to-Output Access Time (ns) 50 20 (17 ns Buffer) 60 17 (10 ns Buffer) 66 15 (7 ns Buffer) 82437FX TSC AND 82438FX TDP 4.3.1 CLOCK LATENCIES Table 8 and Table 9 list the latencies for various processor transfers to and from the second level cache for standard and burst SRAM. The clock counts are identical for pipelined and non-pipelined burst SRAM. Table 8. Second Level Cache Latencies with Standard SRAM Cycle Type HCLK Count Burst Read 3-2-2-2 Burst Write (Write Back) 4-3-3-3 Single Read 3 Single Write 4 Table 9. Second Level Cache Latencies with Burst SRAM Cycle Type HCLK Count Burst Read 3-1-1-1 Burst Write (Write Back) 3-1-1-1 Single Read 3 Single Write 3 Pipelined Back-to-Back Burst Reads 3-1-1-1, 1-1-1-1 4.3.2 SNOOP CYCLES Snoop cycles are used to maintain coherency between the caches (first and second level) and main memory. The TSC generates a snoop (or inquire) cycle to probe the first level and second level caches when a PCI master attempts to access main memory. Snoop cycles are performed by driving the PCI master address onto the host address bus and asserting EADSY. To maintain optimum PCI bandwidth to main memory, the TSC utilizes a ``snoop ahead'' algorithm. Once the snoop for the first cache line of a transfer has completed, the TSC automatically snoops the next sequential cache line. This algorithm enables the TSC to continue burst transfers across cache line boundaries. Reads If the snoop cycle generates a first level cache hit to a modified line, the line in the first level cache is written back to main memory (via the DRAM Posted Write Buffers). The line in the second level cache (if it exists) is invalidated. Note that the line in the first level cache is not invalidated if the INV pin on the CPU is tied to the KENY signal from the TSC. The TSC drives KENY/INV low with EADSY assertion during PCI master read cycles. At the same time as the first level snoop cycle, the TSC performs a tag look-up to determine whether the addressed memory is in the second level cache. If the snoop cycle generates a second level cache hit to a modified line and there was not a hit in the first level cache (HITMY not asserted), the second level cache line is written back to main memory (via the DRAM Posted Write Buffers) and changed to the ``clean'' state. The PCI master read completes after the data has been written back to main memory. Writes PCI Master write cycles never result in a write directly into the second level cache. A snoop hit to a modified line in either the first or second caches results in a write-back of that line to main memory. If both the first and second level caches have modified lines, the line is written back from the first level cache. In all cases, lines in the first and second level caches are invalidated and the PCI write to main memory occurs after the writeback completes. A PCI master write snoop hit to an unmodified line in either the first or second level caches results in the line being invalidated. The TSC drives KENY/INV with EADSY assertion during PCI master write cycles. 4.3.3 CACHE ORGANIZATION Figure 3, Figure 4, Figure 5, Figure 6, and Figure 7 show the connections between the TSC and the external tag RAM and data SRAM. A 512K standard SRAM cache is implemented with 64Kx8 data SRAMs and a 16Kx8 tag RAM. The second ADSY pin from the CPU should be used to drive the ADSPY pin on Burst or Pipelined Burst SRAMs. 35 82437FX TSC AND 82438FX TDP 4.3.4 Clarification On How to Flush the L2 Cache The SCFMI (Force Miss/Invalidate) mode is intended to allow flushing of dirty L2 lines back to memory. Since the flushed dirty line is posted to the DRAM write buffer in parallel with the linefill, the new line (which is filled to both L1 and L2) is guaranteed to be stale data. The implication of the actual operation is that any program that is attempting to flush the L2 must not be run from the L2 itself, unless the L2 code image is coherent with DRAM. For example, if a DOS program to flush the L2 is loaded, it is loaded from disk using a string move. The MOVS may result in load- ing the program partially into L2, since the memory writes will (likely) hit previously valid lines in the L2. When the flush program sets the SCFMI bit to force misses, subsequent code fetches may be serviced from L2 which contain the stale code image. An important aspect to consider when flushing L2 is to ensure that the code being used to flush the cache is not in the current 256K page (256K L2 being used here) residing in L2. The BIOS algorithm will also work if it is executed from non-cacheable or write-protected DRAM space (e.g., BIOS region). If this can't be guaranteed, then an alternate software flush algorthm is to read 2X the size of the L2. Note that this implies a protected-mode code for the 512K L2 case. 290518 - 5 Figure 3. 256-Kbyte Second Level Cache (Standard SRAM) 36 82437FX TSC AND 82438FX TDP 290518 - 6 Figure 4. 256-Kbyte Second Level Cache (Burst SRAM) 37 82437FX TSC AND 82438FX TDP 290518 - 7 Figure 5. 256-Kbyte Second Level Cache (Burst SRAM) 38 82437FX TSC AND 82438FX TDP 290518 - 8 Figure 6. 512-Kbyte Second Level Cache (Burst SRAM) 39 82437FX TSC AND 82438FX TDP 290518 - 9 Figure 7. Two Bank 512-Kbyte Second Level Cache (Pipelined Burst SRAM) 40 82437FX TSC AND 82438FX TDP 4.4 DRAM Interface The 82430FX PCIset's main memory DRAM interface supports a 64-bit wide memory array and main memory sizes from 4 to 128 Mbytes. The TSC generates the RASY, CASY, WEY (using MOEY) and multiplexed addresses for the DRAM array and controls the data flow through the 82438FX TDP's. For CPU-to-DRAM cycles the address flows through the TSC and data flows through the TDP's. For PCI or ISA cycles to memory the address flows through the TSC and data flows to the TDP's through the TSC and PLINK bus. The TSC and TDP DRAM interfaces are synchronous to the CPU clock. The 82430FX PCIset supports industry standard 32-bit wide memory modules with fast page-mode DRAMs and EDO (Extended Data Out) DRAMs (also known as Hyper Page mode). With twelve multiplexed address lines (MA [11:0] ), the TSC supports 512Kx32, 1M32, 2Mx32, and 4Mx32 SIMM's (both symmetrical and asymmetrical addressing). Five RASY lines permit up to five rows of DRAM and eight CASY lines provide byte write control over the array. The TSC supports 60 ns and 70 ns DRAMs (both single and double-sided SIMM's). The TSC also provides an automatic RASY only refresh, at a rate of 1 refresh per 15.6 ms at 66 MHz, 60 MHz, and 50 MHz. A refresh priority queue and ``smart refresh'' algorithm are used to minimize the performance impact due to refresh. The DRAM controller interface is fully configurable through a set of control registers (see Register Description section for programming details). The DRAM interface is configured by the DRAM Control Mode Register, the five DRAM Row Boundary (DRB) Registers, and the DRAM Row Type (DRT) Register. The DRAM Control Mode Registers configure the DRAM interface to select fast page-mode or EDO DRAMs, RAS timings, and CAS rates. The five DRB Registers define the size of each row in the memory array, enabling the TSC to assert the proper RASY line for accesses to the array. Seven Programmable Attribute Map (PAM) Registers are used to specify the cacheability, PCI enable, and read/write status of the memory space between 640 Kbytes and 1 Mbyte. Each PAM Register defines a specific address area enabling the system to selectively mark specific memory ranges as cacheable, read-only, write-only, read/write, or disabled. When a memory range is disabled, all CPU accesses to that range are forwarded to PCI. The TSC also supports one of two memory holes; either from 512 Kbytes b 640 Kbytes or from 15 Mbytes b 16 Mbytes in main memory. Accesses to the memory holes are forwarded to PCI. The memory hole can be enabled/disabled through the DRAM Control Register. All other memory from 1 Mbyte to the top of main memory is read/write and cacheable. The SMRAM memory space is controlled by the SMRAM Control Register. This register selects if the SMRAM space is enabled, opened, closed, or locked. SMRAM space is between 640 Kbytes and 768 Kbytes. See section 3.2.17 for more details on SMRAM. 4.4.1 DRAM ORGANIZATION Figure 8 illustrates a 4-SIMM configuration that supports 4 double-sided SIMM's and motherboard DRAM. RAS0Y is used for motherboard memory. This memory should not be implemented with SIMMs. Except for motherboard memory, a row in the DRAM array is made up of two SIMM's that share a common RASY line. Within any given row, the two SIMMs must be the same size. For different rows, SIMM densities can be mixed in any order. Each row is controlled by 8 CAS lines. EDO and Standard page mode DRAM's can be mixed between rows or within a row. When DRAM types are mixed (EDO and standard page mode), each row will run optimized for that particular type of DRAM. If DRAM types are mixed within a row, page mode timings must be selected. SIMMs can be used for the sockets connected to RAS [2:1] Y and RAS [4:3] Y. The two RAS lines permit double-sided SIMMs to be used in these socket pairs. The following rules apply to the SIMM configuration. 1. SIMM sockets can be populated in any order. 2. SIMM socket pairs need to be populated with the same densities. For example, SIMM sockets RAS [2:1] Y should be populated with identical densities. However, SIMM sockets using RAS [4:3] Y can be populated with different densities than the SIMM socket pair using RAS [2:1] Y. 41 82437FX TSC AND 82438FX TDP 3. The TSC only recognizes a maximum of 128 Mbytes of main memory, even if populated with more memory. 4.4.3 DRAM ADDRESS TRANSLATION The multiplexed row/column address to the DRAM memory array is provided by MA[11:0] which are derived from the host address bus or PCI address as defined by Table 10. The TSC has a 4-Kbyte page size. The page offset address is driven on the MA [8:0] lines when driving the column address. The MA [11:0] lines are translated from the address lines A [24:3] for all memory accesses. 4. EDO's and standard page mode can both be used. 4.4.2 MAIN MEMORY ADDRESS MAP The main memory organization (Figure 9) represents the maximum 128 Mbytes of address space. Accesses to memory space above the top of main memory, video buffer range, or the memory gaps (if enabled) are not cacheable and are forwarded to PCI. Below 1 Mbyte, there are several memory segments with selectable cacheability. Table 10. DRAM Address Translation Memory Address, MA [11:0] 11 10 9 8 7 6 5 4 3 2 1 0 Row Address A24 A23 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Column Address X A24 A22 A11 A10 A9 A8 A7 A6 A5 A4 A3 The types of DRAMs depth configuration supported are: Depth 42 Row Width Column Width 512K 10 9 1M 10 10 2M 11 10 4M 11 11 4M 12 10 82437FX TSC AND 82438FX TDP 290518 - 10 Figure 8. DRAM Array Connections 43 82437FX TSC AND 82438FX TDP 4.4.4 DRAM PAGE MODE For any row containing standard page mode DRAM on read cycles, the TSC keeps CAS [7:0] Y asserted until data is sampled by the TDPs. 290518 - 11 Figure 9. Memory Space Organization 44 82437FX TSC AND 82438FX TDP 4.4.5 EDO MODE Extended Data Out (or Hyper Page Mode) DRAM is designed to improve the DRAM read performance. EDO DRAM holds the memory data valid until the next CASY falling edge. Note that standard page mode DRAM tri-states the memory data when CASY negates to precharge. With EDO, the CASY precharge overlaps the memory data valid time. This allows CASY to negate earlier while still satisfying the memory data valid window time. The EDO Detect Mode Enable bit in the DRAM Control Register enables a special timing mode for BIOS to detect the DRAM type on a row by row basis. 2. For each bank row (Row1, Row2, Row3, Row4, Row5) # Write all 1's to a QWORD address within the row. # Enable EDO detection mode by setting the EDO Detect Mode Enable bit in the DRAMC register (TSC PCI Config. Offset 57h) to 1. # # # 4.4.5.1 BIOS Configuration of DRAM Array When Using EDO DRAMs Immediately read back the value of the QWORD ADDRESS. If the value is not all 1's, then standard page mode DRAMs are installed in that row. Otherwise the EDO mode DRAMs are installed in that row. Disable EDO detection mode by clearing the EDO Detect Mode Enable bit in the DRAMC register. The following algorithm should be followed in order to dynamically detect if EDO DRAMs are installed in the system. When this algorithm has completed, the DRAM type installed in each row is programmed into the DRAM Row Type register (TSC PCI Config. Offset 68h): 3. Depending on the findings of Step Y2, program the DRAM row type into the corresponding bit in the DRT register (TSC PCI Config. Offset 68h): set for EDO type (1) or reset for standard page mode (0). Do not program this register until all of the bank rows have been tested. 1. Initialize all of the DRAM Row Type values to `EDO' in the DRT register (TSC PCI Config. Offset 68h). Since there are five rows, the DRT register value becomes `1Fh'. Once all DRAM row banks have been tested for EDO, the EDME bit should be cleared in DRAMC (TSC PCI Config. Offset 57h, bit 2 is 0). It is very important that the EDME bit be cleared afterwards or performance will be seriously impacted. Table 11. CPU to DRAM Performance Summary Processor Cycle Type (Pipelined) Burst read page hit Read row miss Read page miss Back-to-back burst reads page hit Clock Count (ADSY to BRDYY) Comments 7-2-2-2 EDO 9-2-2-2 (note 1) EDO 12-2-2-2 EDO 7-2-2-2-3-2-2-2 EDO Burst read page hit 7-3-3-3 Standard page mode Burst read row miss 9-3-3-3 (note 1) Standard page mode Burst read page miss 12-3-3-3 Standard page mode Back-to-back burst read page hit Posted write Retire data for posted write 7-3-3-3-3-3-3-3 Standard page mode 3-1-1-1 EDO/Standard page mode Every 3 clocks EDO/Standard page mode NOTES: 1. Due to the MA[11:2] to RASY setup requirements, if a page is open, two clocks are added to the leadoff. 2. Read and write rates to DRAM are programmable via the DRAMT Register. 45 82437FX TSC AND 82438FX TDP 4.4.6 DRAM PERFORMANCE The DRAM performance is controlled by the DRAM Timing Register, processor pipelining, and by the type of DRAM used (EDO or standard page mode). Table 11 lists both EDO and standard page mode optimum timings. 4.4.7 DRAM REFRESH The TSC supports RASY only refresh and generates refresh requests. The rate that requests are generated is determined by the DRAM Control Register. When a refresh request is generated, the request is placed in a four entry queue. The DRAM controller services a refresh request when the refresh queue is not empty and the controller has no other requests pending. When the refresh queue is full, refresh becomes the highest priority request and is serviced next by the DRAM controller, regardless of other pending requests. When the DRAM controller begins to service a refresh request, the request is removed from the refresh queue. There is also a ``smart refresh'' algorithm implemented in the refresh controller. Except for Bank 0, refresh is only performed on banks that are populated. For bank 0, refresh is always performed. If only one bank is populated, using bank 0 will result in better performance. 4.4.8 SYSTEM MANAGEMENT RAM the use of System Management Mode. When this function is disabled, the TSC memory map is defined by the DRB and PAM Registers. When SMRAM is enabled, the TSC reserves the A and B segments of main memory for use as SMRAM. SMRAM is placed at A0000-BFFFFh via the SMRAM Space Register. Enhanced SMRAM features can also be enabled via this register. PCI masters can not access SMRAM when it is programmed to the A and B segments. When the TSC detects a CPU stop grant special cycle, it generates a PCI Stop Grant Special cycle with 0002h in the message field (AD [15:0] ) and 0012h in the message dependent data field (AD [31:16] ) during the first data phase (IRDYY asserted). A system using 5mm interrupts with addresses directed to SMM memory space in segments A0000 and B0000h must not have the 512K - 640K memory hole enabled. 4.5 82438FX Data Path (TDP) The TDP's provide the data path for host-to-main memory, PCI-to-main memory, and host-to-PCI cycles. Two TDP's are required for the 82430FX PCIset system configuration. The TSC controls the data flow through the TDP's with the PCMD [1:0] , HOEY, POEY, MOEY, MSTBY, and MADVY signals. The 82430FX PCIset support the use of main memory as System Management RAM (SMRAM), enabling 290518 - 12 Figure 10. TDP 64-Bit Data Path Partitioning 46 82437FX TSC AND 82438FX TDP The TDP's have three data path interfaces; the host bus (HD [63:0] ). the memory bus (MD [63:0] ), and the PLINK [15:0] bus between the TDP and TSC. The data paths for the TDP's are interleaved on byte boundaries (Figure 10). Byte lanes 0, 2, 4, and 6 from the host CPU data bus connects to the even order TDP and byte lanes 1, 3, 5, and 7 connect to the odd order TDP. PLINK [7:0] connects to the even order TDP and PLINK [15:8] connect to the odd order TDP. 4.6 PCI Bus Arbitration The TSC's PCI Bus arbiter allows PCI peer-to-peer traffic concurrent with CPU main memory/second level cache cycles. The arbiter supports five PCI masters (Figure 11). REQ [3:0] Y/GNT [3:0] Y are used by PCI masters other than the PCI-to-ISA expansion bridge (PIIX). PHLDY/PHLDAY are the arbitration request/grant signals for the PIIX and provide guaranteed access time capability for ISA masters. PHLDY/PHLDAY also optimize system performance based on PIIX known policies. rotation. The rotation priority chain is fixed (Figure 12). If the highest priority agent does not request the bus, the next agent in the chain is the highest priority, and so forth down the chain. When no PCI agents are requesting the bus, the CPU is the default owner of the bus. CPU cycles incur no additional delays in this state. The grant signals (GNTxY) are normally negated after FRAMEY assertion or 16 PCLKs from grant assertion, if no cycle has started. Once asserted, PHLDAY is only negated after PHLDY has been negated. A possible PCI contention condition is possible if a PCI master had been requesting the PCI bus for some time and the TSC has just flushed its CPU-toPCI write posting buffers. In this case, the TSC could grant the master the bus one clock early. The TSC will be in the process of floating its output buffers while a newly granted master is starting to drive the bus. Some contention is possible on AD [31:0] , C/BE [3:0] Y and PAR signals. 4.6.1.1 Arbitration Signaling Protocol: REQY Functionality 290518 - 13 Figure 11. Arbiter 4.6.1 PRIORITY SCHEME AND BUS GRANT The arbitration mechanism employs two interacting priority queues; one for the CPU and one for the PCI agents. The CPU queue guaranatees that the CPU is explicity granted the bus on every fourth arbitration event. The PCI priority queue determines which PCI agent is granted when PCI wins the arbitration event. A rotating priority scheme is used to determine the highest priority requester in the case of simultaneous requests. If the highest priority input at arbitration time does not have an active request, the next priority active requester is granted the bus. Granting the bus to a lower priority requester does not change the rotation order, but it does advance the priority PCI Masters should follow the intent of the PCI Specification as quoted from the PCI Specification below: 1. ``Agents must only use REQY to signal a true need to use the bus.'' 2. ``An Agent must never use REQY to ``park'' itself on the bus.'' A ``well behaved'' card should use REQY when the bus is really needed. Typically REQY should be removed, once the PCI master has been granted the bus, after FRAMY is asserted. REQY line behavior, of future PCI Cards, that may not operate as required could include: 1. Glitching REQY lines for one or more clocks without any apparent reason. 2. Glitching REQY lines and then not waiting for GNTY assertion. 3. Continually asserting REQY lines in an attempt to park itself on the PCI bus. 4. Failing to assert FRAMEY with several clocks of GNTY assertion when bus is idle. 47 82437FX TSC AND 82438FX TDP 290518 - 14 NOTES: 1. For the CPU/PCI priority queue, the CPU is granted the PCI Bus after three consecutive PCI grants. 2. For the PCI priority queue, the last agent granted is always dropped to the bottom of the queue for the next arbitration cycle. However, the order of the chain is always preserved. Figure 12. Arbitration Priority Rotation PCI Cards that do not operate properly may not function properly with the TSC. 4.7 Clock Generation and Distribution 4.6.2 CPU POLICIES The TSC and CPU should be clocked from one clock driver output to minimize skew between the CPU and TSC. The TDPs should share another clock driver output. The CPU never explicitly requests the bus. Instead, the arbiter grants the bus to the CPU when: # the CPU is the highest priority # PCI agents do not require main memory (peer-topeer transfers or bus idle) and the PCI Bus is not currently locked by a PCI master When the CPU is granted as highest priority, the MLT timer is used to guarantee a minimum amount of system resources to the CPU before another requesting PCI agent is granted. An AHOLD mechanism controls granting the bus to the CPU. 48 4.7.1 RESET SEQUENCING The TSC is asynchronously reset by the PCI reset (RSTY). After RSTY is negated, the TSC resets the TDP by driving HOEY, MOEY, and POEY to 1 for two HCLKs. The TSC changes HOEY, MOEY, and POEY to their default value after the TDP is reset. Arbiter (Central Resource) Functions on Reset The TSC arbiter includes support for PCI central resource functions. These functions include driving the AD [31:0] , C/BE [3:0] Y, and PAR signals when no agent is granted the PCI Bus and the bus is idle. The TSC drives 0's on these signals during reset and drives valid levels when no other agent is granted and the bus is idle. 82437FX TSC AND 82438FX TDP 5.0 PINOUT AND PACKAGE INFORMATION 5.1 82437FX Pinout 290518 - 15 Figure 13. 82437FX Pin Assignment 49 82437FX TSC AND 82438FX TDP Table 12. 82437FX Alphabetical Pin Assignment Name 50 PinY Type A3 37 I/O A4 40 I/O A5 43 A6 42 A7 A8 Name PinY Type AD0 3 I/O AD1 206 I/O I/O AD2 205 I/O AD3 204 41 I/O AD4 44 I/O AD5 A9 56 I/O A10 46 I/O A11 45 A12 57 A13 A14 Name PinY Type AD29 161 I/O AD30 160 I/O I/O AD31 159 I/O I/O ADSY 70 I 203 I/O AHOLD 65 O 202 I/O BE0Y 80 I AD6 201 I/O BE1Y 81 I AD7 200 I/O BE2Y 82 I I/O AD8 198 I/O BE3Y 83 I I/O AD9 197 I/O BE4Y 84 I 59 I/O AD10 194 I/O BE5Y 85 I 58 I/O AD11 193 I/O BE6Y 86 I A15 60 I/O AD12 192 I/O BE7Y 87 I A16 47 I/O AD13 191 I/O BOFFY 68 O A17 48 I/O AD14 190 I/O BRDYY 66 O A18 49 I/O AD15 189 I/O C/BE0Y 199 I/O A19 50 I/O AD16 177 I/O C/BE1Y 188 I/O A20 55 I/O AD17 176 I/O C/BE2Y 178 I/O A21 29 I/O AD18 175 I/O C/BE3Y 167 I/O A22 32 I/O AD19 174 I/O CAB3 25 O A23 28 I/O AD20 173 I/O CACHEY 63 I A24 30 I/O AD21 172 I/O 14 O A25 34 I/O AD22 171 I/O CADSY/ CAA3 A26 33 I/O AD23 168 I/O CADVY/ CAA4 13 O A27 31 I/O AD24 166 I/O CAS0Y 141 O A28 35 I/O AD25 165 I/O CAS1Y 139 O A29 39 I/O AD26 164 I/O CAS2Y 143 O A30 38 I/O AD27 163 I/O CAS3Y 137 O A31 36 I/O AD28 162 I/O CAS4Y 140 O 82437FX TSC AND 82438FX TDP Table 12. 82437FX Alphabetical Pin Assignment (Continued) Name PinY Type CAS5Y 138 O CAS6Y 142 O CAS7Y 136 CCSY/ CAB4 24 COEY 15 O CWE0Y 20 O CWE1Y 21 O CWE2Y 22 O CWE3Y 23 O CWE4Y 16 O CWE5Y 17 O CWE6Y 18 O CWE7Y 19 O D/CY 71 I DEVSELY 184 I/O EADSY 69 O FRAMEY 179 I/O GNT0Y 150 O GNT1Y 148 O GNT2Y 146 O GNT3Y 144 O HCLKIN 76 I HITMY 72 I HLOCKY 61 I HOEY 112 O IRDYY 180 I/O KENY 64 O LOCKY 186 I/O M/IOY 62 I MA2 119 O Name PinY Type MA3 120 O MA4 121 O O MA5 122 O MA6 123 MA7 MA8 Name PinY Type PLINK8 96 I/O PLINK9 97 I/O O PLINK10 98 I/O O PLINK11 99 I/O 124 O PLINK12 100 I/O 125 O PLINK13 101 I/O MA9 126 O PLINK14 102 I/O MA10 127 O PLINK15 107 I/O MA11 128 O POEY 113 O MAA0 115 O RAS0Y 134 O MAA1 116 O RAS1Y 135 O MAB0 117 O RAS2Y 132 O MAB1 118 O RAS3Y 133 O MADVY 111 O RAS4Y 129 O MOEY 114 O REQ0Y 151 I MSTBY 110 O REQ1Y 149 I NAY 67 O REQ2Y 147 I PAR 187 I/O REQ3Y 145 I PCLKIN 154 I RSTY 77 I PCMD0 108 O SMIACTY 74 I PCMD1 109 O STOPY 185 I/O PHLDY 153 I TIO0 4 I/O PHLDAY 152 O TIO1 5 I/O PLINK0 88 I/O TIO2 6 I/O PLINK1 89 I/O TIO3 11 I/O PLINK2 90 I/O TIO4 10 I/O PLINK3 91 I/O TIO5 9 I/O PLINK4 92 I/O TIO6 8 I/O PLINK5 93 I/O TIO7 7 I/O PLINK6 94 I/O TRDYY 181 I/O PLINK7 95 I/O TWEY 12 O 51 82437FX TSC AND 82438FX TDP Table 12. 82437FX Alphabetical Pin Assignment (Continued) 52 Name PinY Type Name PinY Type Name PinY Type VDD3 27 V VDD5 183 V VSS 79 V VDD3 53 V VDD5 196 V VSS 105 V VDD3 104 V VDD5 207 V VSS 106 V VDD3 130 V VDD5 208 V VSS 131 V VDD5 54 V VSS 1 V VSS 155 V VDD5 78 V VSS 2 V VSS 156 V VDD5 103 V VSS 26 V VSS 169 V VDD5 157 V VSS 51 V VSS 182 V VDD5 158 V VSS 52 V VSS 195 V VDD5 170 V VSS 75 V W/RY 73 I 82437FX TSC AND 82438FX TDP 5.2 82438FX Pinout 290518 - 16 NOTES: VDD3 is connected to the 3.3V rail; VDD5 is connected to the 5V, VDD3/5 is connected to the 3.3V rail for 3.3V DRAMs and to the 5V rail for 5V DRAMs. Figure 14. 82438FX Pin Assignment 53 82437FX TSC AND 82438FX TDP Table 13. 82438FX Alphabetical Pin Assignment 54 Name PinY Type HCLK 30 I HD0 96 I/O HD1 97 I/O HD2 98 I/O Name PinY Type HD29 33 I/O HD30 34 I/O HD31 35 HOEY 81 Name PinY Type MD25 42 I/O MD26 46 I/O I/O MD27 54 I/O I MD28 58 I/O HD3 99 I/O MADVY 82 I MD29 66 I/O HD4 100 I/O MD0 41 I/O MD30 70 I/O HD5 3 I/O MD1 45 I/O MD31 74 I/O HD6 4 I/O MD2 51 I/O MOEY 77 I HD7 5 I/O MD3 57 I/O MSTBY 83 I HD8 6 I/O MD4 61 I/O PCMD0 85 I HD9 7 I/O MD5 63 I/O PCMD1 84 I HD10 8 I/O MD6 69 I/O PLINK0 95 I/O HD11 9 I/O MD7 73 I/O PLINK1 94 I/O HD12 10 I/O MD8 39 I/O PLINK2 93 I/O HD13 11 I/O MD9 43 I/O PLINK3 92 I/O HD14 12 I/O MD10 47 I/O PLINK4 91 I/O HD15 13 I/O MD11 55 I/O PLINK5 90 I/O HD16 14 I/O MD12 59 I/O PLINK6 89 I/O HD17 15 I/O MD13 67 I/O PLINK7 88 I/O HD18 16 I/O MD14 71 I/O POEY 78 I HD19 17 I/O MD15 75 I/O VDD3 2 V HD20 18 I/O MD16 40 I/O VDD3 24 V HD21 20 I/O MD17 44 I/O VDD5 29 V HD22 21 I/O MD18 50 I/O VDD3 36 V HD23 22 I/O MD19 56 I/O VDD3/5 48 V HD24 23 I/O MD20 60 I/O VDD5 52 V HD25 25 I/O MD21 62 I/O VDD3/5 64 V HD26 26 I/O MD22 68 I/O VDD3/5 76 V HD27 27 I/O MD23 72 I/O VDD3 79 V HD28 32 I/O MD24 38 I/O VDD5 86 V 82437FX TSC AND 82438FX TDP Table 13. 82438FX Alphabetical Pin Assignment (Continued) Name PinY Type VSS 1 V VSS 19 V VSS 28 VSS 31 Name PinY Type VSS 37 V VSS 49 V V VSS 53 V V VSS 65 V Name PinY Type VSS 80 V VSS 87 V 5.3 82437FX Package Dimensions 290518 - 17 Figure 15. 208 Pin Quad Flat Pack (QFP) Dimensions 55 82437FX TSC AND 82438FX TDP Table 14. 208 Pin Quad Flat Pack (QFP) Dimensions Symbol A 56 Description Seating Height Value (mm) 4.25 (max) A1 Stand-off 0.05 (min); 0.40 (max) b Lead Width 0.2 g 0.10 C Lead Thickness 0.15 a 0.1/-0.05 D Package Length and Width, including pins 30.6 g 0.4 D1 Package Length and Width, excluding pins 28 g 0.2 e1 Linear Lead Pitch 0.5 g 0.1 Y Lead Coplanarity 0.08 (max) L1 Foot Length 0.5 g 0.2 T Lead Angle 0 - 10 82437FX TSC AND 82438FX TDP 5.4 82438FX Package Dimensions 290518 - 18 Figure 16. 100 Pin Plastic Quad Flat Pack (PQFP) Dimensions 57 82437FX TSC AND 82438FX TDP Table 15. 100 Pin Quad Flat Pack (QFP) Dimensions Symbol Description Value (mm) 6.0 82437FX TSC TESTABILITY 6.1 Test Mode Description A Seating Height 3.3 (max) A1 Stand-off 0.0 (min); 0.50 (max) b Lead Width 0.3 g 0.10 C Lead Thickness 0.15 a 0.1/-0.05 D Package Width, including pins 17.9 g 0.4 Test RSTY REQ0Y REQ1Y REQ2Y REQ3Y Mode D1 Package Width, excluding pins 14 0.2 NAND Tree E Package Length, including pins 23.9 g 0.4 E1 Package Length, excluding pins 20 g 0.2 e1 Linear Lead Pitch 0.65 g 0.12 Y Lead Coplanarity 0.1 (max) L1 Foot Length 0.8 0.2 T Lead Angle 0 - 10 The test modes are decoded from the REQY [3:0] and qualified with the RESETY pin. Test mode selection is asynchronous, these signals need to remain in their respective state for the duration of the test modes. The test modes are defined as follows. 0 0 0 0 0 6.2 NAND Tree Mode Tri-states all outputs and bi-directional buffers except for RSTY, REQY [3:0] , GNTY [3:1] . The NAND tree follows the pins sequentially around the chip REQY [3:0] , and skipping only RESETY, GNTY [3:1] . The first input of the NAND chain GNT0Y, and the NAND chain is routed counterclockwise around the chip (e.g., GNT0Y, PHLDAY, . . . ). The only valid outputs during NAND tree mode are GNT1Y, GNT2Y, and GNT3Y. GNT1Y and GNTY3 are both final outputs of the NAND tree, and GNT2Y is the halfway point of the NAND tree. To perform a NAND tree test, all pins included in the NAND tree should be driven to 1 with the exception of PCLKIN which should be driven to 0. Beginning with GNT0Y and working counter-clockwise around the chip, each pin can be toggled with a resulting toggle observed on GNT3Y, GNT2Y, and GNT1Y. The GNT2Y output is provided so that the NAND tree test can be divided into two sections. 58 82437FX TSC AND 82438FX TDP Table 16. NAND Tree Cell Order for the 82437FX Pin Y Pin Name 77 RSTY Pin Y Pin Name Must be 0 to enter NAND tree mode. This signal must remain 0 during the entire NAND tree test. 171 AD22 172 AD21 173 AD20 Must be 0 to enter NAND tree mode. This signal must remain 0 during the entire NAND tree test. 174 AD19 175 AD18 176 AD17 Must be 0 to enter NAND tree mode. This signal must remain 0 during the entire NAND tree test. 177 AD16 178 C/BE2Y 179 FRAMEY Must be 0 to enter NAND tree mode. This signal must remain 0 during the entire NAND tree test. 180 IRDYY 181 TRDYY 184 DEVSELY Must be 0 to enter NAND tree mode. This signal must remain 0 during the entire NAND tree test. 185 STOPY 186 LOCKY 187 PAR 188 C/BE1Y 189 AD15 190 AD14 191 AD13 192 AD12 193 AD11 AD31 194 AD10 160 AD30 197 AD9 161 AD29 198 AD8 162 AD28 199 C/BE0Y 163 AD27 200 AD7 164 AD26 201 AD6 165 AD25 202 AD5 AD24 203 AD4 167 C/BE3Y 204 AD3 168 AD23 205 AD2 145 147 149 151 150 REQ3Y REQ2Y REQ1Y REQ0Y GNT0Y 152 PHLDAY 153 PHOLDY 154 159 166 PCLKIN Notes Start of the NAND tree chain. PCLKIN needs to be 0 to pass the NAND-tree chain, a logic 1 will block the NANDtree chain. Notes 59 82437FX TSC AND 82438FX TDP Table 16. NAND Tree Cell Order for the 82437FX (Continued) Pin Y Pin Name 206 3 Pin Y Pin Name AD1 33 A26 AD0 34 A25 4 TIO0 35 A28 5 TIO1 36 A31 6 TIO2 37 A3 7 TIO7 38 A30 8 TIO6 39 A29 9 TIO5 40 A4 10 TIO4 41 A7 11 TIO3 42 A6 12 TWEY 43 A5 13 CADVY/ CAA4 44 A8 45 A11 14 CADSY/ CAA3 46 A10 15 COEY 47 A16 48 A17 49 A18 50 A19 55 A20 56 A9 57 A12 58 A14 59 A13 60 A15 61 HLOCKY 16 CWE4Y 17 CWE5Y 18 CWE6Y 19 CWE7Y 20 CWE0Y 21 CWE1Y 22 CWE2Y 23 CWE3Y 24 CCSY/ CAB4 Notes 25 CAB3 62 M/IOY 28 A23 63 CACHEY 29 A21 64 KENY 30 A24 65 AHOLD 31 A27 66 BRDYY 32 A22 60 Notes 82437FX TSC AND 82438FX TDP Table 16. NAND Tree Cell Order for the 82437FX (Continued) Pin Y Pin Name 67 68 Notes Pin Y Pin Name NAY 101 PLINK13 BOFFY 102 PLINK14 69 EADSY 107 PLINK15 70 ADSY 108 PCMD0 71 D/CY 109 PCMD1 72 HITMY 110 MSTBY 73 W/RY 111 MADVY 74 SMIACTY 112 HOEY 76 HCLKIN 113 POEY 80 BE0Y 114 MOEY 81 BE1Y 115 MAA0 82 BE2Y 116 MAA1 83 BE3Y 117 MAB0 84 BE4Y 118 MAB1 85 BE5Y 119 MA2 86 BE6Y 120 MA3 87 BE7Y 121 MA4 88 PLINK0 122 MA5 89 PLINK1 123 MA6 90 PLINK2 124 MA7 91 PLINK3 125 MA8 92 PLINK4 126 MA9 93 PLINK5 127 MA10 94 PLINK6 128 MA11 95 PLINK7 129 RAS4Y 96 PLINK8 132 RAS2Y 97 PLINK9 133 RAS3Y 98 PLINK10 134 RAS0Y 99 PLINK11 135 RAS1Y 100 PLINK12 136 CAS7Y Notes 61 82437FX TSC AND 82438FX TDP Table 16. NAND Tree Cell Order for the 82437FX (Continued) Pin Y Pin Name 137 138 139 CAS1Y 140 CAS4Y 141 CAS0Y 142 CAS6Y 62 Notes Pin Y Pin Name Notes CAS3Y 143 CAS2Y CAS5Y 144 GNT3Y Final output of the NAND tree chain. 146 GNT2Y Half way point of the NAND tree chain. 148 GNT1Y Final output of the NANDtree chain. 82437FX TSC AND 82438FX TDP Figure 17 is a schematic of the NAND tree circuitry. 290518 - 19 Figure 17. 82437FX NAND Tree Circuitry 63 82437FX TSC AND 82438FX TDP NAND Tree Timing Requirements 7.2 NAND Tree Mode Allow 800 ns for the input signals to propagate to the NAND tree outputs (input-to-output propagation delay specification). Tri-states all outputs and bidirectional buffers except for MD0 which is the output of the NAND tree. The NAND tree follows the pins sequentially around the chip skipping only HCLK and MD0. The first input of the NAND chain is HD5, and the NAND chain is routed counter-clockwise around the chip (e.g., HD5, HD6 . . .). The only valid output during NAND tree mode is MD0. 7.0 82438FX TDP TESTABILITY 7.1 Test Mode Description The test modes are decoded from HOEY, MOEY, POEY, and MSTBY. HCLK must be active for at least one clock to sample the above signals. Once these signals are sampled then HCLK must be asserted to 0 for the duration of the NAND tree test. The test modes are defined as follows. Test Mode HOEY MOEY POEY MSTBY NAND Tree 1 1 1 1 NAND tree mode is exited by starting HCLK with HOEY, MOEY, and POEY not equal to ``111''. 64 To perform a NAND tree test, all pins included in the NAND tree should be driven to 1, with the exception of HCLK and MDO. Beginning with HD5 and working counter-clockwise around the chip, each pin can be toggled with a resulting toggle observed on MD0. After changing an input pin to 0, keep it at 0 for the remainder of the NAND tree test. 82437FX TSC AND 82438FX TDP Table 17. NAND Tree Cell Order for the 82438FX Pin Y Pin Name 77 MOEY 78 81 83 30 POEY HOEY MSTBY HCLK Notes Pin Y Pin Name Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. 13 HD15 14 HD16 15 HD17 Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. 16 HD18 17 HD19 18 HD20 Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. 20 HD21 21 HD22 22 HD23 Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. 23 HD24 25 HD25 26 HD26 27 HD27 32 HD28 33 HD29 34 HD30 35 HD31 MD24 HCLK must clock at least once to sample MOEY, POEY, HOEY, and MSTBY to select NAND tree mode. Then to enter NAND tree mode HCLK must remain 0. To exit NAND tree mode HCLK must be started. 41 MD0 Output of the NAND tree chain. 38 39 MD8 3 HD5 First signal in the NAND tree chain. 40 MD16 4 HD6 42 MD25 5 HD7 43 MD9 6 HD8 44 MD17 7 HD9 45 MD1 8 HD10 46 MD26 9 HD11 47 MD10 10 HD12 50 MD18 11 HD13 51 MD2 12 HD14 54 MD27 55 MD11 Notes 65 82437FX TSC AND 82438FX TDP Table 17. NAND Tree Cell Order for the 82438FX (Continued) Pin Y Pin Name 56 MD19 57 MD3 58 MD28 59 Pin Y Pin Name 81 HOEY MD12 82 MADVY 60 MD20 83 MSTBY 61 MD4 62 MD21 63 MD5 84 PCMD1 66 MD29 85 PCMD0 67 MD13 88 PLINK7 68 MD22 89 PLINK6 69 MD6 90 PLINK5 70 MD30 91 PLINK4 71 MD14 92 PLINK3 72 MD23 93 PLINK2 73 MD7 94 PLINK1 74 MD31 95 PLINK0 75 MD15 96 HD0 MOEY Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. 97 HD1 98 HD2 99 HD3 Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. 100 HD4 77 78 66 POEY Notes Notes Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. Must be 1 to enter NAND tree mode. This pin is included in the NAND tree mode input pin sequence. Final signal in the NAND tree chain. 82437FX TSC AND 82438FX TDP Figure 18 is a schematic of the NAND tree circuitry. 290518 - 20 Figure 18. 82438FX NAND Tree Circuitry NAND Tree Timing Requirements Allow 500 ns for the input signals to propagate to the NAND tree outputs (input-to-output propagation delay specification). 67