Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE OCTOBER 1992
1992 Integrated Device Technology, Inc. DSC-8022/3
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
HIGH-SPEED BiCMOS
ECL STATIC RAM
4K (1K x 4-BIT) SRAM
PRELIMINARY
IDT10474, IDT10A474
IDT100474, IDT100A474
IDT101474, IDT101A474
FEATURES:
• 1024-words x 4-bit organization
• Address access time: 2.7/3/3.5/4/4.5/5/7/8/10/15 ns
• Low power dissipation: 1000mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• Corner and Center power pin pinouts
• Standard through-hole and surface mount packages
• Guaranteed-performance die available for MCMs/hybrids
• MIL-STD-883, Class B product available
DESCRIPTION:
The IDT10474(10A474), IDT100474(100A474) and
IDT101474(101A474) are 4,096-bit high-speed BiCMOS ECL
static random access memories organized as 1Kx4, with
separate data inputs and outputs. All I/Os are fully compatible
with ECL levels.
These devices are part of a family of asynchronous four-
bit-wide ECL SRAMs. This device is available in both the
traditional corner-power pinout, and "revolutionary" center-
power pin configurations. Because they are manufactured in
BiCMOS technology, power dissipation is greatly reduced
over equivalent bipolar devices. Low power operation pro-
vides higher system reliability and makes possible the use of
the plastic SOJ package for high-density surface mount
assembly.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
A
9
D
0
D
1
D
2
D
3
WE
CS
4,096-BIT
MEMORY
ARRAY
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
Q
1
Q
2
Q
3
DECODER
V
CC
V
EE
2760 drw 01
2
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
Center Power
"A"
Top View
A5
A3
A9
A8
A7
D2
D3
D1
Q0
Q1
VCC
VCCA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A6
VEE
CS
WE
D0
Q2
Q3
A0
A1
A2
NC
A4
2760 drw 02a
PACKAGES
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Q0
Q1
Q2
Q3
CS WE
D0D1D2D3
2760 drw 06
LOGIC SYMBOL
PIN DESCRIPTIONS
Symbol Pin Name
A0 through A9Address Inputs
D0 through D3Data Inputs
Q0 through Q3Data Outputs
WE
Write Enable Input
CS
Chip Select Input (Internal pull down)
VEE More Negative Supply Voltage
VCC Less Negative Supply Voltage
2760 tbl 01
CAPACITANCE (TA = +25°C, f = 1.0MHz)
DIP SOJ
Symbol Parameter Typ. Max. Typ. Max. Unit
CIN Input
Capacitance 4 — 3 — pF
COUT Output
Capacitance 6 — 3 — pF
2760 tbl 02
TRUTH TABLE(1)
CS
CS WE
WE
DataOUT Function
H X L Deselected
L H RAM Data Read
L L L Write
NOTE: 2760 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care
400-Mil-Wide
CERDIP PACKAGE
D24-3 2760 drw 03
Corner Power
"Non-A"
Top View
A
9
A
7
D
3
D
2
D
1
Q
2
Q
3
VCC
A
A
0
A
1
A
2
A
3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CS
D
0
Q
1
Q
0
V
CC
A
4
A
5
NC
A
6
V
EE
WE
A
8
2760 drw 02b
300-Mil-Wide
PLASTIC SOJ PACKAGE
SO24-4
2760 drw 04
Hi-Rel Die
For Hybrid and MCM
Applications
2760 drw 05
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE
3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Value Unit
VTERM Terminal Voltage +0.5 to –7.0 V
With Respect to GND
TAOperating 10K 0 to +75 °C
Temperature 100K 0 to +85
101K 0 to +75
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Ceramic –65 to +150 °C
Temperatuure Plastic –55 to +125
PTPower Dissipation 1.5 W
IOUT DC Output Current –50 mA
(Output High)
NOTE: 2760 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
AC/DC ELECTRICAL OPERATING RANGES
I/O VEE TA
10K –5.2V ± 5% 0 to +75°C, air flow exceeding 2 m/sec
100K –4.5V ± 5% 0 to +85°C, air flow exceeding 2 m/sec
101K –4.75V to –5.46V 0 to +75°C, air flow exceeding 2 m/sec
2760 tbl 05
DC ELECTRICAL CHARACTERISTICS (1)
10K 100K/101K
Symbol Parameter Min. Max. TA Min. Max. Unit
VOH Output HIGH Voltage –1000 –840 0°C –1025 –880 mV
(VIN= VIH(Max) or VIL(Min)) –960 –810 25°C
–900 –720 75°C
VOL Output LOW Voltage –1870 –1665 0°C –1810 –1620 mV
(VIN= VIH(Max) or VIL(Min)) –1850 –1650 25°C
–1830 –1625 75°C
VOHC Output Threshold HIGH Voltage –1020 — 0°C –1035 — mV
(VIN= VIH(Min) or VIL(Max)) –980 — 25°C
–920 — 75°C
VOLC Output Threshold LOW Voltage — –1645 0°C — –1610 mV
(VIN= VIH(Min) or VIL(Max)) — –1630 25°C
— –1605 75°C
VIH Input HIGH Voltage –1145 –840 0°C –1165 –880 mV
(Guaranteed Input Voltage –1105 –810 25 °C
High for All Inputs) –1045 –720 75°C
VIL Input LOW Voltage –1870 –1490 0°C –1810 –1475 mV
(Guaranteed Input Voltage –1850 –1475 25°C
Low for All Inputs) –1830 –1450 75°C
IIH Input HIGH Current
VIN= VIH(Max) CS — 220 — — 220 µA
Others — 110 — — 110 µA
IIL Input LOW Current
VIN= VIL(Min) CS 0.5 170 — 0.5 170 µA
Others –50 90 — –50 90 µA
IEE Supply Current –210 — — –190 (100K) — mA
–210 (101K) —
NOTE:
1. RL = 50Ω to -2V, air flow exceeding 2 m/sec.
2760 tbl 05
4
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE
WRITE TIMING
To write data to the device, a Write Pulse need be formed
on the Write Enable input (WE) to control the write to the
SRAM array. While CS and ADDR must be set-up when WE
goes low, DataIN can settle after the falling edge of WE, giving
the data path extra margin. Data is written to the memory cell
at the end of the Write Pulse, and addresses and Chip Select
must be held after the rising edge of the Write Pulse to ensure
satisfactory completion of the cycle.
DataOUT is disabled (held LOW) during the Write Cycle. If
CS is held LOW (active) and addresses remain unchanged,
the Data OUT pins will output the written data after "Write
Recovery time" (tWR).
Because of the very short Write Pulse requirement, these
devices can be cycled as quickly for Writes as for Reads.
AC TEST LOAD CONDITION AC TEST INPUT PULSE
FUNCTIONAL DESCRIPTION
The IDT10474(10A474), IDT100474(100A474), and
IDT101474(101A474) BiCEMOS ECL static RAMs provide
high speed with low power dissipation typical of BiCMOS ECL.
These devices are available in both the traditional corner-
power pinout and the "revolutionary" center-power pinout for
reduced noise and improved system performance.
READ TIMING
The read timing on these asynchronous devices is straight-
forward. DataOUT is held LOW until the device is selected by
Chip Select (CS). The Address (ADDR) settles and data
appears on the output after time tAA. Note that DataOUT is
held for a short time (tOH) after the address begins to change
for the next access, then ambiguous data is on the bus until a
new time tAA.
RISE/FALL TIME
Symbol Parameter Min. Typ. Max. Unit
tR Output Rise Time — 1.5 — ns
tF Output Fall Time — 1.5 — ns
2760 tbl 06
2760 drw 08
tR
–1.7V
Note: All timing measurements are
referenced to 50% input levels.
–0.9V
tF
20%
80%
tR = tF = 1.5ns typ.
VCC (GND)
DATA
VEE –2.0V
50Ω
*Includes probe and jig capacitance.
C < 5pF (2.7,3.0, 3.5nS speed grades)
C < 30pF (all other speed grades)
0.01µF
OUT
C*
2760 drw 07
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE
5
AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
S2.7 S3 S3.5 S4 S4.5 S5 S7,8,10,15
Symbol Parameter(1) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tACS Chip Select Access Time — 2.0 — 2.0 — 2.5 — 2.5 — 2.5 — 3.0 — 3.5 ns
tRCS Chip Select Recovery Time — 2.0 — 2.0 — 2.5 — 2.5 — 2.5 — 3.0 — 3.5 ns
tAA Address Access Time — 2.7 — 3.0 — 3.5 — 4.0 — 4.5 — 5.0 — 7.0 ns
tOH Data Hold from Address 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
Change
NOTE: 2760 tbl 07
1. Input and Output reference level is 50% point of waveform.
2. Output load capacitance, C < 5pF (2.7, 3.0, 3.5ns speed grades only), see "AC Test Load Condition" on previous page.
READ CYCLE GATED BY CHIP SELECT (1, 2)
DATAOUT
tACS tRCS
CS
2670 drw 09
READ CYCLE GATED BY ADDRESS (1, 3)
ADDR
tOH
tAA
DATAOUT
2670 drw 10
NOTE:
1. WE is HIGH for read cycle.
2. Address valid prior to or minimum tAA-tACS before CS active.
3. CS active prior to or minimum tAA-tACS after address valid.
6
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE
WRITE CYCLE TIMING DIAGRAM
2670 drw 11
ADDR
DATAOUT
tWSCS
tWS
tWSD2
CS
DATAIN
WE
tWSA
tWSD
tWHCS
tWHA
tWHD
tWtWR
AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
S2.7 S3.0 S3.5 S4 S4.5 S5 S7,8,10,15
Symbol Parameter(1) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWWrite Pulse Width 2.5 — 2.5 — 3.0 — 3.0 — 3.5 — 4.0 — 6.0 — ns
(tWSA = minimum)
tWSD Data Set-up Time 0 — 0 — 0 — 0 — 0 — 0 — 0 — ns
tWSD2(2) Data Set-up Time to WE HIGH 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 3.0 — 5.0 — ns
tWSA Address Set-up Time 0 — 0 — 0 — 0 — 0 — 0 — 0 — ns
(tW = minimum)
tWSCS Chip Select Set-up Time 0 — 0 — 0 — 0 — 0 — 0 — 0 — ns
tWHD Data Hold Time 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
tWHA Address Hold Time 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
tWHCS Chip Select Hold Time 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
tWS Write Disable Time — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 5.0 ns
tWR(3) Write Recovery Time — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 5.0 ns
NOTE: 2760 tbl 08
1. Input and Output reference level is 50% point of waveform.
2. tWSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires t WSD2 with
respect to rising edge of WE.
3. tWR is defined as the time to reflect the newly written data on the Data Outputs (Q0 to Q3) when no new Address Transition occurs.
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE
7
ORDERING INFORMATION
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 FAX 408-492-8674
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
NOTE:
1. Please contact your IDT Sales Representative for more information on
specifications and availability of Military and Die products.
Package
IDT nnnnn
Device Type aa
Architecture nn
Speed a a
Process/
Temp. Range Blank
B(1)
DF
U(1)
Y
2.7
3
3.5
4
4.5
5
7
8
10
15
S
CERDIP
Hi-Rel Die for MCMs and/or Hybrids
Plastic SOJ
Speed in Nanoseconds
Standard Architecture
10474
10A474
100474
100A474
101474
101A474
4K (1K x 4-bits) BiCMOS ECL-10K
Corner-Power Pin Static RAM
4K (1K x 4-bits) BiCMOS ECL-10K
Center-Power Pin Static RAM
4K (1K x 4-bits) BiCMOS ECL-100K
Corner-Power Pin Static RAM
4K (1K x 4-bits) BiCMOS ECL-100K
Center-Power Pin Static RAM
4K (1K x 4-bits) BiCMOS ECL-101K
Corner-Power Pin Static RAM
4K (1K x 4-bits) BiCMOS ECL-101K
Center-Power Pin Static RAM
2760 drw 12
Commercial
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
