PRELIMINARY IDT10474, IDT10A474 IDT100474, IDT100A474 IDT101474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM Integrated Device Technology, Inc. These devices are part of a family of asynchronous fourbit-wide ECL SRAMs. This device is available in both the traditional corner-power pinout, and "revolutionary" centerpower pin configurations. Because they are manufactured in BiCMOS technology, power dissipation is greatly reduced over equivalent bipolar devices. Low power operation provides higher system reliability and makes possible the use of the plastic SOJ package for high-density surface mount assembly. The fast access time and guaranteed Output Hold time allow greater margin for system timing variation. DataIN setup time specified with respect to the trailing edge of Write Pulse eases write timing allowing balanced Read and Write cycle times. FEATURES: * 1024-words x 4-bit organization * Address access time: 2.7/3/3.5/4/4.5/5/7/8/10/15 ns * Low power dissipation: 1000mW (typ.) * Guaranteed Output Hold time * Fully compatible with ECL logic levels * Separate data input and output * Corner and Center power pin pinouts * Standard through-hole and surface mount packages * Guaranteed-performance die available for MCMs/hybrids * MIL-STD-883, Class B product available DESCRIPTION: The IDT10474(10A474), IDT100474(100A474) and IDT101474(101A474) are 4,096-bit high-speed BiCMOS ECL static random access memories organized as 1Kx4, with separate data inputs and outputs. All I/Os are fully compatible with ECL levels. FUNCTIONAL BLOCK DIAGRAM A0 VCC DECODER 4,096-BIT MEMORY ARRAY VEE A9 D0 D1 D2 Q0 SENSE AMPS AND READ/WRITE CONTROL D3 Q1 Q2 Q3 WE CS 2760 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE OCTOBER 1992 1992 Integrated Device Technology, Inc. DSC-8022/3 1 IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM PIN CONFIGURATIONS D1 D2 D3 Q0 Q1 VCC VCCA Q2 Q3 A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 D0 CS WE A9 A8 A7 VEE A6 NC A5 A4 A3 24 23 22 21 20 19 18 17 16 15 14 13 COMMERCIAL TEMPERATURE RANGE PACKAGES VCCA Q2 Q3 A0 A1 A2 A3 A4 A5 NC A6 VEE Center Power "A" Top View 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 VCC Q1 Q0 D3 D2 D1 D0 CS WE A9 A8 A7 300-Mil-Wide PLASTIC SOJ PACKAGE SO24-4 400-Mil-Wide CERDIP PACKAGE D24-3 2760 drw 03 2760 drw 04 Corner Power "Non-A" Top View 2760 drw 02a 2760 drw 02b PIN DESCRIPTIONS Symbol A0 through A9 Pin Name Address Inputs D0 through D3 Data Inputs Q0 through Q3 Data Outputs WE CS Hi-Rel Die For Hybrid and MCM Applications Write Enable Input Chip Select Input (Internal pull down) VEE More Negative Supply Voltage VCC Less Negative Supply Voltage 2760 drw 05 2760 tbl 01 LOGIC SYMBOL CAPACITANCE (TA = +25C, f = 1.0MHz) DIP Symbol Parameter CIN COUT D0 D1 D2 D3 SOJ Typ. Max. Typ. Max. Unit Input Capacitance 4 -- 3 -- pF Output Capacitance 6 -- 3 -- pF A0 A1 A2 2760 tbl 02 A3 Q0 A4 A5 Q1 Q2 Q3 A6 TRUTH TABLE(1) A7 CS WE DataOUT Function H X L Deselected L H RAM Data Read L L L Write NOTE: 1. H = HIGH, L = LOW, X = Don't Care A8 A9 CS 2760 tbl 03 WE 2760 drw 06 2 IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA Rating Terminal Voltage With Respect to GND Operating Temperature 10K 100K 101K AC/DC ELECTRICAL OPERATING RANGES Value Unit +0.5 to -7.0 V 0 to +75 0 to +85 0 to +75 C VEE TA 10K -5.2V 5% 0 to +75C, air flow exceeding 2 m/sec 100K -4.5V 5% 0 to +85C, air flow exceeding 2 m/sec 101K -4.75V to -5.46V 0 to +75C, air flow exceeding 2 m/sec 2760 tbl 05 TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperatuure -65 to +150 -55 to +125 C PT Power Dissipation 1.5 W IOUT DC Output Current (Output High) -50 mA Ceramic Plastic I/O NOTE: 2760 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (1) 10K Symbol Parameter VOH 100K/101K Min. Max. TA Min. Max. Unit Output HIGH Voltage (VIN= VIH(Max) or VIL(Min)) -1000 -960 -900 -840 -810 -720 0C 25C 75C -1025 -880 mV VOL Output LOW Voltage (VIN= VIH(Max) or VIL(Min)) -1870 -1850 -1830 -1665 -1650 -1625 0C 25C 75C -1810 -1620 mV VOHC Output Threshold HIGH Voltage (VIN= VIH(Min) or VIL(Max)) -1020 -980 -920 -- -- -- 0C 25C 75C -1035 -- mV VOLC Output Threshold LOW Voltage (VIN= VIH(Min) or VIL(Max)) -- -- -- -1645 -1630 -1605 0C 25C 75C -- -1610 mV VIH Input HIGH Voltage (Guaranteed Input Voltage High for All Inputs) -1145 -1105 -1045 -840 -810 -720 0C 25C 75C -1165 -880 mV VIL Input LOW Voltage (Guaranteed Input Voltage Low for All Inputs) -1870 -1850 -1830 -1490 -1475 -1450 0C 25C 75C -1810 -1475 mV Input HIGH Current CS VIN= VIH(Max) Others -- -- 220 110 -- -- -- -- 220 110 A A Input LOW Current VIN= VIL(Min) CS Others 0.5 -50 170 90 -- -- 0.5 -50 170 90 A A -210 -- -- -190 (100K) -- mA -210 (101K) -- IIH IIL IEE Supply Current NOTE: 1. RL = 50 to -2V, air flow exceeding 2 m/sec. 2760 tbl 05 3 IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM AC TEST LOAD CONDITION COMMERCIAL TEMPERATURE RANGE AC TEST INPUT PULSE VCC (GND) DATAOUT 50 -0.9V 80% 20% -1.7V C* tR 0.01F VEE tF tR = tF = 1.5ns typ. -2.0V *Includes probe and jig capacitance. C < 5pF (2.7,3.0, 3.5nS speed grades) C < 30pF (all other speed grades) Note: All timing measurements are referenced to 50% input levels. 2760 drw 08 2760 drw 07 RISE/FALL TIME Symbol Parameter Min. Typ. Max. Unit tR Output Rise Time -- 1.5 -- ns tF Output Fall Time -- 1.5 -- ns 2760 tbl 06 FUNCTIONAL DESCRIPTION WRITE TIMING The IDT10474(10A474), IDT100474(100A474), and IDT101474(101A474) BiCEMOS ECL static RAMs provide high speed with low power dissipation typical of BiCMOS ECL. These devices are available in both the traditional cornerpower pinout and the "revolutionary" center-power pinout for reduced noise and improved system performance. To write data to the device, a Write Pulse need be formed on the Write Enable input (WE) to control the write to the SRAM array. While CS and ADDR must be set-up when WE goes low, DataIN can settle after the falling edge of WE, giving the data path extra margin. Data is written to the memory cell at the end of the Write Pulse, and addresses and Chip Select must be held after the rising edge of the Write Pulse to ensure satisfactory completion of the cycle. DataOUT is disabled (held LOW) during the Write Cycle. If CS is held LOW (active) and addresses remain unchanged, the Data OUT pins will output the written data after "Write Recovery time" (tWR). Because of the very short Write Pulse requirement, these devices can be cycled as quickly for Writes as for Reads. READ TIMING The read timing on these asynchronous devices is straightforward. DataOUT is held LOW until the device is selected by Chip Select (CS). The Address (ADDR) settles and data appears on the output after time tAA. Note that DataOUT is held for a short time (tOH) after the address begins to change for the next access, then ambiguous data is on the bus until a new time tAA. 4 IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range) S2.7 Symbol Parameter(1) S3 S3.5 S4 S4.5 S5 S7,8,10,15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tACS Chip Select Access Time tRCS Chip Select Recovery Time -- 2.0 -- 2.0 -- 2.5 -- 2.5 -- 2.5 -- 3.0 -- 3.5 ns tAA Address Access Time -- 2.7 -- 3.0 -- 3.5 -- 4.0 -- 4.5 -- 5.0 -- 7.0 ns tOH Data Hold from Address Change 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- ns -- 2.0 -- 2.0 -- 2.5 -- 2.5 -- 2.5 -- 3.0 -- 3.5 NOTE: 1. Input and Output reference level is 50% point of waveform. 2. Output load capacitance, C < 5pF (2.7, 3.0, 3.5ns speed grades only), see "AC Test Load Condition" on previous page. ns 2760 tbl 07 READ CYCLE GATED BY CHIP SELECT (1, 2) CS tACS tRCS DATAOUT 2670 drw 09 READ CYCLE GATED BY ADDRESS (1, 3) ADDR tAA tOH DATAOUT 2670 drw 10 NOTE: 1. WE is HIGH for read cycle. 2. Address valid prior to or minimum tAA-tACS before CS active. 3. CS active prior to or minimum tAA-tACS after address valid. 5 IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range) S2.7 Symbol Parameter(1) S3.0 S3.5 S4 S4.5 S5 S7,8,10,15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tW Write Pulse Width (tWSA = minimum) tWSD Data Set-up Time tWSD2(2) Data Set-up Time to WE HIGH tWSA 2.5 -- 2.5 -- 3.0 -- 3.0 -- 3.5 -- 4.0 -- 6.0 -- ns 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- ns 2.0 -- 2.0 -- 2.0 -- 2.0 -- 2.0 -- 3.0 -- 5.0 -- ns Address Set-up Time (tW = minimum) 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- ns tWSCS Chip Select Set-up Time 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- ns tWHD Data Hold Time 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- ns tWHA tWHCS tWS Address Hold Time Chip Select Hold Time Write Disable Time 1.0 1.0 -- -- -- 2.7 1.0 1.0 -- -- -- 3.0 1.0 1.0 -- -- -- 3.0 1.0 1.0 -- -- -- 3.0 1.0 1.0 -- -- -- 3.0 1.0 1.0 -- -- -- 3.0 1.0 1.0 -- -- -- 5.0 ns ns ns tWR(3) Write Recovery Time -- 2.7 -- 3.0 -- 3.0 -- 3.0 -- 3.0 -- 3.0 -- 5.0 ns NOTE: 2760 tbl 08 1. Input and Output reference level is 50% point of waveform. 2. tWSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires tWSD2 with respect to rising edge of WE. 3. tWR is defined as the time to reflect the newly written data on the Data Outputs (Q0 to Q3) when no new Address Transition occurs. WRITE CYCLE TIMING DIAGRAM CS tWSCS tWHCS tWSA tWHA ADDR DATAIN tWSD tWHD tWSD2 WE tW tWS tWR DATAOUT 2670 drw 11 6 IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474 HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT nnnnn Device Type aa Architecture nn Speed a Package a Process/ Temp. Range Blank B(1) Commercial Military (-55C to +125C) Compliant to MIL-STD-883, Class B DF U(1) Y CERDIP Hi-Rel Die for MCMs and/or Hybrids Plastic SOJ 2.7 3 3.5 4 4.5 5 7 8 10 15 Speed in Nanoseconds S Standard Architecture 10474 4K (1K x 4-bits) BiCMOS ECL-10K Corner-Power Pin Static RAM 10A474 4K (1K x 4-bits) BiCMOS ECL-10K Center-Power Pin Static RAM 100474 4K (1K x 4-bits) BiCMOS ECL-100K Corner-Power Pin Static RAM 100A474 4K (1K x 4-bits) BiCMOS ECL-100K Center-Power Pin Static RAM 101474 4K (1K x 4-bits) BiCMOS ECL-101K Corner-Power Pin Static RAM 101A474 4K (1K x 4-bits) BiCMOS ECL-101K Center-Power Pin Static RAM NOTE: 1. Please contact your IDT Sales Representative for more information on specifications and availability of Military and Die products. 2760 drw 12 Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product. Integrated Device Technology, Inc. 2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 7 FAX 408-492-8674