Semiconductor
MSC23440D-xxBS10/DS10
4,194, 304- word x 40- bit DY NAMIC RAM MO DULE : FAST PAGE MODE TY P E
This vers ion: Mar. 8. 1999
DESCRIPTION
The MSC23440D-xxBS10/DS10 is a fully decoded, 4,194,304-word x 40-bit CMOS dynamic random access
m em ory modul e com posed of ten 16Mb DRAM s (4Mx 4) in SO J packages m ounted with t en decoupl ing c apaci tors
on a 72-pin glass epoxy single i n-l i ne package. T his modul e supports any appli cati on where hi gh densi t y and l arge
capacity of stor age memory ar e r equired.
FEATURES
· 4, 194,304-word x 40- bit or ganizat ion
· 72-pin Single In-Li ne M emory M odule
MSC23440D-xxBS10 : Gold tab
MSC23440D-xxDS10 : S older t ab
· Singl e +5V supply ± 10% tol er anc e
· I nput : T TL compatible
· Output : TTL compatible, 3-state
· Refresh : 2048cycles/32ms
· / CA S befor e /RAS refr esh, hidden refresh, /RAS only refresh capability
· F ast page mode, r ead modify writ e c apability
· Multi-bit t est mode capability
PRODUCT FAMILY
Access Time (Max. ) Power Dissipat i on
Family tRAC tAA tCAC tOEA
Cycle
Time
(Min.) Operating (Max. ) Standby (Max.)
MSC23440D-60BS10/DS10 60ns 30ns 15ns 15ns 110ns 6050mW
MSC23440D-70BS10/DS10 70ns 35ns 20ns 20ns 130ns 5500mW 55mW
Semiconductor MSC23440D
MODULE OUTLINE
1
72
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
φ3.18
25.4±0.2
101.19Typ.
107.95±0.2
*1
3.38Typ.
5.28Max.
1.27
(Un i t : m m)
MSC23440D-xxBS10/DS10
*1 The common size difference of the board width 12.5mm of its height is specified as ±0.2.
The value above 12.5mm is specified as ±0.5.
Semiconductor MSC23440D
PIN C ONFIGURATI ON
Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me
1V
SS 19 /OE 37DQ1955DQ28
2 DQ0 20 DQ8 38 DQ20 56 DQ29
3DQ121DQ939V
SS 57 DQ30
4 DQ2 22 DQ10 40 /CAS0 58 DQ31
5 DQ3 23 DQ11 41 A10 59 VCC
6 DQ4 24 DQ12 42 NC 60 DQ32
7 DQ5 25 DQ13 43 NC 61 DQ33
8 DQ6 26 DQ14 44 /RAS0 62 DQ34
9 DQ7 27 DQ15 45 NC 63 DQ35
10 VCC 28 A7 46 DQ21 64 DQ36
11 PD5 29 DQ16 47 /WE 65 DQ37
12 A0 30 VCC 48 VSS 66 DQ38
13 A1 31 A8 49 DQ22 67 PD1
14 A2 32 A9 50 DQ23 68 PD2
15 A3 33 NC 51 DQ24 69 PD3
16 A4 34 NC 52 DQ25 70 PD4
17 A5 35 DQ17 53 DQ26 71 DQ39
18 A6 36 DQ18 54 DQ27 72 VSS
Presence Det ect P ins
Pin No. Pin Na me MSC23440D
-60BS10/DS10 MSC23440D
-70BS10/DS10
67 PD1 VSS VSS
68 PD2 NC NC
69 PD3 NC VSS
70 PD4 NC NC
11 PD5 VSS VSS
Semiconductor MSC23440D
BLOCK DIAGRAM
/WE
/CAS0
/RAS0
A0-A10
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
V
CC
V
SS
C1-C10
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
V
CC
V
SS
V
CC
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
V
CC
V
SS
A0-A10
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
V
CC
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
V
CC
V
SS
/OE
DQ
DQ
DQ
DQ
Semiconductor MSC23440D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Volt age on Any Pin Relat i ve to VSS VIN, VOUT -0.5 to +7.0 V
Vol t age on VCC Supply Relative to V SS VCC -0.5 to +7.0 V
Short Ci r cuit Output Current IOS 50 mA
Power Dissipation PD *10W
Operating Temperature TOPR 0 to +70 °C
Storage Temperature TSTG - 40 to +125 °C
* Ta = 25°C
Recommen ded O perating Conditions ( Ta = 0°C to +70°C )
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Suppl y Volt age VSS 000V
Input High Volt age VIH 2.4 - VCC + 0.5 V
Input Low Vol tage VIL -0.5 - 0.8 V
Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz )
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 - A10) CIN1 -70pF
Input Capaci t ance (/RAS0, /CAS0, /WE, / O E) CIN2 -80pF
I/O Capacitance (DQ0 - DQ39) CDQ -16pF
Semiconductor MSC23440D
DC Characteristics (VCC = 5V ± 10% , Ta = 0°C to +70°C )
MSC23440D
-60BS10/DS10 MSC23440D
-70BS10/DS10
Parameter Symbol Condition
Min. Max. Min. Max.
Unit Note
Input Leakage Current ILI
0V ≤ VIN ≤ 6.5V;
All ot her pins not
under test = 0V -100 100 -100 100 µA
Out put Leakage Current ILO DQ disabl e
0V ≤ VOUT ≤ 5.5V -10 10 -10 10 µA
Out put Hi gh Volt age VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V
Out put Low Vol tage VOL IOL = 4.2mA 0 0.4 0 0.4 V
Average Power
Supply Current
(Operating) ICC1 /RAS, /CAS cyc ling ,
tRC = Min. - 1100 - 1000 m A 1, 2
/RAS, /CAS = VIH -20-20mA1
Power Suppl y Curr ent
(Standby) ICC2 /RAS, /CAS
≥ VCC -0.2V -10-10mA1
Average Power
Supply Current
(/RAS only r efresh) ICC3
/RAS cy c lin g ,
/CAS = VIH,
tRC = Min. - 1100 - 1000 m A 1, 2
Average Power
Supply Current
(/CAS before /RAS refresh) ICC6 /RAS c y c lin g,
/CAS before /RAS - 1100 - 1000 mA 1, 2
Average Power
Supply Current
(Fast Page Mode) ICC7
/RAS = VIL,
/CAS cy c lin g ,
tPC = Min. - 900 - 800 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less whil e /RAS = VIL.
3. Address can be changed once or less whil e /CAS = VIH.
Semiconductor MSC23440D
AC Characteristics (1/2) (VCC = 5V ± 10% , Ta = 0°C to +70°C ) Note: 1, 2, 3, 11, 12
MSC23440D
-60BS10/DS10 MSC23440D
-70BS10/DS10
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Random Read or Wr ite Cycle Time tRC 110 - 130 - ns
Read Modify Wri t e Cycle Ti me tRWC 155 - 185 - ns
Fast Page Mode Cycle Time tPC 40 - 45 - ns
Fast Page Mode Read Modify Write Cycle Time tPRWC 85 - 100 - ns
Access Time from /RAS tRAC - 60 - 70 ns 4, 5, 6
Access Time from /CAS tCAC - 15 - 20 ns 4, 5
Access Time from Colum n Address tAA - 30 - 35 ns 4, 6
Access Time from /CAS Precharge tCPA - 35 - 40 ns 4
Access Time from /OE tOEA - 15 - 20 ns 4
Out put Low Impedance Tim e from /CAS t CLZ 0-0-ns4
/CAS to Data Output Buffer Turn-off Delay Time t OFF 0 15 0 20 ns 7
/OE to Data Output Buffer Turn-off Delay Ti me tOEZ 0 15 0 20 ns 7
Transi tion Time tT3 50 3 50 ns 3
Refr esh Period tREF -32-32ms
/RAS Pr echarge Time tRP 40 - 50 - ns
/RAS Pulse Wi d th tRAS 60 10K 70 10K ns
/RAS Pulse Widt h ( Fast Page Mode) tRASP 60 100K 70 100K ns
/RAS Hold Time tRSH 15 - 20 - ns
/RAS Hold Time referenced to /OE tROH 15 - 20 - ns
/CAS Precharge Time (Fast Page Mode) tCP 10 - 10 - ns
/CAS Pulse Wi d th tCAS 15 10K 20 10K ns
/CAS Hold Time tCSH 60 - 70 - ns
/CAS t o /RAS Prechar ge Time tCRP 5-5-ns
/RAS Hold Time from /CAS Precharge tRHCP 35 - 40 - ns
/RAS to /CAS Delay Time tRCD 20 45 20 50 ns 5
/RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6
Row Address Set-up Time tASR 0-0-ns
Row Address Hol d Ti me tRAH 10 - 10 - ns
Column Address Set-up Time tASC 0-0-ns
Col u mn Add ress Hol d Ti me tCAH 15 - 15 - ns
Column Address to /RAS Lead Time tRAL 30 - 35 - ns
Semiconductor MSC23440D
AC Characteristics (2/2) (VCC = 5V ± 10% , Ta = 0°C to +70°C ) Note: 1, 2, 3, 11, 12
MSC23440D
-60BS10/DS10 MSC23440D
-70BS10/DS10
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Read Com mand Set-up Tim e tRCS 0-0-ns
Read Com mand Hold Time tRCH 0-0-ns8
Read Com mand Hold Time referenced t o / RAS tRRH 0-0-ns8
W r ite Command Set-up Time tWCS 0-0-ns9
W r ite Command Hold Time t WCH 10 - 15 - ns
W r ite Command Pulse Wi dt h tWP 10 - 10 - ns
/O E Comm and Hol d Time tOEH 15 - 20 - ns
W r ite Command to / RAS Lead Ti me t RWL 15 - 20 - ns
W r ite Command to / CAS Lead time tCWL 15 - 20 - ns
Data-i n Set-up Time tDS 0-0-ns10
Dat a-i n Ho ld Time t DH 10 - 15 - ns 10
/OE to Data-in Delay Tim e tOED 15 - 20 - ns
/CAS to /W E Delay Tim e tCWD 40 - 50 - ns 9
Column Address to /W E Delay Time tAWD 55 - 65 - ns 9
/RAS to /W E Delay Tim e tRWD 85 - 100 - ns 9
/CAS Pr echarge /WE Del ay Time tCPWD 60 - 70 - ns 9
/CAS Active Delay Time from /RAS Precharge tRPC 5-5-ns
/RAS to /CAS Set-up Time
(/ CAS b efore /RAS) tCSR 10 - 10 - ns
/RAS to /CAS Hold Tim e
(/ CAS b efore /RAS) tCHR 10 - 10 - ns
/WE to /RAS Precharge Ti me
(/ CAS b efore /RAS) tWRP 10 - 10 - ns
/WE Hold Time from /RAS
(/ CAS b efore /RAS) tWRH 10 - 10 - ns
/RAS to /W E Set-up Time
(Test Mode) tWTS 10 - 10 - ns
/RAS to /W E Hold Tim e
(Test Mode) tWTH 10 - 10 - ns
Semiconductor MSC23440D
Notes: 1. A start- up delay of 200µs is required after power-up, followed by a mi nimum of eight ini tializ ation cycles
(/RA S only refr esh or / CA S befor e /RAS refr esh) before pr oper device operat ion i s achieved.
2. The AC c har ac teri stics assumes tT = 5ns.
3. VIH(Min. ) and VIL(Max .) are ref erence l ev els for measuring input timi ng signals. Transiti on ti me (tT) are
m easured bet ween VIH and VIL.
4. This parameter i s measured wi th a load c ircuit equivalent to 2TT L loads and 100pF.
5. Operation within the tRCD(M ax. ) li mit ensures that t RAC(Max . ) can be met.
tRCD(Max.) is s pecified as a reference point only . If tRCD is greater than the s pecified tRCD(Max.) limit, then
the acc ess ti me is controlled by tCAC.
6. Operation within the tRAD(Max.) li mit ensures that tRAC(Max . ) can be met.
tRAD(Max.) is s pecified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, the n
the acc ess ti me is controlled by tAA.
7. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are
not refer enc ed to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restri ctiv e operati ng paramet ers. T hey are i ncluded in the data
sheet as elect r ical characteri stics only. I f tWCS ≥ tWCS(Min.), the cycle is an early write cycle and t he data
out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD ≥
tRWD(Min.), t AWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Mi n. ), the cycle is a read modify wri t e cycle and data out
will contain data read from the selected cell; if neither or the abov e sets of conditions is satisfied, the
condi tions of the data out (at access time) is indet er minate.
10. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge
in an / OE control wri te cycle or a read modi fy write cycle.
11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bi t parall el test function. CA0, CA1 and CA10 are not used. In a read cycl e, if all internal bits are
equal, the DQ pin w ill ind ica te a h igh le vel. If an y in ter na l b its ar e n o t equal, the DQ pin will in dic at e a low
level. T he test mode is clear ed and the memory device returned t o its normal operati ng state by a /RAS
only refresh or /CAS bef ore /RAS ref resh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the abov e value to the specified
value in this data sheet.