For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
AttenuAtors - DIGItAL - sMt
8
8 - 4
HMC624LFLP4E
v00.0511
0.5 dB LSB GaAs MMIC 6-BIT
DIGITAL ATTENUATOR, 60 - 500 MHz
Bias Voltage Table
Vdd (V) Idd (Typ.) (mA)
30.12
50.15
PUP Truth TablePower-Up States
Control Voltage Input Reference
Insertion
Loss
D5 D4 D3 D2 D1 D0
High High High High High High 0 dB
High High High High High Low -0.5 dB
High High High High Low High -1 dB
High High High Low High High -2 dB
High High Low High High High -4 dB
High Low High High High High -8 dB
Low High High High High High -16 dB
Low Low Low Low Low Low -31.5 dB
Any combination of the above states will provide an attenuation
equal to the sum of the bits selected.
Truth Table
Timing Diagram (Latched Parallel Mode)
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch
Enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the LE is pulsed. See timing diagram above for reference.
LE PUP1 PUP2 Relative Attenuation
000 -31.5
010 -24
001 -16
011 Insertion Loss
1X X 0 to -31.5 dB
Note: The logic state of D0 - D5 determines the power-
up state per truth table shown below when LE is high
at power-up.
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines the
power-up state of the part per truth table. The attenu-
ator latches in the desired power-up state approxi-
mately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Parameter Typ.
Min. serial period, tSCK 100 ns
Control set-up time, tCS 20 ns
Control hold-time, tCH 20 ns
LE setup-time, tLN 10 ns
Min. LE pulse width, tLEW 10 ns
Min LE pulse spacing, tLES 630 ns
Serial clock hold-time from LE, tCKN 10 ns
Hold Time, tPH. 0 ns
Latch Enable Minimum Width, tLEN 10 ns
Setup Time, tPS 2 ns
Control Voltage Table
State Vdd = +3V Vdd = +5V
Low 0 to 0.5V @ <1 µA 0 to 0.8V @ <1 µA
High 2 to 3V @ <1 µA 2 to 5V @ <1 µA