2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM 2Mb ZBT(R) SRAM MT55L128L18P1, MT55L64L32P1, MT55L64L36P1 3.3V VDD, 3.3V I/O FEATURES * * * * * * * * * * * * * * * * * * * High frequency and 100 percent bus utilization Fast cycle times: 7.5ns and 10ns Single +3.3V 5% power supply Advanced control logic for minimum control signal interface Individual BYTE WRITE controls may be tied LOW Single R/W# (read/write) control pin CKE# pin to enable clock and suspend operations Three chip enables for simple depth expansion Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed, fully coherent WRITE Internally self-timed, registered outputs eliminate the need to control OE# SNOOZE MODE for reduced-power standby Common data inputs and data outputs Linear or Interleaved Burst Modes Burst feature (optional) Pin/function compatibility with 4Mb, 8Mb, and 16Mb ZBT SRAM 100-pin TQFP package 165-pin FBGA package Automatic power-down OPTIONS 100-Pin TQFP** 165-Pin FBGA (Preliminary Package Data) MARKING * Timing (Access/Cycle/MHz) 4.2ns/7.5ns/133 MHz 5ns/10ns/100 MHz -7.5 -10 * Configurations 128K x 18 64K x 32 64K x 36 MT55L128L18P1 MT55L64L32P1 MT55L64L36P1 * Package 100-pin TQFP 165-pin FBGA T F * Temperature Commercial (0C to +70C) **JEDEC-standard MS-026 BHA (LQFP). GENERAL DESCRIPTION The Micron(R) Zero Bus TurnaroundTM (ZBT(R)) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The MT55L128L18P1 and MT55L64L32/36P1 SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization, eliminating turnaround cycles for READ to WRITE, or WRITE to READ, transitions. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), cycle start input None Part Number Example: MT55L128L18P1T-10* * A Part Marking Guide for the FBGA devices can be found on Micron's web site--http://www.micronsemi.com/support/index.html. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM FUNCTIONAL BLOCK DIAGRAM 128K x 18 17 17 SA1 SA1' D1 Q1 SA0 SA0' BURST D0 Q0 LOGIC MODE CLK CKE# 15 17 ADDRESS REGISTER 0 SA0, SA1, SA ADV/LD# K K WRITE ADDRESS REGISTER 1 17 WRITE ADDRESS REGISTER 2 17 S E N S E ADV/LD# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa# 128K x 9 x 2 WRITE DRIVERS 18 O U T P U T MEMORY ARRAY R E G I S T E R S A M P S BWb# R/W# 18 OE# CE# CE2 CE2# B U F F E R S S T E E R I N G E INPUT REGISTER 1 E O U T P U T D A T A 18 DQPa DQPb E INPUT REGISTER 0 E 18 READ LOGIC FUNCTIONAL BLOCK DIAGRAM 64K x 32/36 16 16 SA1 SA1' D1 Q1 SA0 SA0' BURST D0 Q0 LOGIC MODE CLK CKE# 14 16 ADDRESS REGISTER 0 SA0, SA1, SA ADV/LD# K K WRITE ADDRESS REGISTER 1 16 WRITE ADDRESS REGISTER 2 16 ADV/LD# BWa# BWb# WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC 64K x 8 x 4 (x32) 36 BWc# WRITE DRIVERS 64K x 9 x 4 (x36) MEMORY ARRAY BWd# R/W# O U T P U T S E N S E R E G I S T E R S A M P S E INPUT REGISTER 1 E OE# CE# CE2 CE2# NOTE: 36 D A T A S T E E R I N G INPUT REGISTER 0 E O U T P U T B U F F E R S 36 DQPa DQPb DQPc DQPd E 36 READ LOGIC Functional Block Diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM GENERAL DESCRIPTION (continued) (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc# and BWd#) and read/write (R/W#). Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The data-out (Q), enabled by OE#, is registered by the rising edge of CLK. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE, and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV/LD#). Use of burst mode is optional. It is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address. To allow for continuous, 100 percent use of the data bus, the pipelined ZBT SRAM uses a LATE LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The data associated with the address is required two cycles later, or on the rising edge of clock cycle three. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; and BWd# controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions. Micron's 2Mb ZBT SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTLcompatible. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. Please refer to Micron's Web site (www.micronsemi.com/datasheets/zbtds.html) for the latest data sheet. PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x18 NC NC NC x32 x36 NC DQPc DQPc DQPc DQc DQc VDDQ VSS NC DQc DQc NC DQc DQc DQb DQc DQc DQb DQc DQc VSS VDDQ DQb DQc DQc DQb DQc DQc VDD VDD VDD VSS DQb DQd DQd DQb DQd DQd VDDQ VSS DQb DQd DQd DQb DQd DQd DQPb DQd DQd NC DQd DQd PIN # x18 x32 x36 26 VSS 27 VDDQ 28 NC DQd DQd 29 NC DQd DQd 30 NC NC DQPd 31 MODE (LBO#) 32 SA 33 SA 34 SA 35 SA 36 SA1 37 SA0 38 DNU 39 DNU 40 VSS 41 VDD 42 DNU 43 DNU 44 SA 45 SA 46 SA 47 SA 48 SA 49 SA 50 NC/SA* PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x18 NC NC NC x32 NC DQa DQa VDDQ VSS NC DQa NC DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD VDD VSS DQa DQb DQa DQb VDDQ VSS DQa DQb DQa DQb DQPa DQb NC DQb x36 DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb PIN # x18 x32 x36 76 VSS 77 VDDQ 78 NC DQb DQb 79 NC DQb DQb 80 SA NC DQPb 81 SA 82 SA 83 NF* 84 NF* 85 ADV/LD# 86 OE# (G#) 87 CKE# 88 R/W# 89 CLK 90 VSS 91 VDD 92 CE2# 93 BWa# 94 BWb# 95 NC BWc# BWc# 96 NC BWd# BWd# 97 CE2 98 CE# 99 SA 100 SA * Pins 50, 83, and 84 are reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS VDD VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN ASSIGNMENT (Top View) 100-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x18 NC/SA** SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQPb* DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VDD VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQPa* NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x32/x36 NC/SA** SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQPc* DQPc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd* SA SA NF** NF** ADV/LD# OE# (G#) CKE# R/W# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA * NC for x32 version, DQPx for x36 version. ** Pins 50, 83, and 84 are reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM PIN DESCRIPTIONS TQFP (x18) 37 36 32-35, 44-49, 80-82, 99, 100 TQFP (x32/x36) SYMBOL 37 SA0 36 SA1 32-35, 44-49, SA 81, 82, 99, 100 TYPE Input 93 94 - - 93 94 95 96 BWa# BWb# BWc# BWd# Input 89 89 CLK Input 98 98 CE# Input 92 92 CE2# Input 97 97 CE2 Input 86 86 OE# (G#) Input 85 85 ADV/LD# Input 87 87 CKE# Input 64 64 ZZ Input 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 50, 83, and 84 are reserved as address bits for the higher-density 4Mb, 8Mb, and 16Mb ZBT SRAMs, respectively. SA0 and SA1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BWs are associated with addresses and apply to subsequent data. BYTE WRITEs need to be asserted on the same cycle as the address. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD# LOW). This input can be used for memory depth expansion. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDECstandard term for OE#. Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM PIN DESCRIPTIONS (continued) TQFP (x18) 88 TQFP (x32/x36) SYMBOL 88 R/W# 38, 39, 42, 43 38, 39, 42, 43 DNU (a) 58, 59, 62, 63, 68, 69, 72, 73 (b) 8, 9, 12, 13, 18, 19, 22, 23 (a) 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 51 80 1 30 N/A DQa 74 24 DQb TYPE Input DESCRIPTION Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. - Do Not Use: These signals may either be unconnected or wired to GND to minimize thermal impedance. Input/ SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb Output pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd NC NC/ I/O 31 MODE (LBO#) Input 50 50 NC/SA NC 83, 84 83, 84 NF - 14-16, 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 14-16, 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VDD Supply VDDQ Supply VSS Supply 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 95, 96 31 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 NC No Connect/Data Bits: On the x32 version, these pins are no connect (NC) and can be left floating or connected to GND to minimize thermal impedance. On the x36 version, these bits are DQs. No Connect: These pins can be left floating or connected to GND to minimize thermal impedance. Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. No Connect: NC pin 50 is reserved as an address bit for the higher-density 4Mb ZBT SRAM. This pin can be left floating or connected to GND to minimize thermal impedance. No Function: These pins are internally connected to the die and will have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. Pins 83 and 84 are reserved as address bits for the 8Mb and 16Mb ZBT SRAMs. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM PIN LAYOUT (TOP VIEW) 165-PIN FBGA x18 x32/x36 1 2 3 4 5 6 7 8 9 10 11 NC SA CE# BWb# NC CE2# CKE# ADV# NC SA SA NC SA CE2 NC BWa# CLK R/W# OE# (G#) NC SA NC NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa VDD VDD NC VDD VSS VSS VSS VDD NC NC ZZ DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC A A B DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQPb NC VDDQ VSS NC NC VDD VSS VDDQ NC NC NC NC SA SA DNU SA1 DNU SA SA SA NC MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA NC BWd# BWa# CLK R/W# OE# (G#) NC SA NC VSS VDDQ NC NC/DQPb VSS VDD VDDQ DQb DQb VSS VSS VDD VDDQ DQb DQb VSS VSS VSS VDD VDDQ DQb DQb VDD VSS VSS VSS VDD VDDQ DQb DQb NC VDD VSS VSS VSS VDD NC NC ZZ DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa NC/DQPd NC VDDQ VSS NC NC VDD VSS VDDQ NC NC/DQPa NC NC SA SA DNU SA1 DNU SA SA SA NC MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA NC NC SA CE2 NC/DQPc NC VDDQ VSS VSS VSS VSS DQc DQc VDDQ VDD VSS VSS DQc DQc VDDQ VDD VSS DQc DQc VDDQ VDD DQc DQc VDDQ VDD VDD DQd A B C D E F G H J K L M N N P P R NC M N P SA L M N NC K L M ADV# J K L CKE# CE# H J K CE2# SA G H J BWc# BWb# NC F G H 11 E F G 10 5 D E F 9 4 C D E 8 3 B C D 7 2 A B C 6 1 P R R R TOP VIEW TOP VIEW *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL TYPE SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 6R 6R 6P 6P 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 8P, 8R, 9P, 9R, 10A, 10B 9R, 10A, 10B 10P, 10R, 11A 10P, 10R DESCRIPTION 5B 4A - - 5B 5A 4A 4B BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For the x32 and x36 versions, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# controls DQds and DQPd. Parity is only available on the x18 and x36 versions. 6B 6B CLK Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 3A 3A CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 6A 6A CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 7A 7A CKE# Input 11H 11H ZZ Input Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE# is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 7B 7B R/W# Input 3B 3B CE2 Input Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. (continued on next page) 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE 8B 8B OE#(G#) Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. 8A 8A ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on ADV# effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. 1R 1R MODE (LB0#) Input Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, 10E, 1L, 1M, 2D, 10F, 10G, 11D, 2E, 2F, 2G 11E, 11F, 11G (c) 1D, 1E, 1F, 1G, 2D, 2E, 2F, 2G (d) 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M DQa DQb DESCRIPTION Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated DQas; Output Byte "b" is associated with DQbs. For the x32 and x36 versions, Byte "a" is associated with DQas; Byte "b" is associated with DQbs; Byte "c" is associated with DQcs; Byte "d" is associated with DQds. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd 11C 1N - - 11N 11C 1C 1N NC/DQPa NC/DQPb NC/DQPc NC/DQPd NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. 1H, 2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 7N, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M 1H, 2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 7N, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M VDD Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N V DD Q Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. (continued on next page) 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE DESCRIPTION 4C, 4N, 5C, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, 6H, 6J, 6G, 6H, 6J, 6K, 6L, 6M, 6K, 6L, 6M, 7C, 7D, 7E, 7C, 7D, 7E, 7F, 7G, 7H, 7F, 7G, 7H, 7J, 7K, 7L, 7J, 7K, 7L, 7M, 8C, 8N 7M, 8C, 8N VSS 5P, 5R, 7P, 7R 5P, 5R, 7P, 7R DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 1A, 1B, 1C, 1A, 1B, 1P, 1D, 1E, 1F, 2C, 2N, 2P, 1G, 1P, 2C, 2R, 3H, 5N, 2J, 2K, 2L, 6N, 9A, 9B, 2M, 2N, 2P, 9H, 10C, 2R, 3H, 4B, 10H, 10N, 5A, 5N, 6N, 11A, 11B, 9A, 9B, 9H, 11P, 11R 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N, 11P, 11R 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 Supply Ground: GND. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18) FUNCTION R/W# BWa# BWb# READ WRITE Byte "a" WRITE Byte "b" H L L X L H X H L WRITE All Bytes WRITE ABORT/NOP L L L H L H NOTE: Using R/W# and byte write(s), any one or more bytes may be written. PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36) FUNCTION READ WRITE Byte "a" WRITE Byte "b" WRITE Byte "c" WRITE Byte "d" WRITE All Bytes WRITE ABORT/NOP R/W# H L L L BWa# X L H H BWb# X H L H BWc# X H H L BWd# X H H H L L L H L H H L H H L H L L H NOTE: Using R/W# and byte write(s), any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM State Diagram for ZBT SRAM DS BURST DS DS DESELECT TE RI W AD RE READ S WRITE BEGIN READ READ D DS READ BURST BURST AD RE E RIT W BURST KEY: BURST READ COMMAND DS READ WRITE BURST BEGIN WRITE WRITE WRITE BURST WRITE BURST OPERATION DESELECT New READ New WRITE BURST READ, BURST WRITE or CONTINUE DESELECT NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM TRUTH TABLE (Notes 5-10) OPERATION DESELECT CYCLE DESELECT CYCLE DESELECT CYCLE CONTINUE DESELECT CYCLE READ CYCLE (Begin Burst) READ CYCLE (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE CYCLE (Begin Burst) WRITE CYCLE (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE ADDRESS USED None None None None External CE# CE2# CE2 ZZ ADV/ R/W# BWx OE# CKE# CLK DQ NOTES LD# L X X X L L AE H High-Z L X X X L L AE H High-Z L X X X L L AE H High-Z H X X X L L AE H High-Z 1 L H X L L LAE H Q H X X X L X H X X L X X L X H L L L L L Next X X X L H X X L L LAE H External L L H L L H X H L L AE H High-Z 2 Next X X X L H X X H L L AE H High-Z External L L H L L L L X L LAE H D 1, 2, 11 3 Next X X X L H X L X L LAE H D None L L H L L L H X L L AE H High-Z Next X X X L H X H X L L AE H High-Z Current X X X L X X X X H LAE H - None X X X H X X X X X X High-Z Q 1, 11 1, 3, 11 2, 3 1, 2, 3, 11 4 NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first. 2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an application's requirements. 4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#, BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BWa# enables WRITEs to Byte "a" (DQa pins); BWb# enables WRITEs to Byte "b" (DQb pins); BWc# enables WRITEs to Byte "c" (DQc pins); BWd# enables WRITEs to Byte "d" (DQd pins). 7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 8. Wait states are inserted by setting CKE# HIGH. 9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle. 11. The address counter is incremented for all CONTINUE BURST cycles. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. Voltage on VDD Supply Relative to VSS ............................... -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ................................... -0.5V to VDD VIN ........................................... -0.5V to VDDQ + 0.5V Storage Temperature (plastic) ............ -55C to +150C Junction Temperature** ................................... +150C Short Circuit Output Current ........................... 100mA DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD, VDDQ = +3.3V 0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS SYMBOL MIN MAX UNITS NOTES DQ pins VIH VIH VIL 2.0 2.0 -0.3 VDD + 0.3 VDD + 0.3 0.8 V V V 1, 2 1, 2 1, 2 ILI ILO -1.0 -1.0 1.0 1.0 A A 3 VOH 2.4 - V 1, 4 IOL = 8.0mA VOL VDD VDDQ - 3.135 3.135 0.4 3.465 VDD V V V 1, 4 1 1, 5 CONDITIONS TA = 25C; f = 1 MHz SYMBOL CI TYP 2.7 MAX 3.5 UNITS pF NOTES 6 VDD = 3.3V CO CA CCK 4 2.5 2.5 5 3.5 3.5 pF pF pF 6 6 6 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance FBGA CAPACITANCE DESCRIPTION CONDITIONS Address/Control Input Capacitance Output Capacitance (Q) TA = 25C; f = 1 MHz Clock Capacitance SYMBOL TYP MAX UNITS NOTES CI 2.5 3.5 pF 6, 7 CO 4 5 pF 6, 7 CCK 2.5 3.5 pF 6, 7 NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA Power-up: VIH +3.465V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply. 6. This parameter is sampled. 7. Preliminary package data. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (0C TA +70C; VDD, VDDQ = +3.3V 0.165V unless otherwise noted) MAX DESCRIPTION CONDITIONS SYMBOL TYP -7.5 -10 Power Supply Current: Operating Device selected; All inputs VIL or * VIH; Cycle time * tKC (MIN); VDD = MAX; Outputs open IDD 100 280 225 mA 1, 2, 3 Power Supply Current: Idle Device selected; VDD = MAX; CKE# * VIH; All inputs VSS + 0.2 or * VDD - 0.2; Cycle time * tKC (MIN) IDD1 10 25 20 mA 1, 2, 3 CMOS Standby Device deselected; VDD = MAX; All inputs VSS + 0.2 or * VDD - 0.2; All inputs static; CLK frequency = 0 ISB2 0.5 10 10 mA 2, 3 Device deselected; VDD = MAX; All inputs VIL or * VIH; All inputs static; CLK frequency = 0 ISB3 7 25 25 mA 2, 3 Device deselected; VDD = MAX; All inputs VSS + 0.2 or * VDD - 0.2; Cycle time * tKC (MIN) ISB4 30 70 65 mA 2, 3 ZZ * VIH ISB2Z 0.5 10 10 mA 3 CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. qJA 40 C/W 4 qJC 8 C/W 4 TTL Standby Clock Running Snooze Mode UNITS NOTES TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) UNITS NOTES FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. qJA 40 C/W 4, 5 qJC 9 C/W 4, 5 qJB 17 C/W 4, 5 Junction to Pins (Bottom) UNITS NOTES NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device is active (not in deselected mode). 3. Typical values are measured at 3.3V, 25C, and 10ns cycle time. 4. This parameter is sampled. 5. Preliminary package data. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM AC ELECTRICAL CHARACTERISTICS (Notes 6, 8, 9) (0C TA +70C; VDD, VDDQ = +3.3V 0.165V) DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in SYMBOL MIN tKHKH 7.5 fKF tKHKL tKLKH tKHQX1 tKHQZ tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX 3.5 3.5 3.5 4.2 0 tGHQZ tAVKH 100 4.2 1.5 1.5 1.5 MAX 10 2.2 2.2 tGLQV tGLQX -10 MIN 133 tKHQV tKHQX -7.5 MAX 5.0 1.5 1.5 1.5 3.5 5.0 0 4.2 5.0 UNITS NOTES ns MHz ns ns 1 1 ns ns ns ns ns ns ns 2 2, 3, 4, 5 2, 3, 4, 5 6 2, 3, 4, 5 2, 3, 4, 5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns ns ns 7 7 7 7 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 7 7 7 7 NOTE: 1. 2. 3. 4. 5. 6. Measured as HIGH above VIH and LOW below VIL. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion on these parameters. This parameter is sampled. Output loading is specified with CL = 5pF as shown in Figure 2. Transition is measured 200mV from steady state voltage. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for turnaround timing. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled. 8. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. 9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM Output Load Equivalents AC TEST CONDITIONS Input pulse levels ................................... VSS to 3.0V Q Input rise and fall times .................................. 1.0ns Z O= 50 50 Input timing reference levels .......................... 1.5V VT = 1.5V Output reference levels ................................... 1.5V Output load ............................. See Figures 1 and 2 Figure 1 +3.3V 317 LOAD DERATING CURVES Q The Micron 128K x 18, 64K x 32, and 64K x 36 ZBT SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 5pF 351 Figure 2 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tRZZ, only a DESELECT or READ cycle should be given. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION MIN MAX UNITS ISB2Z 10 mA tZZ 0 2(tKHKH) ns 1 ZZ inactive to input sampled tRZZ 0 2(tKHKH) ns 1 ZZ active to snooze current tZZI 2(tKHKH) ns 1 ns 1 Current during SNOOZE MODE CONDITIONS SYMBOL ZZ * VIH ZZ active to input ignored tRZZI ZZ inactive to exit snooze current 0 NOTES NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON'T CARE 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM READ/WRITE TIMING 1 2 3 t KHKH 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tEVKH tKHEX tKHKL tKLKH CKE# tCVKH tKHCX CE# ADV/LD# R/W# BWx# ADDRESS A1 A2 tKHQV tDVKH tAVKH tKHAX DQ tKHDX D(A1) tKHQX tKHQX1 D(A2) Q(A3) D(A2+1) tGLQV tKHQZ Q(A4+1) Q(A4) D(A5) Q(A6) tGHQZ tKHQX tGLQX OE# COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DON'T CARE DESELECT UNDEFINED READ/WRITE TIMING PARAMETERS -7.5 SYMBOL tKHKH MIN 7.5 fKF tKHKL tKLKH -10 MAX MIN 10 133 2.2 2.2 tKHQV 4.2 1.5 tKHQX1 1.5 1.5 1.5 1.5 tGLQX NOTE: 1. 2. 3. 4. 100 MHz ns ns tAVKH ns ns tDVKH ns ns ns tKHEX 5.0 1.5 tGLQV UNITS ns 3.5 3.5 tKHQX tKHQZ MAX 3.5 4.2 0 0 3.5 5.0 SYMBOL tGHQZ tEVKH tCVKH tKHAX tKHCX tKHDX -7.5 MIN MAX 4.2 -10 MIN MAX 5.0 UNITS ns 2.0 2.0 2.0 2.0 2.0 2.0 ns ns ns 2.0 0.5 2.0 0.5 ns ns 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns For this waveform, ZZ is tied LOW. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM NOP, STALL, AND DESELECT CYCLES 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CKE# CE# ADV/LD# R/W# BWx# ADDRESS A5 tKHQZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) tKHQX COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DON'T CARE DESELECT CONTINUE DESELECT UNDEFINED NOP, STALL AND DESELECT TIMING PARAMETERS SYMBOL tKHQX tKHQZ -7.5 MIN MAX 1.5 1.5 3.5 -10 MIN 1.5 1.5 MAX 3.5 UNITS ns ns NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE# are tied LOW. 3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM 165-PIN FBGA 0.85 0.075 0.10 A SEATING PLANE A 10.00 +.05 O .45 -.10 TYP 1.00 (TYP) PIN A1 ID 1.20 MAX PIN A1 ID 7.50 0.05 14.00 15.00 0.10 7.00 0.05 1.00 (TYP) MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE 6.50 0.05 SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: O .33mm 5.00 0.05 13.00 0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) PIN #1 ID 22.10 +0.10 -0.15 0.15 +0.03 -0.02 0.32 +0.06 -0.10 0.65 20.10 0.10 DETAIL A 0.62 1.50 0.10 0.10 14.00 0.10 16.00 +0.20 -0.05 0.25 0.10 +0.10 -0.05 GAGE PLANE 1.00 (TYP) 0.60 0.15 1.40 0.05 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical here noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, PIPELINED ZBT SRAM REVISION HISTORY Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/00 CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF CO; TYP 4pF from 6pF; MAX. 5pF from 7pF CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF Removed IT References, REV 7/00, FINAL ..................................................................................................... July/10/00 Added FBGA Part Marking Guide Added Revision History to Datasheet Removed IT from Part Number Example, REV 6/00, FINAL ....................................................................... June/21/00 Added # of datalines to the databus in x32/36 Block Diagram Changed tKQLZ from 4.0ns MIN to 1.5ns MIN Added Note - "Preliminary Package Data" to FBGA Capacitance and Thermal Resistance Tables Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM MT55L128L18P1_2.p65 - Rev. 8/00 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.