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2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L128L18P1_2.p65 – Rev. 8/00 ©2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
PIN DESCRIPTIONS (continued)
TQFP (x18) TQFP (x32/x36) SYMBOL TYPE DESCRIPTION
88 88 R/W# Input Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE opera-
tions and must meet the setup and hold times around the
rising edge of CLK. Full bus-width WRITEs occur if all byte
write enables are LOW.
38, 39, 42, 43 38, 39, 42, 43 DNU –Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
(a) 58, 59, 62, 63, (a) 52, 53, DQa Input/ SRAM Data I/Os: Byte “a” is DQa pins; Byte “b” is DQb
68, 69, 72, 73 56-59, 62, 63 Output pins; Byte “c” is DQc pins; Byte “d” is DQd pins. Input data
(b) 8, 9, 12, 13, (b) 68, 69, DQb must meet setup and hold times around the rising edge of
18, 19, 22, 23 72-75, 78, 79 CLK.
(c) 2, 3, 6-9, DQc
12, 13
(d) 18, 19, DQd
22-25, 28, 29
74 51 NC/DQPa NC/ No Connect/Data Bits: On the x32 version, these pins are
24 80 NC/DQPb I/O no connect (NC) and can be left floating or connected to
1NC/DQPc GND to minimize thermal impedance. On the x36 version,
30 NC/DQPd these bits are DQs.
1-3, 6, 7, 25, N/A NC NC No Connect: These pins can be left floating or connected
28-30, 51-53, to GND to minimize thermal impedance.
56, 57, 75, 78,
79, 95, 96
31 31 MODE Input Mode: This input selects the burst sequence. A LOW on
(LBO#) this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
50 50 NC/SA NC No Connect: NC pin 50 is reserved as an address bit
for the higher-density 4Mb ZBT SRAM. This pin can be
left floating or connected to GND to minimize thermal
impedance.
83, 84 83, 84 NF –No Function: These pins are internally connected to the
die and will have the capacitance of an input pin. It is
allowable to leave these pins unconnected or driven by
signals. Pins 83 and 84 are reserved as address bits for the
8Mb and 16Mb ZBT SRAMs.
14-16, 41, 65, 14-16, 41, 65, V
DD
Supply Power Supply:
See DC Electrical Characteristics and
66, 91 66, 91 Operating Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27, V
DD
Q Supply Isolated Output Buffer Supply:
See DC Electrical
54, 61, 70, 77 54, 61, 70, 77 Characteristics and Operating Conditions for range.
5, 10, 17, 21, 26, 5, 10, 17, 21, V
SS
Supply Ground:
GND.
40, 55, 60, 67, 71, 26, 40, 55, 60,
76, 90 67, 71, 76, 90