SP3243ET/TR - Exar Corporation

SP3243

3 Driver/5 Receiver Intelligent +3.0V to +5.5V

RS-232 Transceivers

The SP3243 products are 3 driver/5 receiver RS-232 transceiver solutions intended for portable or hand-

held applications such as notebook and palmtop computers. The SP3243 includes one complementary

receiver that remains alert to monitor an external device's Ring Indicate signal while the device is

shutdown. The SP3243E and EB devices feature slew-rate limited outputs for reduced crosstalk and

EMI. The "U" and "H" series are optimized for high speed with data rates up to 1Mbps, easily meeting

the demands of high speed RS-232 applications. The SP3243 series uses an internal high-efficiency,

charge-pump power supply that requires only 0.1μF capacitors in 3.3V operation. This charge pump and

Sipex's driver architecture allow the SP3243 series to deliver compliant RS-232 performance from a single

power supply ranging from +3.0V to +5.5V. The AUTO ON-LINE® feature allows the device to

automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected

peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1μA.

FEATURES

■ Meets true EIA/TIA-232-F Standards

from a +3.0V to +5.5V power supply

■ Interoperable with EIA/TIA-232 and

adheres to EIA/TIA-562 down to a +2.7V

power source

■

AUTO ON-LINE®

circuitry automatically

wakes up from a 1μA shutdown

■ Regulated Charge Pump Yields Stable

RS-232 Outputs Regardless of VCC

Variations

■ Enhanced ESD Specifications:

+15kV Human Body Model

+15kV IEC1000-4-2 Air Discharge

+8kV IEC1000-4-2 Contact Discharge

■ 250 Kbps min. transmission rate (EB)

■ 1000 Kbps min. transmission rate (EU)

■ Ideal for High Speed RS-232 Applications

DESCRIPTION

SELECTION TABLE

Now Available in Lead Free Packaging

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R4IN

425

22 SHUTDOWN

C2-

V-

R1IN

R2IN

R3IN ONLINE

C2+

C1-

GND

V+

STATUS

T1IN

11 18

15 R5OUT

T1OUT

T2OUT

T3OUT

T3IN

T2IN R4OUT

R5IN

R3OUT

R2OUT

R1OUT

R2OUT

SP3243

C1+

NOTE 1: V+ and V- can have maximum magnitudes of

7V, but their absolute difference cannot exceed 13V.

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation

of the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may

affect reliability and cause permanent damage to the

device.

VCC.......................................................-0.3V to +6.0V

V+ (NOTE 1).......................................-0.3V to +7.0V

V- (NOTE 1)........................................+0.3V to -7.0V

V+ + |V-| (NOTE 1)...........................................+13V

ICC (DC VCC or GND current).........................+100mA

Input Voltages

TxIN, ONLINE,SHUTDOWN, ...........-0.3V to Vcc +6.0V

RxIN...................................................................+15V

Output Voltages

TxOUT.............................................................+13.2V

RxOUT, STATUS.......................-0.3V to (VCC +0.3V)

Short-Circuit Duration

TxOUT....................................................Continuous

Storage Temperature......................-65°C to +150°C

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX,

C1 - C4 = 0.1μF. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.

Power Dissipation per package

28-pin SOIC (derate 12.7mW/oC above +70oC)....1000mW

28-pin SSOP (derate 11.2mW/oC above +70oC).....900mW

28-pin TSSOP (derate 13.2mW/oC above +70oC)......1059mW

32-pin MLPQ (derate 29.4mW/oC above +70oC)........2352mW

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

DC CHARACTERISTICS

Supply Current,AUTO ON-LINE®1.0 10 μA All RxIN open, ONLINE = GND,

SHUTDOWN = VCC, VCC = +3.3V,

TAMB = +25°C, TxIN = GND or VCC

Supply Current, Shutdown 1.0 10 μA SHUTDOWN = GND, VCC = +3.3V,

TAMB = +25°C, TxIN = VCC or GND

Supply Current, 0.3 1.0 mA ONLINE = SHUTDOWN = VCC, no load,

AUTO ON-LINE® Disabled

= +3.3V, T

AMB

= +25°C, TxIN = GND or V

LOGIC INPUTS AND RECEIVER OUTPUTS

Input Logic Threshold VCC = +3.3V or +5.0V, TxIN,

LOW 0.8 V ONLINE, SHUTDOWN

HIGH 2.4 V

Input Leakage Current ±0.01 ±1.0 μA TxIN, ONLINE, SHUTDOWN,

TAMB = +25°C, VIN = 0V to VCC

Output Leakage Current ±0.05 ±10 μA Receivers disabled, VOUT = 0V to VCC

Output Voltage LOW 0.4 V IOUT = 1.6mA

Output Voltage HIGH VCC - 0.6 VCC - 0.1 V IOUT = -1.0mA

DRIVER OUTPUTS

Output Voltage Swing ±5.0 ±5.4 V All driver outputs loaded with 3KΩ to GND,

TAMB = +25°C

Output Resistance 300 ΩVCC = V+ = V- = 0V, VOUT = ±2V

Output Short-Circuit Current ±35 ±60 mA VOUT = 0V

Output Leakage Current ±25 μAV

CC = 0V or 3.0V to 5.5V, VOUT = ±12V,

Drivers disabled

ELECTRICAL CHARACTERISTICS

Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX,

C1 - C4 = 0.1μF. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

RECEIVER INPUTS

Input Voltage Range -15 15 V

Input Threshold LOW 0.6 1.2 V VCC = 3.3V

Input Threshold LOW 0.8 1.5 V VCC = 5.0V

Input Threshold HIGH 1.5 2.4 V VCC = 3.3V

Input Threshold HIGH 1.8 2.4 V VCC = 5.0V

Input Hysteresis 0.3 V

Input Resistance 3 5 7 kΩ

AUTO ON-LINE® CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = VCC) 25°C

STATUS Output Voltage LOW 0.4 V IOUT = 1.6mA

STATUS Output Voltage HIGH VCC - 0.6 V IOUT = -1.0mA

Receiver Threshold to Drivers 350 μS Figure 20

Enabled (tONLINE)

Receiver Positive or Negative 0.2 μS Figure 20

Threshold to STATUS HIGH

(tSTSH)

Receiver Positive or Negative 30 μS Figure 20

Threshold to STATUS LOW

(tSTSL)

TIMING CHARACTERISTICS

Maximum Data Rate (U) 1000 Kbps RL = 3KΩ, CL = 250pF, one driver active

(H) 460 RL = 3KΩ, CL = 1000pF, one driver active

(B) 250 RL = 3KΩ, CL = 1000pF, one driver active.

( - ) 120 RL = 3KΩ, CL = 1000pF, one driver active

Receiver Propagation Delay

tPHL 0.15 μs Receiver input to Receiver output, CL = 150pF

tPLH 0.15

Receiver Output Enable Time 200 ns Normal operation

Receiver Output Disable Time 200 ns Normal operation

Driver Skew (E, EB) 100 500 ns | tPHL - tPLH |

(EU) 50 100

Receiver Skew 50 ns | tPHL - tPLH |

Transition-Region Slew Rate (U) 90 V/μsV

CC = 3.3V, RL = 3KΩ, TAMB = 25°C,

(EB) 6 30 measurements taken from -3.0V to +3.0V or

+3.0V to -3.0V

ELECTRICAL CHARACTERISTICS

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000kbps data rate, all drivers

loaded with 3kΩ, 0.1μF charge pump capacitors, and TAMB = +25°C.

Figure 2. Transmitter Output Voltage VS. Supply

Voltage for the SP3243EU

Figure 6. Transmitter Output Voltage VS. Supply

Voltage for the SP3243EU

Figure 1. Transmitter Skew VS. Load Capacitance

0 250 500 1000 1500 2000

200

150

100

Load Capacitance (pF)

Skew (ns)

T1 at 500Kbps

T2 at 31.2Kbps

All TX loaded 3K // CLoad

Figure 3. Transmitter Output Voltage VS. Load

Capacitance for the SP3243EU

Figure 5. Supply Current VS. Supply Voltage for the

SP3243EU

Figure 4. Supply Current VS. Load Capacitance for the

SP3243EU

TYPICAL PERFORMANCE CHARACTERISTICS

2.7 3 3.5 4 4.5 5

Supply Voltage (V)

Transmitter Output

Voltage (V)

-2

-4

-6

1Driver at 1Mbps

Other Drivers at 62.5Kbps

All Drivers Loaded with 3K // 250pF

2.7 3 3.5 4 4.5 5

Supply Voltage (V

)

Supply Current (mA)

1 Transmitter at 250Kbps

2 Transmitters at 15.6Kbps

All drivers loaded with 3K // 1000pF

-2

-4

-6 2.7 3 3.5 4 4.5 5

Supply Voltage (V

)

Transmitter Output

Voltage (V)

TxOUT -

TxOUT +

Supply Current (mA)

Load Capacitance (pF)

0 1000 2000 3000 4000 5000

250Kbps 120Kbps

20Kbps

1 Transmitter at full Data Rate

2 Transmitters at 15.5 Kbps

All Transmitters loades 3K + Load Cap

-2

-4

-6 2.7 3 3.5 4 4.5 5

Supply Voltage (V

)

Transmitter Output

Voltage (V)

TxOUT -

TxOUT +

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000kbps data rate, all drivers

loaded with 3kΩ, 0.1μF charge pump capacitors, and TAMB = +25°C.

Figure 8. Slew Rate VS. Load Capacitance

Figure 10. Supply Current VS. Supply Voltage

Figure 7. Transmitter Output Voltage VS. Load

Capacitance

Figure 9. Supply Current VS. Load Capacitance

TYPICAL PERFORMANCE CHARACTERISTICS

-2

-4

-6 0 1000 2000 3000 4000 5000

TxOUT +

TxOUT -

Transmitter Output

Voltage (V)

Load Capacitance (pF)

00 500 1000 2000 3000 4000 5000

Slew rate (V/μs)

Load Capacitance (pF)

- Slew

+ Slew

1 Transmitter at 250Kbps

2 Transmitter at 15.6Kbps

All drivers loaded 3K + Load Cap

Supply Current (mA)

Load Capacitance (pF)

0 1000 2000 3000 4000 5000

250Kbps 120Kbps

20Kbps

1 Transmitter at full Data Rate

2 Transmitters at 15.5 Kbps

All Transmitters loades 3K + Load Cap

2.7 3 3.5 4 4.5 5

Supply Voltage (V

)

Supply Current (mA)

1 Transmitter at 250Kbps

2 Transmitters at 15.6Kbps

All drivers loaded with 3K // 1000pF

Table 1. Device Pin Description

PIN NUMBER

SP3243EUCR

NAME FUNCTION SP3243EU MLPQ

EN Receiver Enable. Apply logic LOW for normal operation. - -

Apply logic HIGH to disable the receiver outputs (high-Z state).

C1+ Positive terminal of the voltage doubler charge-pump capacitor. 28 28

V+ Regulated +5.5V output generated by the charge pump. 27 26

C1- Negative terminal of the voltage doubler charge-pump capacitor. 24 22

C2+ Positive terminal of the inverting charge-pump capacitor. 1 29

C2- Negative terminal of the inverting charge-pump capacitor. 2 31

V- Regulated -5.5V output generated by the charge pump. 3 32

R1IN RS-232 receiver input. 4 2

R2IN RS-232 receiver input. 5 3

R3IN RS-232 receiver input. 6 4

R4IN RS-232 receiver input. 7 5

R5IN RS-232 receiver input. 8 6

R1OUT TTL/CMOS receiver output. 19 17

R2OUT TTL/CMOS receiver output. 18 16

R2OUT Non-inverting receiver-2 output, active in shutdown. 20 18

R3OUT TTL/CMOS receiver output. 17 15

R4OUT TTL/CMOS receiver output. 16 14

R5OUT TTL/CMOS receiver output. 15 13

STATUS TTL/CMOS Output indicating online and shutdown status. 21 19

T1IN TTL/CMOS driver input. 14 12

T2IN TTL/CMOS driver input. 13 11

T3IN TTL/CMOS driver input. 12 10

ONLINE Apply logic HIGH to override Auto-Online circuitry keeping 23 21

drivers active (SHUTDOWN must also be logic HIGH,

refer to Table 2).

T1OUT RS-232 driver output. 9 7

T2OUT RS-232 driver output. 10 8

T3OUT RS-232 driver output. 11 9

GND Ground. 25 23

VCC +3.0V to +5.5V supply voltage. 26 25

SHUTDOWN Apply logic LOW to shut down drivers and charge pump. 22 20

This overrides all AUTO ON-LINE® circuitry and ONLINE

(refer to Table 2).

NC No Connection - 1,24,27,30

Figure 13. SP3243 QFN Pinout Configuration

SP3243

V-

V+

R1IN

R2IN

R3IN

R4IN

R5IN

T1OUT

T2OUT

T3OUT

T3IN

T2IN

T1IN

R5OUT

R4OUT

R3OUT

R2OUT

GND

C1-

ONLINE

SHUTDOW

STATUS

R2OUT

R1OUT

Figure 15. SP3243 Typical Operating Circuit

SP3243

5KΩ

GND

C1+

C1-

C2+

C2-

V+

V-

0.1

+C3

0.1

RS-232

OUTPUTS

RS-232

INPUTS

TTL/CMOS

INPUTS

TTL/CMOS

OUTPUTS

To μP Supervisor

Circuit

T1IN

R1OUT R1IN

T2OUT

R2OUT

T2IN

T3IN T3OUT

T1OUT

R2IN

R3IN

R4IN

R5IN

R2OUT

R3OUT

R4OUT

R5OUT

ONLINE

SHUTDOWN

STATUS

DESCRIPTION

The SP3243 transceivers meet the EIA/TIA-232

and ITU-T V.28/V.24 communication protocols

and can be implemented in battery-powered,

portable, or hand-held applications such as note-

book or palmtop computers. The SP3243 de-

vices feature Sipex's proprietary and patented

(U.S.-- 5,306,954) on-board charge pump cir-

cuitry that generates ±5.5V RS-232 voltage lev-

els from a single +3.0V to +5.5V power supply.

The SP3243EU devices can operate at a data rate

of 1000kbps fully loaded.

The SP3243 is a 3-driver/5-receiver device, ideal

for portable or hand-held applications. The

SP3243 includes one complementary

always-active receiver that can monitor an

external device (such as a modem) in shutdown.

This aids in protecting the UART or serial

controller IC by preventing forward biasing

of the protection diodes where VCC may be

disconnected.

The SP3243 series is an ideal choice for power

sensitive designs. The SP3243 devices feature

AUTO ON-LINE® circuitry which reduces the

power supply drain to a 1μA supply current. In

many portable or hand-held applications, an RS-

232 cable can be disconnected or a connected

peripheral can be turned off. Under these condi-

tions, the internal charge pump and the drivers

will be shut down. Otherwise, the system auto-

matically comes online. This feature allows de-

sign engineers to address power saving concerns

without major design changes.

THEORY OF OPERATION

The SP3243 series is made up of four basic

circuit blocks:

1. Drivers

2. Receivers

3. the Sipex proprietary charge pump, and

4. AUTO ON-LINE® circuitry.

Drivers

The drivers are inverting level transmitters that

convert TTL or CMOS logic levels to 5.0V EIA/

TIA-232 levels with an inverted sense relative to

the input logic levels. Typically, the RS-232

output voltage swing is +5.4V with no load and

+5V minimum fully loaded. The driver outputs

are protected against infinite short-circuits to

ground without degradation in reliability. These

drivers comply with the EIA-TIA-232-F and all

previous RS-232 versions. Unused drivers in-

puts should be connected to GND or VCC.

The drivers have a minimum data rate of 250kbps

(EB) or 1000kbps (EU) fully loaded.

Figure 17 shows a loopback test circuit used to

test the RS-232 Drivers. Figure 18 shows the test

results where one driver was active at 1Mbps and

all three drivers loaded with an RS-232 receiver

in parallel with a 250pF capacitor. Figure 19

Figure 16. Interface Circuitry Controlled by Micropro-

cessor Supervisory Circuit

SP3243

5KΩ

GND

C1+

C1-

C2+

C2-

V+

V-

VCC

0.1μF

+C3

0.1μF

RS-232

OUTPUTS

RS-232

INPUTS

VCC

OUT R

OUT

IN T

OUT

ONLINE

SHUTDOWN

STATUS

UART

Serial μC

μP

Supervisor

TxD

RTS

DTR

RxD

CTS

DSR

DCD

VIN

RESET

shows the test results of the loopback circuit with

all drivers active at 250kbps with typical

RS-232 loads in parallel with 1000pF capacitors. A

superior RS-232 data transmission rate of 1Mbps

makes the SP3243EU an ideal match for high

speed LAN and personal computer peripheral

applications.

Receivers

Table 2. SHUTDOWN Truth Tables

Note: In AUTO ON-LINE® Mode where ONLINE =

GND and SHUTDOWN = VCC, the device will shut down

if there is no activity present at the Receiver inputs.

Figure 17. Loopback Test Circuit for RS-232 Driver

Data Transmission Rates

The receivers convert +5.0V EIA/TIA-232

levels to TTL or CMOS logic output levels.

Receivers are active when the AUTO ON-LINE®

circuitry is enabled or when in shutdown.

During the shutdown, the receivers will continue

to be active. If there is no activity present at the

receivers for a period longer than 100μs or when

SHUTDOWN is enabled, the device goes into a

standby mode where the circuit draws 1μA. The

Figure 18. Loopback Test results at 1Mbps Figure 19. Loopback Test results at 250Kbps

SP3243

GND

C1+

C1-

C2+

C2-

V+

V-

0.1μF

+C3

0.1μF

TTL/CMOS

INPUTS

+3V to +5V

SHUTDOWN

5kΩ

OUT

5kΩ

OUT

TTL/CMOS

OUTPUTS

ONLINE

OUT

STATUS

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truth table logic of the SP3243 driver and receiver

outputs can be found in Table 2.

The SP3243 includes an additional non-invert-

ing receiver with an output R2OUT. R2OUT is an

extra output that remains active and

monitors activity while the other receiver

outputs are forced into high impedance.

This allows Ring Indicator (RI) from a

peripheral to be monitored without forward

biasing the TTL/CMOS inputs of the other

devices connected to the receiver outputs.

Since receiver input is usually from a transmis-

sion line where long cable lengths and system

interference can degrade the signal, the inputs

have a typical hysteresis margin of 300mV. This

ensures that the receiver is virtually immune to

noisy transmission lines. Should an input be left

unconnected, an internal 5KΩ pulldown resistor

to ground will commit the output of the receiver

to a HIGH state.

Charge Pump

The charge pump is a Sipex–patented design

(U.S. 5,306,954) and uses a unique approach

compared to older less–efficient designs. The

charge pump still requires four external

capacitors, but uses a four–phase voltage

shifting technique to attain symmetrical 5.5V

power supplies. The internal power supply con-

sists of a regulated dual charge pump that pro-

vides output voltages 5.5V regardless of the

input voltage (VCC) over the +3.0V to +5.5V

range. This is important to maintain compliant

RS-232 levels regardless of power supply

fluctuations.

The charge pump operates in a discontinuous

mode using an internal oscillator. If the output

voltages are less than a magnitude of 5.5V, the

charge pump is enabled. If the output voltages

exceed a magnitude of 5.5V, the charge pump is

disabled. This oscillator controls the four phases

of the voltage shifting. A description of each

phase follows.

Phase 1

— VSS charge storage — During this phase of

the clock cycle, the positive side of capacitors

C1 and C2 are initially charged to VCC. Cl+ is

then switched to GND and the charge in C1– is

transferred to C2–. Since C2+ is connected to

VCC, the voltage potential across capacitor C2 is

now 2 times VCC.

Phase 2

— VSS transfer — Phase two of the clock

connects the negative terminal of C2 to the VSS

storage capacitor and the positive terminal of C2

to GND. This transfers a negative generated

voltage to C4. This generated voltage is

regulated to a minimum voltage of -5.5V.

Simultaneous with the transfer of the voltage to

C4, the positive side of capacitor C1 is switched

to VCC and the negative side is connected to

GND.

Phase 3

— VDD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C1 produces –VCC in the negative

terminal of C1, which is applied to the negative

side of capacitor C2. Since C2+ is at VCC, the

voltage potential across C2 is 2 times VCC.

Phase 4

— VDD transfer — The fourth phase of the clock

connects the negative terminal of C2 to GND,

and transfers this positive generated voltage

across C2 to C3, the VDD storage capacitor. This

voltage is regulated to +5.5V. At this voltage,

the internal oscillator is disabled. Simultaneous

with the transfer of the voltage to C3, the

positive side of capacitor C1 is switched to VCC

and the negative side is connected to GND,

allowing the charge pump cycle to begin again.

The charge pump cycle will continue as long as

the operational conditions for the internal

oscillator are present.

Since both V+ and V– are separately generated

from VCC, in a no–load condition V+ and V– will

be symmetrical. Older charge pump approaches

that generate V– from V+ will show a decrease in

the magnitude of V– compared to V+ due to the

inherent inefficiencies in the design. The clock

rate for the charge pump typically operates at

greater than 250kHz. The external capacitors

can be as low as 0.1μF with a 16V breakdown

voltage rating.

The SP3243 devices have a patent pending AUTO

ON-LINE® circuitry on board that saves power

in applications such as laptop computers, palmtop

(PDA) computers and other portable systems.

The SP3243 devices incorporate an AUTO ON-

LINE® circuit that automatically enables itself

when the external transmitters are enabled and

the cable is connected. Conversely, the AUTO

ON-LINE® circuit also disables most of the

internal circuitry when the device is not being

used and goes into a standby mode where the

device typically draws 1mA. This function can

also be externally controlled by the ONLINE

pin. When this pin is tied to a logic LOW, the

AUTO ON-LINE® function is active. Once ac-

tive, the device is enabled until there is no

activity on the receiver inputs. The receiver

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input typically sees at least +3V, which are

generated from the transmitters at the other end

of the cable with a +5V minimum. When the

external transmitters are disabled or the cable is

disconnected, the receiver inputs will be pulled

down by their internal 5kΩ resistors to ground.

When this occurs over a period of time, the

internal transmitters will be disabled and the

device goes into a shutdown or standy mode.

When ONLINE is HIGH, the AUTO ON-LINE®

mode is disabled.

The AUTO ON-LINE® circuit has two stages:

1) Inactive Detection

2) Accumulated Delay

AUTO ONLINE CIRCUITRY

The Sipex-patented charge pumps are designed

to operate reliably with a range of low cost

capacitors. Either polarized or non polarized

capacitors may be used. If polarized capacitors

are used they should be oriented as shown in the

Typical Operating Circuit. The V+ capacitor

may be connected to either ground or Vcc.

The charge pump operates with 0.1μF capacitors

for 3.3V operation. For other supply voltages,

see the table for required capacitor values. Do

not use values smaller than those listed. Increasing

the capacitor values (e.g., by doubling in value)

reduces ripple on the transmitter outputs and

may slightly reduce power consumption. C2,

C3, and C4 can be increased without changing

C1’s value.

For best charge pump efficiency locate the charge

pump and bypass capacitors as close as possible

to the IC. Surface mount capacitors are best for

this purpose. Using capacitors with lower

equivalent series resistance (ESR) and self-

inductance, along with minimizing parasitic PCB

trace inductance will optimize charge pump

operation. Designers are also advised to consider

that capacitor values may shift over time and

operating temperature.

The first stage, shown in Figure 28, detects an

inactive input. A logic HIGH is asserted on

RXINACT if the cable is disconnected or the

external transmitters are disabled. Otherwise,

RXINACT will be at a logic LOW. This circuit is

duplicated for each of the other receivers.

The second stage of the AUTO ON-LINE® cir-

cuitry, shown in Figure 29, processes all the

receiver's RXINACT signals with an accumu-

lated delay that disables the device to a 1μA

supply current.

The STATUS pin goes to a logic LOW when the

cable is disconnected, the external transmitters

are disabled, or the SHUTDOWN pin is

invoked. The typical accumulated delay is around

20μs.

When the SP3243 drivers or internal charge

pump are disabled, the supply current is reduced

to 1μA. This can commonly occur in hand-held

or portable applications where the RS-232 cable

is disconnected or the RS-232 drivers of the

connected peripheral are turned off.

The AUTO ON-LINE® mode can be disabled by

the SHUTDOWN pin. If this pin is a logic LOW,

the AUTO ON-LINE® function will not operate

regardless of the logic state of the ONLINE pin.

Table 3 summarizes the logic of the AUTO ON-

LINE® operating modes. The truth table logic of

the SP3243 driver and receiver outputs can be

found in Table 2.

The STATUS pin outputs a logic LOW signal

if the device is shutdown. This pin goes to a

logic HIGH when the external transmitters are

enabled and the cable is connected.

When the SP3243 devices are shut down, the

charge pumps are turned off. V+ charge pump

output decays to VCC, the V- output decays to

GND. The decay time will depend on the size of

capacitors used for the charge pump. Once in

shutdown, the time required to exit the shut

down state and have valid V+ and V- levels is

typically 200μs.

For easy programming, the STATUS can be

used to indicate DSR or a Ring Indicator signal.

Tying ONLINE and SHUTDOWN together

will bypass the AUTO ON-LINE® circuitry so

this connection acts like a shutdown input pin.

Figure 20. AUTO ON-LINE® Timing Waveforms

RECEIVER

RS-232 INPUT

VOLTAGES

STATUS

+5V

-5V

tSTSL

tSTSH

tONLINE

VCC

DRIVER

RS-232 OUTPUT

VOLTAGES

+2.7V

-2.7V

Figure 22. Charge Pump — Phase 2

= +5V

–5.5V

Storage Capacitor

–

––

VCC = +5V

–5V –5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

C1C2

–

––

Figure 21. Charge Pump — Phase 1

Figure 23. Charge Pump Waveforms

Ch1 2.00V Ch2 2.00V M 1.00μs Ch1 1.96V

T[]

+6V

a) C

b) C

-6V

Figure 24. Charge Pump — Phase 3

= +5V

–5V

+5V

–5V

Storage Capacitor

–

––

Figure 25. Charge Pump — Phase 4

= +5V

+5.5V

Storage Capacitor

–

––

Figure 26. SP3243 Driver Output Voltages vs. Load

Current per Transmitter

Figure 27. Circuit for the connectivity of the SP3243 with a DB-9 connector

-2

-4

-6

Transmitter Output Voltage [V]

Load Current Per Transmitter [mA]

Vout+

Vout-

0.62

0.869

0.939

1.02

1.12

1.23

1.38

1.57

1.82

2.67

3.46

4.93

8.6

The SP3243 driver outputs are able to maintain

voltage under loading of up to 2.5mA per driver,

ensuring sufficient output for mouse-driving ap-

plications.

DB-9

Connector

6. DCE Ready

7. Request to Send

8. Clear to Send

9. Ring Indicator

DB-9 Connector Pins:

1. Received Line Signal Detector

2. Received Data

3. Transmitted Data

4. Data Terminal Ready

5. Signal Ground (Common)

SP3243

5KΩ

GND

C1+

C1-

C2+

C2-

V+

V-

0.1μF

To μP Supervisor

Circuit

OUT R

OUT

IN T

OUT

ONLINE

SHUTDOWN

STATUS

OUT

LANGIS232-SR

REVIECERTA

TUPNI

NWODTUHS

TUPNI TUPNIENILNOTUPTUOSUTATS REVIECSNART

SUTATS

SEYHGIH-HGIH noitarepOlamroN

ONHGIHHGIHWOL noitarepOlamroN

ONHGIHWOLWOL nwodtuhS

(

enilnO-otuA

)

SEYWOL-HGIH nwodtuhS

ONWOL-WOL nwodtuhS

Table 3. AUTO ON-LINE® Logic

Figure 28. Stage I of AUTO ON-LINE® Circuitry

Figure 29. Stage II of AUTO ON-LINE® Circuitry

RS-232

Receiver Block

RXINACT

Inactive Detection Block

RXIN RXOUT

R1INACT R2INACT R3INACT R4INACT R5INACT

Delay

Stage Delay

Stage

SHUTDOWN

STATUS

LOW

HIGH / LOW

(Auto-Online)

ESD TOLERANCE

The SP3243 series incorporates ruggedized ESD

cells on all driver output and receiver input pins.

The ESD structure is improved over our previ-

ous family for more rugged applications and

environments sensitive to electro-static dis-

charges and associated transients. The improved

ESD tolerance is at least +15kV without damage

nor latch-up.

There are different methods of ESD testing

applied: a) MIL-STD-883, Method 3015.7

b) IEC1000-4-2 Air-Discharge

c) IEC1000-4-2 Direct Contact

The Human Body Model has been the generally

accepted ESD testing method for semi-

conductors. This method is also specified in

MIL-STD-883, Method 3015.7 for ESD testing.

The premise of this ESD test is to simulate the

human body’s potential to store electro-static

energy and discharge it to an integrated circuit.

The simulation is performed by using a test

model as shown in Figure 30. This method will

test the IC’s capability to withstand an ESD

transient during normal handling such as in

manufacturing areas where the ICs tend to be

handled frequently.

The IEC-1000-4-2, formerly IEC801-2, is

generally used for testing ESD on equipment and

systems. For system manufacturers, they must

guarantee a certain amount of ESD protection

since the system itself is exposed to the outside

environment and human presence. The premise

with IEC1000-4-2 is that the system is required

to withstand an amount of static electricity when

ESD is applied to points and surfaces of the

equipment that are accessible to personnel during

normal usage. The transceiver IC receives most

of the ESD current when the ESD source is

applied to the connector pins. The test circuit for

IEC1000-4-2 is shown on Figure 31. There are

two methods within IEC1000-4-2, the Air

Discharge method and the Contact Discharge

method.

With the Air Discharge Method, an ESD voltage

is applied to the equipment under test (EUT)

through air. This simulates an electrically charged

person ready to connect a cable onto the rear of

the system only to find an unpleasant zap just

before the person touches the back panel. The

high energy potential on the person discharges

through an arcing path to the rear panel of the

system before he or she even touches the system.

This energy, whether discharged directly or

through air, is predominantly a function of the

discharge current rather than the discharge

voltage. Variables with an air discharge such as

approach speed of the object carrying the ESD

potential to the system and humidity will tend to

change the discharge current. For example, the

rise time of the discharge current varies with the

approach speed.

The Contact Discharge Method applies the ESD

current directly to the EUT. This method was

devised to reduce the unpredictability of the

ESD arc. The discharge current rise time is

constant since the energy is directly transferred

without the air-gap arc. In situations such as

hand held systems, the ESD charge can be directly

discharged to the equipment from a person already

holding the equipment. The current is transferred

on to the keypad or the serial port of the equipment

directly and then travels through the PCB and finally

to the IC.

Figure 30. ESD Test Circuit for Human Body Model

SW1

SW2

Device

Under

Test

DC Power

Source

SW1 SW2

DEVICE PIN HUMAN BODY IEC1000-4-2

TESTED MODEL Air Discharge Direct Contact Level

Driver Outputs +15kV +15kV +8kV 4

Receiver Inputs +15kV +15kV +8kV 4

The circuit models in Figures30 and 31 represent

the typical ESD testing circuit used for all three

methods. The CS is initially charged with the DC

power supply when the first switch (SW1) is on.

Now that the capacitor is charged, the second

switch (SW2) is on while SW1 switches off. The

voltage stored in the capacitor is then applied

through RS, the current limiting resistor, onto the

device under test (DUT). In ESD tests, the SW2

switch is pulsed so that the device under test

receives a duration of voltage.

For the Human Body Model, the current limiting

resistor (RS) and the source capacitor (CS) are

1.5kΩ an 100pF, respectively. For IEC-1000-4-

2, the current limiting resistor (RS) and the source

capacitor (CS) are 330Ω an 150pF, respectively.

The higher CS value and lower RS value in the

IEC1000-4-2 model are more stringent than the

Human Body Model. The larger storage capacitor

injects a higher voltage to the test point when

SW2 is switched on. The lower current limiting

resistor increases the current charge onto the test

point.

Figure 32. ESD Test Waveform for IEC1000-4-2

t=0ns t=30ns

15A

30A

t ➙

i ➙

Figure 31. ESD Test Circuit for IEC1000-4-2

Table 4. Transceiver ESD Tolerance Levels

and

add up to 330

or IEC1000-4-2.

and

add up to 330Ω for IEC1000-4-2.

Contact-Discharge Module

SW1

SW2

Device

Under

Test

DC Power

Source

SW1 SW2

Contact-Discharge Module

PACKAGE: PLASTIC

SMALL OUTLINE (SOIC)

(WIDE)

DIMENSIONS (Inches)

Minimum/Maximum

(mm)

28–PIN

0.090/0.104

(2.29/2.649)

0.004/0.012

(0.102/0.300)

0.013/0.020

(0.330/0.508)

0.697/0.713

(17.70/18.09)

0.291/0.299

(7.402/7.600)

0.050 BSC

(1.270 BSC)

0.394/0.419

(10.00/10.64)

0.016/0.050

(0.406/1.270)

0°/8°

(0°/8°)

NX K

NX L

NX K

NX b

0.80 0.90 1.00

0 0.02 0.05

Dimensions in

(mm)

32 PIN QFN

JEDECMO220

(VHHD-4)

0 0.65 1.00

0.20 REF

0.35 0.40 0.45

MIN NOM MAX

3.50 3.65 3.80

E2 3.50 3.65 3.80

5.00 BSC

NE 8

32 PIN QFN

e0.50 BSC

b 0.18 0.25 0.30

Ø 0º - 14º

N32

SEATING PLANE

K0.20 - -

PACKAGE: 32 PIN QFN

PACKAGE: 28 PIN SSOP

WITH LEAD FINISH

BASE METAL

Seating Plane

A2 A

SEE DETAIL “A”

Seaing Plane

2 NX R R1

DETAIL A

Gauge Plane

Section A-A

INDEX AREA

2x2

E1 E

SYMBOL MIN NOM MAX

A--2

A1 0.05 - -

A2 1.65 1.75 1.85

b 0.22 - 0.38

c 0.09 - 0.25

D 9.9 10.2 10.5

E 7.4 7.8 8.2

E1 5 5.3 5.6

L 0.55 0.75 0.95

ø 0º4º8º

Note: Dimensions in (mm)

28 Pin SSOP JEDEC MO-150 (AH) Variation

1.25 REF

e 0.65 BSC

▲

PACKAGE: 28 PIN TSSOP

Seating Plane

A2 A

SEE DETAIL “A”

Seaing Plane

Ø1

DETAIL A

Ø2

Ø3

Section B-B

E1 E

INDEX AREA

2x2

SYMBOL MIN NOM MAX

A - - 1.2

A1 0.05 - 0.15

A2 0.8 1 1.05

b 0.19 - 0.3

c 0.09 - 0.2

D 9.6 9.7 9.8

E1 4.3 4.4 4.5

L 0.45 0.6 0.75

Ø1 0º - 8º

Ø2

Ø3

Note: Dimensions in (mm)

12º REF

28 Pin TSSOP JEDEC MO-153 (AE)

Variation

6.40 BSC

1.00 REF

0.65 BSC

SP 3243 E U EY L /TR

Tape and Reel options

“L” suffix indicates Lead Free packaging

Package Type A= SSOP

P= PDIP

Y=TSSOP

Temperature Range C= Commercial Range 0ºC to 70ºC

E= Extended Range -40ºC to 85ºC

Speed Indicator Blank= 120Kbps

B= 250Kbps

H= 450Kbps

U= 1Mbps

ESD Rating E= 15kV HBM and IEC 1000-4

Sipex

Part Number

PRODUCT NOMENCLATURE

CLICK HERE TO ORDER SAMPLES

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Corporation

Solved by SipexTM

ORDERING INFORMATION

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP3243EUEA/TR = standard; SP3243EUEA-L/TR = lead free

/TR = Tape and Reel. Pack quantity is 1,500 for SSOP, TSSOP and WSOIC.

Note 2: Not recommended for New Designs in QFN Package. See Factory for Availability.

Part Number Speed (kbps) Temp Range Package

SP3243EBCA 250 -0 to 70C 28 Pin SSOP

SP3243EBCA/TR 250 -0 to 70C 28 Pin SSOP

SP3243EBCR 250 -0 to 70C 32 Pin QFN: see Note 2

SP3243EBCR/TR 250 -0 to 70C 32 Pin QFN: see Note 2

SP3243EBCT 250 -0 to 70C 28 Pin WSOIC

SP3243EBCT/TR 250 -0 to 70C 28 Pin WSOIC

SP3243EBCY 250 -0 to 70C 28 Pin TSSOP

SP3243EBCY/TR 250 -0 to 70C 28 Pin TSSOP

SP3243EBEA 250 -40 to 85C 28 Pin SSOP

SP3243EBEA/TR 250 -40 to 85C 28 Pin SSOP

SP3243EBET 250 -40 to 85C 28 Pin WSOIC

SP3243EBET/TR 250 -40 to 85C 28 Pin WSOIC

SP3243EBEY 250 -40 to 85C 28 Pin TSSOP

SP3243EBEY/TR 250 -40 to 85C 28 Pin TSSOP

SP3243ECA 120 -0 to 70C 28 Pin SSOP

SP3243ECA/TR 120 -0 to 70C 28 Pin SSOP

SP3243ECT 120 -0 to 70C 28 Pin WSOIC

SP3243ECT/TR 120 -0 to 70C 28 Pin WSOIC

SP3243ECY 120 -0 to 70C 28 Pin TSSOP

SP3243ECY/TR 120 -0 to 70C 28 Pin TSSOP

SP3243EEA 120 -40 to 85C 28 Pin SSOP

SP3243EEA/TR 120 -40 to 85C 28 Pin SSOP

SP3243EET 120 -40 to 85C 28 Pin WSOIC

SP3243EET/TR 120 -40 to 85C 28 Pin WSOIC

SP3243EEY 120 -40 to 85C 28 Pin TSSOP

SP3243EEY/TR 120 -40 to 85C 28 Pin TSSOP

SP3243EUCA 1000 -0 to 70C 28 Pin SSOP

SP3243EUCA/TR 1000 -0 to 70C 28 Pin SSOP

SP3243EUCR 1000 -0 to 70C 32 Pin QFN: see Note 2

SP3243EUCR/TR 1000 -0 to 70C 32 Pin QFN: see Note 2

SP3243EUCT 1000 -0 to 70C 28 Pin WSOIC

SP3243EUCT/TR 1000 -0 to 70C 28 Pin WSOIC

SP3243EUCY 1000 -0 to 70C 28 Pin TSSOP

SP3243EUCY/TR 1000 -0 to 70C 28 Pin TSSOP

SP3243EUEA 1000 -40 to 85C 28 Pin SSOP

SP3243EUEA/TR 1000 -40 to 85C 28 Pin SSOP

SP3243EUER 1000 -40 to 85C 32 Pin QFN: see Note 2

SP3243EUER/TR 1000 -40 to 85C 32 Pin QFN: see Note 2

SP3243EUET 1000 -40 to 85C 28 Pin WSOIC

SP3243EUET/TR 1000 -40 to 85C 28 Pin WSOIC

SP3243EUEY 1000 -40 to 85C 28 Pin TSSOP

SP3243EUEY/TR 1000 -40 to 85C 28 Pin TSSOP

ORDERING INFORMATION

Legacy Part Number Recommended Upgrade Legacy Part Number Recommended Upgrade

SP3243BCA SP3243EBCA SP3243EHCA SP3243EUCA

SP3243BCA/TR SP3243EBCA/TR SP3243EHCA/TR SP3243EUCA/TR

SP3243BCA-L SP3243EBCA-L SP3243EHCT SP3243EUCT

SP3243BCA-L/TR SP3243EBCA-L/TR SP3243EHCT/TR SP3243EUCT/TR

SP3243BCR SP3243EBCR SP3243HCA SP3243EUCA

SP3243BCR/TR SP3243EBCR/TR SP3243HCA/TR SP3243EUCA/TR

SP3243BCR-L SP3243EBCR-L SP3243HCA-L SP3243EUCA-L

SP3243BCR-L/TR SP3243EBCR-L/TR SP3243HCA-L/TR SP3243EUCA-L/TR

SP3243BCT SP3243EBCT SP3243HCT SP3243EUCT

SP3243BCT/TR SP3243EBCT/TR SP3243HCT/TR SP3243EUCT/TR

SP3243BCT-L SP3243EBCT-L SP3243HCT-L SP3243EUCT-L

SP3243BCT-L/TR SP3243EBCT-L/TR SP3243HCT-L/TR SP3243EUCT-L/TR

SP3243BCY SP3243EBCY SP3243UCA SP3243EUCA

SP3243BCY/TR SP3243EBCY/TR SP3243UCA/TR SP3243EUCA/TR

SP3243BCY-L SP3243EBCY-L SP3243UCA-L SP3243EUCA-L

SP3243BCY-L/TR SP3243EBCY-L/TR SP3243UCA-L/TR SP3243EUCA-L/TR

SP3243BEA SP3243EBEA SP3243UCR SP3243EUCR

SP3243BEA/TR SP3243EBEA/TR SP3243UCR/TR SP3243EUCR/TR

SP3243BEA-L SP3243EBEA-L SP3243UCR-L SP3243EUCR-L

SP3243BEA-L/TR SP3243EBEA-L/TR SP3243UCR-L/TR SP3243EUCR-L/TR

SP3243BET SP3243EBET SP3243UCT SP3243EUCT

SP3243BET/TR SP3243EBET/TR SP3243UCT/TR SP3243EUCT/TR

SP3243BET-L SP3243EBET-L SP3243UCT-L SP3243EUCT-L

SP3243BET-L/TR SP3243EBET-L/TR SP3243UCT-L/TR SP3243EUCT-L/TR

SP3243BEY SP3243EBEY SP3243UCY SP3243EUCY

SP3243BEY/TR SP3243EBEY/TR SP3243UCY/TR SP3243EUCY/TR

SP3243BEY-L SP3243EBEY-L SP3243UCY-L SP3243EUCY-L

SP3243BEY-L/TR SP3243EBEY-L/TR SP3243UCY-L/TR SP3243EUCY-L/TR

SP3243CA SP3243ECA SP3243UEA SP3243EUEA

SP3243CA/TR SP3243ECA/TR SP3243UEA/TR SP3243EUEA/TR

SP3243CA-L SP3243ECA-L SP3243UEA-L SP3243EUEA-L

SP3243CA-L/TR SP3243ECA-L/TR SP3243UEA-L/TR SP3243EUEA-L/TR

SP3243CT SP3243ECT SP3243UER SP3243EUER

SP3243CT/TR SP3243ECT/TR SP3243UER/TR SP3243EUER/TR

SP3243CT-L SP3243ECT-L SP3243UER-L SP3243EUER-L

SP3243CT-L/TR SP3243ECT-L/TR SP3243UER-L/TR SP3243EUER-L/TR

SP3243EA SP3243EEA SP3243UET SP3243EUET

SP3243EA/TR SP3243EEA/TR SP3243UET/TR SP3243EUET/TR

SP3243EA-L SP3243EEA-L SP3243UET-L SP3243EUET-L

SP3243EA-L/TR SP3243EEA-L/TR SP3243UET-L/TR SP3243EUET-L/TR

SP3243ET SP3243EET SP3243UEY SP3243EUEY

SP3243ET/TR SP3243EET/TR SP3243UEY/TR SP3243EUEY/TR

SP3243ET-L SP3243EET-L SP3243UEY-L SP3243EUEY-L

SP3243ET-L/TR SP3243EET-L/TR SP3243UEY-L/TR SP3243EUEY-L/TR

Contact factory for availability of the following legacy part numbers. For long term availability

Sipex recommends upgrades as listed below. All upgrade part numbers shown are fully pinout

and function compatible with legacy part numbers. Upgrade part numbers may contain

feature and/or performance enhancements or other changes to datasheet parameters.