DATASHEET
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ICS670-01
IDT®
LOW PHASE NOISE ZERO DELAY BU FFER A ND MULTIP LIE R 1
ICS670-01 REV L 012315
Description
The ICS670-01 is a high-speed, low phase noise, Zero
Delay Buffer (ZDB) which integrates IDT’s proprietary
analog/digital Phase Locked Loop (PLL) techniques. The
zero delay feature means that the rising edge of the input
clock aligns with the rising edges of the outputs. There are
two identical outputs on the chip. FBCLK should be
connected to FBIN. Each output has its own output enable
pin.
The ICS670-01 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to video. By allowing off-chip feedback
paths, the ICS670-01 can eliminate the delay through other
devices. The 15 different on-chip multipliers work in a
variety of applications. Arbitrary multiplication factors
(including fractions) can be configured on the ICS527.
Features
Packaged in 16-pin SOIC
Pb (lead) free package, RoHS compliant
Clock inputs from 5 to 160 MHz (see page 2)
Patented PLL with low phase noise
Output clocks up to 160 MHz at 3.3 V
15 selectable on-chip multipliers
Power down mode available
Low phase noise: -124 dBc/Hz at 10 kHz
Output enable function tri-states outputs
Low jitter–15 ps one sigma
Full swing CMOS outputs with 25 mA drive capability at
TTL levels
Advanced, low power, sub-micron CMOS process
Industrial temperature version available
Operating voltage of 3.3 V or 5 V
Block Diagram
Voltage
Controlled
Oscillator FBCLK
OE1
Phase
Detector,
Charge
Pump, and
Loop Filter
FBIN
S3:S0
ICLK
CLK2
4
OE2
VDD
3
GND
3
External Feedback from FBCLK is recommended.
ROM-
Based
Multipliers
ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER
IDT®
LOW PHASE NOISE ZERO DELAY BU FFER A ND MULTIP LIE R 2
ICS670-01 REV L 012315
Pin Assignment Multiplier Select Table
Pin Descriptions
12
1
11
2
10
3
9
VDD
4
VDD
5
VDD
6
GND
7
CLK2
8
OE2
GND
S0
S1
FBCLK
S3
OE1
ICLK
16
15
14
13
FBIN
GND
S2
S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz)
0000Low (Power down entire
chip)
-
0001 Input x1.333 18 - 120
0010 Input x6 5 - 26.67
0011 Input x1.5 16.67 - 107
0100 Input x3.333 7.5 - 48
0101 Input x2.50 10 - 64
0110 Input x4 6 - 40
0111 Input x1 25 - 160
1000 Input x2.333 11 - 69
1001 Input x2.666 10 - 60
1010 Input x12 5 - 13.33
1011 Input x3 8 - 53.33
1100 Input x10 5 - 16
1101 Input x5 6 - 32
1110 Input x8 5 - 20
1111 Input x2 12 - 80
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 - 3 VDD Input Power supply. Connect all pins to the same voltage (either 3.3 V or 5 V). Pins
1 and 2 supply the analog sections of the chip.
4 CLK2 Output Clock output from VCO. Output frequency equals the input frequency times
multiplier.
5 OE2 Input Output clock enable 2. Tri-states the clock 2 output when low.
6 FBCLK Output Clock output from VCO. Output frequency equals the input frequency times
multiplier.
7 OE1 Input Output clock enable 1. Tri-states the feedback clock output when low.
8 FBIN Input Feedback clock input.
9 ICLK Input Clock input. Connect to a 5 - 210 MHz clock.
10 S3 Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up.
11 S2 Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up.
12 S1 Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up.
13 S0 Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up.
14 - 16 GND Power Connect to ground.
ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER
IDT®
LOW PHASE NOISE ZERO DELAY BU FFER A ND MULTIP LIE R 3
ICS670-01 REV L 012315
External Components
The ICS670-01 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01µF should be connected from each VDD pin to the ground plane, as close to the device as possible. A series
termination resistor of 33 should be used to each clock output pin.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS670-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=3.3V ±10%, Ambient temperature -40 to +85C, unless stated otherwise
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature 0 to +70C
Ambient Operating Temperature, ICS670-01I -40 to +85C
Storage Temperature -65 to +150C
Junction Temperature 125C
Soldering Temperature 260C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature 0 +70 C
Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.0 5.5 V
Input High Voltage VIH 2V
Input Low Voltage VIL 0.8 V
Output High Voltage VOH IOH = -12 mA 2.4 V
Output Low Voltage VOL IOL = 12 mA 0.4 V
Output High Voltage,
CMOS level
VOH IOH = -4 mA VDD-0.4 V
Operating Supply Current IDD No Load 35 mA
Short Circuit Current IOS Each output ±50 mA
Internal Pull-up Resistor RPU OE, select pins 200 k
Input Capacitance CIN OE, select pins 5 pF
ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER
IDT®
LOW PHASE NOISE ZERO DELAY BU FFER A ND MULTIP LIE R 4
ICS670-01 REV L 012315
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature -40 to +85C, unless stated otherwise
Note 1: Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and
15 pF load on CLK2. See graph on page 5 for skew vs. frequency and loading.
Thermal Characteristics
Parameter Symbol Conditions Min. Typ. Max. Units
Input Clock Frequency fIN See table on page 2 5 160 MHz
Output Clock Frequency 160 MHz
PLL Stabilization Time tSTAB Input frequency 5 MHz to 160 MHz 4 10 µs
Output Rise Time tOR 0.8 to 2.0 V, no load 1.5 ns
Output Fall Time tOF 2.0 to 0.8 V, no load 1.5 ns
Output Clock Duty Cycle tDC measured at VDD/2 45 50 55 %
Input to Output Skew Note 1 ±100 ps
Maximum Absolute Jitter short term ±45 ps
Maximum Jitter one sigma 15 ps
Phase Noise, relative to
carrier, 125 MHz (x5)
100 Hz offset -110 dBc/Hz
1 kHz offset -122 dBc/Hz
10 kHz -124 dBc/Hz
200 kHz -117 dBc/Hz
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
JA Still air 120 C/W
JA 1 m/s air flow 115 C/W
JA 3 m/s air flow 105 C/W
Thermal Resistance Junction to Case JC 58 C/W
ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER
IDT®
LOW PHASE NOISE ZERO DELAY BU FFER A ND MULTIP LIE R 5
ICS670-01 REV L 012315
Figure 1. Skew from ICLK to CLK2, with change in load capacitance (VDD = 3.3V)
Adjusting Input/Output Skew
The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum possible skew
between ICLK and CLK2. With a 125 MHz output, for example, having a total load capacitance of 15 pF will result
in nearly zero skew between ICLK and CLK2. Note that the load
capacitance includes board trace capacitance, input capacitance of the load being driven by the ICS670-01, and
any additional capacitors connected to CLK2.
Figure 2. Phase Noise for 125 MHz output, 25 MHz clock input (VDD = 3.3V)
-400
-300
-200
-100
0
100
200
300
25 50 75 100 125 150
CLK2 F requency (MHz)
Skew (ps)
Sk ew ( ps) 20 pF Sk ew ( ps) 10 pF
ICS670 Phase noi se
-140
-120
-100
-80
-60
-40
-20
0
10.E+0 100.E+0 1.E+3 10.E+3 100.E+3 1.E+6 10.E+6
offset frequency
L(f) dBc
ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER
IDT®
LOW PHASE NOISE ZERO DELAY BU FFER A ND MULTIP LIE R 6
ICS670-01 REV L 012315
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
"LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility
for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to
change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
Revision History
Part / Order Number Marking Shipping Packaging Package Temperature
670M-01LF 670M-01LF Tubes 16-pin SOIC 0 to +70 C
670M-01LFT 670M-01LF Tape and Reel 16-pin SOIC 0 to +70 C
670M-01ILF 670M-01ILF Tubes 16-pin SOIC -40 to +85 C
670M-01ILFT 670M-01ILF Tape and Reel 16-pin SOIC -40 to +85 C
INDEX
AREA
1 2
16
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004) C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.330.51.013.020
C 0.19 0.25 .0075 .0098
D 9.80 10.00 .3859 .3937
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.250.50.010.020
L 0.401.27.016.050
0808
Rev. Date Originator Description of Change
L 01/23/15 RDW Updated AC characterization table with new parameter "PLL Stabilization Time".
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ICS670-01
LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER