CS5180-BL - Cirrus Logic, Inc.

Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.



Cirrus Logic, Inc. 1999

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

CS5180

∆Σ

Modulator & 8 kHz to 400 kHz 16-Bit ADC

Features

l16-Bit Delta-Sig ma A/D Converter

lFully Differential Input with 4.0 Vpp Range

lDynamic Range: 93 dB

lSpurious Free Dynamic Range: 96 dB

lTotal Harmonic Distortion: -95 dB @ 22 kHz

lUp to 400 kHz Output Word Rate

lNo Missing Codes

lNon-Aliasing Low-Pass Digital Filter

lHigh Spe ed 3-Wire Serial Interface

lSupply Options:

-VA+ = 5 V, VD+ = 5 V, 690 mW

-VA+ = 5 V, VD+ = 3 V, 368 mW

lModula tor Output Mode

lPower Do wn Mode

Description

CS5180 is a fully calibrated high-speed ∆Σ analog-to-

digital converter, capable of 400 kSamp les/second out-

put word ra te (OWR). The OWR scales wi th the master

clock. It consists of a 5th order ∆Σ modu lato r, de cim ation

filter, a nd se rial in terfac e. The c hip can u se the 2.375 V

on-chip voltage reference, or an external 2.5 V refer-

ence. Th e in put v olt ag e range is 1.6 × VR EFIN V pp ful ly

differen tial. Multip le CS 5180s can be ful ly syn chroni zed

in multi-channel applications with a SYNC signal. The

part has a power-down mode to minimize power con-

sumption at times of system inactivity. The high speed

digital I/O lines h ave complem entary signa ls to help r e-

duce radiated noise from traces on the PC board. The

CS5180 can also be operated in modulator-only mode

which provides the delta-sigma modulator bitstream as

the output.

ORDERING INFORMATION

CS5180-BL -40 °C to +85 °C 28-pin PLCC

CS5180-BQ -40 °C to +85 °C 44-pin TQFP

AIN+

AIN-

VREF+

VREFIN

VREFOUT

VREFCAP

PWDN SYNC RESET MODE

VA+

AGND

VD+

DGND

MCLK

MFLAG

SDO

SCLK

FSO

Decimator Clock

x1.6

Reference Timing

and

Control

Serial

Interface

∆Σ

Modulator

VREF-

Mode

Selector

MAY ‘99

DS259PP3

CS5180
2DS259PP3
 TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................4
ANALOG CHARACTERISTICS...................................................................4
DYNAMIC CHARACTERISTICS.................................................................6
DIGITAL CHARACTERISTICS....................................................................6
SWITCHING CHAR ACTERISTICS........................................... ..................7
RECOMMENDED OPERATING CONDITIONS..........................................8
ABSOLUTE MAXIMUM RATINGS.............................................................. 8
GENERAL DESCRIPTION  ..................................................................................9
THEORY OF OPERATION ..................................................................................9
Converter Initialization:  Calibration and Synchronization  ..........................9
Clock Generator ........................................................................................10
Voltage Reference ....................................................................................10
Analog Input  .............................................................................................11
Output Coding  ..........................................................................................11
Modulator-Only mode ...............................................................................11
Instability Indicator ....................................................................................13
Digital Filter Characteristics ......................................................................13
Serial Interface ..........................................................................................13
Power Supplies / Board Layout  ................................................................13
Power-down Mode ....................................................................................15
PIN DESCRIPTION ............................................................................................16
PARAMETER DEFINITIONS .............................................................................19
APPENDIX A: CIRCUIT APPLICATIONS .........................................................21
PACKAGE OUTLINE DIMENSIONS ................................................................. 26
Contacting Cirrus Logi c Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product inf o rmation describes products which  are i n p roduction, b ut for which full  characterizati on data is not  yet  avai l ab le . Advance product infor-
mation describes products which are in development and subject to development changes.  Cirrus Logic, Inc. has made best efforts to ensure that the information
contained i n this docum ent is  accurate and  reli able.  However , the i nfor mation is sub ject  to change with out no tice and i s provi ded “AS IS” withou t warranty of
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CS5180
DS259PP3 3
LIST OF FIGURES
Figure 1. Serial Po rt Timing (n ot to scale) ......... ....... ...... ...... ....... ...... ....... ...... ....... ..... 7
Figure 2. RESET and SYNC logic and timing.  ........................................................... 9
Figure 3. CS5180 connection diagram for using the internal voltage reference. ...... 10
Figure 4. CS5180 connection diagram for using an external voltage reference. ...... 11
Figure 5. Modulator Only Mode Data RTZ Format. .................................................. 12
Figure 6. Circuit to Reconstruct
 Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream.  12
Figure 7. Magnitude versus frequency spectrum of modulator 
bitstream (MCLK = 25.6 MHz).  .......................................................................... 12
Figure 8. Expanded view of the magnitude versus frequency spectrum of 
modulator bitstream (MCLK = 25.6 MHz).  ......................................................... 12
Figure 9. CS5180 Digital Filter Magnitude Response (MCLK = 25.6 MHz) .............. 13
Figure 10. CS5180 Digital Filter Phase Response
(MCLK = 25.6 MHz)  ........................................................................................... 13
Figure 11. CS5180 System Connection Diagram ..................................................... 14
Figure 12. Single amplifier driving only AIN+, AIN- held at steady dc value ............. 21
Figure 13. Performance of amplifier of Figure 12 overdriving AIN+ input to the 
CS5180 at 4 VPP ............................................................................................... 21
Figure 14. Performance of amplifier of Figure 12 with AIN+ driven at 2 VPP ........... 21
Figure 15. AC-coupled driver using two amplifiers. .................................................. 22
Figure 16. Performance of amplifier in Figure 15 ..................................................... 22
Figure 17. Three amplifier driver  .............................................................................. 23
Figure 18. Performance of amplifier in Figure 17 ..................................................... 23
Figure 19. Four amplifier driver.  ............................................................................... 24
Figure 20. Performance of amplifier in Figure 19 ..................................................... 24
Figure 21. Performance of amplifier in Figure 19 ..................................................... 24
Figure 22. CS5180 Differential Non-linearity plot.
(Data taken with repeating ramp) ....................................................................... 25
Figure 23. Histogram of DNL from Figure 22  ........................................................... 25
Figure 24. CS5180 Noise Histogram, > 60,000 samples.  ........................................ 25

CS5180
4DS259PP3
CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = -40  to 85 °C; VA+  = 5 V ±5%, VD+ = 3 V ±10%; AGND = 
DGND = 0 V; MCLK = 25.6 MHz; VREFIN = VREFOUT; MODE = VD+; Analog source impedance = 301 Ohms 
with 2200 pF to AGND; Full-Scale input sinewave at 22 kHz; Unless otherwise noted)
Notes: 1. Dynamic range is tested with a 22 kHz input signal 60 dB below full scale.
2. Specification guaranteed by design, characterization, and/or test.
3. Full scale fully-differential input span is nominally 1.6 X the VREFIN voltage.  The peak negative 
excursion of the signals at  AIN+ or AIN- should not go below AGND for proper operation.
4. VREFIN current is less than 1 µA under normal operation, but can be as high as ±200 µA during 
calibration.
5. Drift of the on-chip reference alone is typically about ±30 ppm/°C. If using an external reference, total 
full scale drift will be that of the external reference ±20 ppm/°C, which is the typical drift of the X1.6 
buffer.
6. Applies after self-calibration at final operating ambient temperature.
Parameter Symbol Min Typ Max Unit
Dynamic Performance
Dynamic Range (Note 1) DR 90 93 - dB
Total Harmonic Distortion THD -90 -95 - dB
Signal to (Noise + Distortion) SINAD 87 91 - dB
Spurious Free Dynamic Range SFDR 90 96 - dBc
Static Performance
Lineari ty Error (Note 2) INL - ±2 - LSB
Differential Non-Linearity (Note 2) DNL - - ±0.5 LSB
Full Scale Error                                                                     (Note 6) - ±8 - LSB
Full Scale Drift with Internal Reference (Notes 2 and 5) - ±50 - ppm/°C
Offset Error                                                                       (Note 6) - ±8 - LSB
Offset Drift (Note 2) - ±6.0 - µV/°C
Analog Input
Differential Input Voltage Range (Note 3) - 1.6 X 
VREFIN -V
pp
Common Mode Range CMR 1 - VREFIN 
+ 0.25 V
Input Capacitance - 4.0 - pF
Differential Input Impedance MCLK = 25.6 MHz - 500 - kΩ
Common Mode Rejection Ratio (Note 2) CMRR 50 - - dB
Common Mode Input Current MCLK = 25.6 MHz - ±100 ±200 µA
Reference Input
VREFIN 2.25 2.375 2.6 V
VREFIN Current (Note 4) - 1 ±200 µA
Reference Output
VREFOUT Voltage 2.25 2.375 2.5 V
VREFOUT Output Current - - ±500 µA
VREF OU T Impedan ce - 0.1 - Ω

CS5180

DS259PP3 5

ANALOG CHARACTERISTICS (Continued)

Notes: 7. All outputs unloaded. All digital inputs except MCLK held static at VD+ or DGND.

8. Power consumption when PWDN = 0 applies only with no master clock applied (MCLK held high or low).

9. Measured with a 100 mVpp sine wave on the VA+ supplies at a frequency of 100 Hz.

Parameter Symbol Min Typ Max Unit

Power Supplies

Power Supply Current (MODE = 1, PWDN = 1) (Note 7)

VA1+, VA2+ = 5 V

VD1+, VD2+ = 5 V

VD1+, VD2+ = 3 V

110

Power Supply Current (MODE = 1, PWDN = 0) (Notes 7, 8)

VA1+, VA2+ = 5 V

VD1+, VD2+ = 5 V

VD1+, VD2+ = 3 V

3.7

0.068

0.060

0.2

Power Supply Current (MODE = 0, PWDN = 1) (Note 7)

VA1+, VA2+ = 5 V

VD1+, VD2+ = 5 V

VD1+, VD2+ = 3 V

8.5

11.0

Power Supply Current (MODE = 0, PWDN = 0) (Notes 7, 8)

VA1+, VA2+ = 5 V

VD1+, VD2+ = 5 V

VD1+, VD2+ = 3 V

3.7

0.068

0.060

0.2

Power Supply Rejection (Note 9) PSRR - 55 - dB

CS5180

6DS259PP3

DYNAMIC CHARACTERISTICS

DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; VA+ = 5 V ±5%; AGND = DGND = 0 V)

Parameter Symbol Min Typ Max Unit

Modulator Sampling Frequency - MCLK - Hz

Output Word Rate - MCLK/64 - Hz

Filter Characteristics (Note 2)

-3 dB Corner - MCLK/142. 3804 - Hz

Passband Ripple - - ±0.05 dB

Stopband Frequency - MCLK/128 - Hz

Stopband Rejection 90 - - dB

Group Delay - 2370/MCLK - s

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage VD+ = 5 V

VD+ = 3 V VIH

VIH

4.0

2.0 -

-V

Low-Level Input Voltage VD+ = 5 V

VD+ = 3 V VIL

VIL

-0.8

0.8 V

High-Level Output Voltage (IO = -100 µA) VD+ = 5 V

VD+ = 3 V VOH

VOH

2.7 -

-V

Low-Level Output Voltage (IO = 100 µA) VD+ = 5 V

VD+ = 3 V VOL

VOL

-0.4

0.3 V

Input Leakage Current VD+ = 5 V

VD+ = 3 V Iin

Iin

-±1

±1 ±10

±10 µA

µA

Input Capacitance Cin -6-pF

CS5180

DS259PP3 7

SWITCHING CHARACTERISTICS (TA = -40 to 85 °C; VA+ = 5 V ±5%, VD+ = 2.7 V to 5.5 V;

AGND = DGND = 0 V; MODE = VD+)

Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform.

11. RESET, SYNC, and PWDN have Schmitt-trigger inputs.

12. Specifications applicable to complementary signals SCLK and SDO.

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 2) MCLK 0.512 25.6 26 MHz

Master Clock Duty Cycle 45 - 55 %

Rise Times (Notes 2, 10, and 11)

Any Digital Input, Except MCLK

MCLK

Any Digital Output

trise -

100

.2/MCLK

Fall Times (Notes 2, 10, and 11)

Any Digital Input, Except MCLK

MCLK

Any Digital Output

tfall -

100

.2/MCLK

Calibration/Sync

RESET rising to MCLK rising -3 -ns

RESET rising recognized, to FSO falling - 988205/MCLK - s

SYNC rising to MCLK rising - 3 - ns

SYNC rising recognized to FSO falling - 5161/MCLK - s

PWDN rising recognized to FSO falling - 5168/MCLK - s

SYNC high time 1/MCLK - - s

RESET low time 1/MCLK - - s

Serial Port Timing (Note 12)

SCLK frequency - MCLK/3 - Hz

SCLK high time t1-1/MCLK-s

SCLK low time t2-2/MCLK-s

FSO falling to SCLK rising t3-2/MCLK+2E-9 - s

SCLK falling to new data bit available t4-1.5 -ns

SCLK rising to FSO rising t5-1/MCLK-2E-9- s

FSO

SCLK

SDATA

MSB MSB-1 LSB-1 LSB

Figure 1. Serial Port Timing (not to scale)

CS5180

8DS259PP3

RECOMMENDED OPERATING CONDITIONS (AGND = DGND = 0 V)

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

Parameter Symbol Min Typ Max Unit

DC Power Supplies Digital

Analog VD+

VA+ 2.7

4.75 3

55.5

5.25 V

Analog Reference Voltage VREFIN 2.25 2.5 2.6 V

AGND to DGND Differential -100 0 100 mV

Operating Junction Temperature Tj--120°C

Parameter Symbol Min Max Unit

DC Power Supplies Ground

Digital

Analog

AGND/DGND

VD+

VA+

-0.3

0.3

6.0

Input Current, Any pin except Supplies Iin -±10mA

Output Curr ent Iout -±25mA

Power Diss ipation (Total) - 1000 mW

Analog Input Voltage and VREFIN voltage VINA -0.3 (VA+) + 0.3 V

Digital Input Voltage VIND -0.3 (VD+) + 0.3 V

Ambient Operating Temperature TA-40 85 °C

Storage Temperature Tstg -65 150 °C

CS5180

DS259PP3 9

GENERAL DESCRIPTION

The CS5180 is a monolithic CMOS 16-bit A/D

converter designed to operate in a continuous mode

after being reset.

The CS5180 can operate in a modulator-only mo de

in which the unfiltered bit st ream from the modula-

tor is the data output from the device.

THEORY OF OPERATION

The front page of this data sheet illustrates the

block diagram of the CS5180.

Converter Initialization: Calibration and

Synchronization

The CS5180 does not have an internal power-on re-

set circuit. Therefore when power is first applied to

the device the RESET pin should be held low until

power is established and the voltage reference has

stabilized. This resets the converter’s logic to a

known state. When power is fully established the

converter will perform a self-calibration, starting

with the first MCLK rising edge after RESET goe s

high. The converter will use 988,205 MCLK cycles

to complete the calibration and to allow the digital

filter to fully settle, after which, it will output fully-

settled conversion words. The converter will then

continue to output conversion words at an output

word rate equal to MCLK/64. Figure 2 illustrates

the RESET and SYNC logic and timing for the con-

verter.

The CS5180 is designed to perform conversions

continuously with an output rate that is equivalent

to MCLK/64. The conversions are perf ormed and

the serial port is updated independent of external

controls. The converter is designed to measure dif-

ferential bipolar input signals, and unipolar signals,

with a common mode voltage of between 1.0 V and

VREF + 0.25 V. Calibration is performed when the

RESET signal to the device is released. If RESET

is properly framed to MCLK, the converter can be

synchronized to a specific MCLK cycle at the sys-

tem level.

The SYNC signal can also be used to synchronize

multiple converters in a system. When SYNC is

used, the converter does not perform calibration.

The SYNC signal is recognized on the first rising

edge of MCLK after SYNC goes high. SYNC

aligns the output conversion to occur every 64

MCLK clock cycles after the SYNC signal is rec-

ognized and the filter is settled. After the SYNC is

initiated by going high, the converter will wait

5,161 MCLK cycles for the digital filter to settle

before putting out a fully-settled conversion word.

To synchronize multiple converters in a system, the

RESET

MCLK

SYNC

CS5180

CLK

QRESET

MCLK

RESET

FSO

988205 MCLK Cycles

CLK

QSYNC MCLK

SYNC

FSO

5161 MCLK Cycles

Figure 2. RESET and SYNC lo gic and timing.

CS5180

10 DS259PP3

SYNC pulse should rise on a falling edge of the

MCLK signal. This ensures that the SYNC input to

all CS5180s in the system will be recognized on the

next rising edge of MCLK. Use of the SYNC input

is not necessary to make the converter operate

properly. If it is unused it should be tied to DGND.

Conversion data is output from the SDO and SDO

pins of the device. The data is output from the SDO

pin MSB first, in two’s complement format. The

converter furnishes a serial clock SCLK and its

complement SCLK to latch the data bits; and a data

framing signal, Frame Sync Output (FSO), which

frames the output conversion word. The SCLK

output frequency is MCLK/3.

Clock Generator

The CS5180 must be driven from a CMOS-com-

patible clock at its MCLK pin. The MCLK input is

powered from the VD+ supply and its signal input

should not exceed this supply. The required

MCLK is 64 × OWR (Output Word Rate). To

achieve an Output Word Rate of 400 kHz, the

MCLK frequency must be 64 × 400 kHz, or

25.6 MHz. A second clock input pin, MCLK, is

not actually used inside the device but allows the

user to run a fully differential clock to the converter

to minimize radiated noise from the PC board lay-

out.

The CS5180 can be operated with MCLK frequen-

cies from 512 kHz up to 26 MHz. The output word

rate scales with the MCLK rate with

OWR = MCLK/64.

Voltage Reference

The CS5180 can be configured to operate from ei-

ther its internal voltage reference , or from an exter-

nal voltage reference.

The on-chip voltage reference is 2.375 V and is ref-

erenced to the AGND pin. Th is 2.375 V reference is

output from the VREFOUT pin. It is then filtered

and returned to the VREFIN pin. VREFIN pin is

connected to a buffer which has a gain of 1.6. This

scales the on-chip reference of 2.375 V to 3.8 V.

This value sets the peak-to-peak input voltage into

the AIN pins of the converter. Figure 3 illustrates the

CS5180 connected to use the internal voltage refer-

ence. Note that a 1.0 µF and 0.1 µ F capacitor are

shown connected to the VREFCAP pin to filter out

noise. A larger capacitor can be used, but may re-

quire a longer reset period when first applying power

to the part to allow for the reference to ch arge up the

capacitors and stabilize before self-calibration be-

gins.

10 µF 0.1 µF

VREFIN

VREF+

VREF-

VREFOUT

VREFCAP

X1.6

Modulator

Reference

CS5180

10 µF 0.1 µF

1 µF 0.1 µF

Figure 3. CS5180 connection diagram for using the internal voltage reference.

CS5180

DS259PP3 11

Alternatively, the CS5180 can be configured to use

an external voltage reference. Figure 4 illustrates

the CS5180 connected to use a 2.5 V external ref-

erence. In this case, the peak-to-peak input at the

AIN pins is 4 V.

Analog Input

The analog signal to the converter is input into the

AIN+ and AIN- pins. The input signal is fully dif-

ferential with the maximum peak-to-peak ampli-

tude of VREFIN X 1.6 V. The signal needs to have

a common mode voltage in a range from 1 V to

VREF + 0.25 V. A resistor-capac itor filter should

be included on the AIN+ and AIN- inputs of the

converter. This should consist of a 20 Ω resistor

and a 2200 pF capacitor on each input to ground as

illustrated in the system connection diagram (Fig-

ure ).

Output Coding

Table 1 illustrates the output coding for the con-

verter when operating with the digital filter

(MODE = 1). The c onverter outputs its data from

the serial port in twos complement format, MSB

first.

The chip offers an MFLAG signal to indicate when

the modulator has gone unstable. MFLAG is set

when an overrange signal forces the modulator into

an unstable condition. Under this condition, output

codes from the converter will be locked to either

plus or minus full scale as is appropriate for the

overrange condition.

Modulator-Only mode

The CS5180 can be operated in modulator-only

mode by connecting the MODE pin to a logic 0

(DGND).

In modulator-only mode the noise-shaped bit-

stream from the fifth-order delta-sigma modulator

is output from the SDO and SDO (inverse bit-

stream) pins.

10 µF 0.1 µF

VREFIN

VREF+

VREF-

VREFOUT

VREFCAP

X1.6

Modulator

Reference

CS5180

10 µF 0.1 µF

1 µF 0.1 µF

10 µF

0.1 µF

2.5 V

10 µF 0.1 µF

Figure 4. CS5180 connection diagram for using an external voltage reference.

Fully Differential Bipolar

Input Voltage1Twos Complement

>(VFS - 1.5 LSB) 7FFF

VFS - 1.5 LSB 7FFF

7FFE

-0.5 LSB 0000

FFFF

-VFS + 0.5 LSB 8001

8000

<(-VFS + 0.5 LSB) 8000

Notes: 1. VFS = VREFIN x 1.6

Table 1. Out put Coding.

CS5180

12 DS259PP3

The data from the modulator is output from

SDO/SDO in RTZ (Return to Zero) format. The

circuit in Figure 6 can be used to reconstruct the

data so it can be captured with the rising or falling

edge of MCLK.

Table 2 illustrates the magnitude of the input signal

into the chip versus the ones density out of the

modulator. The table does not take into account the

potential offset and gain errors of the modulator

and their effect on the ones density.

Figure 7 and Figure 8 illustrate magnitude versus

frequency plots of the modulator bitstream when

running at 25.6 MHz.

Fully Differential Bipolar

Input Voltage2Modulator Ones

Density3

VFS 75%

050%

-VFS 25%

Notes: 2. VFS = VREFIN x 1.6

3. Ones density is approximate; it does not

take offset and gain errors into

consideration.

Table 2. Modulator-Only Mode Ones Density.

MCLK

Modulator

Data

SDO

Reconstructed

Data

SDO

Figure 5. Modulator Only Mode Data RTZ Format.

SDO Reconstructed

Data

SDO Reconstructed

Data

Figure 6. Circuit to Reconstruct

Return-to-Zero (RTZ) Data from

SDO/SDO into Or iginal Modulator Bitstream.

Figure 7. Magnitude versus frequency spectrum of

modulator bitstream

(MCLK = 25.6 MHz).

Figure 8. Expanded view of the magnitude versus fre-

quency spectrum of modulator bitstream

(MCLK = 25.6 MHz).

CS5180

DS259PP3 13

Instability Indicator

The MFLAG signal is functional in both modes of

operation of the part and indicates when the modu-

lator has been overdriven into an unstable condi-

tion. In the modulator only m ode (MODE = 0), the

MFLAG signal will rema in s et for 3 M CLK c ycles

when the modulator goes unstable, before being re-

turned to the reset state. While the input condition

causing modulator instability persists, the MFLAG

signal will continually get set for 3 MCLK cycles

and then get reset.

When the de cimation filter on th e part is operation-

al (MODE = 1), the MFLAG signal is set when the

modulator goes unstable. In this mode, however,

the MFLAG signal stays set until 5,120 MCLK cy-

cles after the input condition causing modulator in-

stablility is removed. This delay is provided to

allow the digital filter time to settle, and the part

will output fully settled conversion words after the

MFLAG signal goes low.

Digital Filter Characteristics

Figure 9 illustrates the magnitude versus frequency

plot of the converter when operating at 400 kHz

output word rate. The filter is a non-al iasing 4265

tap filter with a -3 dB corner at 0.4495 of t he output

word rate and an out-of-band attenuation of at l east

90 dB at frequencies above one half the output

word rate. The passband ripple is less than

±0.05 dB up to the -3 dB corner frequency.

Figure 10 illustrates the phase response of the dig-

ital filter with the converter operating at 400 kHz

output word rate. The filter characteristics change

proportional to changes in the MCLK rate.

The group delay of the digital filter is 2,370 MCLK

cycles (92.6 µ s with MCLK = 25.6 MHz), and the

settling time is 4,740 MCLK cycles (185.2 µs).

Serial Interface

The CS5180 has a serial interface through which

conversion words are output in a synchronous self-

clocking format. The serial port consists of the Se-

rial Data Output pin (SDO), and its complement

(SDO); Serial Clock (SCLK), and its complement

(SCLK); and the Frame Sync Output (FSO). FSO

falls at the beginning of an output word. Data is

output in twos complement format, MSB first.

FSO stays low for 16 SCLK cycles. SCLK is out-

put at a rate equal to MCLK/3.

Power Supplies / Board Layout

The CS5180 can be operated with VA+ supplies at

5 V and V D+ supplies at 5 V; or with VA+ at 5 V

and VD+ at 3 V.

Figure illustrates the system connection diagram

for the chip. For best performance, each of the

Figure 9. CS5180 Digital Filter Magnitude Response

(MCLK = 25.6 MHz)

Figure 10. CS5180 Digital Filter Phase Response

(MCLK = 25.6 MHz)

CS5180

14 DS259PP3

supply pins should be bypassed to the nearest

ground pin on the chip. The bypass capacitors

should be located as close to the chip as possible. If

the chip is surface mounted the bypass capacitors

should be on the same side of the circuit card as the

chip.

The CS5180 is a high speed component that re-

quires adherence to standard high-freque ncy print-

ed circuit board layout techniques to maintain

optimum performance. These include the use of

ground and power planes, using low noise power

supplies in conjunction with proper supply decou-

pling, minimizing circuit trace lengths, and physi-

cal separation of digital and analog components

and circuit traces.

It is preferred that any clock osc illator circuitry be

located on a ground plane separate from the digital

plane in order to ensure that digital noise does not

induce clock jitter.

For additional insight, see the CDB5180 evaluation

board for more details. Also refer to Application

Note AN18 about layout and design rules for data

converters.

AGND1

+5 V

3.8 V Fully

Differential

CMV = 2.375 V

+5 V o r

+3.0 V

VA1+

VA2+

AGND2

AGND3

VREFOUT

VREFIN

VREF-

VREF+

VREFCAP

AIN+

AIN-

DGND1

VD1+

VD2+

DGND2

PWDN

MODE

RESET

SYNC

MFLAG

MCLK

FSO

SCLK

SDO

SCLK

SDO

Control

Logic

Clock

Source

Data

Interface

CS5180

0.1 µF

10 µF

1 µF

2200 pF

Ω

The 3.8 Vpp fully differential input span is set by the converter’s internal voltage reference at 2.375 V.

An input span of 4.0 Vpp fully differential would result if an external voltage reference of 2.5 V is used.

† Miniature surface mount 25.6 MHz clock oscillators may be ordered from the CTS Reeves Company.

For 4.5 V to 5.5 Volt Operation, order P/N 974-7725-0000A

For 3.0 to 3.6 Volt Operation, order P/N 974-7727-0000A

Figure 11. CS5180 System Connection Diagram

†

CS5180

DS259PP3 15

Power-down Mode

The CS5180 has a PWDN (power-down) function.

When active low, power to most of the converter’s

circuitry will be reduced. If MCLK is to be stopped

to save power, it should not be stopped until at least

ten clock cycles after PWDN is taken low. The ten

clock cycles are required to allow the part to turn

off it’s internal circuitry. If the part does not get the

full ten clock cycles, it will still go into a power

down state, but the power dissipation could be

more than is listed in the specifications for the full

power down condition. When PWDN is active, the

calibration information inside of the converter is

maintained. When coming out of the power-down

state, the converter is not recalibrated and will

start-up similar to when SYNC is initiated.

CS5180

16 DS259PP3

PIN DESCRIPTION

Analog Ground AGND

Pos. Reference VREF+ VA1+ Positive Analog Supply

Neg. Refere nce VREF- AIN- Negative Analog Input

Reference Output VREFOUT AIN+ Positive Analog Input

Pos. Reference Input VREFIN PWDN Power Down Mode

Reference Bypass VREFCAP MODE Modulator Only Mode

Analog Ground AGND RESET Reset and Calibration

Analog Supply VA2+ DGND Digital Ground

Invalid Conver sion MFLAG VD1+ Positive Digital Supply

Sync. Filter SYNC MCLK Master Clock

Digital Ground DGND MCLK Inverse Master Clock

Pos. Digital Supply VD2+ AGND Analog Ground

Inve rse Ser ial Cloc k SCLK FSO Frame Sync Output

Serial Clock SCLK SDO Serial Data Out

SDO Inverse Serial Data Out\

CS5180

1234282726

1112 13 14 15 16 17 19

AGND Analog Ground

Analog Ground AGND VA1+ Positive Analog Supply

Pos. Reference VREF+ AGND Analog Ground

Neg. Reference VREF- AIN- Negative Analog Input

Reference Output VREFOUT AIN+ Positive Analog Input

Analog Ground AGND AGND Analog Ground

Analog Ground AGND PWDN Powe r Down Mod e

Reference Input VREFIN MODE Modulator Only Mode

Reference Bypass VREFCAP RESET Reset and Calibration

Analog Ground AGND DGND Digital Ground

Analog Sup pl y VA2+ VD1+ Posi tive Digital Supply

Invalid Conversion MFLAG DGND Digital Ground

Sync. Filter SYNC MCLK Master Clock

Digital Ground DGND MCLK Inverse Master Clock

Digital Ground DGND DGND Digital Ground

Pos. Digital Supply VD2+ NC

Pos. Digital Supply VD2+ AGND Analog Ground

Digital Ground DGND NC

Inverse Serial Clock SCLK FSO Frame Sync Output

Serial Clock SCLK SDO Serial Data Out

SDO Inverse Serial Data Out\

11 1213141516171819202122

4443424140393837363534

CS5180

DS259PP3 17

Supply Inputs

VA1+, VA2+ — Positive Analog Supply

Input for positive analog supply is +5 V typical when AGND is 0 V.

AGND — Analog Ground

Analog ground for circuits supplied by VA+.

VD1+, VD2+ — Positive Digital Supply

Input for positive digital supply is +5 V typical when DGND is 0 V.

DGND — Digital Ground

Digital ground for circuits supplied by VD+.

Signal and Reference Related Inputs

AIN+, AIN- — Differential Analog Inputs

Fully differential signal inputs.

VREFIN — Voltage Reference Input

VREFOUT or an external reference is connected to VREFIN. Analog input voltage (full scale

fully differential peak-to-peak) into the converter is 1.6 times this value.

VREF+ — Positive Voltage Reference

Filter capacitor connection for the reference input buffer. The voltage on this pin equals

VREFIN X 1.6.

VREF- — Negative Voltage Reference

VREF- is connected to AGND.

VREFOUT — Voltage Reference Output

Output pin for the 2.375 volt on-chip reference relative to AGND.

VREFCAP — Reference Bypass

Filter capacitor connection for the internal reference.

Serial Interface I/O Signals

SCLK, SCLK — Serial Interface Clock

Serial Clock Output. A gated serial clock output from the converter at a rate equal to 1/3 the

MCLK clock rate. The SCLK output is a complement of SCLK and helps reduce radiated noise

if the two lines are run adjacent on the PC board layout.

CS5180

18 DS259PP3

SDO, SDO — Serial Data Out

Serial Data Output. Output pin for 16-bit serial data word. The SDO output is the complement

of SDO and helps to reduce radiated noise if the two lines are run adjacent on the PC board

layout. Output data is output in twos complement format MSB first.

FSO — Frame Sync Output

The Frame Sync Output indicates the beginning of an output word from the SDO pin by falling

to a logic low state. FSO remains low until all 16 bits are clocked out.

Control Pins

RESET — Reset and Calibration

When the RESET pin is pulled to a logic low the converter will perform a reset of its digital

logic. When the level on this pin is brought back to a logic high the chip starts normal

operation, following a two clock cycle delay period. When MODE = 1 the chip goes through

an internal gain and offset calibration routine following this reset sequence.

PWDN — Power Down Mode

A logic 0 on PWDN pin will put the device into a power-down mode.

MODE — Modulator Mode

MODE is held at a logic high for normal operation. In normal operation the device utilizes the

digital decimation filter and calibration ciruitry. MODE = 0 puts the part in modulator-only

mode whereby most of the digital circuitry is powered-down and the modulator bit-stream is

output from the SDO and SDO pins.

SYNC — Synchronization of Filter

The SYNC input can be used to restart the digital filter of the converter at the beginning of its

convolution cycle. The SYNC input is used to synchronize the filters of multiple converters in

a system. When the SYNC pin goes high, the filter will be initialized and will begin its

convolution cycle on the next rising edge of MCLK. If not used, tie sync to DGND.

MFLAG — Invalid Conversion Flag

MFLAG goes high if the modulator portion of the converter goes unstable. If MFLAG is high,

the output data from the converter may be invalid.

MCLK, MCLK — Master Clock Signal

Master clock input accepts a CMOS level clock input to the converter with worst case duty

cycle of 45-55% (typically 25.6 MHz). MCLK is not actually used inside the device, but can

be used for radiated noise cancellation if MCLK and MCLK are run adjacent to each other on

the PC board.

CS5180

DS259PP3 19

PARAMETER DEFINITIONS

Differential Non-Linearity Error - DNL

The deviation of a code’s width from ideal. Units in LSBs.

Integral Non-Linearity Error - INL

The deviation of a code from a straight line passing through the endpoints of the transfer

function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2

LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code

transition to all ones. The deviation is measured from the middle of each particular code. Units

in LSB’s.

Full-Scale Error - FSEP

The deviation of the last code transition from the ideal (VREF-3/2 LSB’s). Units in LSB’s.

Offset Error - VOS

The deviation of the mid-scale transition from the ideal (1/2 LSB below 0 Volts). Units in

LSB’s.

Spurious-Free-Dynamic-Range - SFDR

The ratio of the rms value of the full-scale signal, to the rms value of the next largest spectral

component (excepting dc). This component is often an aliased harmonic when the signal

frequency is a significant proportion of the sampling rate. Units in dBc (decibels relative to the

carrier).

Total Harmonic Distortion - THD

The ratio of the rms sum of the significant harmonics (2nd thru 7th), to the rms value of the

full-scale signal. Units in decibels.

Dynamic Range - DR

The ratio of the rms value of the inferred full-scale signal, to the rms sum of the broadband

noise signals below the Nyquist rate (excepting dc and distortion terms). Expressed in

decibels. Dynamic Range is tested with a 22 kHz input signal 60 dB below full scale. 60 dB

is then added to the resulting number to refer the noise level to the full-scale signal. This

technique ensures that the distortion components are below the noise level and do not affect the

measurement.

Signal-to-Noise-and-Distortion (s/[n+d]) - SINAD

The ratio of the rms value of the full-scale signal, to the rms sum of all other spectral

components below the Nyquist rate (excepting dc), including distortion components. Expressed

in decibels.

Group Delay

The time delay through the digital filter section of the part. Units in seconds.

CS5180

20 DS259PP3

Resolution - N

The number of different output codes possible. Expressed as N, where 2N is the number of

available output codes.

Noise -

A measure of the variability of the converter’s output when a fixed DC input (usually ground)

is applied to the input and a large number of samples are taken. RMS noise is determined

statistically as the Standard Deviation of the Probability Density Function derived from the

histogram of the ADC with the differential inputs shorted together and tied to an appropriate

common mode voltage.

Common Mode Rejection Ratio - CMRR

A measure of the device’s ability to cancel out the effect of a common voltage applied to both

of its differential inputs. CMRR is specified as the ratio of the differential signal gain to the

gain for the common-mode signal. Units in dB.

Offset Drift -

Changes in the offset error of the part after self calibration due to changes in ambient

temperature. Specified in microvolts per degree C, relative to the input signal.

Full Scale Drift -

Changes in the full scale error of the part after self calibration due to changes in ambient

temperature. Specified in parts-per-million (PPM) of the full scale range per degree C.

CS5180

DS259PP3 21

APPENDIX A: CIRCUIT APPLICATIONS

Several amplifie r circuits have been teste d with the

CS5180. Performance at higher frequencies is gen-

erally limited by the operational amplifiers used to

drive the A/D converter.

Figure 12 illustrates a single operational amplifier

circuit which can accept a single-ended ground-ref-

erenced signal and condition it for the input of the

CS5180. The amplifier is AC-coupled to the signal

source. In this circuit the AIN- input to the CS5180

is held at a constant DC value and the AIN+ input

is driven (it is actually overdriven to achieve high

dynamic range, but this sacrifices performance

with regard to distortion). The common mode volt-

age for the CS5180 input should be designed to

stay between 1 V and VREF + 0.25 V when driven

at its AIN+ and AIN- inputs. In Figure 12 the dc

voltage at the AIN- input is set so that when driven

with a 4 Vpp signal on the AIN+ pin, the common

mode voltage remains within the proper range.

Figures 13 and 14 illustrate the performance of the

amplifier of Figure 12 operating with a 4 Vpp input

into the AIN+ input; and with 2 Vpp input into the

AIN+ input respectively.

Figure 15 illustrates an AC-coupled two amplifier

circuit. This circuit gives be tter performance than

0.15

C0G

10 k

Ω

+15

-15

Ω

AIN-

VREFOUT

CS5180

10 k

Ω

2200 pF

Ω

2200 pF

5 k

Ω

10 µF

10 µF0.1 µF

1 k

Ω

AIN+

0.1 µF

Figure 12. Single amplifier driving only AIN+, AIN- held at steady dc value

Figure 13. Performance of amplifier of Figure 12 over-

drivi ng AIN+ input to the CS5180 at 4 VPP

Figure 14. Performance of amplifier of Figure 12 with

AIN+ driven at 2 VPP

CS5180

22 DS259PP3

the single amplifier ciruit of Figure 12 because the

inputs to the CS5180 are driven differentially. The

400 and 100 Ω output divider scales down the input

from the amplifier. The scaling should be opti-

mized for the application. Figure 16 illustrates the

performance of the converter when using this a m-

plifier circuit.

The amplifier of Figure 17 uses three amplifiers

and can accept a ground referenced signal or a fully

differential signal. Figure 18 illustrates its perfor-

mance when driven with 57.6 kHz signal.

Figure 19 illustrates a four amplifier circuit which

gives the best performance by keeping everything

balanced. Performa nce is genera lly limite d by the

amplifiers. Again, the output resistors are used to

scale down the input signal. Figures 20 and 21 il-

20 µF 2 k

Ω

10 k

Ω

+15

-15

2 k

Ω

2 k

Ω

2 k

Ω

2200 pF

100

Ω

2200 pF

400

Ω

400

Ω

AIN+

AIN-

VREFOUT

CS5180

0.1 µF 10 µF

0.1 µF

+15

0.1 µF

-15 0.1 µF

Figure 15. AC-coupled driver using two amplifiers.

Figure 16. Performance of amplifier in Figure 15

CS5180

DS259PP3 23

lustrate the performance of the CS5180 with this

amplifier circuit.

Figure 22 illustrates a Differential Non-linearity

plot of the converter. Data for the plot was taken

using a repeating ramp. Figure 23 is a histogram of

the DNL data in Figure 22.

Figure 24 illustrates a noise histogram of the con-

verter with its inputs shorted and connected to a

proper common mode voltage.

7.77 k

Ω

2200 pF

100

Ω

2200 pF

150

Ω

150

Ω

AIN+

AIN-

VREFOUT

CS5180

7.77 k

Ω

10 pF

1 M

Ω

+12 V

0.1 µF

10 k

Ω

-12 V

0.1 µF 0.1 µF 47 µF

10 k

Ω

+12 V 0.1 µF

-12 V

0.1 µF

20 pF

C0G

7.77 k

Ω

20 p F

C0G

7.77 k

Ω

20 pF

C0G

20 pF

C0G

10 µF

C0G

10 µF

C0G

+12 V

0.1 µF

-12 V

0.1 µF

XLR

Figure 17. Three amplifier driver

Figure 18. Performance of amplifier in Figure 17

CS5180

24 DS259PP3

+15 V

-15

2 k

Ω

2 k

Ω

2 k

Ω

2200 pF

100

Ω

2200 pF

301

Ω

301

Ω

AIN+

AIN-

VREFOUT

CS5180

10 k

Ω

10 k

Ω

10 µF

2 k

Ω

+15 V

-15 V

2 k

Ω

10 k

Ω

2 k

Ω

+15 V

-15 V

0.1 µF

0.1 µ F

+15 V

0.1 µF

-15 V

0.1 µF

Figure 19. Four amplifier driver.

Figure 20. Performance of amplifier in Figure 19

Figure 21. Performance of amplifier in Figure 19

CS5180

DS259PP3 25

Figure 22. CS5180 Differential Non-linearity plot.

(Data taken with repeating ramp) Figure 23. Histogram of DNL from Figure 22

105

10684 12085

192

42468

10000

20000

30000

40000

50000

-0.25 to

-0.15

-0.15 to

-0.05

-0.05 to

0.05

0.05 to

0.15

0.15 to

0.25

DNL (LSB) Range

Codes

Figure 24. CS5180 Noise Histogram, > 60,000 samples.

146 88

33885 31415

10000

20000

30000

40000

FFF6 FFF5 FFF4 FFF3

Code ( Hexad ecimal)

Count

1 LSB = 61 µV

STD = 0.507 LSB

Noise (rms) = 31 µV

CS5180

26 DS259PP3

PACKAGE OUTLINE DIMENSIONS

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.165 0.180 4.043 4.572

A1 0.090 0.120 2.205 3.048

B 0.013 0.021 0.319 0.533

D 0.485 0.495 11.883 12.573

D1 0.450 0.456 11.025 11.582

D2 0.390 0.430 9.555 10.922

E 0.485 0.495 11.883 12.573

E1 0.450 0.456 11.025 11.582

E2 0.390 0.430 9.555 10.922

e 0.040 0.060 0.980 1.524

JEDEC # : MS-018

28L PLCC PACKAGE DRAWING

E1 ED2/E2

CS5180

DS259PP3 27

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A --- 0.065 --- 1.60

A1 0.002 0.006 0.05 0.15

B 0.012 0.018 0.30 0.45

D 0.478 0.502 11.70 12.30

D1 0.404 0.412 9.90 10.10

E 0.478 0.502 11.70 12.30

E1 0.404 0.412 9.90 10.10

e* 0.029 0.037 0.70 0.90

L 0.018 0.030 0.45 0.75

∝0.000° 7.000° 0.00° 7.00°

* Nominal pin pitch is 0.80 mm

Controlling dimension is mm.

JEDEC Des ignati on: MS 026

44L TQFP PACKAGE DRAWING

∝