Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Enpirion EN2360QI DC-D C Converter
w/Integrated Inductor Evaluation Boar d
Introduction
Thank you for c hoosing Altera Enpirion pow er produc ts !
This evaluation board user guide applies to the EN2360 devices m ounted on PCB’s with
the part num ber 06978 r e v A, and three c om ponents on the bac ks ide. In addition to this
doc um ent, you will als o need the lates t devic e datas heet.
• The EN2360QI features integrated inductor, power MOSFETS, controller , a bulk
of the c om pens ation network, and protection circuitry against system faults. This
level of integration delivers a substantial reduction in footprint and parts count
over c om peting s olutions . The evaluation board is optimized for engineering ease
of testing through pr ogram m ing options , c lip leads , tes t points etc .
• The EN2360QI features a customer programmable output voltage by means of a
resistor divider. The res is tor divider allows the us er to s et the output voltage t o
any value w ithin the range 0.6V to 3.3V. The evaluation board, as shipped is
populated with a 4 resistor divider option. The upper res is tor is fixed and has a
phas e lead c apac itor in parallel. O ne of the 4 low er res is tor s is s elec ted w ith the
jum per option for different output voltages. To change VOUT, retain the upper
res is tor and c apac itor and c hange only the low er res is tor .
• The input and output c apac itors are X5R or X7R m ulti-layer ceramic chip
capacitors. The Soft-start capacitor is a small value X7R MLCC. Pads are
available to have m ultiple input and output capacitors. This allows for evaluation
of perform anc e over a w ide range of input/output c apac itor c om binations .
• Clip-on term inals are provided for ENA and POK. Banana jacks are provided for
12VIN, AVIN, and VOUT terminals. Several s ignal and GND c lip-on tes t points ar e
als o provided to m eas ur e VIN, VOUT, and GND nodes.
• The Enable pin is pre-wired with a resistor divider to PVIN and GND according to
the datas heet r ec om m endation. Enable m ay als o be c ontrolled by applying an
external signal to the ENA clip-on ter m inal.
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
• Foot print is also provided for a SMA connector to S_IN input. A s w itc hing input
to this pin allows the devic e clock to be phas e loc ked to an external s ignal. This
external c loc k s ync hroniz ation allow s for m oving any offending beat fr equenc y to
be m oved out-of-band. A s w ept frequenc y applied to this pin r es ults in s pread
spectrum operation and reduces the peaks in the nois e s pec trum of em itted EMI.
• A tw o pin header footprint is provided for the S_OUT pin. This s ignal c an be us ed
to s ync hroniz e another EN2360 to the s w itc hing frequenc y c om ing out of the
S_O UT pin.
• The board c om es with input dec oupling and PVIN (12VIN) reverse polarity
protec tion to guard the devic e agains t c om m on s etup m is haps . Pleas e note ther e
is no reverse polarity protection on A VIN input.
Quick Start Guide
STEP 1: This board has some additional components on the bac k s ide including a
resistor divider from PVIN to Enable to GND (indicated as NR1 & NR2 in the
schematic). As a result of these components, ther e is no need for a jum per on J3 (see
Figure 1), and the component FB1 ( to the left of AVIN tes t point TP28) s hould not be
populated. Pleas e c ontac t Altera Power Applic ations support if your board does not
have these c om ponents added on the bac k s ide, or if FB1 is still populated.
Fi gure 1: Enable header wi thout any jum pers
STEP 2: Connect the 12V nom inal P ower Supply to the input pow er c onnec tors , 12VIN
(J7) and GND (J11) as indic ated in Figure 4 and s et the s upply to the des ired voltage.
CAUTION: Be mindful of the polarity. Even though the evaluation board comes
with revers e polar ity pr otec tion diodes , it m ay not protec t the devic e under all
conditions.
STEP 3: Make sure the two-in header J1 is properly populated depending on how you
want to pow er AVIN. If you want to us e the devic e in a s ingle input s upply m ode, and
use the on-c hip AVINO pin, then populate J1 w ith a s horting jum per . If you w ant to
s upply your ow n external AVIN, then rem ove the jum per from J1, and connect a 3.3V
nom inal pow er s upply to the AVIN ( J9) and GND (J11).
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EN2360QI PowerSoC
CAUTION: With the r es is tor divider betw een PVIN and Enable and GND , if you
dec ide to s upply an external AVIN, then AVIN has to be turned on befor e PVIN,
and turned off after PVIN. Not follow ing this s equenc e c an dam age the devic e.
CAUTION: Be mindful of the AVIN input polarity. Ther e is no revers e polarity
protection on this input.
CAUTION: D o not apply an external AVIN to the devic e with the J1 jum per
populated. D oing s o w ill dam age the devic e.
STEP 4: C onnec t the load to the output c onnec tors VO UT ( J6) and GND ( J10), as
indicated in Figure 4.
STEP 5: Selec t the output voltage s etting jum per . Figure 2 shows what output voltages
are ac hieved by s elec ting eac h jum per pos ition. Note that depending on the toleranc e of
the res is tors populated on the board, eac h output voltage s etting m ay have a larger
toler anc e than jus t the VFB pin as s pec ified in the datas heet. Pleas e s ee Figur e 5 and
the Bill of Mater ials s ec tion.
Figure 2: Out put Voltage sel ec tion jum pers J5 . N omin a l jum p e r position volta g e s from left t o
right ar e: 3 . 31V, 1.8V , 1.2V and 1.0V. Jumper s hown s elect s 1.20V out put. D o not
change jum per posit io ns whi le t he boa rd is powered.
Pleas e note: The loop compensation circuit for this version of evaluation board
has be e n chosen for a w ide range of PVIN and VOUT values. In order to optimize
the loop for any specific PVIN/VOUT operating point, please see the com pensation
table in the datasheet. See Figures 4 and 5.
STEP 6: Apply AV IN first, and then 12VIN if us ing dual s upply m ode. For s ingle s upply
mode, just apply 12VIN. The EN2360QI is now powered up since there is a resistor
divider from PVIN to Enable. Var ious m eas urem ents s uc h as effic ienc y, line and load
regulation, input / output ripple, load transient, drop-out voltage measurements may be
conducted at this point. The over curr ent trip level, s hor t c irc uit pr otec tion, under voltage
loc k out thr es holds , tem peratur e c oeffic ient of the output voltage m ay als o be m eas ured
in this configuration.
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Alternatively, you c an control the E NA jum per with an external s our c e. For dual supply
m ode, you c an als o tie Enable to AVIN by rem oving NR1 from the bac k s ide, putting a
s hort ac r os s the FB1 footprint, and c onnec ting the m iddle point of J3 to the left pin us ing
a s horting jum per . Pleas e r eview the Pow er Up Sequence section in the datas heet
before experim enting w ith various turn on/off c om binations .
CAUTION: Please refer to the datasheet for the max imum voltages on the 12V
(PVIN ) and AVIN inputs, and maximum sle w rate s for the PVIN input.
STEP 6A: Power Up/Down Behavior – Connect a pulse generator (output disabled)
s ignal to the clip-on tes t point below ENA and Ground. S et the puls e am plitude to swing
from 0 to 2.5 volts . Set the puls e per iod to 10ms ec . and duty c yc le to 50%. Hook up
os c illos c ope probes to E NA, SS , POK and VO UT w ith c lean ground r eturns . Apply
power to evaluation boar d. Enable puls e gener ator output. O bs erve the SS c apac itor
and VOUT voltage ramps as ENA goes high and again as ENA goes low. The devic e
when powered down ramps down the output voltage in a c ont rolled m anner before fully
shutting down. The output voltage level when PO K is as s er ted /de-asserted as the
devic e is pow ered up / dow n m ay be obs erved as w ell as the c lean output voltage r am p
and POK signals.
STEP 7: External Clock Synchronization / Spread Spectrum Modes: In order to
ac tivate this m ode, it m ay be nec es s ar y to a s older a SMA c onnec tor at J4. Alter nately
the input c loc k s ignal leads m ay be direc tly s older ed to the through holes of J4 as
s hown below .
Figure 3: S MA Connector for Exte rna l Clock I nput
GND
Ext. Clock
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Power dow n the devic e. Move ENA into dis able pos ition. C onnec t the c loc k s ignal as
jus t indic ated. The c loc k s ignal s hould be c lean and have a fr equenc y r ange s pec ified in
the datas heet, and an am plitude 0 to 2.5 volts w ith a duty c yc le betw een 20 and 80%.
With S_IN s ignal dis abled, pow er up the devic e and m ove ENA jum per to E nabled
pos ition. The devic e is now powered up and outputting the des ired voltage. The devic e
is s w itc hing at its free running frequenc y. The s w itc hing w avefor m m ay be obs erved
between test points SW and GND. Now enabling the S_IN signal will automatically
phas e loc k the inter nal s witc hing frequenc y to the externally applied fr equenc y as long
as the external c loc k param eters are within the s pec ified r ange. To obs erve phas e-lock
c onnec t os c illos c ope pr obes to the input c loc k as well as to the SW tes t point. Phase
loc k range c an be determ ined by s w eeping the external c loc k fr equenc y up / dow n until
the devic e jus t goes out of loc k at the tw o extrem es of its range.
For s pread s pec trum operation the input c loc k frequenc y m ay be s wept betw een tw o
frequenc ies that ar e within the loc k range. The s w eep (jitter) repetition rate s hould be
limited to 10 kHz . The radiated EMI s pec trum m ay be now m eas ur ed in various states –
free running, phas e loc ked to a fixed fr equenc y and s pr ead s pec trum .
Before m eas ur ing radiated E MI, plac e a 10uF/0805, X7R c apac itor at the input and
output edges of the PC B (C8 and C9 positions), and c onnec t the PVIN pow er and the
load to the boar d at or near thes e c apac itors . The added c apac itor at the input edge is
for high-frequenc y dec oupling of the input c ables . The one added at the output edge is
m eant to repres ent a typic al load dec oupling c apac itor. We recommend doing E MI
tes ting in s ingle-s upply m ode only as this w ill s im plify the tes t s etup.
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Figure 5: EN2360 Evaluation Board Schematic (NR1-NR3 are additional components on the back side)
D1
S2A
C4
+C14
Rev ision Description Date Approved
R12
12VIN
TP27
J7 J6
J11
VFB
C1
FB1
C3
R13
C10
R14
C11
TP30
TP31
TP6
TP3
J1
1
2
SW
J10
0402
ENA
VOUT
SIN
SOUT
VOUT
0402
J4
AVINO
GND
5.5V MAX
0805
0805
0402
CJR
C3, 10, 11
are 1206/0805
TP9
1
2
AVIN
TP15
TP14
0805
Short across R9
when all other
routing completed
0805
C8
C9
R20
0402
TP32
C2
Provision for Implementing
Adaptive Voltage Scaling
0805
0805
R17
CGND
CGND
C6
0805
C12, 13, 15, 21
are 1206/0805
0805
0603
0805
R8
12VIN
R7
ENA
R3
R6
0805
0402
0402
VOUT GND
GND
SCH 06977 w mods
PCB 06978
C7
GND
0805
0805
0603
0805
AVIN
0805
0805
FADJ
AVINO
0805 0805
0805
AGND
C5
VIN
POK
C20
3/12/2012Preliminary Release
EAIN
VFB
VFB
TP5
R4
J9
Updated names for pins 53 & 60 and associated nets. 6/27/2012 AG
TP28
C16
R5
TP21
TP22
AVIN
C17
EAIN VFB
C19
R15
C12
R11
C13
C15
C21
R2
U1
EN2360
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
NC10
10
NC11
11
NC12
12
NC13
13
NC14
14
NC15
15
VOUT
16
VOUT
17
VOUT
18
VOUT
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
NC25
25
NC26
26
NC(SW)27
27
NC(SW)28
28
PGND
29
PGND
30
PGND
31
PGND
32
PGND
33
PGND
34
S_OUT 48
S_IN 47
BGND 46
VDDB 45
BTMP 44
PG 43
AVINO 42
PVIN 41
PVIN 40
PVIN 39
PVIN 38
PVIN 37
PVIN 36
PVIN 35
NC68 68
NC67 67
NC66 66
NC65 65
NC64 64
NC(SW)63 63
NC(SW)62 62
NC(SW)61 61
CGND 60
NC59 59
FADJ 58
RCLX 57
SS 56
EAIN 55
VFB 54
AGND 53
AGND 52
AVIN 51
ENABLE 50
POK 49
NR1
Thru-hole
NR2
0805
ENA
12VIN
TP2
TP19
1
2
TP20
1
2
R10
12VIN
VOUT
R1
TP10
TP8
TP7
TP33
J5
1
3
5
2
4
6
87
ENA
PIN_53
NR3
Thru-hole
PIN_53 R18
TP29
TP17
1
2
TP18
1
2
R9
R19
VR1
5.1V
TP11
R16
TP12
12VIN
J3
1
2
3
AVIN
TP4
TP1
AVIN
TP23
TP24
TP16
TP25
TP13
TP26
TP34
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Test Recommend atio ns
To guarantee m eas ur em ent ac c urac y, the follow ing prec autions s hould be obs er ved:
1. Make all input and output voltage m eas ur em ents at the board us ing the tes t
points pr ovided (TP 13 to TP16). This w ill elim inate voltage drop across the
line and load c ables that c an produc e fals e readings .
2. Meas ur e input and output c ur rent w ith s eries am m eters or ac c urate s hunt
res is tor s . This is es pec ially im portant w hen m eas uring effic ienc y.
3. Us e a low-loop-inductance scope probe tip similar to the one s how n below to
measure switching signals and input / output ripple to avoid nois e c oupling
into the probe ground lead. Input ripple, output ripple, and load trans ient
deviation are bes t m eas ur ed near the res pec tive input / output c apac itors . For
m ore ac c urate ripple m eas ur em ent, pleas e s ee Enpirion App Note regarding
this s ubjec t.
4. The board inc ludes a pull-up resistor for the POK signal and ready to monitor
the power OK status at c lip lead m ar ked PO K.
5. This produc t has built-in short-circuit protection. If protection against an
overload condition is required, an appropriate external solution needs to be
us ed. Pleas e r efer to the E npirion applic ation note for further details on this
subject.
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Bill of Materials
Designator
Qty
Description
C2
1
CAP, 47000PF 0805 X7R 10% 50V CERAMIC
C3
1
CAP CER 22UF 25V 10% X5R 1206
C5
1
CAP CER 0.22UF 16V X5R 0402
C6
1
CAP CER 47000PF 25V X7R 0402
C7
1
C AP, 1 8 PF 0805 NP0 5% 50V CERAMIC
C12
1
CAP CER 100UF 6.3V X5R 1206
C13, C15
2
CAP CER 47UF 10V X5R 1206
C14
1
CAP, SMT ELECT ROLYT IC , 150UF, 25V
C19
1
C AP, 0 .10UF 0402 X5R 10% 50V CERAMIC
C19, C20
2
CAP, 1.0UF 0402 X5R 10% 16V CERAMIC
C1, C4, C8 −C11,
C16−C18, C21,
FB1, J4, R2, R9,
R12−R15, R19,
TP3, VR1
21
NOT US ED
D1
1
S2A DI ODE, Micro Comm ercial S2A-TP
J1 1
CONNECT OR HEADER, 2 POSIT ION,
Samtec TSW-102-07-T-S
J3 1
CONNECT OR HEADER, 3 POSIT ION,
Samtec TSW-103-07-T-S
J5 1
CONNECT OR HEADER, 8 POSIT ION Dual,
Samtec TSW-104-24-T-D
J6, J7 , J9 -J11
5
BAN AN A JAC K, KE YSTON E 5 7 5 -4
R1
1
RES 100K OHM 1/16W 1% 0402 SMD
R3, R7
2
R ES 2 0 0K OHM 1/8W 0.1% 0805 SM D
R4
1
R ES ZER O OHM 1/8W 5% 0805 SM D
R5
1
RES 44.2K OHM 1/8W 1% 0805 SM D
R6
1
RES 301K OHM 1/8W 0.1% 0805 SMD
R8
1
RES 100K OHM 1/8W 0.1% 0805 SMD
R10
1
RES 3.01K OHM 1/8W 1% 0805 SM D
R11
1
RES 56.2K OHM 1/8W 1% 0805 SM D
R16
1
RES 36.5K OHM 1/8W 1% 0805 SM D
R17, R18
1
RES Z ERO OHM 1/10W 5% 0402 SMD
TP1, TP4, TP1 3-
TP 16, TP 21,TP22,
TP28,TP32
10
TEST POIN T SU R F AC E MO U N T, KEY STO N E 5 0 1 6
TP 30, TP 31
2
TEST POIN T SU R F AC E MO U N T, KEY STO N E 5 0 1 5
U1
1
EN2360QI QFN 6A
NR1
1
RES 10.0K OHM 1/4W 1% AXI AL
NR2
1
RES 4.02KOHM 1/4W1% 0805 SM D
NR3
1
RES 562 OHM 1/4W 1 % AXIAL
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Enpirion® Power Evaluation Board User Guide
EN2360QI PowerSoC
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, CA 95134
Phone: 408-544-7000
www.altera.com
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Patent and Tr ade ma r k Of fice and in other countr ie s. All other w or ds and logos identi fi e d as tr ademar ks or ser v ice mar ks ar e the
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semiconductor pr oducts to c ur r ent specificat io ns in accor dan c e with Al ter a ' s standar d w ar r anty , but r eser v es the r ight to make
changes to any pr oducts and ser v ices at any time w ithou t noti c e . Alter a assumes no r esponsibility or liab il i ty ar ising out of the
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customer s ar e advised to obtain the latest v er sion of device specifi catio ns befor e r elyi ng on any pub li shed infor mat io n and bef o r e
placing or de r s for pr oduc ts or ser vices.
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