© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 6 1Publication Order Number:
MC74VHC595/D
MC74VHC595
8-Bit Shift Register with
Output Storage Register
(3-State)
The MC74VHC595 is an advanced high speed 8−bit shift register
with an output storage register fabricated with silicon gate CMOS
technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHC595 contains an 8−bit static shift register which
feeds an 8−bit storage register.
Shift operation is accomplished on the positive going transition of
the Shift Clock input (SCK). The output register is loaded with the
contents of the shift register on the positive going transition of the
Register Clock input (RCK). Since the RCK and SCK signals are
independent, parallel outputs can be held stable during the shift
operation. And, since the parallel outputs are 3−state, the VHC595 can
be directly connected to an 8−bit bus. This register can be used in
serial−to−parallel conversion, data receivers, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
Features
•High Speed: fmax = 185 MHz (Typ) at VCC = 5 V
•Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
•High Noise Immunity: VNIH = VNIL = 28% VCC
•Power Down Protection Provided on Inputs
•Balanced Propagation Delays
•Designed for 2 V to 5.5 V Operating Range
•Low Noise: VOLP = 1.0 V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Latchup Performance Exceeds 300 mA
•ESD Performance: HBM > 2000 V; Machine Model > 200 V
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
Device Package Shipping†
ORDERING INFORMATION
MC74VHC595DR2G SOIC−16
(Pb−Free) 2500 Tape &
Reel
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
MARKING DIAGRAMS
18
9
16
18
16 9
VHC595G
AWLYWW
A = Assembly Location
WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G= Pb−Free Package
VHC
595
ALYWG
G
MC74VHC595DTR2G,
NLV74VHC595DTR2G TSSOP−16
(Pb−Free) 2500 Tape &
Reel
www.onsemi.com
(Note: Microdot may be in either location)
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
RCK
OE
SI
QA
VCC
SQH
SCLR
SCK
QE
QD
QC
QB
GND
QH
QG
QF
PIN ASSIGNMENT
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
MC74VHC595
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4
FUNCTION TABLE
Operation
Inputs Resulting Function
Reset
(SCLR)
Serial
Input
(SI)
Shift
Clock
(SCK)
Reg
Clock
(RCK)
Output
Enable
(OE)
Shift
Register
Contents
Storage
Register
Contents
Serial
Output
(SQH)
Parallel
Outputs
(QA − QH)
Clear shift register L X X L, H, ↓L L U L U
Shift data into shift
register H D ↑L, H, ↓L D→SRA;
SRN→SRN+1 U SRG→SRHU
Registers remains
unchanged H X L, H, ↓X L U ** U **
Transfer shift register
contents to storage
register
H X L, H, ↓ ↑ L U SRN³STRN* SRN
Storage register remains
unchanged X X X L, H, ↓L * U * U
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high
impedance state X X X X H * ** * Z
SR = shift register contents D = data (L, H) logic level ↓ = High−to−Low * = depends on Reset and Shift Clock inputs
STR = storage register contents U = remains unchanged ↑ = Low−to−High ** = depends on Register Clock input
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage – 0.5 to + 7.0 V
Vin DC Input Voltage – 0.5 to + 7.0 V
Vout DC Output Voltage – 0.5 to VCC + 0.5 V
IIK Input Diode Current − 20 mA
IOK Output Diode Current ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, SOIC Packages†
TSSOP Package† 500
450 mW
Tstg Storage Temperature – 65 to + 150 _C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
Vin DC Input Voltage 0 5.5 V
Vout DC Output Voltage 0 VCC V
TAOperating Temperature, All Package Types − 55 + 125 _C
tr, tfInput Rise and Fall Time VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V 0
0100
20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHC595
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5
The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
TJ= 80 C°
TJ= 90 C°
TJ= 100 C°
TJ= 110 C°
TJ= 130 C°
TJ= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 1. Failure Rate vs. Time
Junction Temperature
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions VCC
(V)
TA = 25°C TA = ≤ 85°C TA = ≤ 125°C
Uni
t
Min Typ Max Min Max Min Max
VIH Minimum High−Level
Input Voltage 2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
VIL Maximum Low−Level
Input Voltage 2.0
3.0
4.5
5.5
0.59
0.9
1.35
1.65
0.59
0.9
1.35
1.65
0.59
0.9
1.35
1.65
V
VOH Minimum High−Leve
l
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = − 50 μA2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA 3.0
4.5 2.58
3.94 2.48
3.80 2.34
3.66
VOL Maximum Low−Leve
l
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOL = 50 μA2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA 3.0
4.5 0.36
0.36 0.44
0.44 0.52
0.52
IIN Maximum Input
Leakage Current VIN = 5.5 V or GND 0 to
5.5 ±0.1 ±1.0 ±1.0 μA
ICC Maximum Quiescent
Supply Current VIN = VCC or GND 5.5 4.0 40.0 40.0 μA
IOZ Three−State Output
Off−State Current VIN = VIH or VIL
VOUT = VCC or
GND
5.5 ±0.25 ±2.5 ±2.5 μA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
MC74VHC595
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6
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbo
l
Parameter Test Conditions
TA = 25°C TA = ≤ 85°C TA = ≤ 125°C
Uni
t
Min Typ Max Min Max Min Max
fmax Maximum Clock
Frequency (50%
Duty Cycle)
VCC = 3.3 ± 0.3 V 80 150 70 70 MHz
VCC = 5.0 ± 0.5 V 135 185 115 115
tPLH,
tPHL Propagation
Delay, SCK to
SQH
VCC = 3.3 ± 0.3 V CL = 15pF
CL = 50pF 8.8
11.3 13.0
16.5 1.0
1.0 15.0
18.5 1.0
1.0 15.0
18.5 ns
VCC = 5.0 ± 0.5 V CL = 15pF
CL = 50pF 6.2
7.7 8.2
10.2 1.0
1.0 9.4
11.4 1.0
1.0 9.4
11.4
tPHL Propagation
Delay,
CPLR to SQH
VCC = 3.3 ± 0.3 V CL = 15pF
CL = 50pF 8.4
10.9 12.8
16.3 1.0
1.0 13.7
17.2 1.0
1.0 13.7
17.2 ns
VCC = 5.0 ± 0.5 V CL = 15pF
CL = 50pF 5.9
7.4 8.0
10.0 1.0
1.0 9.1
11.1 1.0
1.0 9.1
11.1
tPLH,
tPHL Propagation
Delay, RCK to
QA−QH
VCC = 3.3 ± 0.3 V CL = 15pF
CL = 50pF 7.7
10.2 11.9
15.4 1.0
1.0 13.5
17.0 1.0
1.0 13.5
17.0 ns
VCC = 5.0 ± 0.5 V CL = 15pF
CL = 50pF 5.4
6.9 7..4
9.4 1.0
1.0 8.5
10.5 1.0
1.0 8.5
10.5
tPZL,
tPZH Output Enable
Time,
OE to QA−QH
VCC = 3.3 ± 0.3 V CL = 15pF
RL = 1 kWCL = 50pF 7.5
9.0 11.5
15.0 1.0
1.0 13.5
17.0 1.0
1.0 13.5
17.0 ns
VCC = 5.0 ± 0.5 V CL = 15pF
RL = 1 kWCL = 50pF 4.8
8.3 8.6
10.6 1.0
1.0 10.0
12.0 1.0
1.0 10.0
12.0
tPLZ,
tPHZ Output Disable
Time,
OE to QA−QH
VCC = 3.3 ± 0.3 V CL = 50pF
RL = 1 kW
12.1 15.7 1.0 16.2 1.0 16.2 ns
VCC = 5.0 ± 0.5 V CL = 50pF
RL = 1 kW
7.6 10.3 1.0 11.0 1.0 11.0
CIN Input Capacitance 4 10 10 10 pF
COUT Three−State
Output
Capacitance
(Output in
High−Impedance
State), QA−QH
6 10 10 pF
CPD Power Dissipation Capacitance (Note 1)
Typical @ 25°C, VCC = 5.0V
pF
87
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
Symbo
l
Characteristic
TA = 25°C
Uni
t
Typ Max
VOLP Quiet Output Maximum Dynamic VOL 0.8 1.0 V
VOLV Quiet Output Minimum Dynamic VOL − 0.8 − 1.0 V
VIHD Minimum High Level Dynamic Input Voltage 3.5 V
VILD Maximum Low Level Dynamic Input Voltage 1.5 V
MC74VHC595
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7
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbo
l
Parameter VCC
V
TA = 25_CTA = − 40 to
85°CTA = − 55 to
125°C
Unit
Typ Limit Limit Limit
tsu Setup Time, SI to SCK 3.3
5.0 3.5
3.0 3.5
3.0 3.5
3.0 ns
tsu(H) Setup Time, SCK to RCK 3.3
5.0 8.0
5.0 8.5
5.0 8.5
5.0 ns
tsu(L) Setup Time, SCLR to RCK 3.3
5.0 8.0
5.0 9.0
5.0 9.0
5.0 ns
thHold Time, SI to SCK 3.3
5.0 1.5
2.0 1.5
2.0 1.5
2.0 ns
th(L) Hold Time, SCLR to RCK 3.3
5.0 0
00
01.0
1.0 ns
trec Recovery Time, SCLR to SCK 3.3
5.0 3.0
2.5 3.0
2.5 3.0
2.5 ns
twPulse Width, SCK or RCK 3.3
5.0 5.0
5.0 5.0
5.0 5.0
5.0 ns
tw(L) Pulse Width, SCLR 3.3
5.0 5.0
5.0 5.0
5.0 5.0
5.0 ns
MC74VHC595
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8
SCK
SQH
VCC
GND
50%
50% VCC
tPLH tPHL
tw
1/fmax
SCLR
SQH
SCK
tw
50%
50% VCC
50%
VCC
GND
VCC
GND
tPHL
trec
Figure 2. Figure 3.
SWITCHING WAVEFORMS
RCK
QA-QH
50%
tPLH tPHL
VCC
GND
Figure 4. Figure 5.
QA-QH
QA-QH
50%
50% VCC
tPZL tPLZ
tPZH tPHZ
VCC
GND
HIGH
IMPEDANC
E
VOL +0.3V
VOH -0.3V
HIGH
IMPEDANC
E
OE
50% VCC
SI 50%
50%
SCK or RCK
VCC
GND
VALID
tsu th
Figure 6.
tsu(H)
50%
50%
VC
C
GN
D
VC
C
GN
D
SCK
RCK
VCC
GND tw
Figure 7.
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kΩ
Figure 8. Figure 9.
50% VCC
SCLR 50%
VCC
GND
MC74VHC595
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PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
ÇÇÇ
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74VHC595
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11
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC74VHC595/D
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