081642 DALLAS SEMICONDUCTOR FEATURES Form, fit, and function compatible with the MK48T02 Timekeeping RAM Integrated NV SRAM, real time clock, crystal, power fail control circuit and lithium energy source Standard JEDEC bytewide 2K x 8 static RAM pinout Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations. Totally nonvolatile with over 10 years of operation in the absence of power Access times of 120 ns and 150 ns Quartz accuracy 1 minute a month @ 25C, factory calibrated * BCD coded year, month, date, day, hours, minutes, and seconds Power fail write protection allows for +10% Vcc power supply tolerance DESCRIPTION The DS1642 is an 2K x 8 nonvolatile static RAM with a full function real time clock which are both accessible in a bytewide format. The nonvolatile time keeping RAM is pin and function equivalent to any JEDEC standard 2Kx 8 SRAM. The device can also be easily substituted in ROM, EPROM and EEPROM sockets providing read/ write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and se- conds data in 24 hour BCD format. Corrections for the DS1642 Nonvolatile Timekeeping RAM PIN ASSIGNMENT A7[] 1 240 Vcc As] 2 23 7] As A5T] 3 22 1] as A4[] 4 211) WE As] 5 20 [] OF A2[] 6 19 [] Ato AIT] 7 18] CE AOC] 8 17 +bez Dao [] 9 16 [] pas pai] to 18 [] DOs pe2T] 11 147) Dae GND [] 12 13 ~baa PIN DESCRIPTION A0-A10 - Address Input CE - Chip Enable OE - Output Enable WE - Write Enable Voc - +5 Volts GND - Ground DQ0-DQ7 - Data Input/Output day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock up- date cycles. The double buffered system also prevents time loss as the timekeeping countdown continues un- abated by access to time register data. The DS1642 also contains its own power fail circuitry which deselects the device when the Vcc supply is in an out of tolerance condition. This feature prevents loss of data from un- predictable system operation brought on by low Voc as errant access and update cycles are avoided. 090895 1/10 528 oO 1995 by Dallas Semiconductor Corporation. fonts and Other ntokecioa tigen please vetor pa Dales Somloondustr deta Docks,CLOCK OPERATIONS-READING THE CLOCK While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the seventh most significant bit in the control register. As long as a 1 remains in that position, updating is halted. After a halt DS1642 BLOCK DIAGRAM Figure 1 081642 is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock reg- isters of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1642 registers are updated simul- taneously after the clock status is reset. Updating is within a second after the read bit is written to zero. s27eef_]] oS NIBORN KO neaistens =| CHAIN 7 La CE | WE 2KXBNVSRAM [* 1, OF POWER MONITOR, POWER GOOD Kaa +{ SWITCHING, AND WRITE PROTECTION Voc DS1642 TRUTH TABLE Table 1 Veo ce | OF | WE MODE Da POWER Vin Xx x DESELECT HIGH Z STANDBY Vit x Vi WRITE DATA IN ACTIVE 5 VOLTS + 10% Vi | Va | Vi READ DATA OUT ACTIVE Vi | Via | Vag READ HIGH Z ACTIVE <4.5 VOLTS x x x DESELECT HIGH Z CMOS STANDBY >VBaT <Veat Xx Xx x DESELECT HIGH Z DATA RETENTION MODE 090895 2/10 529081642 SETTING THE CLOCK The eighth bit of the control register is the write bit. Set- ting the write bit to a 1, like the read bit, halts updates to the DS1642 registers. The user can then load them with the correct day, date and time data in 24 hour BCD for- mat. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. Note that both the read bit and write bit perform similar functions and setting both bits during the same access cycle will prevent the clock reg- isters from updating. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To in- crease the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Settingittoa 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is 0S1642 REGISTER MAP - BANK1 Table 2 running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQG line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, and OE low) and address for seconds register remain valid and stable. CLOCK ACCURACY The DS1642 is guaranteed to keep time accuracy to within +1 minute per month at 25C. The clock is cali- brated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS 1642 does not require additional calibration and tem- perature deviations will have a negligible effect in most applications. For this reason, methods of field clock cal- ibration are not available and not necessary. Attempts to calibrate the clock that may be used with similar de- vice types (MK48T02 family) will not have any effect even though the DS1642 appears to accept calibration data. DATA ADDRESS FUNCTION B, Be B; B, B, B, By By 7FF . - - - - - - - YEAR _ 00-99 7FE x x x - - - - - MONTH 01-12 7FD x x - - - - - - DATE _01-31 7FC x FT x x x - . - DAY 01-07 7FB x x - - - - - - HOUR 00-23 7FA x - - - - - . . MINUTES 00-59 7F9 St - - . - . . - | SECONDS 00-59 7F8 Ww R - - - - - - | CONTROL A OSC = STOP BIT R = READBIT FT = FREQUENCY TEST W = WRITEBIT X = UNUSED NOTES: X bits are unused but must be set to zero during write cycle to insure proper clock operation. Bits 0 through 5 of control register A are not dedicated to any particular function and can be used as normal RAM bits. 090895 3/10 530DS1642 RETRIEVING DATA FROM RAM OR CLOCK The DS1642 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within ta, after the last address input is stable, providing that the CE and OE access times are satisfied. If CE or GE access times are not met, valid data will be available at the latter of chip en- able access (tcea) or at output enable access time (toga). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before taa, the data lines are driven to an intermediate state until tag. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (to}4) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK | __ The DS 1642 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE. The ad- dresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of twr prior to the initiation of another read or write cycle. Data in must be valid tps prior to the end of write and remain valid for ton afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then dis- able the outputs twez after WE goes active. DATA RETENTION MODE When Vcc; is within nominal limits (Vcc > 4.5 volts) the DS1642 can be accessed as described above by read or write cycles. However, when Vcc is below the power fail point Vpr (point at which write protection occurs) the internal clock registers and RAM is blocked from ac- cess. This is accomplished internally by inhibiting ac- cess via the CE signal. When Vcc falls below the ievel of the internal battery supply, power input is switched from the Vcc pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until Voc is returned to nominal level. INTERNAL BATTERY LONGEVITY The DS1642 has a self contained lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the Vcc; supply is not present. The capability of this internal power supply is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For specifi- cation purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of Voc power. The DS1642 is shipped from Dallas Semiconductor with the clock oscillator turned off, so the expected life should be considered to start from the time the clock oscillator is first turned on. Actual life ex- pectancy of the DS1642 will be much longer than 10 years since no internal lithium battery energy is con- sumed when Vcc is present. In fact, in most applica- tions, the life expectancy of the DS 1642 will be approxi- mately equal to the shelf life (expected useful life of the lithium battery with no load attached) of the lithium bat- tery which may prove to be as long as 20 years. $31 090895 4/10081642 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0C to 70C Storage Temperature -20C to +70C Soldering Temperature 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage Vec 45 5.0 5.5 Vv 1 Logic 1 Voltage All Inputs Vin 2.2 Vect0.3 Vv Logic 0 Voltage All Inputs Vit -0.3 0.8 Vv DC ELECTRICAL CHARACTERISTICS (OC <ta S$ 70C; Voc (MAX) S Vee S Voc (MIN)) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Average Vcc Power Supply lect 30 50 mA 2,3 Current TTL Standby Current (CE = Vin) lece 3 6 mA 2,3 CMOS Standby Current loca 2 4.0 mA 2,3 (CE=Vcc-0.2V) Input Leakage Current (any input) Iie -1 +1 pA Output Leakage Current lot -1 +1 pA Output Logic 1 Voltage Von 2.4 Vv (lout = -1.0 mA) Output Logic 0 Voltage VoL 0.4 v (lout = +2.1 mA) Write Protection Voltage Vip 4.0 4.25 45 Vv 090895 5/10 532081642 AC ELECTRICAL CHARACTERISTICS (0C to 70C; Voc = 5.0V + 10%) DS1642-12 DS1642-15 PARAMETER SYMBOL | MIN MAX MIN MAX UNITS | NOTES Read Cycle Time tac 120 150 ns Address Access Time taa 120 150 ns CE Access Time tcea 120 150 ns CE Data Off Time tcez 40 50 ns Output Enabie Access Time toEA 100 120 ns Output Enable Data Off Time toez 40 50 ns Output Enable to DQ Low-Z toEL 5 5 ns CE to DQ Low-Z tceL 5 5 ns Output Hold from Address ton 5 5 ns Write Cycle Time twe 120 150 ns Address Setup Time tas 0 0 ns CE Pulse Width tcew 100 120 ns Address Hold from End of Write tax 15 20 ns Write Pulse Width twew 120 150 ns WE Data Off Time twez 40 50 ns WE or CE Inactive Time twr 10 15 ns Data Setup Time tos 85 110 ns Data Hoid Time High too 15 20 ns AC TEST CONDITIONS Input Levels: OV to 3V Transition Times: 5ns CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Capacitance on all pins Cc 7 pF (except DQ) Capacitance on DQ pins Cpa 10 pF 533 090895 6/10DS1642 AC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TIMING) (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at Vi}, before Power tpp 0 Us Down Vpr (Max) to Veg (Min) Vcc Falt te 300 HS Time Ver (Min) to Vso Vcc Fall Time trp 10 ys Vso to Vpg (Min) Vcc Rise Time tre 1 ps Vopr (Min) to Vpr (Max) Vcc Rise tR 0 ps Time Power Up trec 15 25 35 ms Expected Data Retention Time tor 10 years 4 (Oscillator On) DS1642 READ CYCLE TIMING READ READ WRITE _. tag. > _ tac _| v AO-A10 x K taa > _ tay ~ ft tas icEA >| CE tceL > OE UY toEA > twr _ Y }+ twew r WE toe. N | ton * toez 0Q0-DQ7 r 4 rm Kd VALID OUT | i VALID OUT, VALID IN 090895 7/10 5340S1642 DS1642 WRITE CYCLE TIMING WRITE -_ two _ WRITE jp . two _ REA\ DB AQ-A10 i twa tag iy r wl ic 7 e ft tan cE / tcew " V \ [* toca OE / twr a twew > | WE r tbH tcez > toy tos twez tos 7y y 7 DQ0- VALID VALI }___{ VALID | VALI Dao ALIDIN L LID IN p}_+ DOUT POWER DOWN/POWER UP TIMING Voc Veg (MAX) r =Vpr (MIN) VpF te \ th - Vso Vso F- 6B \ / jg 188 7 A tep j<| wn trec / 7 Ff ce \ 4 / eo 7 / IBaTT / DATA RETENTION bq pr 535 090895 8/100S1642 NOTES: 1. All voltages are referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Data retention time is at 25C and is calculated from the date code on the device packag. The date code XXYY is the year followed by the week of the year in which the device was manufactured. For example, 9225, would mean the 25th week of 1992. OUTPUT LOAD +5 VOLTS 1.8KQ D.U.T. 1KQ 100 pF 090895 9/10 536DS1642 DS1642 24-PIN PACKAGE . PKG 24-PIN DiM MIN MAX A IN. 1.270 1.290 MM 37,34 37.85 e i 8 IN. | o675 | 0.700 : wm | 17.45 | 17.78 1 leg A o c IN. | 0315 | 0.335 | | MM | 8.00 ast DIN. | 0.075 | 0.105 mM [1.91 2.67 E IN| 0.015 | 0.030 r mm | o38 | 076 c F IN| o140 | 0.180 mm | 3.56 457 TV VUEQUEIUIUY sm | og | au ~ Ly D wll K ela be H_ IN. | 0.590 | 0.630 MM 14.99 16.00 JIN. 0.010 0,018 MM 0.25 0,45 KIN. 0.015 0.025 MM 0.43 0.58 090895 10/10 537