S1C88409D - Seiko Epson Corporation

1

PF952-02

S1C88409

8-bit Single Chip Microcomputer

■DESCRIPTION

The S1C88409 is a single chip microcomputer which consists of a CMOS 8-bit core CPU S1C88 (MODEL3),

8KB ROM, 3.75KB RAM, dot-matrix LCD controller, 3 types of timers/counters, serial interface (IR input/output

function is available), touch panel controller, A/D converter and D/A converter. The S1C88409 operates faster

even with low supply voltage, and is most suitable for various application equipment such as information termi-

nals needing low power operation. Fu r th e r mo r e, th e S1C88409 can control up to 4M × 3 bytes of memory with the

22-bit outside address bus and 3-bit chip enable signals, therefore it can also be applied to systems such as

electronic dictionaries and organizers.

■FEATURES

● Core CPU..............................................CMOS 8-bit core CPU S1C88 (MODEL3)

● OSC1 oscillation circuit.........................Crystal oscillation circuit/CR oscillation circuit/external clock input

32.768 kHz (Typ.)

● OSC3 oscillation circuit.........................Crystal oscillation circuit/ceramic oscillation circuit/CR oscillation

circuit/external clock input 8 MHz (Max.)

● Instruction set........................................Basic instruction: 54 types, Total: 608 types (multiplication/division

instructions are usable)

Addressing mode: 12 types

● Min. instruction execution time .............0.25 µsec/8 MHz (2 clocks)

● Internal ROM capacity ..........................8K bytes

● Internal RAM capacity...........................3.75K bytes (display memory is included; data/display memory

size can be set by mask option)

● Bus line .................................................Address bus: 22 bits

Data bus: 8 bits

CE signal: 3 bits

WR signal: 1 bit

RD signal: 1 bit

● Input port...............................................12 bits

• 2 bits are usable for event counter input

● Output port ............................................30 bits

• They are used as address bus and bus control signals when

external bus is set

• Usable for clock output and buzzer output

● I/O port ..................................................28 bits

• 8 bits are used as data bus when external bus is set

• Usable for serial interface input/output, A/D converter input, D/A

converter output and touch panel output

● Serial interface ......................................1 channel

• Clock synchronous mode/asynchronous mode selectable

• Usable as IrDA interface

Low Voltage

Operation

Products

(usable as general output port or I/O port

when it is not used as a bus signal)

● Original Architecture Core CPU

● Low Current Consumption

● Wide-range Operating Voltage (1.8V to 5.5V)

● High Speed Operation in Low Voltage

● A/D Converter

2

S1C88409

● 16-bit programmable timer....................1 channel

• Usable for 16 bits × 1 channel or 8 bits × 2 channels

• Usable as event counter

● 8-bit programmable timer......................1 channel

• Usable as baud rate generator for serial interface

● Clock timer ............................................1 channel

• Generating 1 sec signal with 32 kHz oscillation

• 60S counter available

● LCD controller .......................................Dot-matrix type

• B&W or 4 gray scale display

• A 240 × 100 dot LCD panel can be driven with external drivers

(S1D16305 or S1D16700, S1D16006 or S1D15700)

• Scroll function available

● Touch panel controller ..........................Supports pressure sensitive and resistive membrane type analog

touch panels

● A/D converter ........................................Resolution 10 bits (input: 8 channels)

● D/A converter ........................................Resolution 8 bits (output: 2 channels)

● Sound generator ...................................Equipped with envelope and volume control functions

● Supply voltage detection (SVD)............Possible to detect 3 voltage levels

● Watchdog timer.....................................Possible to generate NMI

● Interrupt.................................................External: Input interrupt 2 systems (5 types)

Internal: 16-bit programmable timer interrupt 2 systems (4 types)

8-bit programmable timer interrupt 1 system (1 type)

Clock timer interrupt 1 system (5 types)

Watchdog timer interrupt 1 system (1 type)

Serial interface interrupt 1 system (3 types)

LCD controller interrupt 1 system (1 type)

Touch panel interrupt 1 system (2 types)

A/D converter interrupt 1 system (1 type)

● Supply voltage ......................................1.8 V to 5.5 V (operating frequency Max. 1.1 MHz)

2.6 V to 5.5 V (operating frequency Max. 4.4 MHz)

3.5 V to 5.5 V (operating frequency Max. 6.6 MHz)

4.5 V to 5.5 V (operating frequency Max. 8.8 MHz)

● Current consumption ............................SLEEP 0.6 µA Typ. (at 3.0 V) (Normal mode)

HALT (32 KHz) 3.0 µA Typ. (at 3.0 V) (Normal mode)

Run (32 KHz) 15 µA Typ. (at 3.0 V) (Normal mode)

Run (4 MHz) 2 mA Typ. (at 3.0 V) (Normal mode)

Run (8 MHz) 9 mA Typ. (at 5.0 V) (High speed mode)

● Supply form...........................................QFP15-100pin or chip

S1C88409

3

■BLOCK DIAGRAM

Core CPU S1C88

Oscillator

OSC1, OSC3

OSC2, OSC4

(FOUT3)

(FOUT1)

VD1

MCU/MPU

RESET

TEST

(TOUT0)

(TOUT1)

(BZ)

(BYH, BYL)

(BXH, BXL)

Prescaler

Voltage Regulator

System Controller

Reset/Test

Touch Panel Controller

16-bit Programmable

Timer

8-bit Programmable

Timer

Clock Timer

Watchdog Timer

Sound Generator

RAM 3.75K-byte

(Data RAM, Display RAM)

Interrupt Controller

VDD

VSS

(SIN/IRI, SOUT/IRO)

(SCLK, SRDY)

LCDEN, DOFF

XSCL, LP, YD, FR

SD0–SD7

(A0–A21)

(D0–D7)

(RD, WR, CE0–CE2)

K00–K07

K10–K13

R00–R07

R10–R17

R20–R27

R30–R32

R40–R42

P00–P07

P10–P17

P20–P23

P30–P37

(AD0–AD7)

AVDD

AGND

AVSS

AVREF

(DA0, DA1)

Serial Interface

(Synchronous/Asynchronous/IrDA)

LCD Controller

Supply Voltage Detector

External Memory

Interface

Input Port

Output Port

I/O Port

A/D Converter

D/A Converter

ROM 8K-byte

∗ The terminals that are shown in ( ) are shared with Pxx or Rxx terminals.

4

S1C88409

■PIN CONFIGURATION

• Pin layout for single chip mode (initial setting)

INDEX

S1C88409

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

(TOUT1/FOUT1) R41

(BZ) R42

(SIN) P10

(SOUT) P11

(SCLK) P12

(SRDY) P13

(SIN/IRI) P14

(SOUT/IRO) P15

(SCLK) P16

(SRDY) P17

(BYH) P20

(BYL) P21

(BXH) P22

(BXL) P23

TEST

(AD7/DA1) P37

(AD6/DA0) P36

(AD5) P35

(AD4) P34

(AD3) P33

(AD2) P32

(AD1) P31

(AD0) P30

AV

DD

AV

SS

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

V

SS

OSC1

OSC2

V

D1

OSC3

OSC4

V

DD

LCDEN

DOFF

YD

FR

XSCL

LP

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

N.C.

AGND

AV

REF

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

R02

R01

R00

P07

P06

P05

P04

P03

P02

P01

P00

RESET

K13

K12

K11 (EXCL11)

K10 (EXCL00)

K07

K06

K05

K04

K03

K02

K01

K00

MCU/MPU

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

R03

R04

R05

R06

R07

R10

R11

R12

R13

R14

R15

R16

R17

R20

R21

R22

R23

R24

R25

R26

R27

R30

R31

R32

(TOUT0/FOUT3) R40

S1C88409

5

Pin name

V

DD

V

SS

V

D1

AV

DD

AGND

AV

SS

AV

REF

OSC1

OSC2

OSC3

OSC4

MCU/MPU

K00~K07

K10 (EXCL00)

K11 (EXCL01)

K12~K13

R00~R07

R10~R17

R20~R27

R30~R32

R40 (TOUT0/FOUT3)

R41 (TOUT1/FOUT1)

R42 (BZ)

P00~P07

P10 (SIN)

P11 (SOUT)

P12 (SCLK)

P13 (SRDY)

P14 (SIN/IRI)

P15 (SOUT/IRO)

P16 (SCLK)

P17 (SRDY)

P20 (BYH)

P21 (BYL)

P22 (BXH)

P23 (BXL)

P30~P35 (AD0~AD5)

P36, P37

(AD6/DA0, AD7/DA1)

LCDEN

DOFF

YD

FR

XSCL

LP

SD0~SD7

RESET

TEST

Function

Power supply (+) pin

Power supply (GND) pin

Voltage regulator output pin

Power supply (+) pin for analog circuit system

GND pin for analog circuit system

Power supply (GND) pin for analog circuit system

Reference voltage input pin for analog circuit system

OSC1 oscillation input pin

(32 kHz crystal, CR oscillation, external clock input)

OSC1 oscillation output pin

OSC3 oscillation input pin

(crystal/ceramic, CR oscillation, external clock input)

OSC3 oscillation output pin

MCU/MPU mode setting pin

*

1

Input port pin

Input port pin or external clock input pin for event counter (Timer 0)

Input port pin or external clock input pin for event counter (Timer 1)

Input port pin

Output port pin

Output port pin or TOUT0/FOUT3 clock output pin

Output port pin or TOUT1/FOUT1 clock output pin

Output port pin or buzzer signal output pin

I/O port pin

I/O port pin or serial I/F data input pin

I/O port pin or serial I/F data output pin

I/O port pin or serial I/F clock input/output pin

I/O port pin or serial I/F ready signal output pin

I/O port pin, serial I/F data input or IR receiver input pin

I/O port pin, serial I/F data output or IR transmitter output pin

I/O port pin or serial I/F clock input/output pin

I/O port pin or serial I/F ready signal output pin

I/O port pin or touch panel controller BYH signal output pin

I/O port pin or touch panel controller BYL signal output pin

I/O port pin or touch panel controller BXH signal output pin

I/O port pin or touch panel controller BXL signal output pin

I/O port pin or A/D converter analog signal input pin

I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin

LCD controller enable signal output pin

LCD controller forced blank signal output pin

LCD controller scan start pulse output pin

LCD controller frame signal output pin

LCD controller shift clock output pin

LCD controller latch pulse output pin

LCD controller data output pin

Initial reset input pin

Test input pin

*

2

Pin No.

44

50

47

24

27

25

26

49

48

46

45

51

52~59

60

61

62~63

73~80

81~88

89~96

97~99

100

1

2

65~72

3

4

5

6

7

8

9

10

11

12

13

14

23~18

17,16

43

42

41

40

39

38

37~30

64

15

I/O

–

O

–

I

O

I

O

I

O

I/O

O

I

∗1 The MCU/MPU terminal should be connected to VDD.

∗2 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD.

6

S1C88409

• Pin layout for expanded 64K mode (for multi-chip system)

INDEX

S1C88409

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

(TOUT1/FOUT1) R41

(BZ) R42

(SIN) P10

(SOUT) P11

(SCLK) P12

(SRDY) P13

(SIN/IRI) P14

(SOUT/IRO) P15

(SCLK) P16

(SRDY) P17

(BYH) P20

(BYL) P21

(BXH) P22

(BXL) P23

TEST

(AD7/DA1) P37

(AD6/DA0) P36

(AD5) P35

(AD4) P34

(AD3) P33

(AD2) P32

(AD1) P31

(AD0) P30

AV

DD

AV

SS

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

V

SS

OSC1

OSC2

V

D1

OSC3

OSC4

V

DD

LCDEN

DOFF

YD

FR

XSCL

LP

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

N.C.

AGND

AV

REF

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

RESET

K13

K12

K11 (EXCL11)

K10 (EXCL00)

K07

K06

K05

K04

K03

K02

K01

K00

MCU/MPU

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

R20

R21

R22

R23

R24

R25

RD

WR

CE0

(CE1) R31

(CE2) R32

(TOUT0/FOUT3) R40

S1C88409

7

∗1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD.

Pin name

V

DD

V

SS

V

D1

AV

DD

AGND

AV

SS

AV

REF

OSC1

OSC2

OSC3

OSC4

MCU/MPU

K00~K07

K10 (EXCL00)

K11 (EXCL01)

K12~K13

A00~A15

R20~R25

RD

WR

CE0

CE1 (R31)

CE2 (R32)

R40 (TOUT0/FOUT3)

R41 (TOUT1/FOUT1)

R42 (BZ)

D0~D7

P10 (SIN)

P11 (SOUT)

P12 (SCLK)

P13 (SRDY)

P14 (SIN/IRI)

P15 (SOUT/IRO)

P16 (SCLK)

P17 (SRDY)

P20 (BYH)

P21 (BYL)

P22 (BXH)

P23 (BXL)

P30~P35 (AD0~AD5)

P36, P37

(AD6/DA0, AD7/DA1)

LCDEN

DOFF

YD

FR

XSCL

LP

SD0~SD7

RESET

TEST

Function

Power supply (+) pin

Power supply (GND) pin

Voltage regulator output pin

Power supply (+) pin for analog circuit system

GND pin for analog circuit system

Power supply (GND) pin for analog circuit system

Reference voltage input pin for analog circuit system

OSC1 oscillation input pin

(32 kHz crystal, CR oscillation, external clock input)

OSC1 oscillation output pin

OSC3 oscillation input pin

(crystal/ceramic, CR oscillation, external clock input)

OSC3 oscillation output pin

MCU/MPU mode setting pin

Input port pin

Input port pin or external clock input pin for event counter (Timer 0)

Input port pin or external clock input pin for event counter (Timer 1)

Input port pin

Address bus

Output port pin

Read signal output pin

Write signal output pin

Chip enable signal output pin

Chip enable signal output pin or output port pin

Output port pin or TOUT0/FOUT3 clock output pin

Output port pin or TOUT1/FOUT1 clock output pin

Output port pin or buzzer signal output pin

Data bus

I/O port pin or serial I/F data input pin

I/O port pin or serial I/F data output pin

I/O port pin or serial I/F clock input/output pin

I/O port pin or serial I/F ready signal output pin

I/O port pin, serial I/F data input or IR receiver input pin

I/O port pin, serial I/F data output or IR transmitter output pin

I/O port pin or serial I/F clock input/output pin

I/O port pin or serial I/F ready signal output pin

I/O port pin or touch panel controller BYH signal output pin

I/O port pin or touch panel controller BYL signal output pin

I/O port pin or touch panel controller BXH signal output pin

I/O port pin or touch panel controller BXL signal output pin

I/O port pin or A/D converter analog signal input pin

I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin

LCD controller enable signal output pin

LCD controller forced blank signal output pin

LCD controller scan start pulse output pin

LCD controller frame signal output pin

LCD controller shift clock output pin

LCD controller latch pulse output pin

LCD controller data output pin

Initial reset input pin

Test input pin

*

1

Pin No.

44

50

47

24

27

25

26

49

48

46

45

51

52~59

60

61

62~63

73~88

89~94

95

96

97

98

99

100

1

2

65~72

3

4

5

6

7

8

9

10

11

12

13

14

23~18

17,16

43

42

41

40

39

38

37~30

64

15

I/O

–

O

–

I

O

I

O

I

O

I/O

O

I

8

S1C88409

• Pin layout for expanded 4M mode (for multi-chip system)

INDEX

S1C88409

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

(TOUT1/FOUT1) R41

(BZ) R42

(SIN) P10

(SOUT) P11

(SCLK) P12

(SRDY) P13

(SIN/IRI) P14

(SOUT/IRO) P15

(SCLK) P16

(SRDY) P17

(BYH) P20

(BYL) P21

(BXH) P22

(BXL) P23

TEST

(AD7/DA1) P37

(AD6/DA0) P36

(AD5) P35

(AD4) P34

(AD3) P33

(AD2) P32

(AD1) P31

(AD0) P30

AV

DD

AV

SS

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

V

SS

OSC1

OSC2

V

D1

OSC3

OSC4

V

DD

LCDEN

DOFF

YD

FR

XSCL

LP

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

N.C.

AGND

AV

REF

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

RESET

K13

K12

K11 (EXCL11)

K10 (EXCL00)

K07

K06

K05

K04

K03

K02

K01

K00

MCU/MPU

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

RD

WR

CE0

(CE1) R31

(CE2) R32

(TOUT0/FOUT3) R40

S1C88409

9

Pin name

V

DD

V

SS

V

D1

AV

DD

AGND

AV

SS

AV

REF

OSC1

OSC2

OSC3

OSC4

MCU/MPU

K00~K07

K10 (EXCL00)

K11 (EXCL01)

K12~K13

A00~A21

RD

WR

CE0

CE1 (R31)

CE2 (R32)

R40 (TOUT0/FOUT3)

R41 (TOUT1/FOUT1)

R42 (BZ)

D0~D7

P10 (SIN)

P11 (SOUT)

P12 (SCLK)

P13 (SRDY)

P14 (SIN/IRI)

P15 (SOUT/IRO)

P16 (SCLK)

P17 (SRDY)

P20 (BYH)

P21 (BYL)

P22 (BXH)

P23 (BXL)

P30~P35 (AD0~AD5)

P36, P37

(AD6/DA0, AD7/DA1)

LCDEN

DOFF

YD

FR

XSCL

LP

SD0~SD7

RESET

TEST

Function

Power supply (+) pin

Power supply (GND) pin

Voltage regulator output pin

Power supply (+) pin for analog circuit system

GND pin for analog circuit system

Power supply (GND) pin for analog circuit system

Reference voltage input pin for analog circuit system

OSC1 oscillation input pin

(32 kHz crystal, CR oscillation, external clock input)

OSC1 oscillation output pin

OSC3 oscillation input pin

(crystal/ceramic, CR oscillation, external clock input)

OSC3 oscillation output pin

MCU/MPU mode setting pin

Input port pin

Input port pin or external clock input pin for event counter (Timer 0)

Input port pin or external clock input pin for event counter (Timer 1)

Input port pin

Address bus

Read signal output pin

Write signal output pin

Chip enable signal output pin

Chip enable signal output pin or output port pin

Output port pin or TOUT0/FOUT3 clock output pin

Output port pin or TOUT1/FOUT1 clock output pin

Output port pin or buzzer signal output pin

Data bus

I/O port pin or serial I/F data input pin

I/O port pin or serial I/F data output pin

I/O port pin or serial I/F clock input/output pin

I/O port pin or serial I/F ready signal output pin

I/O port pin, serial I/F data input or IR receiver input pin

I/O port pin, serial I/F data output or IR transmitter output pin

I/O port pin or serial I/F clock input/output pin

I/O port pin or serial I/F ready signal output pin

I/O port pin or touch panel controller BYH signal output pin

I/O port pin or touch panel controller BYL signal output pin

I/O port pin or touch panel controller BXH signal output pin

I/O port pin or touch panel controller BXL signal output pin

I/O port pin or A/D converter analog signal input pin

I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin

LCD controller enable signal output pin

LCD controller forced blank signal output pin

LCD controller scan start pulse output pin

LCD controller frame signal output pin

LCD controller shift clock output pin

LCD controller latch pulse output pin

LCD controller data output pin

Initial reset input pin

Test input pin

*1

Pin No.

44

50

47

24

27

25

26

49

48

46

45

51

52~59

60

61

62~63

73~94

95

96

97

98

99

100

1

2

65~72

3

4

5

6

7

8

9

10

11

12

13

14

23~18

17,16

43

42

41

40

39

38

37~30

64

15

I/O

–

O

–

I

O

I

O

I

O

I/O

O

I

∗1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD.

10

S1C88409

■OPTION LIST

1 OSC1 SYSTEM CLOCK

■■ 1. Crystal

■■ 2. External Clock

■■ 3. CR

■■ 4. Crystal (with Gate Capacity)

2 OSC3 SYSTEM CLOCK

■■ 1. Crystal

■■ 2. Ceramic

■■ 3. CR

■■ 4. External Clock

3 MULTIPLE KEY ENTRY RESET

■■ 1. Not Use

■■ 2. Use K00, K01

■■ 3. Use K00, K01, K02

■■ 4. Use K00, K01, K02, K03

4 MPU MODE INITIAL SET

■■ 1. 4M MAXIMUM

■■ 2. 4M MINIMUM

■■ 3. 64K

5 INPUT PORT PULL UP RESISTOR

• K00 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K01 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K02 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K03 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K04 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K05 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K06 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K07 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K10 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K11 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K12 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K13 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• RESET ................. ■■ 1. With Resistor ■■ 2. Gate Direct

• MCU/MPU ............ ■■ 1. With Resistor ■■ 2. Gate Direct

6 I/O PORT PULL UP RESISTOR

• P00 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P01 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P02 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P03 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P04 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P05 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P06 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P07 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P10 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P11 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P12 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P13 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P14 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P15 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P16 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P17 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

S1C88409

11

• P20 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P21 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P22 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P23 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P30 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P31 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P32 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P33 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P34 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P35 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P36 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

• P37 ....................... ■■ 1. With Resistor ■■ 2. Gate Direct

7 RAM OPTION ■■ 1. LCD RAM 2K Byte

■■ 2. LCD RAM 2.25K Byte

■■ 3. LCD RAM 2.5K Byte

■■ 4. LCD RAM 2.75K Byte

■■ 5. LCD RAM 3K Byte

■■ 6. LCD RAM 3.25K Byte

■■ 7. LCD RAM 3.5K Byte

8 TOUCH PANEL CONTROLLER DRIVE PORT

■■ 1. Use

■■ 2. Not Use

9 TPC INPUT PORT

• P30 ....................... ■■ 1. Use ■■ 2. Not Use

• P31 ....................... ■■ 1. Use ■■ 2. Not Use

• P32 ....................... ■■ 1. Use ■■ 2. Not Use

• P33 ....................... ■■ 1. Use ■■ 2. Not Use

• P34 ....................... ■■ 1. Use ■■ 2. Not Use

• P35 ....................... ■■ 1. Use ■■ 2. Not Use

10 TPC INPUT PORT TYPE

• P30 ....................... ■■ 1. Y Input ■■ 2. X Input ■■ 3. Not Use

• P31 ....................... ■■ 1. X Input ■■ 2. Y Input ■■ 3. Not Use

• P32 ....................... ■■ 1. Not Use ■■ 2. X Input ■■ 3. Y Input

• P33 ....................... ■■ 1. Not Use ■■ 2. X Input ■■ 3. Y Input

• P34 ....................... ■■ 1. Not Use ■■ 2. X Input ■■ 3. Y Input

• P35 ....................... ■■ 1. Not Use ■■ 2. X Input ■■ 3. Y Input

■ELECTRICAL CHARACTERISTICS

●Absolute Maximum Ratings

Rating

Supply voltage

Analog supply voltage

Reference supply voltage

Input voltage

Output voltage

High-level output current

Low-level output current

Operating temperature

Storage temperature

Permissible disspation

Note) 1.

Symbol

V

DD

AV

DD

AV

REF

V

I

V

O

I

OH

I

OL

Topr

Tstg

P

D

Unit

V

mA

°C

mW

Note

1

Value

-0.3 to +7.0

-0.3 to AV

DD

+0.3

-0.3 to V

DD

+0.3

-0.3 to V

DD

+0.3

-5

-20

-5

-20

-20 to +70

-65 to +150

200

In case of plastic package.

Condition

1 terminal

Total of all terminals

1 terminal

Total of all terminals

Ta=25°C

(V

SS

=0V)

12

S1C88409

●Recommended Operating Conditions

Condition

Supply voltage

Analog supply voltage

Clock frequency

Operating temperature

Capacitor between V

SS

and V

D1

Note) 1.

(V

SS

=0V)

Symbol

V

DD

AV

DD

f

OSC1

f

OSC3

Topr

C

1

Unit

V

kHz

MHz

°C

µF

Note

1

Max.

5.5

V

DD

+0.05

50.000

1.1

4.4

6.6

8.8

+70

Typ.

32.768

0.1

Min.

1.8

V

DD

-0.05

30.000

0.03

-20

When an external clock is input from the OSC1 terminal by setting the mask option, do not connect anything to the OSC2

terminal. When an external clock is input from the OSC3 terminal, do not connect anything to the OSC4 terminal.

Remark

AV

DD

≥2.7 V

V

DD

=1.8 to 5.5 V

V

DD

=1.8 to 5.5 V

V

DD

=2.6 to 5.5 V

V

DD

=3.5 to 5.5 V

V

DD

=4.5 to 5.5 V

●DC Characteristics

Characteristic

High-level input voltage

Low-level input voltage

High-level input voltage

Low-level input voltage

High-level schmitt trigger input voltage

Low-level schmitt trigger input voltage

Schmitt trigger hysteresis voltage

High-level output current

Low-level output current

Input leak current

Output leak current

Input pull-up resistance

Input terminal capacitance

Note) 1.

2.

3.

4.

5.

6.

7.

(Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=-20 to 70°C)

Symbol

VIH1

VIL1

VIH2

VIL2

VT+

VT-

VHS

IOH

IOL

ILI1

ILI2

ILO

RIN

CIN

Unit

V

mA

µA

kΩ

pF

Note

1,3

1,4

1,5

1,6

1,3

1,4

1,5

1,6

7

1

2

Max.

VDD

0.2VDD

VDD

0.3

0.6

0.8

1.0

0.9VDD

0.5VDD

0.5

1

500

15

Typ.Min.

0.8VDD

0

1.3

1.8

2.4

3.2

0

0.5VDD

0.1VDD

0.2

-0.5

-1

100

When external clock is selected by mask option.

When pull-up resistor is added by mask option.

Low-power mode (VD1C1 = "0", VD1C0 = "1")

Normal mode (VD1C1 = "0", VD1C0 = "0")

High-speed mode 1 (VD1C1 = "1", VD1C0 = "0")

High-speed mode 2 (VD1C1 = "1", VD1C0 = "1")

Characteristics when only one terminal is driven. If two or more terminals are driven simultaneously, the characteristics had

happen to reduced because the VOH and VOL voltages drop due to the parasitic resistance on the power line in the IC.

Condition

Pxx, MCU/MPU, Kxx

OSC1, OSC3, VD1 = 1.6V

OSC1, OSC3, VD1 = 2.4V

OSC1, OSC3, VD1 = 3.2V

OSC1, OSC3, VD1 = 4.2V

OSC1, OSC3, VD1 = 1.6V

OSC1, OSC3, VD1 = 2.4V

OSC1, OSC3, VD1 = 3.2V

OSC1, OSC3, VD1 = 4.2V

RESET

RESET, VHS=VT+–VT-

Pxx, Rxx, VOH=VDD-0.2 V

Pxx, Rxx, VOL=0.2 V

Kxx, Pxx, MCU/MPU, RESET

OSC1, OSC3

Pxx, Rxx

Kxx, Pxx, MCU/MPU, RESET

Kxx, Pxx, VIN=0 V, φ=1 MHz, Ta=25°C

V

DD

V

DD

V

T+

V

IN

[V]

V

OUT

[V]

V

T-

0

S1C88409

13

●Analog Circuit Characteristics and Current Consumption

Characteristic

SVD voltage

SVD circuit response time

Power current

Low-power mode

VD1C1="0", VD1C0="1"

Power current

Normal mode

VD1C1="0", VD1C0="0"

Power current

High-speed mode 1

VD1C1="1", VD1C0="0"

Power current

High-speed mode 2

VD1C1="1", VD1C0="1"

SVD circuit current

OSC1 CR oscillation current

(Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25°C, OSC1=32.768kHz crystal oscillation, OSC3=external clock input)

Symbol

VSVD

t

SVD

IDD1

IDD2

IDD3

IDD4

IDD1

IDD2

IDD3

IDD4

IDD1

IDD2

IDD3

IDD4

IDD1

IDD2

IDD3

IDD4

ISVDN

ICR1

Unit

V

µs

µA

mA

µA

mA

µA

mA

µA

mA

µA

Note

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

5

6

Max.

3.75

3.05

2.1

100

1.0

5.0

20.0

0.5

1.5

7.0

25.0

0.7

2.0

12.0

35.0

1.0

3.0

20.0

50.0

1.4

15

50

Typ.

3.4

2.8

1.9

0.45

1.8

9.0

0.3

0.55

3.0

14.0

0.45

0.65

5.0

21.0

0.65

0.75

9.0

32.0

0.9

7

20

Min.

3.05

2.55

1.7

Condition

SVD1="1", SVD0=X

SVD1="0", SVD0="1"

SVD1="0", SVD0="0"

In SLEEP status

In HALT status

CPU is in operating (32.768 kHz)

CPU is in operating (1 MHz)

In SLEEP status

In HALT status

CPU is in operating (32.768 kHz)

CPU is in operating (1 MHz)

In SLEEP status

In HALT status

CPU is in operating (32.768 kHz)

CPU is in operating (1 MHz)

In SLEEP status

In HALT status

CPU is in operating (32.768 kHz)

CPU is in operating (1 MHz)

VDD=5.0 V

RCR=1.5MΩ, normal mode

Note) 1.

2.

3.

4.

5.

6.

OSC1: Stop OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Stop SVD: Off Others: Stop

OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run SVD: Off Others: Stop

OSC1: On OSC3: Stop CPU, ROM, RAM: Run Clock Timer: Run SVD: Off Others: Stop

OSC1: On OSC3: On CPU, ROM, RAM: Run Clock Timer: Run SVD: Off Others: Stop

OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run SVD: On Others: Stop

When the OSC1 CR oscillation circuit is selected by mask option.

●AC Characteristics

External memory access

• Read cycle

Item

Address set-up time in read cycle

Address hold time in read cycle

Read signal pulse width

Data input set-up time in read cycle

Data input hold time in read cycle

Address set-up time in read cycle

Address hold time in read cycle

Read signal pulse width

Data input set-up time in read cycle

Data input hold time in read cycle

Address set-up time in read cycle

Address hold time in read cycle

Read signal pulse width

Data input set-up time in read cycle

Data input hold time in read cycle

Address set-up time in read cycle

Address hold time in read cycle

Read signal pulse width

Data input set-up time in read cycle

Data input hold time in read cycle

Note) 1.

Symbol

tras

trah

trp

trds

trdh

tras

trah

trp

trds

trdh

tras

trah

trp

trds

trdh

tras

trah

trp

trds

trdh

Unit

ns

Note

1

Max.

–

Typ.

–

Min.

t

c+

t

l-200+n∗

t

c/2

t

h-160

t

c-40+n∗

t

c/2

600

0

t

c+

t

l-100+n∗

t

c/2

t

h-80

t

c-20+n∗

t

c/2

300

0

t

c+

t

l-50+n∗

t

c/2

t

h-40

t

c-10+n∗

t

c/2

150

0

t

c+

t

l-50+n∗

t

c/2

t

h-40

t

c-10+n∗

t

c/2

150

0

Substitute the number of states for wait insertion in n.

t

c=input clock cycle time,

t

h=input clock H pulse width,

t

l=input clock L pulse width

Condition

V

DD

=1.8 to 5.5 V

V

D1

=1.6 V

V

DD

=2.6 to 5.5 V

V

D1

=2.4 V

V

DD

=3.5 to 5.5 V

V

D1

=3.2 V

V

DD

=4.5 to 5.5 V

V

D1

=4.2 V

(Unless otherwise specified: V

DD

=5.5V, V

SS

=0V, f

OSC1

=32.768kHz, f

OSC3

=1.0MHz, Ta=-20 to 70°C, C

L

=100 pF,

V

IH

=0.8V

DD

, V

IL

=0.2V

DD

, V

OH

=0.8V

DD

, V

OL

=0.2V

DD

)

14

S1C88409

• Write cycle

Item

Address set-up time in write cycle

Address hold time in write cycle

Write signal pulse width

Data output set-up time in write cycle

Data output hold time in write cycle

Address set-up time in write cycle

Address hold time in write cycle

Write signal pulse width

Data output set-up time in write cycle

Data output hold time in write cycle

Address set-up time in write cycle

Address hold time in write cycle

Write signal pulse width

Data output set-up time in write cycle

Data output hold time in write cycle

Address set-up time in write cycle

Address hold time in write cycle

Write signal pulse width

Data output set-up time in write cycle

Data output hold time in write cycle

Note) 1.

Symbol

t

was

t

wah

t

wp

t

wds

t

wdh

t

was

t

wah

t

wp

t

wds

t

wdh

t

was

t

wah

t

wp

t

wds

t

wdh

t

was

t

wah

t

wp

t

wds

t

wdh

Unit

ns

Note

1

Max.

–

th+160

–

th+160

–

th+160

–

th+160

Typ.

–

Min.

tc-360

th-160

tl-80+n∗tc/2

tc-360+n∗tc/2

th-160

tc-180

th-80

tl-40+n∗tc/2

tc-180+n∗tc/2

th-160

tc-90

th-40

tl-20+n∗tc/2

tc-90+n∗tc/2

th-160

tc-90

th-40

tl-20+n∗tc/2

tc-90+n∗tc/2

th-160

Substitute the number of states for wait insertion in n.

tc=input clock cycle time, th=input clock H pulse width, tl=input clock L pulse width

Condition

V

DD

=1.8 to 5.5 V

V

D1

=1.6 V

V

DD

=2.6 to 5.5 V

V

D1

=2.4 V

V

DD

=3.5 to 5.5 V

V

D1

=3.2 V

V

DD

=4.5 to 5.5 V

V

D1

=4.2 V

(Unless otherwise specified: V

DD

=5.5V, V

SS

=0V, f

OSC1

=32.768kHz, f

OSC3

=1.0MHz, Ta=-20 to 70°C,

C

L

=100pF, V

IH

=0.8V

DD

, V

IL

=0.2V

DD

, V

OH

=0.8V

DD

, V

OL

=0.2V

DD

)

• Read cycle

ICLK

A00–A21

CE

RD

DIN

VOH

VOL

t

h

*

t

ras

t

rah

t

c

*

VOH

VOL

t

rp

VIH

VIL

t

rds

t

rdh

VIH

t

l

*

VIL

∗In the case of crystal or ceramic oscillation:

t

h

=0.5

t

c

±0.05

t

c

,

t

l

=

t

c

-

t

h

In the case of CR oscillation:

t

h

=0.5

t

c

±0.10

t

c

,

t

l

=

t

c

-

t

h

(1/

t

c

: oscillation frequency)

• Write cycle

ICLK

A00–A21

CE

WR

DIN

VOH

VOL

t

h

*

t

was

t

wah

t

c

*

VOH

VOL

t

wp

VIH

VIL

t

wds

t

wdh

VIH

t

l

*

VIL

∗In the case of crystal or ceramic oscillation:

t

h

=0.5

t

c

±0.05

t

c

,

t

l

=

t

c

-

t

h

In the case of CR oscillation:

t

h

=0.5

t

c

±0.10

t

c

,

t

l

=

t

c

-

t

h

(1/

t

c

: oscillation frequency)

S1C88409

15

Serial interface

• Clock synchronous master mode

Item

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Symbol

tsmd

tsms

tsmh

tsmd

tsms

tsmh

tsmd

tsms

tsmh

tsmd

tsms

tsmh

Unit

ns

NoteMax.

400

–

200

–

100

–

100

–

Typ.

–

Min.

–

1000

400

–

500

200

–

250

100

–

250

100

(Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=100kHz, Ta=-20 to 70°C,

CL=100pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD)

Condition

VDD=1.8 to 5.5 V

VD1=1.6 V

VDD=2.6 to 5.5 V

VD1=2.4 V

VDD=3.5 to 5.5 V

VD1=3.2 V

VDD=4.5 to 5.5 V

VD1=4.2 V

SCLK OUT

SOUT

SIN

V

OH

V

OH

V

OL

tsms

tscd

tsmh

tsmd

V

IH

V

IL

V

OL

OSC3

SCLK OUT V

OH

tscd

V

OL

• Clock synchronous slave mode

Item

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Transmit data output delay time

Receive data input set-up time

Receive data input hold time

Symbol

tssd

tsss

tssh

tssd

tsss

tssh

tssd

tsss

tssh

tssd

tsss

tssh

Unit

ns

NoteMax.

1000

–

500

–

250

–

250

–

Typ.

–

Min.

–

400

–

200

–

100

–

100

Condition

VDD=1.8 to 5.5 V

VD1=1.6 V

SCKIN=100 kHz

VDD=2.6 to 5.5 V

VD1=2.4 V

SCKIN=100 kHz

VDD=3.5 to 5.5 V

VD1=3.2 V

SCKIN=100 kHz

VDD=4.5 to 5.5 V

VD1=4.2 V

SCKIN=100 kHz

(Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=100kHz, Ta=-20 to 70°C,

CL=100pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD)

SCLK IN

SOUT

SIN

V

IH

V

OH

V

OL

tsss

tckf tsch

tckr

tscl

tssh

tsccy

tssd

V

IH

V

IL

V

IL

SCLK IN V

IH

V

IL

16

S1C88409

• Asynchronous mode

Item

Start bit detection error time

Erroneous start bit detection range time

Note) 1.

2.

Symbol

t

sa1

t

sa2

Unit

s

Note

1

2

Max.

t/16

9t/16

Typ.

–

Min.

0

8t/16

Start bit detection error time is a logical delay time from inputting a start bit until the internal sampling starts operating. (AC time

is not included.)

Erroneous start bit detection range time is a logical time from starting sampling clock (detecting a start bit) until the start bit is

detected again whether a low level (start bit) has still been input. When a high level is detected, the start bit detection circuit is

reset and goes into a start bit waiting status. (AC time is not included.)

Condition

(Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=-20 to 70°C, VIH=0.7VDD, VIL=0.3VDD, VOH=0.7VDD, VOL=0.3VDD)

SIN

Sampling

clock

Erroneous

start bit

detection signal

t

sa2

t

sa1

Start bit Stop bit

Input clock

• OSC1, OSC3 external clock

Item

OSC1 input clock time

OSC3 input clock time

Input clock rising time

Input clock falling time

OSC1 input clock time

OSC3 input clock time

Input clock rising time

Input clock falling time

OSC1 input clock time

OSC3 input clock time

Input clock rising time

Input clock falling time

OSC1 input clock time

OSC3 input clock time

Input clock rising time

Input clock falling time

Symbol

t

o1cy

t

o1h

t

o1l

t

o3cy

t

o3h

t

o3l

t

osr

t

osf

t

o1cy

t

o1h

t

o1l

t

o3cy

t

o3h

t

o3l

t

osr

t

osf

t

o1cy

t

o1h

t

o1l

t

o3cy

t

o3h

t

o3l

t

osr

t

osf

t

o1cy

t

o1h

t

o1l

t

o3cy

t

o3h

t

o3l

t

osr

t

osf

Unit

µs

ns

µs

ns

µs

ns

µs

ns

NoteMax.

32

16

32000

16000

25

32

16

32000

16000

25

32

16

32000

16000

25

32

16

32000

16000

25

Typ.

–

Min.

20

10

1000

500

–

20

10

240

120

–

20

10

155

77.5

–

20

10

115

57.5

–

Condition

V

DD

=1.8 to 5.5 V

V

D1

=1.6 V

V

IH

=1.3 V

V

IL

=0.3 V

V

DD

=2.6 to 5.5 V

V

D1

=2.4 V

V

IH

=1.8 V

V

IL

=0.6 V

V

DD

=3.5 to 5.5 V

V

D1

=3.2 V

V

IH

=2.4 V

V

IL

=0.8 V

V

DD

=4.5 to 5.5 V

V

D1

=4.2 V

V

IH

=3.2 V

V

IL

=1.0 V

Cycle time

"H" pulse width

"L" pulse width

Cycle time

"H" pulse width

"L" pulse width

Cycle time

"H" pulse width

"L" pulse width

Cycle time

"H" pulse width

"L" pulse width

Cycle time

"H" pulse width

"L" pulse width

Cycle time

"H" pulse width

"L" pulse width

(Unless otherwise specified: V

SS

=0V, Ta=-20 to 70°C)

Cycle time

"H" pulse width

"L" pulse width

Cycle time

"H" pulse width

"L" pulse width

t

osf

t

o1h

t

osr

t

o1l

t

o1cy

OSC1

OSC3

V

IH

VIL

t

osf

t

o3h

t

osr

t

o3l

t

o3cy

VIH

VIL

S1C88409

17

• RESET input clock

Item

RESET pulse width Symbol

t

sr

Unit

µsNoteMax.

–

Typ.

–

Min.

100

Condition

(Unless otherwise specified: V

DD

=1.8 to 5.5V, V

SS

=0V, Ta=-20 to 70°C, V

IH

=0.5V

DD

, V

IL

=0.1V

DD

)

RESET

tsr

V

IL

V

IH

LCD controller

Item

XSCL H-level pulse width (B&W, 4 bits)

XSCL H-level pulse width (gray, 4 bits)

LP falling edge to XSCL rising edge

LCD data setup time

LCD data hold time

YD H-level pulse width

LP H-level pulse width

YD setup time

YD hold time

FR change from LP falling edge

XSCL H-level pulse width (B&W, 4 bits)

XSCL H-level pulse width (gray, 4 bits)

LP falling edge to XSCL rising edge

LCD data setup time

LCD data hold time

YD H-level pulse width

LP H-level pulse width

YD setup time

YD hold time

FR change from LP falling edge

XSCL H-level pulse width (B&W, 4 bits)

XSCL H-level pulse width (gray, 4 bits)

LP falling edge to XSCL rising edge

LCD data setup time

LCD data hold time

YD H-level pulse width

LP H-level pulse width

YD setup time

YD hold time

FR change from LP falling edge

XSCL H-level pulse width (B&W, 4 bits)

XSCL H-level pulse width (gray, 4 bits)

LP falling edge to XSCL rising edge

LCD data setup time

LCD data hold time

YD H-level pulse width

LP H-level pulse width

YD setup time

YD hold time

FR change from LP falling edge

Symbol

tHXS(1)

tHXS(2)

tLPXS

tDS

tDH

tHYD

tHLP

tYDLPL

tLPYD

tLPFR

tHXS(1)

tHXS(2)

tLPXS

tDS

tDH

tHYD

tHLP

tYDLPL

tLPYD

tLPFR

tHXS(1)

tHXS(2)

tLPXS

tDS

tDH

tHYD

tHLP

tYDLPL

tLPYD

tLPFR

tHXS(1)

tHXS(2)

tLPXS

tDS

tDH

tHYD

tHLP

tYDLPL

tLPYD

tLPFR

Unit

ns

NoteMax.

–

300

–

200

–

100

–

100

Typ.

–

Min.

tc-360

tc-tl-360

6∗tc-360

tc-360

tc(f

OSC1

)-3

tl(f

OSC1

)-1.5

tl(f

OSC1

)-1.5

th(f

OSC1

)-1.5

-300

tc-180

tc-tl-180

6∗tc-180

tc-180

tc(f

OSC1

)-3

tl(f

OSC1

)-1.5

tl(f

OSC1

)-1.5

th(f

OSC1

)-1.5

-200

tc-90

tc-tl-90

6∗tc-90

tc-90

tc(f

OSC1

)-3

tl(f

OSC1

)-1.5

tl(f

OSC1

)-1.5

th(f

OSC1

)-1.5

-100

tc-90

tc-tl-90

6∗tc-90

tc-90

tc(f

OSC1

)-3

tl(f

OSC1

)-1.5

tl(f

OSC1

)-1.5

th(f

OSC1

)-1.5

-100

tc=OSC3 clock cycle time, th=OSC3 clock H pulse width, tl=OSC3 clock L pulse width, tc(f

OSC1

)=OSC1 clock cycle time

th(f

OSC1

)=OSC1 clock H pulse width, tl(f

OSC1

)=OSC1 clock L pulse width

Condition

V

DD

=1.8 to 5.5 V

V

D1

=1.6 V

V

DD

=2.6 to 5.5 V

V

D1

=2.4 V

V

DD

=3.5 to 5.5 V

V

D1

=3.2 V

V

DD

=4.5 to 5.5 V

V

D1

=4.2 V

(Unless otherwise specified: V

DD

=5.5V, V

SS

=0V, f

OSC1

=32.768kHz, f

OSC3

=2.0MHz, Ta=-20 to 70°C,

C

L

=100pF, V

IH

=0.8V

DD

, V

IL

=0.2V

DD

, V

OH

=0.8V

DD

, V

OL

=0.2V

DD

)

FR

YD

LP

XSCL

SD0–SD3

t

DS

t

HYD

t

DH

t

HLP

t

LPFR

t

LPYD

t

HXS

t

LPXS

t

YDLPL

18

S1C88409

Power-on reset

Item

Operating voltage

RESET input width

Symbol

Vsr

t

psr

Unit

V

ms

NoteMax.

–

Typ.

–

Min.

2.6

10

Condition (Unless otherwise specified: VSS=0V, Ta=-20 to 70°C)

VDD

RESET

tpsr

Vsr

0.5VDD

0.1VDD

Power ON

*1 When the built-in pull up resistor is not used.

*2 Because the potential of the RESET terminal

not reached VDD level or higher.

VDD

RESET

VSS

*2

*1

Switching operating mode

Item

Stabilization time

Note) 1.

Symbol

t

vdc Unit

ms Note

1

Max.

–

Typ.

–

Min.

5

Stabilization time is the time from switching on the operating mode until operating mode is stabilized. For example, when

turning the OSC3 oscillation circuit on, stabilization time is needed after the operating mode is switched on.

Condition

(Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=-20 to 70°C)

●Oscillation Characteristics

Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following char-

acteristics as reference values. In particular, when a ceramic oscillator or crystal oscillator is used for OSC3, use the

oscillator manufacturer's recommended values for constants such as capacitance and resistance. The oscillation start time

is important because it becomes the waiting time when OSC3 clock is used. (If OSC3 is used as CPU clock before oscilla-

tion stabilizes, the CPU may malfunction.)

• OSC1 crystal oscillation

Item

Oscillation start time

External gate capacitance

Built-in drain capacitance

Frequency/IC deviation

Frequency/supply voltage deviation

Frequency adjustment range

Frequency/operating mode deviation

Note) 1.

Symbol

tsta

C

G1

C

D1

∂f/∂IC

∂f/∂V

∂f/∂C

G

∂f/∂MD

Unit

s

pF

ppm

ppm/V

ppm

Note

1

Max.

3

25

10

1

20

Typ.

15

Min.

5

-10

25

When crystal oscillation is selected by mask option.

Condition

Including board capacitance

In case of the chip

V

DD

=constant

V

DD

=constant, C

G

=5 to 25 pF

V

DD

=constant

(Unless otherwise specified: V

DD

=1.8 to 5.5V, V

SS

=0V, Ta=25°C,

Crystal oscillator=Q12C2(made by Seiko Epson corporation), C

G1

=25pF(External), C

D1

=Built-in)

• OSC1 CR oscillation

Item

Oscillation start time

Frequenct/IC deviation

Symbol

t

sta

∂f/∂IC

Unit

ms

%

NoteMax.

3

25

Typ.Min.

-25

Condition

RCR=constant

(Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25°C, RCR=1.8MΩ)

• OSC3 crystal oscillation

Item

Oscillation start time

Note) 1.

Symbol

tsta Unit

ms Note

1

Max.

20

Typ.Min.

The crystal oscillation start time changes by the crystal oscillator to be used, CG2 and CD2.

Condition

(Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5V, VSS=0V, Ta=25°C,

Crystal oscillator=Q21CA301xxx(made by Seiko Epson corporation), RF=1MΩ, CG2=CD2=15pF)

S1C88409

19

• OSC3 CR oscillation

Item

Oscillation start time

Frequenct/IC deviation

Symbol

t

sta

∂f/∂IC

Unit

ms

%

NoteMax.

1

25

Typ.Min.

-25

Condition

R

CR

=constant

(Unless otherwise specified: V

DD

=2.6/3.5/4.5 to 5.5V, V

SS

=0V, Ta=25°C)

• OSC3 ceramic oscillation

Item

Oscillation start time Symbol

tsta Unit

ms NoteMax.

5

Typ.Min.Condition

(Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5V, VSS=0V, Ta=25°C,

Ceramic oscillator=CSA4.00MG/CSA8.00MTZ(made by Murata Mfg. corporation), RF=1MΩ, CG2=CD2=30 pF)

• OSC1 CR oscillation characteristics (for reference) Ta = 25˚C, Typ. value

• OSC3 CR oscillation characteristics (for reference) Ta = 25˚C, Typ. value

100

10

100

CR oscillatiing resistor value R

CR

[kΩ]

CRoscillation frequency f

OSC1

[kHz]

1000 10000

1

V

D1

= 4.2V

V

D1

= 3.2V

V

D1

= 2.4V

V

D1

= 1.6V

1

10

100

1000

10000

CR oscillatiing resistor value RCR [kΩ]

CR oscillation frequency fOSC3 [kHz]

10 100 1000 10000

100000 V

D1

= 4.2V

V

D1

= 3.2V

V

D1

= 2.4V

V

D1

= 1.6V

1

20

S1C88409

●A/D Converter Characteristics

Item

Zero-scale error

Full-scale error

Non-linearity error

Total error

A/D converter

current consumption

Input clock frequency

Symbol

Ezs

Efs

El

Et

I

AD

f

Unit

LSB

mA

MHz

NoteMax.

1.50

3.00

1.00

3.50

4

Typ.

–

0.50

1.80

2

Min.

-1.50

-3.00

–

∗ Zero-scale error: Ezs = deviation from the ideal value at zero point

∗ Full-scale error: Efs = deviation from the ideal value at the full scale point

∗ Non-linearity error: El = deviation of the real conversion curve from the end point line

∗ Total error: Et = max(Ezs, Efs, Eabs), Eabs = deviation from the ideal line (including quantization error)

Condition

V

DD

=AV

DD

=AV

REF

=2.7 to 5.5V, AV

SS

=0V,

ADCLK=2MHz, Ta=25°C

V

DD

=AV

DD

=AV

REF

=3.0V, ADCLK=2MHz, Ta=25°C

AV

REF

and ADCLK divider current not included

V

DD

=AV

DD

=AV

REF

=5.0V, ADCLK=2MHz, Ta=25°C

AV

REF

and ADCLK divider current not included

V

DD

=AV

DD

=AV

REF

=2.7 to 5.5 V, Ta=25°C

(Unless otherwise specified: V

DD

=AV

DD

=AV

REF

=5.0 V, V

SS

=AV

SS

=AGND=0 V, f

OSC1

=32.768 kHz, f

OSC3

=4.0 MHz, Ta=25°C)

The following characteristics apply to the plastic package model only.

●D/A Converter Characteristics

Item

D/A conversion speed

Integral linearity error

Differential linearity error

Total error

D/A converter

current consumption

Symbol

t

DA

E

l

DA

E

d

DA

EtDA

IDA

Unit

µs

LSB

mA

NoteMax.

10

30

1.50

1.00

2.50

1

2

Typ.

–

0.35

0.7

Min.

–

-1.50

-1.00

-2.50

–

Condition

VDD=AVDD=AVREF=VD1=5.5 V

Load capacitance=

parasitic capacitance only

VDD=AVDD=AVREF=VD1=5.5 V

Load capacitance=100 pF+

parasitic capacitance

VDD=AVDD=VD1=AVREF=3.0 V,

IL=1 µA, Ta=-20 to 70°C

VDD=AVDD=VD1=AVREF=5.0 V,

IL=1 µA, Ta=-20 to 70°C

VDD=AVDD=VD1=AVREF=3.0 V,

IL=1 µA, Ta=-20 to 70°C

VDD=AVDD=VD1=AVREF=5.0 V,

IL=1 µA, Ta=-20 to 70°C

VDD=AVDD=VD1=AVREF=3.0V,

IL=1µA, Ta=-20 to 70°C

VDD=AVDD=VD1=AVREF=5.0V,

IL=1µA, Ta=-20 to 70°C

VDD=AVDD=AVREF=3.0V, Ta=25°C, 55H output

Reference resistor current not included

VDD=AVDD=AVREF=5.5V, Ta=25°C, 55H output

Reference resistor current not included

∗ Integral linearity error: ElDA = difference between the real conversion characteristic and the end point line

∗ Differential linearity error: EdDA = difference between the real step width and the ideal step width

∗ Total error: EtDA = max(Ezs, Efs, Eabs) Eabs = deviation from the ideal line (including quantization error)

Ezs = deviation from the ideal value at zero point (zero-scale error)

Efs = deviation from the ideal value at the full scale point (full-scale error)

(Unless otherwise specified: VDD=AVDD=AVREF=5.0 V, VSS=AVSS=AGND=0 V, fOSC1=32.768 kHz, fOSC3=1.0 MHz, Ta=25°C)

The following characteristics apply to the plastic package model only.

S1C88409

21

■BASIC EXTERNAL CONNECTION DIAGRAM

VSS

AGND

AVSS

OSC1

OSC2

OSC3

OSC4

VD1

RESET

VDD

MCU/MPU

TEST

AVDD

BZ (R42)

AVREF

K00–K07

K10–K13

(A00–A07) R00–R07

(A08–A15) R10–R17

(A16–A21) R20–R25

(RD) R26

(WR) R27

(CE0) R30

(CE1) R31

(CE2) R32

(TOUT0/FOUT3) R40

(TOUT1/FOUT1) R41

(D0–D7) P00–P07

(SIN) P10

(SOUT) P11

(SCLK) P12

(SRDY) P13

(SIN/IRI) P14

(SOUT/IRO) P15

(SCLK) P16

(SRDY) P17

(BYH, BYL, BXH, BXL) P20–P23

(AD0–AD5) P30–P35

(AD6/DA0, AD7/DA1) P36, P37

LCDEN

DOFF

YD

FR

XSCL

LP

SD0–SD7

S1C88409

LCD panel/driver

Input

I/O

Output

[The potential of the substrate

(back of the chip) is VSS]

Symbol

X'tal1

RCR

X'tal2

CR

Rf

CG1

CG2

CD2

C1–3

CP

Cres

Name

Crystal oscillator

Resistor for CR oscillation

Crystal oscillator

Ceramic oscillator

Feedback resistor

Trimmer capacitor

Gate capacitor

Drain capacitor

Capacitor between VSS and VD1

Capacitor for power supply

Capacitor for RESET terminal

Recommended value

32.768 kHz, CI(Max.) = 35 kΩ

1.8 MΩ

4, 6, 8 MHz

1 MΩ

5–25 pF

15 pF

0.1 µF

3.3 µF

0.47 µF

Recommended values for external parts

CG1

Rf

RCR

CP1

-

CG2

+

CP2

-

+

CP3

-

+

+-

Cres

X'tal1

CD2 C1

X'tal2

or CR

1.8–5.5 V

PiezoCoil

Note: The above table is simply an example, and is not guaranteed to work.

22

S1C88409

■PAD COORDINATES

● Diagram of Pad Layout

Y

X

(0, 0)

1

51015202530

6056 65 70 75 80

35

31

40

45

50

55

108

7.58 mm

6.47 mm

85

90

95

100

105

81

Die No.

Chip thickness: 400 µm

Pad opening: 100 µm (PAD No. 1–80, 84–108)

60 µm (PAD No. 81–83)

S1C88409

23

● Pad Coordinates

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

Pad name

MCU/MPU

K00

K01

K02

K03

K04

K05

K06

K07

K10/EXCL00

K11/EXCL11

K12

K13

RESET

P00/D0

P01/D1

P02/D2

P03/D3

P04/D4

P05/D5

P06/D6

P07/D7

R00/A0

R01/A1

R02/A2

N.C.

R03/A3

R04/A4

R05/A5

R06/A6

R07/A7

R10/A8

R11/A9

R12/A10

R13/A11

R14/A12

R15/A13

R16/A14

R17/A15

R20/A16

R21/A17

R22/A18

R23/A19

R24/A20

R25/A21

R26/RD

R27/WR

R30/CE0

R31/CE1

R32/CE2

X

2,143

1,943

1,793

1,593

1,443

1,293

1,143

993

843

693

543

393

243

93

-80

-230

-380

-530

-680

-830

-990

-1,150

-1,330

-1,530

-1,790

-2,146

-2,306

-2,466

-2,616

-2,776

-3,107

Y

3,664

2,131

1,865

1,412

1,259

1,106

953

800

647

494

341

188

35

-118

-271

-424

-577

-730

-883

-1,036

-1,189

-1,342

-1,495

-1,648

-1,798

No.

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

Pad name

R40/TOUT0/FOUT3

R41/TOUT1/FOUT1

R42/BZ

P10/SIN

P11/SOUT

P12/SCLK

P13/SRDY

P14/SIN/IRI

P15/SOUT/IRO

P16/SCLK

P17/SRDY

P20/BYH

P21/BYL

P22/BXH

P23/BXL

TEST

P37/AD7/DA1

P36/AD6/DA0

P35/AD5

P34/AD4

P33/AD3

P32/AD2

P31/AD1

P30/AD0

AV

DD

AV

SS

N.C.

AV

REF

AGND

N.C.

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

LP

XSCL

FR

YD

DOFF

LCDEN

V

DD

OSC4

OSC3

V

D1

OSC2

OSC1

V

SS

X

-3,107

-2,069

-1,869

-1,689

-1,519

-1,369

-1,219

-1,069

-919

-769

-619

-469

-319

-169

-19

131

281

431

582

732

882

1,032

1,232

1,432

1,632

1,882

3,127

3,107

Y

-2,100

-3,665

-3,390

-3,137

-2,870

-2,600

-2,400

-2,173

-2,018

-1,863

-1,708

-1,553

-1,398

-1,243

-1,088

-933

-774

-610

-463

-259

-88

92

262

1,313

1,495

1,650

1,805

1,987

2,148

2,318

Unit: µm

S1C88409

NOTICE:

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko

Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of

any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that

this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual

property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this

material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the

subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export

license from the Ministry of International Trade and Industry or other approval from another government agency.

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

IC Marketing & Engineering Group

ED International Marketing Department Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone : 042-587-5812 FAX : 042-587-5564

ED International Marketing Department Asia

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone : 042-587-5814 FAX : 042-587-5110

http://www.epson.co.jp/device/

■ EPSON Electronic Devices Website

First issue June, 1998 M

Printed July, 2001 in Japan L

■PACKAGE

Plastic QFP15-100pin

(Unit: mm)

Note: The dimensions are subject to change without notice.

14±0.1

16±0.4

5175

14±0.1

16±0.4

26

50

INDEX

0.18 251

100

76

1.4±0.1

0.1

1.7max

1

0.5±0.2

0°

10°

0.125

0.5 +0.1

–0.05

+0.05

–0.025