500V / 600V High Voltage 3-phase Motor Driver ICs
SIM6800M Series Data Sheet
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 1
Jan. 21, 2019 https://www.sanken-ele.co.jp/en
© SANKEN ELECTRIC CO., LTD. 2014
Description
The SIM6800M series ar e high vo lta ge 3-phase motor
driver ICs in which transistors, a pre-driver IC (MIC),
and bootstrap circuits (diodes and resistors) are highly
integrated.
The se produc ts can run on a 3-sh unt current detection
system and optimally control the inverter systems of
small- to medium-capacity motors that require universal
input st and a rd s.
Features
● Built-in Bootstrap Diodes with Current Limiting
Resistors (60 Ω)
● CMOS-compatible Input (3.3 V or 5 V)
● Bare Lead Frame: Pb-free (RoHS Compliant)
● Isolation Voltage: 1500 V (for 1 min)
UL-recognized Component (File No.: E118037)
(SIM6880M UL Recognition Pending)
● Fault Signal Outp ut at Protection Activat ion (FO Pin)
● High-side Shutdown Signal Input (SD Pin)
● Protections Include:
Overcurrent Limit (OCL): Auto-restart
Overcurrent Protection (OCP): Auto-restart
Unde rvoltage Lockout for Power Supply
High-side (UVLO_VB) : Auto-restart
Low-side (UVLO_V CC): A uto-restart
Thermal Shutdown (TSD ) : A uto-restart
Typical Application (SIM681xM)
SD
VCC1VB1B
VB3
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB
V2
OCP
LS3B
LS2
40
LS3A
LS2
V
VB2
VB1A
LS1
C
FO
5 V
R
FO
R
S
R
O
C
O
VCC
Con troller
C
BOOT1
C
BOOT3
C
BOOT2
M
C
DC
C
S
V
DC
MIC
3
4
5
6
7
8
9
12
13
14
15
16
17
1
2
11
21
23
24
26
28
30
31
33
35
37
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
Fault
GND
10
20
19
Package
DIP40
Mold Dimensions: 36.0 mm × 14. 8 mm × 4.0 mm
Leadform 2971
Not to scale
Selection Guide
VDSS/VCES IO Feature
Part
Number
500 V
2.0 A
Power MOSFET
SIM6811M
2.5 A SIM6812M
3.0 A SIM6813M
600 V
3.0 A
IGBT with FRD,
low switching
dissipation
SIM6880M
5.0 A
IGBT with FRD,
low switchin g
dissipation
SIM6822M
5.0 A
IGBT with FRD,
low noise
SIM6827M
Applications
For motor drives such as:
● Refrigerator Compressor Motor
● Fan Motor and Pump Motor for W asher and Dryer
● Fan Motor for Air Conditioner, Air Purifier, and
Electric Fan
40
1
20
21
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 2
Jan. 21, 2019 https://www.sanken-ele.co.jp/en
© SANKEN ELECTRIC CO., LTD. 2014
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings ----------------------------------------------------------------------------- 4
2. Reco mmended Operating Conditions ----------------------------------------------------------------- 5
3. Electrical Characteristics -------------------------------------------------------------------------------- 6
3.1 Characteristics of Control Parts ------------------------------------------------------------------ 6
3.2 Bootstrap Diode Characteristics ----------------------------------------------------------------- 7
3.3 Thermal Resistance Characteristics ------------------------------------------------------------- 7
3.4 Transistor Characteristics ------------------------------------------------------------------------- 8
3.4.1 SIM6811M -------------------------------------------------------------------------------------- 9
3.4.2 SIM6812M -------------------------------------------------------------------------------------- 9
3.4.3 SIM6813M ------------------------------------------------------------------------------------ 10
3.4.4 SIM6880M ------------------------------------------------------------------------------------ 10
3.4.5 SIM6822M ------------------------------------------------------------------------------------ 11
3.4.6 SIM6827M ------------------------------------------------------------------------------------ 11
4. Mechanical Characteristics --------------------------------------------------------------------------- 12
5. Insulation Distance -------------------------------------------------------------------------------------- 12
6. Truth Ta ble ----------------------------------------------------------------------------------------------- 13
7. Block Diagrams ------------------------------------------------------------------------------------------ 14
8. Pin Configuration Definit ions ------------------------------------------------------------------------- 15
9. Typical Applicat ions ------------------------------------------------------------------------------------ 16
10. Physical Dimensions ------------------------------------------------------------------------------------ 17
11. Marking Diagram --------------------------------------------------------------------------------------- 18
12. Functional De sc r iption s -------------------------------------------------------------------------------- 19
12.1 Turning On and Off the IC ---------------------------------------------------------------------- 19
12.2 Pin Descriptions ----------------------------------------------------------------------------------- 19
12.2.1 U, V, V1, V2, W1, and W2 ----------------------------------------------------------------- 19
12.2.2 VB1A, VB1B, VB2, a nd VB3 -------------------------------------------------------------- 19
12.2.3 VCC1 and VCC2 ---------------------------------------------------------------------------- 20
12.2.4 COM1 and C OM2--------------------------------------------------------------------------- 20
12.2.5 HIN1, HIN2 , and HIN3; LIN 1, LIN2, and LIN 3 -------------------------------------- 21
12.2.6 VBB -------------------------------------------------------------------------------------------- 21
12.2.7 LS1, LS2, LS3A , and LS3B ---------------------------------------------------------------- 22
12.2.8 OCP and OCL ------------------------------------------------------------------------------- 22
12.2.9 SD----------------------------------------------------------------------------------------------- 22
12.2.10 FO ---------------------------------------------------------------------------------------------- 22
12.3 Protection Functions ------------------------------------------------------------------------------ 23
12.3.1 Fault Sig nal Output ------------------------------------------------------------------------- 23
12.3.2 Shutdow n Si gnal Input --------------------------------------------------------------------- 23
12.3.3 Undervoltage Lockout for Power Supply (UVLO) ----------------------------------- 23
12.3.4 Overcurrent Limit (OCL) ----------------------------------------------------------------- 24
12.3.5 Overcurrent Protection (OCP) ----------------------------------------------------------- 25
12.3.6 Thermal Shutdow n (TSD) ----------------------------------------------------------------- 26
13. Design Notes ---------------------------------------------------------------------------------------------- 26
13.1 PCB Pattern Layout ------------------------------------------------------------------------------ 26
13.2 Considerations in Heatsin k Mounting -------------------------------------------------------- 26
13.3 Considerations in IC Characteristics Measurement --------------------------------------- 27
14. Calculating Power Losses and Estimating Junction Temperatures --------------------------- 28
14.1 IGBT ------------------------------------------------------------------------------------------------- 28
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 3
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14.1.1 IGBT Stea dy -state Loss, PON -------------------------------------------------------------- 28
14.1.2 IGBT Switching Loss, PSW ----------------------------------------------------------------- 28
14.1.3 Estimating Junction Temperature of IGBT -------------------------------------------- 28
14.2 Power MOSFET ----------------------------------------------------------------------------------- 29
14.2.1 Power MOSFET Steady-state Loss, PRON----------------------------------------------- 29
14.2.2 Power MO S FET Swi tching Loss, PSW --------------------------------------------------- 29
14.2.3 Body D iode Stea dy-state Loss, P SD ------------------------------------------------------- 29
14.2.4 Estimating Junction Temperature of Pow e r M OSFET ------------------------------ 30
15. Performance Curves ------------------------------------------------------------------------------------ 31
15.1 Transient Thermal Resistance Curves -------------------------------------------------------- 31
15.2 Performance Curves of Control Parts --------------------------------------------------------- 32
15.3 Performance Curves of Output Parts --------------------------------------------------------- 37
15.3.1 Output Tra nsistor Perf o rmance Curves ------------------------------------------------ 37
15.3.2 Switching Losses ----------------------------------------------------------------------------- 39
15.4 Allowable Effective Current Curves ----------------------------------------------------------- 42
15.4.1 SIM6811M ------------------------------------------------------------------------------------ 42
15.4.2 SIM6812M ------------------------------------------------------------------------------------ 43
15.4.3 SIM6813M ------------------------------------------------------------------------------------ 44
15.4.4 SIM6880M ------------------------------------------------------------------------------------ 45
15.4.5 SIM6822M ------------------------------------------------------------------------------------ 46
15.4.6 SIM6827M ------------------------------------------------------------------------------------ 47
15.5 Short Circuit SOAs (Safe Operating Areas) ------------------------------------------------- 48
16. Pattern Layout Example ------------------------------------------------------------------------------- 49
17. Typica l Motor D r iver Application ------------------------------------------------------------------- 51
Important Notes ---------------------------------------------------------------------------------------------- 52
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 4
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© SANKEN ELECTRIC CO., LTD. 2014
1. Absolute Maximum Ratings
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, COM1 = COM2 = COM.
Parameter Symbol Conditions Rating Unit Remarks
Main Suppl y Voltage (DC) VDC VBB–LSx
400
V
SIM681xM
450
SIM682xM
SIM6880M
Main Power Voltage (Surge) VDC(SURGE) VBB–LSx
450
V
SIM681xM
500
SIM682xM
SIM6880M
IGBT / Power MOSFET
Breakdown Volta ge
VDSS
V
CC
= 15 V,
ID = 1 µA, VIN = 0 V
500 V SIM681xM
VCES
V
CC
= 15 V,
I
C
= 1 mA, V
IN
= 0 V 600
SIM682xM
SIM6880M
Logic Supply Voltage
VCC
VCCx–COM
20
V
VBS
VB1B–U,
VB2–V,
VB3–W1
20
Output Current (1) IO TC = 25 °C,
TJ < 150 °C
2
A
SIM6811M
2.5
SIM6812M
3
SIM6813M
SIM6880M
5
SIM6822M
SIM6827M
Output Current (Pulse) IOP
TC = 25 °C,
VCC = 15 V,
PW ≤ 1 ms,
single pulse
3
A
SIM6811M
3.75
SIM6812M
4.5
SIM6813M
SIM6880M
7.5
SIM6822M
SIM6827M
Input Volt age VIN
HINx–COM,
LINx–COM
− 0.5 to 7 V
FO Pin Voltage
VFO
FO–COM
−0.5 to 7
V
OCP Pin Voltage
VOCP
OCP–COM
−10 to 5
V
SD Pin Voltage
VSD
SD–COM
−0.5 to 7
V
Operating Case
Temperature
(2)
TC(OP) −30 to 100 °C
Junct ion Temperature(3)
T
J
150
°C
Storage Temperature
TSTG
−40 to 150
°C
Isolation Volta ge(4) VISO(RMS)
Between surface of the
case and each pin; AC,
60 Hz, 1 min
1500 V
(1) Should be derated depending on an actual case temperature. See Section 15.4.
(2) Refers to a case temperature measured during IC operation.
(3) Refers to the junction temperature of each chip built in the IC , includi ng the controller IC (MIC), transistors, and fast
recovery diodes.
(4) Refers to voltage conditions to be applied between the case and all pins. All pins have to be shorted.
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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2. Recommended Operating Conditions
Unless specifically noted, COM1 = COM2 = COM.
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Main Suppl y Voltage VDC VBB–COM — 300 400 V
Logic Supply Voltage
VCC VCCx–COM 13.5 15.0 16.5 V
VBS
VB1B–U,
VB2–V,
VB3–W1
13.5 — 16.5 V
Input Volt age
(HINx, LINx, OCP, SD, FO)
VIN 0 — 5.5 V
Minimum Input Pulse Width tIN(MIN)ON 0.5 — — μs
tIN(MIN)OFF 0.5 — — μs
Dead Time of Input Signal tDEAD 1.5 — — μs
FO P in Pull-up Resistor RFO 3.3 — 10 kΩ
FO P in Pull-up Volta ge VFO 3.0 — 5.5 V
FO Pin Noise Filter Capacitor CFO 0.001 — 0.01 μF
Bootstrap Capacitor CBOOT 1 — 220 μF
Shunt Resistor RS
IP ≤ 3 A 390 — —
mΩ
SIM6811M
IP ≤ 3.75 A 270 — — SIM6812M
IP ≤ 4.5 A 270 — —
SIM6813M
SIM6880M
IP ≤ 7.5 A 150 — —
SIM6822M
SIM6827M
RC Filter Resisto r RO — — 100 Ω
RC Filter Capacitor CO
1000 — 2200
pF
SIM6822M
SIM6827M
SIM6880M
1000 — 10000
SIM6811M
SIM6812M
SIM6813M
PWM Carrier Frequency fC — — 20 kHz
Operating Case Temperature TC(OP) — — 100 °C
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 6
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3. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 15 V, COM1 = COM2 = COM.
3.1 Characteristics of Control Parts
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Power Supply Operation
Logic Operation Start
Voltage
VCC(ON) VCCx–COM 10.5 11.5 12.5 V
VBS(ON)
VB1B–U,
VB2–V,
VB3–W1
9.5 10.5 11.5 V
Logic Operation Stop
Voltage
VCC(OFF) VCCx–COM 10.0 11.0 12.0 V
VBS(OFF)
VB1B–U,
VB2–V,
VB3–W1
9.0 10.0 11.0 V
Logic S upp l y Cur r ent
ICC
VCC1 = VCC2,
VCC pin current in 3-phase
operation
— 3.2 4.5 mA
IBS
VB1B–U or VB2–V or
VB3–W1; HINx = 5 V;
VBx pin current in 1-phase
operation
— 140 400 μA
Input Sig nal
High Level Input
Thresho ld Volta ge
(HINx, LINx, SD, FO)
VIH — 2.0 2.5 V
Lo w Leve l Input
Thresho ld Volta ge
(HINx, LINx, SD, FO)
VIL 1.0 1.5 — V
High Level Input
Current (HINx, LINx)
IIH VIN = 5 V — 230 500 μA
Low Level Inp ut Cur rent
(HINx, LINx)
IIL VIN = 0 V — — 2 μA
Fault Signal Out put
FO Pin Voltage at Fault
Signal O utput
VFOL VFO = 5 V, RFO = 10 kΩ 0 — 0.5 V
FO P in Vol tage in
Normal Operation
VFOH VFO = 5 V, RFO = 10 kΩ 4.8 — — V
Protection
OCL Pin Output Voltage
(L)
VOCL(L) 0 — 0.5 V
OCL Pin Outp ut Vo ltage
(H)
VOCL(H) 4.5 — 5.5 V
Current Limit Reference
Voltage
VLIM 0.6175 0.6500 0.6825 V
OCP Threshol d Vo ltage VTRIP 0.9 1.0 1.1 V
OCP Hold Time tP 20 25 — μs
OCP Blanking Time tBK(OCP) — 2 — μs
Current Limit Blanking
Time
tBK(OCL) — 2 — μs
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
TSD Operating
Temperature
TDH 135 150 — °C
TSD Releasing
Temperature
TDL 105 120 — °C
3.2 Bootstrap Diode Characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Bootstrap Diode Leakage
Current
ILBD VR = 500 V — — 10 μA
Bootstrap Diode Forward
Voltage
VFB IFB = 0.15 A — 1.0 1.3 V
Bootstrap Diode Series
Resistor
RBOOT 45 60 75 Ω
3.3 Thermal Resistance Characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Junction-to-Case Ther mal
Resistance(1)
RJ-C
All power M O SFETs
operating
— — 3.6 °C/W SIM681xM
R
(J-
C)Q
(2)
All IGBTs o perating — — 3.6 °C/W
SIM682xM
SIM6880M
R(J-C)F(3)
All freewheeling diodes
operating
— — 4.2 °C/W
SIM682xM
SIM6880M
Junction-to-Ambient
Thermal Resistance
RJ-A
All powe r M OSF ETs
operating
— — 25 °C/W SIM681xM
R(J-A)Q All IGBTs opera ting — — 25 °C/W
SIM682xM
SIM6880M
R(J-A)F
All freewheeling diodes
operating
— — 29 °C/W
SIM682xM
SIM6880M
(1) Refers to a case temperature at the measurement point described in Figure 3-1, below.
(2) Refers to steady-state thermal resistance between the junction of the built-in transistors and the ca se. For transient
thermal characteristics, see Section 15.1.
(3) Refers to steady-state thermal resistance between the junction of the built-in freewheeling diodes and the case.
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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Measurement point
5 mm
201
21
40
Figure 3-1. Case Temperature Measurement Point
3.4 Transistor Characteristics
Figure 3-2 provides the de fi nitions of s witching characte r istics described in this and the following sections.
HINx/
LINx
I
D
/ I
C
10%
0
V
DS
/
V
CE
t
d(on)
0
0
90%
t
r
t
on
t
rr
t
d(off)
t
f
t
off
Figure 3-2. Switching Characteristics Definitions
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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3.4.1 SIM6811M
Parameter Symbol Conditions Min. Typ. Max. Unit
Drain-to-Source Leaka ge Current IDSS VDS = 500 V, VIN = 0 V — — 100 µA
Drain-to-Source On Resi sta nc e RDS(ON) ID = 1.0 A, VIN = 5 V — 3.2 4.0 Ω
Source-to-Drain Diode Forward
Voltage
VSD ISD =1.0 A, VIN = 0 V — 1.0 1.5 V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
VDC = 300 V, IC = 1.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 150 — ns
Turn-on Delay Time td(on) — 770 — ns
Rise Time tr — 70 — ns
Turn-off Delay Time td(off) — 690 — ns
Fall Time tf — 30 — ns
Low-side Swit c hing
Source-to-Drain Diode Reverse
Recovery Time
trr
VDC = 300 V, IC = 1.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 150 — ns
Turn-on Delay Time td(on) — 690 — ns
Rise Time tr — 90 — ns
Turn-off Delay Time td(off) — 650 — ns
Fall Time tf — 50 — ns
3.4.2 SIM6812M
Parameter Symbol Conditions Min. Typ. Max. Unit
Drain-to-Source Leaka ge Current ICES VDS = 500 V, VIN = 0 V — — 100 µA
Drain-to-Source On Resi sta nc e VCE(SAT) ID = 1.25 A, VIN = 5 V — 2.0 2.4 Ω
Source-to-Drain Diode Forward
Voltage
VF ISD =1.25 A, VIN = 0 V — 1.0 1.5 V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
VDC = 300 V, IC = 1.25 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 140 — ns
Turn-on Delay Time td(on) — 910 — ns
Rise Time tr — 100 — ns
Turn-off Delay Time td(off) — 700 — ns
Fall Time tf — 40 — ns
Low-side Swit c hing
Source-to-Drain Diode Reverse
Recovery Time
trr
VDC = 300 V, IC = 1.25 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 155 — ns
Turn-on Delay Time td(on) — 875 — ns
Rise Time tr — 110 — ns
Turn-off Delay Time td(off) — 775 — ns
Fall Time tf — 35 — ns
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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3.4.3 SIM6813M
Parameter Symbol Conditions Min. Typ. Max. Unit
Drain-to-Source Leaka ge Current IDSS VDS = 500 V, VIN = 0 V — — 100 µA
Drain-to-Source On Resi sta nc e RDS(ON) ID = 1.5 A, VIN = 5 V — 1.4 1.7 Ω
Source-to-Drain Diode Forward
Voltage
VSD ISD =1.5 A, VIN = 0 V — 1.0 1.5 V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
VDC = 300 V, IC = 1.5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 170 — ns
Turn-on Delay Time td(on) — 820 — ns
Rise Time tr — 100 — ns
Turn-off Delay Time td(off) — 810 — ns
Fall Time tf — 50 — ns
Low-side Swit c hing
Source-to-Drain Diode Reverse
Recovery Time
trr
VDC = 300 V, IC = 1.5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 180 — ns
Turn-on Delay Time td(on) — 760 — ns
Rise Time tr — 130 — ns
Turn-off Delay Time td(off) — 750 — ns
Fall Time tf — 50 — ns
3.4.4 SIM6880M
Parameter Symbol Conditions Min. Typ. Max. Unit
Collector-to-E mitter Leakage
Current
ICES VCE = 600 V, VIN = 0 V — — 1 mA
Collector-to-Emitter Saturation
Voltage
VCE(SAT) IC = 3.0 A, VIN = 5 V — 1.85 2.30 V
Diode Forward Voltage VF IF = 3.0 A, VIN = 0 V — 2.0 2.4 V
High-side Switching
Diode Reverse Recovery Time trr
VDC = 300 V, IC = 3.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 100 — ns
Turn-on Delay Time td(on) — 880 — ns
Rise Time tr — 120 — ns
Turn-off Delay Time td(off) — 740 — ns
Fall Time tf — 210 — ns
Low-side Swit c hing
Diode Reverse Recovery Time trr
VDC = 300 V, IC = 3.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 100 — ns
Turn-on Delay Time td(on) — 820 — ns
Rise Time tr — 140 — ns
Turn-off Delay Time td(off) — 660 — ns
Fall Time tf — 200 — ns
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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3.4.5 SIM6822M
Parameter Symbol Conditions Min. Typ. Max. Unit
Collector-to-E mitter Leakage
Current
ICES VCE = 600 V, VIN = 0 V — — 1 mA
Collector-to-Emitter Saturation
Voltage
VCE(SAT) IC = 5 A, VIN = 5 V — 1.75 2.2 V
Diode Forward Voltage VF IF = 5 A, VIN = 0 V — 2.0 2.4 V
High-side Switching
Diode Reverse Recovery Time trr
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 80 — ns
Turn-on Delay Time td(on) — 740 — ns
Rise Time tr — 70 — ns
Turn-off Delay Time td(off) — 570 — ns
Fall Time tf — 100 — ns
Low-side Swit c hing
Diode Reverse Recovery Time trr
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 80 — ns
Turn-on Delay Time td(on) — 690 — ns
Rise Time tr — 100 — ns
Turn-off Delay Time td(off) — 540 — ns
Fall Time tf — 100 — ns
3.4.6 SIM6827M
Parameter Symbol Conditions Min. Typ. Max. Unit
Collector-to-E mitter Leakage
Current
ICES VCE = 600 V, VIN = 0 V — — 1 mA
Collector-to-Emitter Saturation
Voltage
VCE(SAT) IC = 5 A, VIN = 5 V — 1.75 2.2 V
Diode Forward Voltage VF IF = 5 A, VIN = 0 V — 2.0 2.4 V
High-side Switching
Diode Reverse Recovery Time trr
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 100 — ns
Turn-on Delay Time td(on) — 1030 — ns
Rise Time tr — 180 — ns
Turn-off Delay Time td(off) — 590 — ns
Fall Time tf — 150 — ns
Low-side Swit c hing
Diode Reverse Recovery Time trr
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C
— 100 — ns
Turn-on Delay Time td(on) — 1030 — ns
Rise Time tr — 240 — ns
Turn-off Delay Time td(off) — 540 — ns
Fall Time tf — 150 — ns
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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4. Mechanical Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Unit
Remarks
Heat s ink Mounting
Screw Torque
* 0.294 — 0.441 N∙m
Flatness of Heatsink
Attachment Area
See Figure 4-1. 0 — 60 μm
Package Weight — 5.2 — g
* When mounting a heatsink, it is recommended to use a metric screw of M2.5 and a plain washer of 6.0 mm (φ)
together at each end of it. For more details about screw tightening, see Se ction 13.2.
Heasink
+
-
+
-
Measur em ent positio n
Heatsink
Figure 4-1. Flatness Measurement Position
5. Insulation Distance
Parameter
Conditions
Min.
Typ.
Max.
Unit
Remarks
Clearance Between heatsink* and
leads. See Figure 5-1.
1.5 — 2.1 mm
Creepage 1.7 — — mm
* Refers to when a heatsink to be mounted is flat. If your application requires a clearance exceeding the maximum
distance given above, use an alternative (e.g., a convex heatsink) that will meet the target requirement.
Clearance
Creepage
Heatsink
Figure 5-1. Insulation Distance Definitions
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 13
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© SANKEN ELECTRIC CO., LTD. 2014
6. Truth Table
Table 6-1 is a truth table that provid e s the logic level definitions of oper a tion modes.
In the case where HINx and LINx signals in each phase are high at the same time, both the high- and low-side
transistors become on (simultaneous on-state). Therefore, HINx and LINx signals, the input signals for the HINx and
LINx pins, req uire dead ti me setting so that such a s imu lta neous on-state event can be avoided.
After the IC recovers from a UVLO_VCC condition, the low-side transistors resume switching in accordance with
the input logic levels of the LINx signals (level-triggered), whereas the high-side transistors resume switching at the
next rising ed ge of an HI Nx signal (edge-triggered).
After t he IC recovers from a UVLO_VB condition, the high-side transistors re sume switc hing at the ne xt risi ng edge
of an HIN x s ignal (edge-triggered).
Table 6-1. Truth Table for Operation Modes
Mode
HINx
LINx
High-side Transistor
Low-side Transistor
Normal Operation
L
L
OFF
OFF
H
L
ON
OFF
L
H
OFF
ON
H
H
ON
ON
External Shut down Signal Input
FO = Lo w Le vel
L L OFF OFF
H
L
ON
OFF
L
H
OFF
OFF
H
H
ON
OFF
Undervolt age Loc kout for
High-side Power Supply
(UVLO_VB)
L
L
OFF
OFF
H
L
OFF
OFF
L
H
OFF
ON
H
H
OFF
ON
Undervolt age Loc kout for
Low-side Power Supply
(UVLO_VCC)
L
L
OFF
OFF
H
L
OFF
OFF
L H OFF OFF
H
H
OFF
OFF
Overcurrent Protection (OCP)
L
L
OFF
OFF
H
L
ON
OFF
L
H
OFF
OFF
H
H
ON
OFF
Overcurrent Limit (OCL)
(OCL = SD)
L
L
OFF
OFF
H
L
OFF
OFF
L
H
OFF
ON
H
H
OFF
ON
Thermal Shutdown (TSD)
L L OFF OFF
H
L
ON
OFF
L
H
OFF
OFF
H H ON OFF
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SIM6822M, SIM6827M
SIM6800M Series
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7. Block Diagrams
SD
VCC1
VB1B
VB3
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB
V2
OCP
Low
Side
Driver
Input
Logic
VB1A
LS3B
LS2
UVLO UVLO UVLOUVLO
Thermal
Shutdown
OCP and OCL
Input Logic
(OCP reset )
UVLO
3
4
5
6
7
8
9
10
12
13
14
15
16
17
21
23
24
26
28
31
33
35
37
40
VB2
V
20
19
LS3A
1
LS2
2
LS1
11
High Si de
Level Shift Driver
30
Figure 7-1. SIM681xM
SD
VCC1
VB1B
VB3
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB
V2
OCP
Low
Side
Driver
Input
Logic
VB1A
LS3B
LS2
UVLO UVLO UVLO
UVLO
Thermal
Shutdown
OCP and OCL
Input Logic
(OCP reset )
UVLO
3
4
5
6
7
8
9
10
12
13
14
15
16
17
21
23
24
26
28
31
33
35
37
40
VB2
V
20
19
LS3A
1
LS2
2
LS1
11
High Si de
Level Shift Driver
30
Figure 7-2. SIM682xM or SIM688xM
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 15
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© SANKEN ELECTRIC CO., LTD. 2014
8. Pin Configuration Definitions
Top view
Pin Number
Pin Name
Description
1
LS3A
W-phase IGBT emitter, or power MOSFET source
2
LS2
V-phase IGB T emitter, or power MOSFET source
3
OCP
Overcurrent protection signal input
4
FO
Fault signal output and shutdown signal input
5
VCC2
Low-side lo gic sup p l y volta ge inp ut
6
COM2
Low-side lo gi c gr o und
7
LIN1
Logic input for U-p hase low-side gate driver
8
LIN2
Logic input for V-p hase low-side gate driver
9
LIN3
Logic input for W-phas e low-side gate driver
10
OCL
Overcurrent limit signal input
11
LS1
U-phase IGB T emitter, or power MOSFET source
12
SD
High-side shutdown signa l input
13
HIN1
Logic input for U-phase high-side gate driver
14
HIN2
Logic input for V-phase high-side gate driver
15
HIN3
Logic input for W-phase high-side gate driver
16
COM1
High-side logic gr ound
17
VCC1
High-side logic supply voltage input
18
—
(P in removed)
19
V
Bootstrap capacitor connection for V-phase
20
VB2
V-phas e high-side floating supply voltage input
21
VB1A
U-phas e high-side floating supply voltage input
22
—
(P in removed)
23
VB3
W-phase high-side floating supply voltage input
24
W1
W-phase output (connected to W2 externally)
25
NC
(No connection)
26
V1
V-phase output (connected to V2 externally)
27
—
(P in removed)
28
VBB
Positive DC bus supply voltage
29
NC
(No connection)
30
VB1B
U-phas e high-side floating supply voltage input
31
U
U-phase output
32
—
(P in removed)
33
LS2
(Pin trimmed) V-phase IGBT emitter, or power MOSFET source
34
—
(P in removed)
35
V2
V-phase output (connected to V1 externally)
36
NC
(No connection)
37
W2
W-phase output (connected to W1 externally)
38
—
(P in removed)
39
—
(P in removed)
40
LS3B
W-phase IGBT emitter, or power MOSFET source
40
1
20
21
1
20
40
21
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SIM6822M, SIM6827M
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9. Typical Applications
CR filters and Zener diodes should be added to your application as needed. This is to protect each pin against surge
voltages causing malfunctions, and to avoid the IC being used under the conditions exceeding the absolute maximum
ratings where critical damage is inevitable. Then, check all the pins thoroughly under actual operating conditions to
ensure that your a pplication works flawlessly.
SD
VCC1
VB1B
VB3
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB
V2
OCP
LS3B
LS2
40
LS3A
LS2
V
VB2
VB1A
LS1
C
FO
5 V
R
FO
R
S
R
O
C
O
V
CC
Controller
C
BOOT1
C
BOOT3
C
BOOT2
M
C
DC
C
S
V
DC
MIC
3
4
5
6
7
8
9
12
13
14
15
16
17
20
19
1
2
11
21
23
24
26
28
30
31
33
35
37
HIN 1
HIN 2
HIN 3
LIN1
LIN2
LIN3
Fault
GND
10
Figure 9-1. SIM681xM Typi ca l Application Using a Single Shunt Resistor
SD
VCC1
VB1B
VB3
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB
V2
OCP
LS3B
LS2
40
LS3A
LS2
V
VB2
VB1A
LS1
C
FO
5 V
R
FO
V
CC
Controller
C
BOOT1
C
BOOT3
C
BOOT2
M
C
DC
C
S
V
DC
MIC
3
4
5
6
7
8
9
12
13
14
15
16
17
20
19
11
21
23
24
26
28
30
31
33
35
37
HIN 1
HIN 2
HIN 3
LIN1
LIN2
LIN3
Fault
GND
10
R
O3
C
O3
R
S2
R
S1
R
O2
R
O1
C
O2
C
O1
R
S3
2
1
Figure 9-2. SIM681xM Typic a l Application Using Three Shunt Resistors
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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10. Physical Dimensions
● DIP40 Package
40
1
20
21
7.4 ±0.15
14.8
1.8
0.52
4
±0.3
7.6
+0.4
-0.3
±0.3
8.35
8.35
0.42
+0.1
-0.05
14.0
2-R1.5
33.782±0.3
+0.1
-0.05
1.15 max.
φ3.2±0.2
17.4±0.5
±0.3
±0.1
±0.3
±0.2
1.8
±0.3
1.778 ±0.25
±0.2
36
16.7
1.7min.
(Ends of pins)
Gate burr
Pin 1 indicator
Top view
● Reference Through Hole Size and Layout
120
21
40
8.7
33.7
0.04
17.4 typ.
33.782
φ1.1 typ.
Center of screw hole
Pin pich: 1.778
NOTES:
- Dimensions in millimeters
- Bare lead frame: Pb-free (RoHS compliant)
-
The leads illustrated above are for reference only, and may not be actual states of
being bent.
- Maximum gate burr height is 0.3 mm.
Unit: mm
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 18
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11. Marking Diagram
120
Par t Number
L ot Number :
Y is the last digit of th e year of man ufactu re (0 to 9)
M is the m onth of the year (1 to 9, O, N, or D)
DD is the da y of the month (01 to 31)
X is the control number
S I M 6 8 x x M
2140
Y M D D X
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 19
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12. Functional Descriptions
Unless specifically noted, this section uses the
following definitions:
● All the characteristic values given in this section are
typical values.
● All the circ uit diagra ms listed in this section r epresent
the type of IC that incorp orates power MOSFET s. All
the functional descriptions in this section are also
applicable to the type of IC that incorporates IGBTs.
● For pin and peripheral component descriptions, this
section employs a notation system that denotes a pin
name with the arbitrary letter “x”, depending on
context. Thus, “t he VC Cx pin ” is used when referring
to either or both of the VCC1 and VCC2 pins.
● The COM1 pin is always connected to the COM2 pin.
12.1 Turning On and Off the IC
The procedures listed below provide recommended
startup and shutdown sequences. To turn on the IC
properly, do not apply any voltage on the VBB, HINx,
and LI Nx pins until the VC Cx pi n volta ge has reached a
stable state (VCC(ON) ≥ 12.5 V).
It is required to fully charge bootstrap capacitors,
CBOOTx, at startup (see Section 12.2.2).
To turn off the IC, set the HINx and LINx pins to
logic low (or “L”), and then decrease the VCCx pin
voltage.
12.2 Pin Descriptions
12.2.1 U, V, V1, V2, W1, and W2
These pins are the outputs of the three phases, and
serve as the connection terminals to the 3-phase motor.
The V1 and W1 pins must be connected to the V2 and
W2 pins on a PCB, respectively.
The U, V (V1) and W1 pins are the grounds for the
VB1A (VB1B), VB2, and VB3 pins.
The U, V and W1 pins are connected to the negative
nodes of bootstrap capacitors, CBOOTx. The V pin is
internall y co nnected to the V1 pin.
Since high voltages are applied to these output pins
(U, V, V1, V2, W1, and W2), it is required to take
measures for insulating as follows:
● Keep enough distance between the output pins and
low-voltage traces.
● Coat the output pins with insulating resin.
12.2.2 VB1A, VB1B, VB2, and VB3
These pins are connected to bootstrap capacitors for
the high-side floating supply.
In actual applications, use either of the VB1A or
VB1B pin because they are internally connected.
Voltages across the VBx and these output pins should b e
maintained within the recommended range (i.e., the
Logic Supply Voltage, VBS) given in Section 2.
A bootstrap capacitor, CBOOTx, should be connected in
each of the traces between the VB1A (VB1B) and U
pins, the VB2 and V pins, the VB3 and W1 (W2) pins.
For proper s t artup, turn on the lo w-side transistor first,
then fully charge the bootstrap capacitor, CBOOTx.
For the capacitance of the bootstrap capacitors,
CBOOTx, choose the values that satisfy Equations (1) and
(2). Note that capacitance tolerance and DC bias
characteristics must be taken into account when you
choose appropriate values for CBOOTx.
C (F)>800 × t()
(1)
1 FC 220 F
(2)
In Eq uat io n (1), le t tL(OFF) be the maxi mu m off -time of
the low-side transistor (i.e., the non-charging time of
CBOOTx), measured in seconds.
Even while the high-side transistor is off, voltage
across the bootstrap capacitor keeps decreasing due to
power dissipation in the IC. When the VBx pin voltage
decreases to VBS(OFF) or less, the high-side undervoltage
lockout (UVLO_VB) starts operating (see Section
12.3.3.1). Therefore, actual board checking should be
done thoroughly to validate t hat voltage across the VB x
pin maintain s over 11.0 V (VBS > VBS(OFF)) d uri n g a low-
frequency operation such as a startup period.
As Figure 12-1 shows, a bootstrap diode, DBOOTx, and
a current-limiting resistor, RBOOTx, are internally placed
in series between the VCC1 and VB x pins.
Time constant for the charging time of CBOOTx, τ, can
be computed by Equation (3):
= C × R
, (3)
where CBOOTx is the optimized capacitance of the
bootstrap capacitor, and RBOOTx is the resistance of the
current-limiting resistor (60 Ω ± 25%).
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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VCC1
VB1B
VB3
W2
U
COM2
VCC2
COM1
W1
V1
VBB
V
VB2
VCC
CBOOT1
CBOOT3
CBOOT2
M
MIC
5
6
16
17
23
24
26
28
30
31
37
20
19
HO1
HO2
HO3
DBOOT1
DBOOT2
DBOOT3
RBOOT1
RBOOT2
RBOOT3
VDC
Figure 12-1. Bootstrap Circuit
Figure 12-2 sho ws an int ernal level-shi fting circuit. A
high-side output signal, HOx, is generated according to
an input signal on the HINx pin. When an input signal
on the HINx pin transits from low to high (rising edge),
a “Set” si gnal is generated. When the HINx i nput si gnal
transits fro m high to low ( falling edge), a “Reset” signal
is generated. These two signals are then transmitted to
the hi gh -side b y the level-shift ing circuit and are i nput to
the SR flip-flop circuit. Finally, the SR flip-flop circuit
feed s an o utput sig nal, Q (i.e., HOx).
Figure 12-3 is a timing diagram describing how noise
or other detr imental effects will i mprop erly influence t he
level-shifting process. When a noise-induced rapid
voltage drop between the VBx a nd outp ut pi ns (U, V, or
W1; hereafter “VBx–HSx”) occurs after the Set signal
generation, the next Reset signal cannot be sent to the
SR flip-flop circ uit. And the st ate of an HOx signal stays
logic high (or “H”) because the SR flip-flop does not
respond. With the HOx state being held high (i.e., the
high-side transistor is in an on-state), the next LINx
signal turns on the low-side transistor and causes a
simultaneously-on condition, which may result in
critical da mage to the IC. T o pro tect the VB x pin against
such a noise effect, add a bootstrap capacitor, CBOOTx, i n
each phase. CBOOTx must be placed near the IC, and be
connected between the VBx and HSx pins with a
minimal length of traces. To use an electrolytic capacitor,
add a 0.01 μF to 0.1 μF bypass capacitor, CPx, in parallel
near these pins used for the same phase.
HINx Input
logic Pulse
generator
COM1
Set
Reset
HOx
VBx
HSx
S
R
Q
U1
16
Figure 12-2. Internal Level-shift in g C i rcuit
HINx
Set
Reset
VBx–HSx
Q
0
VBS(OFF)
0
0
0
0
VBS(ON)
Stays logic h igh
Figure 12-3. Waveforms at VBx–HSx Voltage Drop
12.2.3 VCC1 and VCC2
These are the power supply pins for the built-in
control IC. The VCC1 and VCC2 pins must be
externally connected on a PCB because they are not
internally connected. To pr e vent ma l fu nct io n ind uce d by
supply ripples or other factors, put a 0.01 μF to 0.1 μF
ceramic capacitor, CVCC, near these pins. To prevent
damage caused by surge voltages, put an 18 V to 20 V
Zener di ode, DZ, between the VC Cx and COMx pins.
Voltages to be ap plied between the VCCx a nd COM x
pins should be regulated within the recommended
operational range of VCC, given in Sect io n 2.
VCC1
COM2
VCC2
COM1
VCC MIC
5
6
16
17
CVCC
DZ
Figure 12-4. VCCx Pin Peripheral Circuit
12.2.4 COM1 and COM2
These are the logic ground pins for the built-in control
IC. The COM1 and COM2 pins should be connected
externally on a PCB because they are not internally
connected. Varying electric p ote ntial of the logic ground
can be a cause of improper operations. Therefore,
connect the logic ground as close and short as possible
to shunt resistors, RSx, at a single-point ground (or star
ground) which is separated from the power ground (see
Figure 12-5).
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 21
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COM1
VBB
LS3A
LS2
LS1
COM2
V
DC
R
S1
R
S2
R
S3
C
DC
C
S
OCP
11
1
2
28
16
6
Cr eate a si ngle-point
ground (a star ground )
near R
Sx
, bu t ke e p it
separated from t he
p owe r ground.
Connect the COM1
and COM2 pins on
a PCB.
U1
Figure 12-5. Connections to Logic Ground
12.2.5 HIN1, HIN2, and HIN3;
LIN1, LIN2, and LIN3
These are the input pins of the internal motor drivers
for each phase. The HINx pin acts as a high-side
controller; the LINx pin acts as a low-side controller.
Figure 12-6 shows an internal circuit diagram of the
HINx or LINx pin. This is a CMOS Schmitt trigger
circuit with a built-in 20 kΩ pull-down resistor, and its
input logic is active high.
Input signals across the HINx–COMx and the LINx–
COMx pins in each phase should be set within the
ranges provided in Table 12-1, below. Note that dead
time setting must be done for HINx and LINx signals
because the IC does not have a dead time generator.
The higher PWM carrier frequency rises, the more
switching loss increases. Hence, the PWM carrier
frequency must be set so that operational case
temperatures and junction temperatures have sufficient
margins against t he absolute maximum ranges, specified
in Sectio n 1.
If the signals from the microcontroller become
unstable, the IC may result in malfunctions. To avoid
this event, the outputs from the microcontroller output
line should not be high impedance.
Also, if the traces from the microcontroller to the
HINx o r LINx pi n (or both) ar e too long, the trace s ma y
be interfered by noise. Therefore, it is recommended to
add an additional filter or a pull-down resistor near the
HINx or LINx pin as needed (see Figure 12-7).
Here are filter circuit constants for reference:
- RIN1x: 33 Ω to 100 Ω
- RINx: 1 kΩ to 10 kΩ
- CINx: 100 pF to 1000 pF
Care should be taken when adding RIN1x and RIN2x to
the traces. When they are connected to each other, the
input voltage of the HINx and LINx pins becomes
slightly lower than the output voltage of the
microcontroller.
Table 12-1. Input Signals for HINx and LINx Pins
Parameter
High Level Signal
Low Level Signal
Input
Voltage
3 V < VIN < 5.5 V 0 V < VIN < 0.5 V
Input
Pulse
Width
≥0.5 μs ≥0.5 μs
PWM
Carrier
Frequency
≤20 kHz
Dead
Time
≥1.5 μs
HINx
(LINx)
COM1
(COM2)
5 V
2 kΩ
20 kΩ
U1
2 kΩ
Figure 12-6. Internal Circuit Diagram of HINx or
LINx P in
R
IN1x
R
IN2x
C
INx
U1
Input
signal
Controller
HINx/
LINx
SIM68xxM
Figure 12-7. Filter Circuit for HINx or LINx Pin
12.2.6 VBB
This is the input pin for the main supply voltage, i.e.,
the positive DC bus. All of the IGBT collectors (power
MOSFET drains) of the high-side are connected to this
pin. Voltages between the VBB and COMx pins should
be se t wit hi n t he r ec o mme nd ed ra nge of t he mai n sup p l y
voltage, VDC, given in Section 2.
To suppress surge voltages, put a 0.01 μF to 0.1 μF
bypass capacitor, CS, near the VBB pin and an
electrolytic capacitor, CDC, with a minimal length of
PCB trac e s to the VBB p in.
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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12.2.7 LS1, LS2, LS3A, and LS3B
These are the emitter (source) pins of the low-side
IGBTs (power MOSFETs). For current detection, the
LS1, LS2, and LS3 (LS3B) pins should be connected
externally on a PCB via shunt resistors, RSx, to the
COMx pin. In actual applications, use either of the
LS3A or LS3B pin because they are internally connected.
When connecting a shunt resistor, place it as near as
possible to the IC with a minimum le ngth of tra c e s to the
LSx and COM x pi ns. Other wise, malfunction may occur
because a longer circuit trace increases its inductance
and thus increases its susceptibility to improper
operations. In applications where long PCB traces are
required, add a fast recovery diode, DRSx, between the
LSx and COMx pins in order to prevent the IC from
malfunctioning.
COM1
VBB
LS3A
LS2
LS1
COM2
V
DC
R
S1
R
S2
R
S3
C
DC
C
S
11
1
2
28
16
6
P ut a shunt resistor near
the I C with a m inimum
length to the LSx pin.
Add a fas t recover y
diode to a long trace.
D
RS1
D
RS2
D
RS3
U1
Figure 12-8. Co nnections to LSx P in
12.2.8 OCP and OCL
The OCP pin serves as the input for the overcurrent
protections which monitor the currents going through
the output transistor s.
In normal operation, the OCL pin logic level is low.
In case one or more of the protections listed below are
activated by an OCP input signal, the OCL pin logic
level becomes high. If the OCL pin is connected to the
SD pin so that the SD pin will res pond to t he O CL inp ut
signal, the high-side transistors can be turned off when
the protections (OCP and OCL) are activated.
● Overcurrent Limit (OCL)
When t he OCP pin volta ge ex ceeds the Current Limit
Reference Voltage, VLIM, the OCL pin logic level
becomes high. While the OCL is in working, the output
transistors operate according to an i nput sig nal (HI Nx or
LINx). If the OCL pin is connected to the SD pin, the
high-side transistors can be turned off. For a more
detailed OCL description, see Section 12.3.4.
● Overcurrent Pprotection (OCP)
Thi s functio n detects inrush c urrents lar ger tha n those
detected by the OCL. When the OCP pin voltage
exceeds the OCP Threshold Voltage, VTRIP, the IC
operates as follows: the OCL pin = logic high, the low-
side transist ors = off, the FO pin = logic low.
In addition, if the OC L pin is connected to the SD p in,
the high-side transistors can be turned off. For a more
detailed OCP description, see Section 12.3.5.
12.2.9 SD
When a 5 V or 3.3 V signal is input to t he SD pin, th e
high-side transisto rs tur n off i ndepe ndentl y of any HINx
signals. This i s b ec ause t he SD pin does not respond to a
pulse shorter than an i nternal filter of 3.3 μs (typ.).
The SD-OCL pin connection, as described in Section
12.2.8, allows the IC to turn off the high-side transistor s
at OCL or OCP activation. Also, inputting the inverted
signal of the FO pin to the SD pin permits all the high-
and low-side transistors to turn off, when the IC detects
an abnormal condition (i.e., some or all of the
protections such as TSD, OCP, and UVLO are activated).
12.2.10 FO
This pin operates as the fault signal output and the
low-side shutdown signal input. Sections 12.3.1 and
12.3.2 explain the two functions in detail, respectively.
Figure 12-9 illustrates an internal circuit diagram of the
FO pin and its pe ripheral circ uit.
5 V
50 Ω
2 kΩ1 MΩ
Blanking
filter
Output SW turn-off
a nd Q
FO
turn-on
Q
FO
3.0 µs (typ.)
V
FO
C
FO
INT
R
FO
U1
FO
COM
Figure 12-9. Internal Circu it Diagram of FO Pin and
Its Peripheral Circuit
Because of its open-collector nature, the FO pin
should be tied by a pull-up resistor, RFO, to the external
power supply. The external power supply voltage (i.e.,
the FO P in Pull -up Volta ge, VFO) should range from 3.0
V to 5.5 V. When the pull-up resistor, RFO, has a too
small resistance, the FO pin voltage at fault signal output
becomes high due to the saturation voltage drop of a
built-in transistor, QFO. Therefore, it is recommended to
use a 3.3 kΩ to 10 kΩ pull-up r esist or . To suppre ss noise ,
add a filter capacitor, CFO, near the I C with mini miz i ng a
trace le ngth betwe en the FO and COMx pins.
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To avoid the repetition of OCP activations, the
external microcontroller must shut off any input signals
to the I C withi n a n OCP ho ld t i me, tP, which occurs after
the internal transistor (QFO) turn-on. tP is 15 μs where
minimum values of thermal characteristics are taken into
account. (For more details, see Section 12.3.5.) Our
recommendation is to use a 0.001 μF to 0.01 μF filter
capacitor.
12.3 Protection Functions
This section describes the various protection circuits
provided in the SIM6800M series. The protection
circuits include the undervoltage lockout for power
supplie s (UVLO) , the overcurrent pr otection (OCP) , and
the thermal shutdown (TSD). In case one or more of
these protection circuits are activated, the FO pin
outputs a fault signal; as a result, the external
microcontroller can stop the operations of the three
phases by receiving the fault signal. The external
microcontroller can also shut down IC operations by
inputting a fault signal to the FO pin.
In the following functional descriptions, “HOx”
denotes a gate input signal on the high-side transistor,
whereas “LOx” denotes a gate input signal on the low-
side transist or..
12.3.1 Fault Signal Output
In case one or more of the following protections are
actuated, an internal transistor, QFO, turns on, then the
FO pin becomes logic low (≤0.5 V).
1) Low-side undervoltage lockout (UVLO_VCC)
2) Overcurrent protection (OCP)
3) Thermal shut down (TSD)
While the FO pin is in the low state, all the low-side
transistors turn off. In normal operation, the FO pin
outputs a high signal of 5 V. T he fault signal outp ut ti me
of the FO pin at OCP activation is the OCP hold time
(tP) of 25 μs (typ.), fixed by a built-in feature of the IC
itself (see Section 12.3.5). The external microcontroller
rec eives the faul t signals wit h its interrupt pi n (INT), and
must be programmed to put the HINx and LINx pins to
logic low within t he predeter mined OCP hold time, tP.
12.3.2 Shutdown Signal Input
The FO pin also acts as the input pin of shutdown
signals. When the FO pin becomes logic low, all the
low-side transistors tur n o f f.
The voltages and puls e widths of the shutdown s ignals
to be applied between the FO and COMx pins are listed
in Table 12-2.
Table 12-2. Shutdown Signals
Parameter High Level Signal Low Level Signal
Input Volt age 3 V < VIN < 5.5 V 0 V < VIN < 0.5 V
Input Pulse
Width
— ≥6 μs
12.3.3 Undervoltage Lockout for
Power Supply (UVLO)
In case the gate-driving voltages of the output
transistors decrease, their steady-state p ower dissipa tions
increase. This overheating condition may cause
permanent damage to the IC in the worst case. To
prevent this event, the SIM6800M series has the
undervoltage lockout (UVLO) circuits for both of the
high- and low-side power supplies in the monolithic IC
(MIC).
12.3.3.1. Undervoltage Lockout for
High-side Power Supply
(UVLO_VB)
Figure 12-10 shows operational waveforms of the
undervoltage lockout for high-side power supply (i.e.,
UVLO_VB).
LINx
HINx
VBx-HSx
HOx
LOx
FO
V
BS(OFF)
V
BS(ON)
No FO output at
UVLO_VB.
0
0
0
0
0
0
UV LO rele ase
UVLO_VB
operation
About 3 µs
HOx restarts at
positive edge after
UVLO_VB release.
Figure 12-10. UVLO_VB Operational Waveforms
When the voltage between the VBx and output pins
(VBx–HSx shown in Figure 12-10) decreases to the
Logic Oper ation Stop Voltage (VBS(OFF), 10.0 V) or le ss,
the UVLO_VB circuit in the corresponding phase gets
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activated a nd sets an HOx sig nal to logic low. W hen t he
voltage between the VBx and HSx pins increases to the
Logic Oper a tion Start Vo ltage ( V BS(ON), 10.5 V) or more,
the IC releases the UVLO_VB operation. Then, t he H O x
signal becomes logic high at the rising edge of the first
input command after the UVLO_VB release. Any fault
signals are not output from the FO pin during the
UVLO_VB operation. In addition, the VBx pin has an
internal UVLO_VB filter of about 3 μs, in order to
prevent noise-induced malfunctions.
12.3.3.2. Undervoltage Lockout for
Low-side Power Supply
(UVLO_VCC)
Figure 12-11 shows operational waveforms of the
undervoltage lockout for low-side power supply (i.e.,
UVLO_VCC).
When the VCC2 pin voltage decreases to the Logic
Operation Stop Voltage (VCC(OFF), 11.0 V) or less, the
UVLO_VCC circuit in the corresponding phase gets
activated a nd se ts bo th of H Ox a nd LOx signal s to logic
low. Whe n the V CC2 pin voltage increases to the Logic
Operation Start Voltage (VCC(ON), 11.5 V) or more, the
IC releases the UVLO_VCC operation. Then, the IC
resumes the following transmissions: an LOx signal
according to an LINx pin input command; an HOx
signal according to the rising edge of the first HINx pin
input command after the UVLO_VCC release. During
the UVLO_VCC operation, the FO pin becomes logic
low and sends fault signals. In addition, the VCC2 pin
has an internal UVLO_VCC filter of about 3 μs, in order
to prevent nois e-i nduc ed ma lf unct i o ns.
About 3 µs
LINx
HINx
VCC2
HOx
LOx
FO
V
CC(OFF)
V
CC(ON)
LOx r esponds to input si gnal.
0
0
0
0
0
0
UVLO_VCC
operation
Figure 12-11. UVLO_VCC Operational Waveforms
12.3.4 Overcurrent Limit (OCL)
The overcurrent limit (OCL) is a protection against
relatively low overcurrent conditions. Figure 12-12
shows an internal circuit of the OCP and OCL pins;
Figure 12-13 shows OCL operational waveforms.
When the OCP pin voltage increases to the Current
Limit Reference Voltage (VLIM, 0.6500 V) or more, and
remains in this condition for a period of the Current
Limit Blanking Ti me (tBK(OCP), 2 μs) or longer, the OCL
circuit is activated. Then, the O C L pin go es lo gic hig h.
During the OCL operation, the gate logic levels of the
low-side tr ansist ors respond to an inp ut co mma nd o n the
LIN x pi n. T o turn off the high-side tr a nsi st o rs d ur i ng t he
OCL operation, c onnec t the OCL and SD pins on a PCB.
The SD pin has an internal filter of about 3.3 μs (typ.).
When the OCP pin voltage falls below VLIM (0.6500
V), the OCL pin logic level becomes low. After the O CL
pin logic has become low, the high-side transistors
remain tur ned o ff until t he first lo w-to-high t ra nsit ion o n
an HINx input s ignal occurs (i.e., edge-triggered).
OCP
COM2
200 kΩ
U1
2 kΩ
3
6
OCL
0.65 VFilter
200 kΩ
2 kΩ
10
Figure 12-12. Internal Circuit o f OCP and OCL Pins
LINx
HINx
OCP
HOx
LOx
OCL
(SD)
V
LIM
0
0
0
0
0
0
t
BK(OCP)
3.3 µs (typ.)
HOx restarts at
positive edge after
OCL release.
Figure 12-13. OCL Operational Waveforms
(OCL = SD)
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12.3.5 Overcurr en t Prot ec ti on (OCP)
The overcurrent protection (OCP) is a protection
against large inrush currents (i.e., high di/dt). Figure
12-14 is an internal circuit diagram describing the OCP
pin and its perip her a l c ircuit.
The OCP pin d etects overcurrents with voltage across
external shunt resistors, RSx. Because the OCP pin is
internally pulled down, the OCP pin voltage increases
proportionally to a rise in the currents running through
the s hunt r esis t ors, RSx.
Figure 12-15 is a timing chart that represents
operation waveforms during OCP operation. When the
OCP pin voltage increases to the OCP Threshold
Voltage (VTRIP, 1.0 V) or more, and remains in this
condition for a period of the OCP Bla nking T ime (tBK, 2
μs) or longer, the OCP circuit is activated. The enabled
OCP circuit shuts off the low-side transistors and puts
the FO pin into a low state. Then, output current
decreases as a result of the output transistors turn-off.
Even if the OCP pin voltage falls below VTRIP, the IC
holds the FO pin in the low state for a fixed OCP hold
time (tP) of 25 μs (typ.). Then, the output transistors
operate ac cord ing to input s ig nals.
The OCP is used for detecting abnormal conditions,
such as an output transistor shorted. In case short-circuit
conditions occur repeatedly, the output transistors can be
destroyed. To prevent such event, motor operation must
be controlled by the external microcontroller so that it
can immediately stop the motor when fault signals are
detected.
For proper shunt resistor setting, your application
must meet the following:
● Use the shunt resistor that has a recommended
resistance, RSx (see Section 2).
● Set the OCP pin inp ut volta ge to va r y wit hin t he r ated
OCP pin vo lta ges, V OCP (see S ection 1).
● Keep the current through the output transistors below
the rated output current (pulse), IOP (see Section 1).
It is required to use a resistor with low internal
inductance because high-frequency switching current
will flow through the shunt resistors, RSx. In addition,
choose a resistor with allowable power dissipation
according to your application.
When you connect a CR filter (i.e., a pair of a filter
resistor, RO, and a filter capacitor, CO) to the OCP pin,
care should be taken in setting the time constants of RO
and CO. T he lar ger t he ti me c o nsta nt, t he lo nger the time
that the OCP pin voltage rises to VTRIP. And this may
cause permanent damage to the transistors.
Consequently, a propagation delay of the IC must be
taken into account when you determine the time
constants. For RO and CO, their time constants must be
set to the values listed in Table 12-3. And place CO as
close as possible to the IC with minimizing a trace
length between the OCP and COM x pins.
Note that overcurrents are undetectable when one or
more of the U, V/V1/V2, and W1/W2 pins or their traces
are shorted to ground (ground fault). In case any of these
pins falls into a state of ground fault, the output
transistor s may be destr oyed.
VBB
LSx
COM
OCP
COM2
A/D
RSx
ROx
CO
DRSx
VTRIP
200 kΩBlanking
filter
Output SW turn-off
a nd Q
FO
turn-on
-
+
1.65 µs (typ.)
U1
3
6
28
2 kΩ
Figure 12-14. Internal Circuit Diagram of OCP Pin
and Its Peripheral Circuit
LINx
HINx
HOx
LOx
FO
0
0
0
0
0
OCP
V
TRIP
t
BK
t
BK
t
P
t
BK
0
V
LIM
HOx responds to input signal.
FO restarts
automatically after t
P
.
Figure 12-15. OCP Operational Waveforms
Table 12-3. Reference Time Constants for CR Filter
Part Number
Time Constant
(µs)
SIM681x ≤2
SIM682x
SIM688x
≤0.2
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12.3.6 Thermal Shutdown (TSD)
The SIM6800M series incorporates a thermal
shutdown (TSD) circuit. Figure 12-16 shows TSD
operational waveforms. In case of overheating (e.g.,
increased power dissipation due to overload, a rise in
ambient temperature at the device, etc.), the IC shuts
down the low-side output tran sisto r s.
The T SD circuit in the monol ithic IC (MIC) monitors
temperatures (see Section 7). When the temperature of
the monolithic IC (MIC) exceeds the TSD Operating
Temperature (TDH, 150 °C), the TSD circuit is activated.
When the temperature of the monolithic IC (MIC)
decreases to the TSD Releasing Temperature (TDL,
120 °C) or less, the shutdown condition i s released. The
output transistors then resume operating according to
input si g nal s.
During the TSD operation, the FO pin becomes logic
low and trans mits fault signals .
Note that junction temperatures of the output
transistors themselves are not monitored; therefore, do
not use the TSD function as an overtemperature
prevention for the output tran sistors.
LINx
HINx
T
j(MIC)
HOx
LOx
FO
LOx responds to input signals.
T
DH
T
DL
0
0
0
0
0
0
TSD operation
Figure 12-16. TSD Operational Waveforms
13. Design Notes
13.1 PCB Pattern Layout
Figure 13-1 shows a schematic diagram of a motor
driver circuit. The motor driver circuit consists of
current paths having h igh fre quenc ies a nd hig h volta ges,
which also bring about negative influences on IC
operation, noise interference, and power dissipation.
Therefore, PCB trace layo uts and component placements
play an important role in circu it designing.
Current loops, which have high frequencies and high
voltages, should be as small and wide as possible, in
order to maintain a low-impedance state. In addition,
ground traces should be as wide and short as possible so
that radiated EMI levels can be reduced.
W2
U
W1
V1
VBB
V2
LS3A
LS2
1
MIC
24
26
28
31
2
35
37
M
VDC
High-frequency, high-voltage
current loops should be a s
s mall and wi de a s pos sible.
Grou nd traces
s hould be wi de
a n d s ho rt.
11 LS1
Figure 13-1. High-fr equency, High-vol tage Current
Paths
13.2 Considerations in Heatsink Mounting
The following are the key considerations and the
guidelines fo r mounti ng a heats i nk:
● It is recommended to use a pair of a metric screw of
M2.5 and a plain washer of 6.0 mm (φ). To tighten
the screws, use a torque screwdriver. Tighten the two
screws firstly up to about 30% of the maximum screw
torque, then finally up to 100% of the prescribed
maximum screw torque. Perform appropriate
tightening within the range of screw torque defined in
Section 4.
Not Recommended for New Designs:
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● When mounting a heatsink, it is recommended to use
silicone greases. If a thermally conductive sheet or an
electrically insulating sheet is used, package cracks
may be occurred due to creases at screw tightening.
Therefore, you should conduct thorough evaluations
before using these materials.
● When applying a silicone grease, make sure that there
must be no foreign substances between the IC and a
heatsink. Extreme care should be taken not to apply a
silicone grease onto any device pins as much as
possible. The following requirements must be met for
proper grease application:
- Grease thi ckness: 100 µm
- Heatsink flatness: ±100 µm
- Apply silicone grease within the area indicated in
Figure 13-2, below.
Heatsink
Thermal silicone
gr ease application area
1.251.25 31.3
Unit: mm
7.4
7.4 M2.5 M2.5
Scr ew ho le Scr ew ho le
Figure 13-2. Reference Application Area for Thermal
Silicone Grease
13.3 Considerations in IC Characteristics
Measurement
When measuring the breakdown voltage or leakage
current of the transis tors inco rpo rate d in the IC, note that
the gate and emitter (source) of each transistor should
have the same potential. Moreover, care should be taken
when performing the measurements, because each
transistor is connected as follows:
● All the high-side collectors (drains) are internally
connected to the VBB pin.
● In the U-phase, the high-side emitter (source) and the
low-side collector (drain) are internally connected,
and are also connected to the U pin.
(In the V- and W-phases, the high- and low-side
transistors are unconnected inside the IC.)
The gates of t he high -side transisto rs are pulled down
to the corresponding output (U, V/V1, and W1) pins;
similarly, the gates of the low-side transistors are pulled
down to t he COM2 pin.
When measuring the breakdown voltage or leakage
current of the transistors, note that all of the output (U,
V/V1, and W1), LSx, and COMx pins must be
appropriately connected. Otherwise the switching
trans istors may result in permanent damage.
The following are circuit diagrams representing
typical measurement circuits for breakdown voltage:
Figure 13-3 shows the high-side transistor (Q1H) in the
U-phase; Figure 13-4 shows the low-side trans istor ( Q1L)
in the U-phase. And all the pins that are not represented
in these figures are open.
When measuring the high-side transistors, leave all
the pins not be measured open. When measuring the
low-side transistors, connect the LSx pin to be measured
to the COMx p in, then leave other unused pins open.
W2
U
COM2
COM1
W1
V1
VBB
V2
LS3B
LS2
40
LS3A
LS2
V
LS1
MIC
16
1
2
24
26
33
35
37
19
Q
1H
Q
1L
Q
2L
Q
3L
Q
2H
Q
3H
V
11
6
31
28
Figure 13-3. Typical Meas ure ment Circuit for High-
side Tra nsist or (Q1H) in U -phase
W2
U
COM2
COM1W1
V1
VBB
V2
LS3B
LS2
40
LS3A
LS2
V
LS1
MIC
16
1
2
24
26
28
33
35
37
19
Q
1H
Q
1L
Q
2L
Q
3L
Q
2H
Q
3H
V
11
6
31
Figure 13-4. Typical Meas ure ment Circuit for Low-
side Tra nsist or (Q1L) in U -phase
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14. Calculating Power Losses and
Estimating Junction Temperatures
This section describes the procedures to calculate
power losses in switching transistors, and to estimate a
junction temperature. Note that the descriptions listed
here are applicable to the SIM6800M series, which is
controlled by a 3-phase sine-wave PWM driving
strategy.
For quick and easy references, we offer calculation
support tools online. Please visit our website to find out
more.
● DT0026: SIM 681xM Calculation Tool
http://www.semicon.sanken-ele.co.jp/en/calc-
tool/sim681xm_caltool_en.html
● DT0027: SIM682xM and SIM6880M Calculation
Tool
http://www.semicon.sanken-ele.co.jp/en/calc-
tool/sim682xm_caltool_en.html
14.1 IGBT
Total power loss in an IGBT can be obtained by
taking the sum of steady-state loss, PON, and switching
loss, PSW. The following subsections contain the
mathematical procedures to calculate these losses (PON
and PSW) and the junction temperature of all IGBTs
operating.
14.1.1 IGBT Steady-state Loss, PON
Steady-state loss in an IGBT can be computed by
using the VCE(SAT) vs. IC curves, listed in Section 15.3.1.
As expressed by the curves in Figure 14-1, linear
approximations at a range the IC is actually used are
obtained by: VCE(SAT) = α × IC + β. T he value s gained by
the above calculation are then applied as parameters in
Equation (4), below. Hence, the equation to obtain the
IGBT steady-state loss, PON, is:
P
=1
2V
()
()× I
()×DT × d
= 1
21
2+4
3M × cos I
+2
1
2+
8M × cos I .
(4)
Where:
VCE(SAT) is the collector-to-emitter saturation voltage of
the IGBT (V),
IC is the collector current of the IGBT (A),
DT is the dut y cycle, which is given b y
DT =1 + M × sin(+)
2 ,
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear approximation in the
VCE(SAT) vs. IC curve, and
β is the intercept of the linear approximation in the
VCE(SAT) vs. IC curve.
Figure 14-1. Linear Approximate Equation of
VCE(SAT) vs. I C Curve
14.1.2 IGBT Switching Loss, PSW
Switching loss in an IGBT can be calculated by
Equation (5), letting IM be the effective current value of
the motor:
P
=2
× f×× I×V
300 .
(5)
Where:
fC is the PWM carrier frequency (Hz),
VDC is the main power supply voltage (V), i.e., the
VBB pin input voltage, and
αE is the slop e of the switching loss c urve (see Section
15.3.2).
14.1.3 Estimating Junction Temperature
of IGBT
The junction temperature of all IGBTs operating, TJ,
can be estimated with Equation (6):
T= R()×{(P
+ P
)× 6}+ T .
(6)
Where:
R(J-C)Q is the junction-to-case thermal resistance
(°C/W) of all the IGBTs operating, and
TC is the case temperature (°C), measured at the point
defined in Figure 3-1.
y = 0.19x + 0.92
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0 1.0 2.0 3.0 4.0 5.0
V
CE(SAT)
(V)
I
C
(A)
VCC = 15 V
25°C
75°C
125°C
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14.2 Power MOSFET
Total power loss in a power MOSFET can be
obtained by taking the sum of the following losses:
steady-state loss, PRON; switching loss, PSW; the steady-
state loss of a body diode, PSD. In the calculation
procedure we offer, the recovery loss of a body diode,
PRR, is considered negligibly small compared with the
ratios of other losses.
The following subsections contain the mathematical
procedures to calculate these l osse s (P RON, PSW, and PSD)
and the junction temperature of all power MOSFETs
operating.
14.2.1 Power MOSFET Steady-state Loss,
PRON
Steady-state loss in a power MOSFET can be
computed by using the RDS(ON) vs. ID curves, listed in
Section 15.3.1. As expressed by the curves in Figure
14-2, linear approximations at a range the ID is actually
used are obtained by: RDS(ON) = α × ID + β. The values
gained by the above calculation are then applied as
parameters in Equation (7), below. Hence, the equation
to obtain the power MOSFET steady-state loss, PRON, is:
P
=1
2I
()
× R
()
()×DT × d
= 22 1
3+3
32 M × cos I
+21
8+1
3M × cos I .
(7)
Where:
ID is the drain current of the power MOSFET (A),
RDS(ON) is the drain-to-source on-resistance of the
po wer MOSFE T (Ω),
DT is the dut y cycle, which is given b y
DT =1 + M × sin(+)
2 ,
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear approximation in the R DS(ON)
vs. ID curve , and
β is the intercept of the linear approximation in the
RDS(ON) vs. ID curve.
Figure 14-2. Linear Approximate Equation of
RDS(ON) vs. ID Curve
14.2.2 Power MOSFET Switching Loss,
PSW
Switching loss i n a po wer MOSFET can be calculated
by Eq uation (8), letting IM be the effective current value
of the motor:
P
=2
× f×× I×V
300 .
(8)
Where:
fC is the PWM carrier frequency (Hz),
VDC is the main power supply voltage (V), i.e., the
VBB pin input voltage, and
αE is the slop e of the switching loss c urve (see Section
15.3.2).
14.2.3 Body Diode Steady-state Loss, PSD
Steady-state loss in the body diode of a power
MOSFET can be computed by using the VSD vs. ISD
curves, listed in Section 15.3.1. As expressed by the
curves in Figure 14-3, linear approximations at a range
the ISD is actuall y used are obtained by: VSD = α × ISD + β.
The values gained by the above calculation are then
applied as parameters in Equation (9), below. Hence, the
equation to obtain the body diode steady-state loss, PSD,
is:
P
=1
2V
()× I
()×(1DT)× d
= 1
2
1
2
4
3
M × cos I
+2
1
2
8
M × cos I . (9)
0
1
2
3
4
5
6
7
8
0.0 0.5 1.0 1.5 2.0
R
DS(ON)
(Ω)
I
D
(A)
VCC = 15 V
25°C
75°C
125°C
y = 0.53x + 5.64
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Where:
VSD is t he so urce -to-drain diode forward voltage of t he
po wer MOSFE T (V),
ISD is the source-to-drain diode forward current of the
po wer MOSFE T (A),
DT is the dut y cycle, which is given b y
DT =1 + M × sin(+)
2 ,
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear app roximatio n i n t he VSD vs.
ISD curve, and
β is the intercept of the linear approximation in the
VSD vs. ISD curve.
Figure 14-3. Linear Approximate Equation of
VSD vs. ISD Curve
14.2.4 Estimating Junction Temperature
of Power MOSFET
The junction temperature of all power MOSFETs
operating, TJ, can be estimated with Equation (10):
T= R ×{(P
+ P
+ P
)× 6}+ T .
(10)
Where:
RJ-C is the junction-to-case thermal resistance (°C/W)
of all the power MOSFETs operating, and
TC is the case temperature (°C), measured at the point
defined in Figure 3-1.
y = 0.24x + 0.55
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5 2.0
VSD (V)
I
SD
(A)
25°C 75°C
125°C
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15. Performance Curves
15.1 Transient Thermal Resistance Curves
The following graphs represent transient thermal resistance (the ratios of transient thermal resistance), with steady-
state thermal resistance = 1.
Figure 15-1. Transient Thermal Resistance Curve: SIM681xM
Figure 15-2. Transient Thermal Resistance Curve: SIM682xM
Figure 15-3. Transient Thermal Resistance Curve: SIM6818M
0.01
0.10
1.00
0.001 0.01 0.1 1 10
Ratio of Transient Thermal
Resistance
Time (s)
0.01
0.10
1.00
0.001 0.01 0.1 1 10
Ratio of Transient Thermal
Resistance
Time (s)
0.01
0.10
1.00
0.001 0.01 0.1 1 10
Ratio of Transient Thermal
Resistance
Time (s)
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15.2 Performance Curves of Control Parts
Figure 15-4 to Figure 15-28 provide performance curves of the control parts integrated in the SIM6800M series,
including variety-dependent characteristics and thermal characteristics. TJ represents the junction temperature of the
control pa rts.
Table 15-1. Typical Characteristics of Control Parts
Figure Number
Figure Caption
Figure 15-4
Logic S upp l y Cur r ent , ICC vs. T C (INx = 0 V)
Figure 15-5
Logic S upp l y Cur r ent , ICC vs. TC (INx = 5 V)
Figure 15-6
VCCx P in Vo ltage, VCC vs. Lo gi c Suppl y Current, ICC curve
Figure 15-7
Logic S upp l y Cur r ent (1-phase) IBS vs. TC (HINx = 0 V)
Figure 15-8
Logic S upp l y Cur r ent (1-phase) IBS vs. TC (HINx = 5 V)
Figure 15-9
VBx Pin Voltage, VB vs. Logic Supply Curr ent, IBS (HINx = 0 V)
Figure 15-10
Logic Operation Start Voltage, VBS(ON) vs. TC
Figure 15-11
Logic Operation Stop Vo lta ge, VBS(OFF) vs. TC
Figure 15-12
Logic Operation Start Voltage, VCC(ON) vs. TC
Figure 15-13
Logic Operation Stop Voltage, VCC(OFF) vs. TC
Figure 15-14
UVLO_VB Filtering Ti me vs. TC
Figure 15-15
UVLO_VCC Filtering Time vs. TC
Figure 15-16
High Level Input Thre s hold Vo ltage, VIH vs. T C
Figure 15-17
Lo w Leve l Input Thresho l d Voltage, VIL vs. TC
Figure 15-18
Input Current a t Hi gh Le vel (HINx or LINx), IIN v s . TC
Figure 15-19
High-side T urn-on Propagation Delay vs. TC (from HINx to HOx)
Figure 15-20
Low-side Turn-on Propagatio n Delay vs. TC (from LINx to LOx)
Figure 15-21
Minimum Tr a nsmittable Pul se Wid th for H igh-side Switching, tHIN(MIN) vs. TC
Figure 15-22
Minimum Tr a nsmittable Pul se Wid th for Low-sid e Switching, tLIN(MIN) vs. TC
Figure 15-23
SD Pin Filtering Time vs. TC
Figure 15-24
FO Pin Filtering Time vs. TC
Figure 15-25
Current Limit Reference Voltage, VLIM vs. TC
Figure 15-26
OCP Thre s hold Volt age, VTRIP vs. TC
Figure 15-27
OCP Hold Time, tP vs. TC
Figure 15-28
OCP B lanking Time, tBK(OCP) vs . T C; Current Limit Blanking T ime, tBK(OCL) vs. TC
Figure 15-4. Logic Supply Current, ICC vs. TC
(INx = 0 V) Figure 15-5. Logic Supply Current, ICC vs. TC
(INx = 5 V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
ICC (mA)
TC (°C)
Max.
Typ.
Min.
VCCx = 15 V, HINx = 0 V, LINx = 0 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
ICC (mA)
TC (°C)
Max.
Typ.
Min.
VCCx = 15 V, HINx = 5 V, LINx = 5 V
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Figure 15-6. VCCx Pin V oltage, VCC vs. Logic
Supply Current, ICC curve Figure 15-7. Logic Supply Curre nt (1-phase) I BS vs. TC
(HINx = 0 V)
Figure 15-8. Logi c Supply Current (1-phase) IBS vs.
TC (HINx = 5 V) Figure 15-9. VBx Pi n Volt age, VB vs. Logic Supply
Current, IBS ( HI Nx = 0 V)
Figure 15-10. Logic Operation Start Voltage, VBS(ON)
vs. TC Figure 15-11. Logic Oper ation Stop Volta ge, VBS(OFF)
vs. TC
2.6
2.8
3.0
3.2
3.4
3.6
3.8
12 13 14 15 16 17 18 19 20
ICC (mA)
V
CC
(V)
HINx = 0 V, LINx = 0 V
−30°C
25°C
125°C
0
50
100
150
200
250
-30 0 30 60 90 120 150
IBS (µA)
TC (°C)
VBx = 15 V, HINx = 0 V
Max.
Typ.
Min.
0
50
100
150
200
250
300
-30 0 30 60 90 120 150
IBS (µA)
TC (°C)
VBx = 15 V, HINx = 5 V
Max.
Typ.
Min.
40
60
80
100
120
140
160
180
12 13 14 15 16 17 18 19 20
IBS (µA)
VB (V)
VBx = 15 V, HINx = 0 V
−30°C
25°C
125°C
9.5
9.7
9.9
10.1
10.3
10.5
10.7
10.9
11.1
11.3
11.5
-30 0 30 60 90 120 150
VBS(ON) (V)
TC (°C)
Max.
Typ.
Min.
9.0
9.2
9.4
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
-30 0 30 60 90 120 150
VBS(OFF) (V)
TC (°C)
Max.
Typ.
Min.
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Figure 15-12. Logic Operation Start Voltage, VCC(ON)
vs. TC Figure 15-13. Logic Opera tion Stop Volta ge, VCC(OFF)
vs. TC
Figure 15-14. UVLO_VB Filter ing Time vs. T C Figure 15-15. UVLO_VCC Filtering Ti me vs. TC
Figure 15-16. High Level Input Thre s hold Volt age,
VIH vs. TC Figure 15-17. Low Leve l Input Threshold V olta ge, VIL
vs. TC
10.5
10.7
10.9
11.1
11.3
11.5
11.7
11.9
12.1
12.3
12.5
-30 0 30 60 90 120 150
V
CC(ON)
(V)
TC (°C)
Max.
Typ.
Min.
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
11.6
11.8
12.0
-30 0 30 60 90 120 150
VCC(OFF) (V)
TC (°C)
Max.
Typ.
Min.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
UVLO_VB Filtering Time (µs)
TC (°C)
Max.
Typ.
Min.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
UVLO_VCC Filtering Time (µs)
TC (°C)
Max.
Typ.
Min.
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
-30 0 30 60 90 120 150
VIH (V)
TC (°C)
Max.
Typ.
Min.
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-30 0 30 60 90 120 150
VIL (V)
TC (°C)
Max.
Typ.
Min.
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Figure 15-18. Input Current at High Level (HINx or
LINx), IIN vs. TC Figure 15-19. High-side Turn-on Propaga t ion Dela y vs .
TC (from HINx to HOx)
Figure 15-20. Low-side Turn-on Pro paga t ion Dela y
vs. TC (from LIN x to LOx) Figure 15-21. Mini mu m Tr a ns mittable Pulse Width for
High-side Switc hing, tHIN(MIN) vs. TC
Figure 15-22. Minimum Transmittable Pulse Width
for Low-side Switching, tLIN(MIN) vs. TC Figure 15-23. SD P in Filter ing Time vs. TC
0
50
100
150
200
250
300
350
400
-30 0 30 60 90 120 150
IIN (µA)
TC (°C)
INHx or INLx = 5 V
Max.
Typ.
Min.
0
100
200
300
400
500
600
700
800
-30 0 30 60 90 120 150
High-side T ur n-on
Propaga tion Dela y (ns)
TC (°C)
Max.
Typ.
Min.
0
100
200
300
400
500
600
700
-30 0 30 60 90 120 150
Low-side Turn-on Propaga tion
Delay (ns)
TC (°C)
Max.
Typ.
Min.
0
50
100
150
200
250
300
350
400
-30 0 30 60 90 120 150
tHIN(MIN) (ns)
TC (°C)
Max.
Typ.
Min.
0
50
100
150
200
250
300
350
400
-30 0 30 60 90 120 150
tLIN(MIN) (ns)
TC (°C)
Max.
Typ.
Min.
0
1
2
3
4
5
6
-30 0 30 60 90 120 150
tSD (ns)
TC (°C)
Max.
Typ.
Min.
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Figure 15-24. FO Pin Filtering Time vs. TC Figure 15-25. Current Limit Reference Voltage, VLIM vs.
TC
Figure 15-26. OCP Threshold Volt age, VTRIP vs. TC Figure 15-27. OCP Hold Tim e , tP vs. TC
Figure 15-28. OCP Blanki ng Time, tBK(OCP) vs. TC;
Current Limit Blanking Time, tBK(OCL) vs. T C
0
1
2
3
4
5
6
-30 0 30 60 90 120 150
tFO (ns)
TC (°C)
Max.
Typ.
Min.
0.550
0.575
0.600
0.625
0.650
0.675
0.700
0.725
0.750
-30 0 30 60 90 120 150
VLIM (ns)
TC (°C)
Max.
Typ.
Min.
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
-30 0 30 60 90 120 150
VTRIP (ns)
TC (°C)
Max.
Typ.
Min.
0
5
10
15
20
25
30
35
40
45
50
-30 0 30 60 90 120 150
tP (µs)
TC (°C)
Max.
Typ.
Min.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-30 0 30 60 90 120 150
tBK (µs)
TC (°C)
Max.
Typ.
Min.
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15.3 Performance Curves of Output Parts
15.3.1 Output Transistor Performance Curves
15.3.1.1. SIM6811M
Figure 15-29. Power MOSFET RDS(ON) vs. ID Figure 15-30. Power MOSFET VSD vs. ISD
15.3.1.2. SIM6812M
Figure 15-31. Power MOSFET RDS(ON) vs. ID Figure 15-32. Power MOSFET VSD vs. ISD
0
1
2
3
4
5
6
7
8
0.0 0.5 1.0 1.5 2.0
R
DS(ON)
(Ω)
I
D
(A)
VCC = 15 V
25°C
75°C
SIM6811M
125°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5 2.0
VSD (V)
ISD (A)
25°C 75°C
125°C
SIM6811M
0
1
2
3
4
5
0.0 0.5 1.0 1.5 2.0 2.5
RDS(ON) (Ω)
ID (A)
VCC = 15 V
25°C
75°C
125°C
SIM6812M
0
0.2
0.4
0.6
0.8
1
1.2
0.0 0.5 1.0 1.5 2.0 2.5
VSD (V)
ISD (A)
25°C 75°C
125°C
SIM6812M
VCC = 15 V
SIM6812M
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15.3.1.3. SIM6813M
Figure 15-33. Power MOSFET RDS(ON) vs. ID Figure 15-34. Power MOSFET VSD vs. ISD
15.3.1.4. SIM6880M
Figure 15-35. IGBT VCE(SAT) vs. IC Figure 15-36. FRD V F vs. IF
15.3.1.5. SIM6822M and SIM6827M
Figure 15-37. IGBT VCE(SAT) vs. IC
Figure 15-38. FRD VF vs. IF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
R
DS(ON)
(Ω)
ID (A)
VCC = 15 V
25°C
75°C
125°C
SIM6813M
0
0.2
0.4
0.6
0.8
1
1.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VSD (V)
ISD (A)
VCC = 15 V
25°C 75°C
125°C
SIM6813M
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VCE(SAT) (V)
IC (A)
VCC = 15 V
25°C
75°C
SIM6880M
125°C
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VF (V)
IF (A)
VCC = 15 V
125°C
75°C
SIM6880M
25°C
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0 1.0 2.0 3.0 4.0 5.0
VCE(SAT) (V)
IC (A)
VCC = 15 V
25°C
75°C
SIM6822M/27M
125°C
0.0
0.5
1.0
1.5
2.0
2.5
0.0 1.0 2.0 3.0 4.0 5.0
VF (V)
IF (A)
VCC = 15 V
25°C
75°C
SIM6822M/27M
125°C
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15.3.2 Switching Losses
Conditions: VBB = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on los s and turn -off los s .
15.3.2.1. SIM6811M
Figure 15-39. High-side Switching Loss Figure 15-40. Low-side Switc hing Loss
15.3.2.2. SIM6812M
Figure 15-41. High-side Switching Loss Figure 15-42. Low-side Switc hing Loss
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
E (µJ)
I
D
(A)
VB = 15 V
SIM6811M
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
E (µJ)
ID (A)
VCC = 15 V
SIM6811M
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
E (µJ)
ID (A)
VB = 15 V
SIM6812M
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
E (µJ)
ID (A)
VCC = 15 V
SIM6812M
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 40
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15.3.2.3. SIM6813M
Figure 15-43. High-side Switching Loss Figure 15-44. Low-side Switc hing Loss
15.3.2.4. SIM6880M
Figure 15-45. High-side Switching Loss Figure 15-46. Low-side Switc hing Loss
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0
E (µJ)
ID (A)
VB = 15 V
SIM6813M
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0
E (µJ)
ID (A)
VCC = 15 V
SIM6813M
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0
E (µJ)
IC (A)
VB = 15 V
SIM6880M
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0
E (µJ)
IC (A)
VB = 15 V
SIM6880M
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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15.3.2.5. SIM6822M
Figure 15-47. High-side Switching Loss Figure 15-48. Low-side Switc hing Loss
15.3.2.6. SIM6827M
Figure 15-49. High-side Switching Loss Figure 15-50. Low-side Switc hing Loss
0
50
100
150
200
250
300
350
400
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
E (µJ)
I
C
(A)
VB = 15 V
SIM6822M
0
50
100
150
200
250
300
350
400
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
E (µJ)
IC (A)
VCC = 15 V
SIM6822M
0
50
100
150
200
250
300
350
400
450
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
E (µJ)
IC (A)
VB = 15 V
SIM6827M
0
50
100
150
200
250
300
350
400
450
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
E (µJ)
IC (A)
VCC = 15 V
SIM6827M
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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15.4 Allowable Effective Current Curves
The following curves represent allowable effective currents in 3-phase sine-wave PWM driving with parameters such
as typical RDS(ON) or VCE(SAT), and typical swi tc hing losses.
Ope rating co nditions: VBB pin input voltage, VDC = 300 V; VCC pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, TJ = 150 °C.
15.4.1 SIM6811M
Figure 15-51. Allowable Effective Current ( fC = 2 kHz): SIM6811M
Figure 15-52. Allowable Effective Current ( fC = 16 kHz): SIM6811M
0.0
0.5
1.0
1.5
2.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
0.5
1.0
1.5
2.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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15.4.2 SIM6812M
Figure 15-53. Allowable Effective Current (fC = 2 kHz): SIM6812M
Figure 15-54. Allowable Effective Current ( fC = 16 kHz): SIM6812M
0.0
0.5
1.0
1.5
2.0
2.5
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
0.5
1.0
1.5
2.0
2.5
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz fC = 16 kHz
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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15.4.3 SIM6813M
Figure 15-55. Allowable Effective Current (fC = 2 kHz): SIM6813M
Figure 15-56. Allowable Effective Current ( fC = 16 kHz): SIM6813M
0.0
0.5
1.0
1.5
2.0
2.5
3.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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15.4.4 SIM6880M
Figure 15-57. Allowable Effective Current ( fC = 2 kHz): SIM6880M
Figure 15-58. Allowable Effective Current ( fC = 16 kHz): SIM6880M
0.0
0.5
1.0
1.5
2.0
2.5
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
0.5
1.0
1.5
2.0
2.5
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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15.4.5 SIM6822M
Figure 15-59. Allowable Effective Current ( fC = 2 kHz): SIM6822M
Figure 15-60. Allowable Effec tive Current (fC = 16 kHz): SIM6822M
0.0
1.0
2.0
3.0
4.0
5.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
1.0
2.0
3.0
4.0
5.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 47
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15.4.6 SIM6827M
Figure 15-61. Allowable Effective Current ( fC = 2 kHz): SIM6827M
Figure 15-62. Allowable Effective Current ( fC = 16 kHz): SIM6827M
0.0
1.0
2.0
3.0
4.0
5.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
1.0
2.0
3.0
4.0
5.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 48
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15.5 Short Circuit SOAs (Safe Operating Areas)
This section provides the graphs illustrating the short circuit SOAs of the SIM6800M series devices whose output
transistor s consi st of bui l t-in IGBTs.
Conditions: VDC ≤ 400 V, 13.5 V ≤ VCC ≤ 16.5 V, TJ = 12 5 °C, 1 pulse.
Figure 15-63. Short Circuit SOA: SIM6880M
Figure 15-64. Short Circuit SOA: SIM6822M, SIM6827M
0
10
20
30
40
0 1 2 3 4 5
Collector Current, I
C(Peak) (A)
Pulse Width (µs)
Short Circuit SOA
0
25
50
75
100
0 1 2 3 4 5
Collector Current, IC(Peak) (A)
Pulse Width (µs)
Short Circuit SOA
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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16. Pattern Layout Example
This section contains the schematic diagrams of a PCB pattern layout example using an SIM6800M series device.
For more details on t hrough holes, see Section 10.
Figure 16-1. Top View
Figure 16-2. Bottom View
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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R9
R20
R19
R18
C10
C11
C12
CX1
C18
R23
R1
R2
R3
R4
R5
R6
CN2
3
2
1
R8
R22
R7
R21
DZ1
C4
1
2
CN1
C17
C16
C15
C14
C13
SD
VCC1
VB1B
VB3
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN2
HIN3
OCL
W1
V1
VBB
V2
OCP LS3B
LS2
40
LS3A
LS2
V
VB2VB1A
LS1
5
8
9
13
14
15
16
17
11
21
23
28
33
35
CN3
1
2
3
4
5
6
HIN1
CN4
10
9
8
7
6
5
4
3
2
1
37
31
30
26
24
20
19
12
10
4
3
2
1
6
7
R17
R16
R10
C19
C20
C9
C8
C2 C6
C7 C3
C5
C1
Figure 16-3. Circuit Diagram of PCB Pattern Layout Example
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
SIM6800M-DSE Rev.1.8 SANKEN ELECTRIC CO., LTD 51
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17. Typical Motor Driver Application
Thi s sec ti on c o nta i ns the infor mation o n the typica l motor dr iver app licatio n listed in the p revious section, i ncludi ng
a circuit diagram, specifications, and the bill of the materials used.
● Motor Driver Specifications
IC
SIM6822M
Main Suppl y Voltage, VDC
300 VDC (typ.)
Rated Outp ut Power
500 W
● Circuit Diagram
See Figure 16-3.
● Bill of Materials
Symbol
Part Type
Ratings
Symbol
Part Type
Ratings
C1
Electrolytic
47 μF, 50 V
R3
General
100 Ω, 1/8 W
C2
Electrolytic
47 μF, 50 V
R4
General
100 Ω, 1/8 W
C3
Electrolytic
47 μF, 50 V
R5
General
100 Ω, 1/8 W
C4 Electrolytic 100 μF, 50 V R6 General 100 Ω, 1/8 W
C5
Ceramic
0.1 μF, 50 V
R7*
Metal plate
0.15 Ω, 2 W
C6
Ceramic
0.1 μF, 50 V
R8*
Metal plate
0.15 Ω, 2 W
C7 Ceramic 0.1 μF, 50 V R9* Metal p la te 0.15 Ω, 2 W
C8
Ceramic
0.1 μF, 50 V
R10
General
100 Ω, 1/8 W
C9
Ceramic
0.1 μF, 50 V
R16
General
3.3 kΩ, 1/8 W
C10
Ceramic
100 pF, 50 V
R17
General
0 kΩ, 1/8 W
C11
Ceramic
100 pF, 50 V
R18
General
100 Ω, 1/8 W
C12
Ceramic
100 pF, 50 V
R19
General
100 Ω, 1/8 W
C13
Ceramic
100 pF, 50 V
R20
General
100 Ω, 1/8 W
C14 Ceramic 100 pF, 50 V R21 General Open
C15
Ceramic
100 pF, 50 V
R22
General
Open
C16
Ceramic
100 pF, 50 V
R23
General
Open
C17 Ceramic 100 pF, 50 V ZD1 Zener diode VZ = 21 V (max.)
C18
Ceramic
100 pF, 50 V
IPM1
IC
SIM6822M
C19
Ceramic
0.01 μF, 50 V
CN1
Pin header
Equiv. to B2P3-VH
C20
Ceramic
100 pF, 50 V
CN2
Pin header
Equiv. to B2P5-VH
CX1
Film
0.033 μF, 630 V
CN3
Connector
Equiv. to MA06-1
R1
General
100 Ω, 1/8 W
CN4
Connector
Equiv. to MA10-1
R2
General
100 Ω, 1/8 W
* Refers to a part that requires adjustment based on operation performance in an actual application.
Not Recommended for New Designs:
SIM6822M, SIM6827M
SIM6800M Series
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Important Notes
● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
products listed herein (the “Sanken Products”) are cu rrent as of the dat e this docu ment is issu ed. The Information is subject to any
change without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales
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DSGN-CEZ-16003
Not Recommended for New Designs:
SIM6822M, SIM6827M
