BLOCK DIAGRAM IS SHOWN BELOW Vcc OUTPUT, QUTPLT, OUTPUT 4 a 6 5 | x x x x BUFFERED BUFFERED BUFFERED | DELAY DELAY DELAY MECHANICAL DETAIL IS SHOWN BELOW ee Pin Na. l". T 6 & V 040205 SS2FLDL- @TTL-___ IN, INg IN C Pin No. 12 & @ EF? ors2 Je MADE GN SLO LA 060 | a NP. oon pus, TyE-el be e ~i 100 TYP ; [a 5 ive 450 | + an es Loolo odes *Thru-hole Lead ne = 32S 020 1 el baw TYR | * [e100 rP. oa TYR 4 [+ 150| 0 EL agp eye TYR *Gull Wing Lead ie 25 | ae e100 TYP. et AT Pe f Poof 7 pr | TYE oye ;_ + bE le a0 T Ye =| | J 150 |, TP. we a25 *J Lead | OF 0 . rye ae 150 TYP ata || | 338 ogg TYP ae! |e *Tucked Lead 395 FEF. 2 4 INPUT , INPUT INPUT GROUND TEST CONDITIONS 1. All measurements are made at 25C. 2. Vec supply voltage is maintained at 5.0V DC, 3, All units are tested using a Schottky toggle-type positive input pulse and one Schottky load at the output. 4. Input pulse width used is 100% longer than delay of module under test; spacing between pulses (falling edge to rising edge) is three times the pulse width used. OPERATING SPECIFICATIONS *Vec supply vollage:. ...-- 2s .. es 4.75 to 5.25 DC Veo Supply current: : Constant "O"in ..... setae ee al Constant vin a ee ee ee were Lagie 1 Input: WoHAQG case eee ee ae eee OV ming Vee max. Current... ss Cee 2.7V = 20uA max. 6.5V = 1mA max. Logic 0 Input: VONSHG oc ae Se Se es wae) BY eX, Current yo See ae foe Geek ane 6mA max. Logic 1 Voltage out: ..... ae -.. 2.7 min, Logic O Voltage oub ..,.. 2... . ae) OOM Max. Qperating temperature range: ...... Oto 7C Storage temperature:..... eee es) (55 tO 41725C, * Delays increase or decrease approximately 2% for a respective increase or decrease of 5% in supply voltage. PART NUMBER TABLE Suffix Part Number with G (for Gull Wing Lead), J (for J Lead), F (for Thru-hole Lead) or T (for Tucked Lead). Examples: SS3FLDL-TTL-10G (Gull Wing), SS3FLDL- TTL-25J (J Lead), SS3FLDL-TTL-70F (Thru-hole Lead) or SS3FLDL-TTL-15T (Tucked Lead). @ DELAYS AND TOLERANCES (in ns) PART NO. OUTPUT PART NO. OUTPUT SS3FLDL-TTL-5 5+.5 || SSS3FLDOL-TTL-23 23 +1 SS3FLDL-TTL-6 B+.5 || SSSFLDL-TTL-24 24 +1 SS3FLBL-TTL-? 7*.5 || SSSFLDOL-TTL-25 25 +1 SS3FLDL-TTL-8 84.5 || SSSFLDL-TTL-30 30 41.5 SS3FLDL-TTL-9 94.5 || SSSFLDL-TTL-35 35 1.5 SS3FLDL-TTL-10 104.5 || SS3FLDL-TTL40 40 21.5 SS3FLOL-TTL-11 11 +.75 || SS3FLDL-TTL-45 45 #2 SS3FLDL-TTL-12 12 +.75 || SSS3FLDL-TTL-50 50 42 SSGFLDL-TTL-13 13 +.75 || SSSFLDL-TTL-55 55 +2 SS3FLDL-TTL-14 144.75 || SSSFLDL-TTL-60 60 +2 SS3FLDL-TTL-15 154.75 || SSS3FLDL-TTL-65 65 42.5 SS3FLDL-TTL-16 16 +.75 || SSSFLDL-TTL-70 YO #2.5 SS3FLBL-TTL-17 17 +.75 || SSSFLDL-TTL-75 a #25 SS3FLDBL-TTL-18 18 +.75 || SS3FLDL-TTL-60 BO 42.5 SS3FLDL-TTL-19 19 +.75 || SS3FLDL-TTL-85 85 +3 SS3FLDL-TTL-20 20 +.75 || SSGFLDL-TTL-90 90 +3 SS3FLDL-TTL-21 21 +1 SS3FLDL-TTL-95 95 +3 SS3FLDOL-TTL-22 22 +1 SSSFLDL-TTL-100 | 10043 @All modules can be operated with a minimum input pulse width of 100% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions. Special modules. can be readily manufactured to improve accuracies and/or provide customer specified random delay times for specitic applications. Peninenels Catalog No. G/121092