TL/F/6398
54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift Registers
June 1989
54LS164/DM54LS164/DM74LS164
8-Bit Serial In/Parallel Out Shift Registers
General Description
These 8-bit shift registers feature gated serial inputs and an
asynchronous clear. A low logic level at either input inhibits
entry of the new data, and resets the first flip-flop to the low
level at the next clock pulse, thus providing complete con-
trol over incoming data. A high logic level on either input
enables the other input, which will then determine the state
of the first flip-flop. Data at the serial inputs may be changed
while the clock is high or low, but only information meeting
the setup and hold time requirements will be entered. Clock-
ing occurs on the low-to-high level transition of the clock
input. All inputs are diode-clamped to minimize transmis-
sion-line effects.
Features
YGated (enable/disable) serial inputs
YFully buffered clock and serial inputs
YAsynchronous clear
YTypical clock frequency 36 MHz
YTypical power dissipation 80 mW
YAlternate Military/Aerospace device (54LS164) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/63981
Order Number 54LS164DMQB, 54LS164FMQB,
54LS164LMQB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164N
See NS Package Number E20A,
J14A, M14A, N14A or W14B
Function Table
Inputs Outputs
Clear Clock A B QAQB... QH
L X X X L L ... L
HLXXQ
A0 QB0 ... QH0
H
u
HHHQ
An ... QGn
H
u
LX L Q
An ... QGn
H
u
XL L Q
An ... QGn
HeHigh Level (steady state), L eLow Level (steady state)
XeDon’t Care (any input, including transitions)
u
eTransition from low to high level
QA0,Q
B0,Q
H0 eThe level of QA,Q
B
,orQ
H
, respectively, before the
indicated steady-state input conditions were established.
QAn,Q
Gn eThe level of QAor QGbefore the most recent
u
transition of
the clock; indicates a one-bit shift.
Logic Diagram
TL/F/63982
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS and 54LS b55§Ctoa
125§C
DM74LS 0§Ctoa
70§C
Storage Temperature Range b65§Ctoa
150§C
Note:
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ tables will de-
fine the conditions for actual device operation.
Recommended Operating Conditions
Symbol Parameter DM54LS164 DM74LS164 Units
Min Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b0.4 b0.4 mA
IOL Low Level Output Current 4 8 mA
fCLK Clock Frequency (Note 4) 0 25 0 25 MHz
tWPulse Width Clock 20 20 ns
(Note 4) Clear 20 20
tSU Data Setup Time (Note 4) 17 17 ns
tHData Hold Time (Note 4) 5 5 ns
tREL Clear Release Time (Note 4) 30 30 ns
TAFree Air Operating Temperature b55 125 0 70 §C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 1)
VIInput Clamp Voltage VCC eMin, IIeb
18 mA b1.5 V
VOH High Level Output VCC eMin, IOH eMax DM54 2.5 3.4 V
Voltage VIL eMax, VIH eMin DM74 2.7 3.4
VOL Low Level Output VCC eMin, IOL eMax DM54 0.25 0.4
Voltage VIL eMax, VIH eMin DM74 0.35 0.5 V
IOL e4 mA, VCC eMin DM74 0.25 0.4
IIInput Current @Max VCC eMax, VIe7V 0.1 mA
Input Voltage
IIH High Level Input Current VCC eMax, VIe2.7V 20 mA
IIL Low Level Input Current VCC eMax, VIe0.4V b0.4 mA
IOS Short Circuit VCC eMax DM54 b20 b100 mA
Output Current (Note 2) DM74 b20 b100
ICC Supply Current VCC eMax (Note 3) 16 27 mA
Note 1: All typicals are at VCC e5V, TAe25§C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR
input.
Note 4: TAe25§C and VCC e5V.
2
Switching Characteristics at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)
From (Input) RLe2kX
Symbol Parameter To (Output) CLe15 pF CLe50 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 25 MHz
tPLH Propagation Delay Time Clock to 27 30 ns
Low to High Level Output Output
tPHL Propagation Delay Time Clock to 32 40 ns
High to Low Level Output Output
tPHL Propagation Delay Time Clear to 36 45 ns
High to Low Level Output Output
Timing Diagram
TL/F/63983
3
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)
Order Number 54LS164LMQB
NS Package Number E20A
14-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS164DMQB or DM54LS164J
NS Package Number J14A
4
Physical Dimensions inches (millimeters) (Continued)
14-Lead Small Outline Molded Package (M)
Order Number DM74LS164M
NS Package Number M14A
14-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS164N
NS Package Number N14A
5
54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift Registers
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W)
Order Number 54LS164FMQB or DM54LS164W
NS Package Number W14B
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