Applications Note - Microchip Technology

 2001 Microchip Technology Inc. DS00778A-page 1

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INTRODUCTION

The PIC18C601 and PIC18C801 are the very first

members of Microchip’s PIC18 family that are ROM-

less microcontrollers — that is, they have no on-chip

program memory. Both offer the enhanced PIC18

arch itecture, alon g with the a bility to use differe nt types

and siz es of externa l program me mory to exac tly fit any

application. In addition to standard 1.5 Kbytes of gen-

eral purpos e RA M, the P IC18C6 01 ca n addre ss up t o

256 Kbytes of external program memory, while the

PIC18C801 can address up to 2 Mbytes of external

program memory. With this amount of available

addressable space, the PIC18C601/801 devices

become ideal candidates for more complex applica-

tions (e.g. TCP/IP stacks), developed with high level

programming languages, such as ‘C’.

In addition, PIC18C601/801 devices also make

in-system programming possible with its configurable

general pu rpose RAM (“Boot RAM”), which can be con-

figured as a program memory. When program execu-

tion takes place from Boot RAM, the external memory

bus can be mapped to port I/O. This feature enables

the device to perform virtually any programming algo-

rithm in software which does not conform to standard

timing requirements. Also, the PIC18C801 offers a

completely “glueless” external memory interface solu-

tion with its 8-bit De-Multiplexed Interface mode.

The PIC18C601/801 devices provide up to two pro-

grammable chip select signals, to partition address

spa ce into two di f f e rent memories. It al so provi des on e

programmable I/O chip select signal to locate an

8 Kbyte memory mapped I/O region anywhere in the

address space, except the lower 8 Kbyte space.

Given the number and types of memories available

today, finding and interfacing memory to the

PIC18C601/801 devices potentially becomes a chal-

lenging task. This application note describes the

PIC18C601/801 external memory interface modes, as

well as the methods for interfacing different types of

memories with PIC18C601/801. It is expected that the

reader will already be familiar with the general PIC18

architecture and instruction set.

This application note is divided into the following

sections.

•External Program Memory Interface Modes

provide information on the various memory inter-

face modes available with the PIC18C601/801

microcontrollers. It also discusses the require-

ments for configuring the controllers and using

Table Read and Table Write operations.

•Memory Mapping explains the memory maps

and mapping techniques for the PIC18C601/801

devices, using the on-chip programmable chip

select si gnals.

•Memory Mapped I/O explains how to use the

external memory interface as a mapped I/O port

for peripheral devices.

•Memory Devices and Interface provides infor-

mation on selecting and implementing interfaces

for various types of memory devices.

•Memory Timing Analysis explains the memory

timing requirements for PIC18C601/801 devices,

and how to assess memory devices for compat-

ability. The goal of this section is to answer one of

the most fre quently as ked ques ti ons : “Wha t mem-

ory speed shoul d I use with m y x MHz CPU?”

Author: Gaurang Kav aiya

Microchip Technology Inc.

Implementing the External Memory Interface

on PIC18C601/801 MCUs

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DS00778A-page 2  2001 Microchip Technology Inc.

1.0 EXTERNAL PROGRAM

MEMORY INTERFACE MODES

PIC18C60 1/8 01 c on trol lers c an be c on fig ured to run i n

either 8-b it or 16-b it Dat a mo de. The a ppropri ate mod e

is selected by setting the Bus Width configuration bit

(BW) in the Configuration register CONFIG2L. The

default configuration for the controllers is 16-bit, but this

can be changed to 8-bit with the appropriate device

programmer.

The 16-bit Data mode is available only in Multiplexed

mode, regardless of part selection. Depending on the

part chosen, the 8-bit Data mode may be either multi-

plexed or de-multiplexed; the PIC18C601 supports

only the Multiplexed mode, while the PIC18C801 pro-

vides only the De-Multiplexed mode.

If the external address bus is configured as an 8-bit

external interface, some of the external control signals

used in the 16-bit external interface will be mapped to

port I/O functio ns. However, when the e xternal add ress

bus is configured as 16-bit external interface, all of the

external control signals used for th e 8-bit external int er-

face will also be used for the 16-bit interface. External

components are needed to de-mult iplex the address for

all interface modes. The exception is the PIC18C801

configu r ed in 8-bi t Interfa ce mode (Sectio n 1.3.2).

U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1

—BW —————PWRTEN

bit 7 bit 0

bit 7 Unimplemented: Read as ’0’

bit 6 BW: External Bus Data Width bit

1 = 16-bit external bus mode

0 = 8-bit external bus mode

bit 5-1 Unimplemented: Read as ’0’

bit 0 PWRTEN: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed u = Unchanged from programmed state

 2001 Microchip Technology Inc. DS00778A-page 3

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1.1 Physical Im plementation

The Ext ernal Memo ry In terface is im plem ented with up

to 26 pins on the PIC 18C6 01, and up to 38 pins on the

PIC18C801. These pins are reserved for external

address and data bus functions. and are also multi-

plexed with port pins. The port functions are only

enabled when:

•Program ex ecution takes place in internal Boot

RAM, and

•The EBDIS bit in the MEMCON register is set

(MEMCON<7> = ‘1’).

Tables 1-1 a nd 1 -2 li st the typical ma ppi ng s of ext erna l

bus functions on I/O pins for the PIC18C601 and

PIC18C801, respectively.

TABLE 1-1: TYPICAL PORT FUNCTIONS OF PIC18C601

Name 16-bit

mode 8-bit

mode Function

RD0 /AD0 AD0 AD0 Input/Output or System Bus Address bit 0 or Data bit 0

RD1 /AD1 AD1 AD1 Input/Output or System Bus Address bit 1 or Data bit 1

RD2 /AD2 AD2 AD2 Input/Output or System Bus Address bit 2 or Data bit 2

RD3 /AD3 AD3 AD3 Input/Output or System Bus Address bit 3 or Data bit 3

RD4 /AD4 AD4 AD4 Input/Output or System Bus Address bit 4 or Data bit 4

RD5 /AD5 AD5 AD5 Input/Output or System Bus Address bit 5 or Data bit 5

RD7 /AD6 AD6 AD6 Input/Output or System Bus Address bit 6 or Data bit 6

RD6 /AD7 AD7 AD7 Input/Output or System Bus Address bit 7 or Data bit 7

RE0/AD8 AD8 AD8 Input/Output or System Bus Address bit 8 or Data bit 8

RE1/AD9 AD9 AD9 Input/Output or System Bus Address bit 9 or Data bit 9

RE2/AD10 AD10 AD10 Input/O utput or System Bus Address bit 10 or Data bit 10

RE3/AD11 AD11 AD11 Input/Output or System Bus Address bit 11 or Data bit 11

RE4/AD12 AD12 AD12 Input/O utput or System Bus Address bit 12 or Data bit 12

RE5/AD13 AD13 AD13 Input/O utput or System Bus Address bit 13 or Data bit 13

RE6/AD14 AD14 AD14 Input/O utput or System Bus Address bit 14 or Data bit 14

RE7/AD15 AD15 AD15 Input/O utput or System Bus Address bit 15 or Data bit 15

RG0/ALE ALE ALE Address Latch Enable (ALE) Control pin

RG1/OE OE OE Out put Enable (OE) Control pin

RG2/WRL WRL WRL Write Low (WRL) Control pin

RG3/WRH WRH RG3 Input/Out put or Syste m Bus Wr i te High (WR H) Control pin

RG4/BA0 BA0 BA0 Input/Output or System Bus Byte Address bit 0

RF7/LB LB RF7 Input/Output or System Bus Lower Byte Enable (LB) Control pin

RF6/UB UB RF6 Input/Output or System Bus Upper Byte Enable (UB) Control pin

RF3/CSIO CSIO CSIO Input/Output or System Bus Chip Select I/O

RF4/ AD16 AD16 AD16 In put/ Output or S y stem Bus Address bit 16 or Data bit 16

RF5/CS1 CS1 CS1 Input/Output or System Bus Chip Select 1

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DS00778A-page 4  2001 Microchip Technology Inc.

TABLE 1-2: TYPICAL PORT FUNCTIONS OF PIC18C801

Name 16-bit

mode 8-bit

mode Function

RD0/AD0 AD0 A0 Input/Output or System Bus Address bit 0 or Data bit 0

RD1/AD1 AD1 A1 Input/Output or System Bus Address bit 1 or Data bit 1

RD2/AD2 AD2 A2 Input/Output or System Bus Address bit 2 or Data bit 2

RD3/AD3 AD3 A3 Input/Output or System Bus Address bit 3 or Data bit 3

RD4/AD4 AD4 A4 Input/Output or System Bus Address bit 4 or Data bit 4

RD5/AD5 AD5 A5 Input/Output or System Bus Address bit 5 or Data bit 5

RD7/AD6 AD6 A6 Input/Output or System Bus Address bit 6 or Data bit 6

RD6/AD7 AD7 A7 Input/Output or System Bus Address bit 7 or Data bit 7

RE0/AD8 AD8 A8 Input/Output or System Bus Address bit 8 or Data bit 8

RE1/AD9 AD9 A9 Input/Output or System Bus Address bit 9 or Data bit 9

RE2/AD10 AD10 A10 Input/Output or System Bus Address bit 10 or Data bit 10

RE3/AD11 AD11 A11 Input/Output or System Bus Address bit 11 or Data bit 11

RE4/AD12 AD12 A12 Input/Output or System Bus Address bit 12 or Data bit 12

RE5/AD13 AD13 A13 Input/Output or System Bus Address bit 13 or Data bit 13

RE6/AD14 AD14 A14 Input/Output or System Bus Address bit 14 or Data bit 14

RE7/AD15 AD15 A15 Input/Output or System Bus Address bit 15 or Data bit 15

RH0/A16 A16 A16 Input/Output or System Bus Address bit 16

RH1/A17 A17 A17 Input/Output or System Bus Address bit 17

RH2/A18 A18 A18 Input/Output or System Bus Address bit 18

RH3/A19 A19 A19 Input/Output or System Bus Address bit 19

RG0/ALE ALE ALE Address Latch Enable (ALE) Control pin

RG1/OE OE OE Out put Enable (OE) Control pin

RG2/WRL WRL WRL Write Low (WRL) Control pin

RG3/WRH WRH RG3 Input/O ut put or Syst em Bus Wr i te High (WRH) Control pin

RG4/BA0 BA0 BA0 Input/Output or System Bus Byte Address bit 0

RF7/LB LB RF7 Inp ut/O ut put or Syst em bus Low er Byte Enable (LB)

Control pin

RF6/UB UB RF6 Input/Output or System Bus Upper Byte Enable (UB)

Control pin

RF3/CSIO CSIO CSIO Input/Output or System Bus Chip Select I/O

RF4/CS2 CS2 CS2 Input/Output or System Bus Chip Select 2

RF5/CS1 CS1 CS1 Input/Output or system bus Chip Sele ct 1

RJ0/D0 RJ0 D0 Input/Output or System Bus Data bit 0

RJ1/D1 RJ1 D1 Input/Output or System Bus Data bit 1

RJ2/D2 RJ2 D2 Input/Output or System Bus Data bit 2

RJ3/D3 RJ3 D3 Input/Output or System Bus Data bit 3

RJ4/D4 RJ4 D4 Input/Output or System Bus Data bit 4

RJ5/D5 RJ5 D5 Input/Output or System Bus Data bit 5

RJ6/D6 RJ6 D6 Input/Output or System Bus Data bit 6

RJ7/D7 RJ7 D7 Input/Output or System Bus Data bit 7

 2001 Microchip Technology Inc. DS00778A-page 5

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1.2 16-bit External Interfaces

The 16-bit External mode interface can be configured

by settin g BW bit in Con figurati on regis ter, CONFIG2L.

Pins AD15:AD0 carry multiplexed address and data

informa tion, wh ile pins A19:A16 carry address informa-

tion only.

The BA0 signal indicates an even or odd address.

Since all memory accesses by the controller in 16-bit

mode are word-aligned, BA0 is not requi red and shoul d

be left unconnected, even though it is still active. For

16-bit instruction fetch mode, the OE output enable sig-

nal will enable both bytes of program memory at once

to get a 16-bit word.

PIC18C601/801 controllers divide their instruction

cycle into four quarters, Q1 through Q4. During Q1,

ALE is enabled while address information (A15:A0) is

placed on pi ns AD 15:AD0. At the s ame t ime, t he upp er

address information (Ax:A16) is available on the upper

address bus. On the negative edge of ALE, the add ress

is latched in the external latch. At the beginning of Q3,

the OE output enable (active low) signal is generated.

At the end of Q4, OE goes high and data (16-bit word)

is read from memory at the low-to-high transition edge

of OE.

The 16-bit mode is divided into three sub-categories,

depending on how external memory is organized:

•16-bit memory with two individual 8-bit memory

chips (Byte Write mode)

•16-bit memory with Byte Select mode

•True 16-bit memory (16-bit Word Write mode)

The contro l signals used for the 16 -bit modes are listed

in Table 1-3.

TABLE 1-3: 18C601/801 16-BIT MODE CONTROL SIGNALS

Name 18C601

16-bit

mode

18C801

16-bit

mode Function

RG0/ALE ALE ALE Address Latch Enable (ALE) Control pin

RG1/OE OE OE Output Enable (OE) Control pin

RG2/WRL WRL WRL Write Low (WRL) Control pin

RG3/WRH WRH WRH Write High (WRH) Control pin

RG4/BA0 BA0 BA0 Byte Address bit 0

RF3/CSIO CSIO CSIO Chip Select I/O (see Section 3.3)

RF4/CS2 N/A CS2 Chip Select 2 (see Section 3.2)

RF5/CS1 CS1 CS1 Chip Select 1 (see Section 3.1)

RF6/UB UB UB Upper Byte Enable (UB) Contro l pin

RF7/LB LB LB Lower Byte Enable (LB) Control pin

I/O I/O I/O I/O as BYTE/WORD Control pin for JEDEC FLASH

(with Byte Select mode)

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DS00778A-page 6  2001 Microchip Technology Inc.

1.2.1 TABLE READ AND WRITE

OPERATIONS IN 16-BIT MODE

In addition to the program memory space already cov-

ered, PIC18C601/801 devices also have a data mem-

ory space. These memory spaces differ in their

organization: program memory is 16-bits wide, while

data memory is 8-bits wide. To move information

betwee n th ese differently c on figu r ed sp a ce s, t he Table

Read (TBLRD) and Table Write (TBLWT) instructions

have been provided.

Table Read operations retrieve data from program

memory and place it into the data memory space. Tabl e

Write operations, on the other hand, store data from the

data memory space into program memory. Table oper-

ations work with byte entities, moving data through an

8-bit reg ist er, TABLAT. A table blo ck co nt a ini ng data is

not required to be word aligned, so a table block can

start or end at any byte address.

All of the 16-bit modes require spec ial handling of Table

Wr ite o peratio ns. T he ap propriat e b its in the M EMCON

any Table Wri te ope rati on.

At power-on, the default content of MEMCON sets the

following system parameters:

•System bus is enabled

•Program RAM is configured as GPR memory

from 400h to 5FFh

•A 3-wait state cycle count for Table Reads and

Writes is se lecte d

•Table Write operations are set for Byte W rite m ode

uration bits.

Note: The WM <1:0> bits have no ef fect when th e

device is configured for 8-bit execution.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EBDIS PGRM WAIT1 WAIT0 — — WM1 WM0

bit7 bit0

bit 7 EBDIS: External Bus Disable bit

1 = Ex ternal system bus disabled, all external bus drivers are mapped as I/O ports

0 = Ex ternal system bus enabled and I/O ports are disabled

bit 6 PGRM: Program RAM Enable bit

1 = 512 bytes of inte rnal RA M ena bled as intern al prog ram me mory f rom loc ation 1FFE00h to

1FFFFFh, external program memory at these locations is unused. Internal GPR memory

from 400h to 5FFh is disabled and returns 00h.

0 = Internal RAM enabled as internal GPR memory from 400h to 5FFh. Program memory from

location 1FFE00h to 1FFFFFh is configured as external program memory.

bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits

11 = Table reads and writes will wait 0 TCY

10 = Table reads and writes will wait 1 TCY

01 = Table reads and writes will wait 2 TCY

00 = Table reads and writes will wait 3 TCY

bit 3-2 Unimplemented: Read as '0 '

bit 1-0 WM<1:0>: TBLWT Operation with 16-bit Bus bits

1X = Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when

TABLAT<1> written

01 = Byte Select mode: TABLAT data copied on both Most Significant Byte and Least

Significant Byte, WRH and (UB or LB) will activate

00 = Byte Write mode: TABLAT data copied on both Most Significant Byte and Least

Significant Byte, WRH or WRL will activate

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc. DS00778A-page 7

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1.2.1.1 TABLAT and TBLPTR Registers

Two control registers are used in conjunction with the

TBLRD and TBLWT instructions. They are:

•TABLAT register

•TBLPTR regi ste r s

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold

8-bit data during data transfers between program mem-

ory and data memory.

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three special function registers:

•Table Pointer Upper byte (TBLPTRU)

•Table Pointer High byte (TBLPTRH)

•Table Pointer Low byte (TBLPTRL)

These t hree re gis ters j oin to fo rm a 21-bit wide po inte r,

which allows the device to address up to 2 Mbytes of

program memory space. TBLPTR is used by the

TBLRD and TBLWT instructio ns. During Table Read and

Table Write operations, the Least Significant bit of

TBLPTR is copied to BA0. The remainder of TBLPTR

is copied to pins AX:A0 of the external address bus,

with the upper limit being determined by the microcon-

troller and mode being used. As an example, when the

PIC18C801 is being used, the value of TBLPTR<0>

appears on BA0, while the values of TBLPTR<20:1>

appear on pins A19:A0.

1.2.1.2 Table Read

The TBLRD instruction is used to retrieve data from

external program memory and place it into data mem-

ory. TBLPTR points to a byte address in external pro-

gram memory space. Executing TBLRD, places the

byte int o T ABLAT. In addition, TBLPTR can b e modified

automatically for the next Table Read operation. Table

Reads from external program memory are logically per-

formed one byte at a ti me.

If the external interface is 8-bit, the bus interface

circuitry in TABLAT will load the external value into

TABLAT.

If the external interface is 16-bit, interface circuitry in

T ABLAT will select either the high, or the low byte of the

dat a from the 16-b it bus, base d on the Least Significant

bit of the address. That is, when LSb is 0, the lower byte

(D<7:0>) is selected; when LSb is 1, the upper byte

(D<15:8>) is selected.

1.2.1.3 Table Write

The TBLWT instruction stores data from the data memory

space into external program memory. PIC18C601/801

devices perform Table Writes, one byte at a time. Table

Writes to external memory are two-cycle instructions,

unless wait st ates are enabled.

If the external interface is 8-bit, the bus interface cir-

cuitry i n TABLAT will co py it s v alu e to the external data

bus. If the external interface is 16-bit, interface Table

Writes depend on the type of external device that is

connec ted an d the WM<1: 0> bits in the MEMCO N re g-

ister. The code in Ex ample 1-1 describes the use o f the

Table Write operation for the 16-bit external interface.

EXAMPL E 1-1: USING THE TBLWT INSTRUCTION WITH THE 16-BIT INTERFACE

movlw UPPER (SampleTable) ;Initialize Table Pointer

movwf TBLPTRU ;with the starting address

movlw HIGH (SampleTable) ;of the Table

movwf TBLPTRH ;

movlw LOW (SampleTable) ;

movwf TBLPTRL ;

movlw LOW (DataWord) ;Load table latch with low byte

movwf TABLAT ;of value to write

tblwt*+ ;Write to Program memory and increment Table Pointer

movlw HIGH (DataWord) ;Load W register with high byte of value to write

movwf TABLAT ;Transfer high byte of value to table latch

tblwt* ;Write to next location/Word

movf Count,W ;Next Instruction for logic

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DS00778A-page 8  2001 Microchip Technology Inc.

1.2.2 EXTERNAL TABLE WRITE IN

16-BIT BYTE WRITE MODE

This mode is used for two separate 8-bit memories

connected for 16-bit operation. This generally includes

basic EPROM and FLASH devices. It allows Table

Writes to byte-wide external memories. During a

TBLWT instruction cycle, the TABLA T data is presented

on the upper and lower bytes of the AD15:AD0 bus.

The appro priate WRH or W RL control line is strobed o n

the LSb of the TBLPTR.

Figure 1-1 shows a typical implementation of the Byte

Write mode.

FIGURE 1-1: 16-BIT BYTE WRITE MODE

LATCH

LATCH WR(4) WR(4) OE OE

WRL(4) WRL WRH

WRH(4)

CE CE

AD<7:0>

AD<15:8>

ALE

D<15:8>

D<7:0>

(MSB)

(LSB)

Byte-Wide Memory

PIC18C601/801

LEGEND

Address Lines

Data Lines

Control Lines

D<7:0> D<7:0>

A/16(1)/A<19:16>(2)

A<16:0>(1)/

CS1 or CS2(3)

Note 1: PIC18C601 devices only.

2: PIC18C801 devices only.

3: CS2 is available only on the PIC18C801.

4: This signal is not used for ROM and EPROM external memory.

A<19:0>(2) A<16:0>(1)/

A<19:0>(2)

A<16:0>(1)/

A<19:0>(2)

 2001 Microchip Technology Inc. DS00778A-page 9

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1.2.3 EXTERNAL TABLE WRITE IN

16-BIT BYTE SELECT MODE

This mode allows Table Write operations to word-wide

external memories with byte selection capability. This

generally includes both word-wide FLASH and SRAM

devices. During a TBLWT cycle, the TABLAT data is

presented on the upper and lower byte of the

AD15:AD0 bus. The WRH signal is strobed for each

write cycle; the WRL pin is not use d. The BA0 or UB/LB

signal s are us ed to sel ec t the byt e to b e w ritte n, b ase d

on the LSb of the TBLPTR register.

FLASH and SRAM devices use different control signal

combinations to implement Byte Select mode. JEDEC

stan dard FL ASH me mories re quire th at a co ntroll er I/O

port pin be connected to the memory’s BYTE/WORD

pin to provid e the se lect signal. They als o use t he BA0

signal from the controller as a byte address

(Figure 1-2). JEDEC standard static RAM memories,

on the other hand, use the UB or LB signals to select

the byte (Figure 1-3).

FIGURE 1-2: 16-BIT BYTE SELECT MODE (WORD-WIDE FLASH MEMORY)

Note: To program a 16-bit FLASH memory with

byte select capability, user firmware must

dynamically change FLASH memory

access mode from Word to Byte mode.

This can be achieved by connecting one

I/O line to a FLAS H Memory mode pin and

making sure that the FLASH device is

setup in 16-bit mode on power-up. Since

inst ruction fetche s are done in 16-bit mod e

only, care must be t aken that FLASH mod e

is changed only when execution is taking

place from Boot RAM.

For additional information, refer to the

PIC18C601/801 Device Data Sheet

(DS39541).

LATCH

WRH

AD<7:0>

AD<15:8>

A<15:0>

ALE

D<15:0>

JEDEC Word FLASH Memory(5)

OE WR(4)

A<16:1>

WORD/BYTE

D<15:0>

CS1 or CS2(3) CS

WRH(4)

I/O IO

PIC18C601/801

A17(1)/A<20:17>(2)

A16(1)/A<19:16>(2)

A<7:0>

A<15:8>

Note 1: PIC18C601 devices only.

2: PIC18C801 devices only.

3: CS2 is available only on the PIC18C801.

4: This signal is not used for ROM and EPROM external memory.

5: This family of FLASH memory ignores A0 in Word mode.

LEGEND

Address Lines

Data Lines

Control Lines

BA0

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DS00778A-page 10  2001 Microchip Technology Inc.

FIGURE 1-3: 16-BIT BYTE SELECT MODE (WORD-WIDE SRAM)

LATCH

WRH

AD<7:0>

AD<15:8>

ALE

D<15:0>

JEDEC Word SRAM

OE WR

A<15:0>

D<15:0>

WRH

PIC18C601/801

A16(1)/A<19:16>(2) A16(1)/A<19:16>(2)

CS1 or CS2(3)

A<15:0>

A<15:8>

A<7:0>

Note 1: PIC18C601 device s only.

2: PIC18C801 devices only.

3: CS2 is available only on the PIC18C801.

LEGEND

Address Lines

Data Lines

Control Lines

 2001 Microchip Technology Inc. DS00778A-page 11

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1.2.4 EXTERNAL TABLE WRITE IN

16-BIT WORD WRITE MODE

This mode is used for word-wide memories, which

includ es s om e o f the EPROM an d FL ASH typ e m emo-

ries. This mode allows opcode fetches and Table

Reads from all forms of 16-bit memory, and Table

Writes to any type of word-wide external memories.

This method makes a distinction between TBLWT

cycle s to even or odd a ddresses. D uring a TBLWT cycl e

to an even address (TBLPTR<0> = ‘0’), the TABLAT

data is transferred to a holding latch and the external

address dat a bus is tri-st ated for the da ta po rtion of th e

bus cycle. No write signals are activated.

During a TBLWT cycle to an odd address (TBLPTR<0>

= ‘1’), the TABLAT data is pres ente d on th e upp er by te

of the AD 15:AD0 bus. The conte nts of the holdin g latch

are presented on the lower byte of the AD15:AD0 bus.

The WRH signal is strobed for each write cycle; the

WRL pin is unused. The signal on the BA0 pi n indicates

the LSb of T BLP TR, but it is left unc on nec ted . Inst ea d,

the UB and LB signal s are ac tive to se lect b oth byte s.

The obvious limitation to this method is that the Table

Write must be done in pairs on a specific word bound-

ary to correctly write a word location.

Figure 1-4 shows a typical implementation of this

mode.

FIGURE 1-4: 16-BIT WORD WRITE MODE

LATCH

WRH(4)

AD<7:0>

AD<15:8>

A<15:0>

ALE

D<15:0>

CS1 or CS2(3)

JEDEC Word FLASH Memory

OE WR(4)

A<15:0>

D<15:0>

WRH

PIC18C601/801

A16(1)/A<19:16>(2)

A16(1)/ A<19:16>(2)

A<7:0>

A<15:8>

Note 1: PIC18C601 devices only.

2: PIC18C801 devices only.

3: CS2 is available only on the PIC18C801.

4: This signal is not used for ROM and EPROM external memory .

LEGEND

Address Lines

Data Lines

Control Lines

AN778

DS00778A-page 12  2001 Microchip Technology Inc.

1.3 8-bit External Interfaces

1.3.1 8-BIT MULTIPLE XE D EXTERNA L

INTERFACE

This interface is only available on the PIC18C601. It

requires the use of either a lower processor operating

frequency as compared to 16-bit modes, or the use of

a faster memory device.

In this mo de, the low orde r ad dres s and data bytes a re

multiplexed, and require a single latch to de-multiplex

the address and data busses. Instructions are fetched

as two 8-bi t by tes withi n on e in struction cycl e. Pin BA0

from the controller must be connected to address pin

A0 of the memo ry devic e(s); bec ause of th is, controll er

address pins A16:A0 are connected to memory

address pins A17:A1. The output enable (OE) signal

will enable the first byte of program memory for a por-

tion of the cycle, the second byte will be read to from

the 16-bit instruction word when BA0 changes.

When the 8-bit interface is se le cte d, th e WR H, UB an d

LB pins are not used; they revert to I/O port functions.

The WRL signal is active on every external write.

The external address is 18-bits wide, which allows for

addressing of up to 256 Kbytes. External Table R eads

and Table Write are performed one byte at a time.

Figure 1-5 shows a typical implementation of this

mode. The control signals are described in Table 1-4.

FIGURE 1-5: 8-BIT MULTIPLEXED MODE FOR PIC18C601

TABLE 1-4: 8-BIT MULTIPLEXED MODE CONTROL SIGNALS

LATCH

WR(1)

WRL

WRL(1)

A<16:9>

AD<7:0>

A16

AD<15:8> A<15:8>

ALE

BA0

D7:D0

D<7:0>

PIC18C601

CS1 CS1

A<8:1>

A17

A<7:0>

LEGEND

Address Lines

Data Lines

Control Lines

Note 1: This signal is not used for ROM and EPROM external memory.

Name 8-bit Mux

mode Function

RG0/ALE ALE Address Latch Enable (ALE) Control pin

RG1/OE OE O utput Enable (OE) Control pin

RG2/WRL WRL Write Low (WRL) Control pin

RG4/BA0 BA0 Byte Address bit 0

RF3/CSIO CSIO Chip Select I/O (see Section 3.3)

RF5/CS1 CS1 Chip Select 1 (see Section 3.1)

 2001 Microchip Technology Inc. DS00778A-page 13

AN778

1.3.2 8-BIT WITH DE-MULTIPLEXED

EXTERN AL IN TERFACE

This interface is only available on the PIC18C801. It

requires the use of either a lower processor operating

frequency as compared to 16-bit modes, or the use of

a faster memory device.

The address and data busses are separate and do not

require any external latches for de-multiplexing. The

instructions are fetched as two 8-bit bytes on a dedi-

cated data bus (PORTJ); the address is presented for

the entire duration of the fetch cycle on a separate

address bus. The two bytes are fetched during one

instruction cycle.

Pin BA0 from the controller must be connected to

address pin A0 of the memory device(s); because of

this, controller address pins A19:A0 are connected to

memory ad dres s pins A20:A1. The output enable (OE)

signal will enable the first byte of program memory for

a portion of the cycle; the second byte will be read to

from the 16-bit instruction word when BA0 changes.

The external address is 21-bits wide, which allows for

addressing of up to 2 Mbytes. External Table Reads

and Table Writes are performed one byte at a time.

When th e 8-bit d e-multipl exed int erface is selected, the

WRH, UB and LB pins are not used; they revert to I/O

port func tions. The WR L signal is active on e very exter-

nal write.

The control signals for this interface are described in

Table 1-5.

FIGURE 1-6: 8-BIT DE-MULTIPLEXED MODE FOR PIC18C801

TABLE 1-5: 8-BIT DE-MULTIPLEXED MODE CONTROL SIGNALS

WR(1)

WRL(1) WRL

A<20:1>

D<7:0>

A<19:0>

BA0

D<7:0>

D7:D0

PIC18C801

A<19:0>

LEGEND

Address Lines

Data Lines

Control Lines

CS1 or CS2(2) CS

Note 1: This signal is not used for ROM and EPROM external memory.

2: CS2 is available only on the PIC18C801.

Name 8-bit De-M ux

Mode Function

RG0/ALE ALE Address Latch Enable (ALE) Control pin

RG1/OE OE Output Enable (OE) Control pin

RG2/WRL WRL Write Low (WR L) Control pin

RG4/BA0 BA0 Byte Address bit 0

RF3/CSIO CSIO Chip Select I/O (see Section 3.3)

RF4/CS2 CS2 Chip Select 2 (see Section 3.2)

RF5/CS1 CS1 Chip Select 1 (see Section 3.1)

AN778

DS00778A-page 14  2001 Microchip Technology Inc.

2.0 MEMORY MAPPED I/O

In general, ROMless microcontrollers have less dedi-

cated I/O ports available than their ROM equipped

counterparts. To get around this limitation, additional

I/O channels are made available through memory

mapped com mu nic at ion s with perip heral devices. N or-

mally, this is achieved in one of two ways:

•Using discrete digital logic

•Using programmable per ipher als

2.1 Discrete Digital Logic

In general, latches are required for output ports, while

tri-state buffers are used for input ports.

Figur e 2-1 demonstrates the requi rem ents for a typical

output port. Normally, latches have one active high

control signal, with data being latched at the signal’s

high-to-l ow t ransiti on. Th e co ntrolle r dat a bu s (D <7:0>)

is connected to the data input bus of the latch. The

CSIO and appropriate WR control lines are NORed to

produce the latch control signal.

Figure 2-2 demonstrates the requirements for a digital

input interface. Tri-state buf fers usually have one active

low cont rol si gna l; when it is activ e, inp ut data is trans-

ferred to the buffer output. The controller data bus

(D<7:0>) is connected to the output bus of the buffer.

The CSIO an d OE lines are ORed to produc e the buff er

control signal.

FIGURE 2-1: OUTPUT INTERFACE USING DISCRETE DIGITAL LOGIC

FIGURE 2-2: INPUT INTERFACE USING DISCRETE DIGITAL LOGIC

WRH

CSIO

D<7:0>

PIC18C601/801

WRL

AD<7:0>(1)

D<7:0>(2)

LATCH

Figure –7

Digital

Output

MODE NOR Gate Input

8-bit WRL

16-bit, Byte Write WRL

16-bit, Word Write WRH

16-bit, Byte Select WRH

Note 1: Configuration for PIC18C601 and PIC18C801 in 16-bit mode.

2: Configuration for PIC18C801 in 8-bit mode..

CSIO

PIC18C601/801

AD<7:0>(1)

D<7:0>(1)

Digital

Input

D<7:0>

BUFFER

Note 1: Configuration for PIC18C601 and PIC18C801 in 16-bit m ode.

2: Configuration for PIC18C801 in 8-bit mode..

 2001 Microchip Technology Inc. DS00778A-page 15

AN778

2.2 Programmable Peripherals

Some commonly used peripherals, such as the Intel®

compatible 8255 (programmable peripheral interface)

and the 8279 (programmable keyboard/display inter-

face), hav e 8-bit interfac es. These de vices ca n be con-

nected to ROMless microcontrollers for memory

mapped I/O operation, using CSIO as a control line.

Figures 2-3 through 2-5 d emonstrate meth ods for inter-

facing p rogram mable pe ripheral de vices wit h ROMl ess

microcontrollers. Some peripherals (such as the 8255

and 8279) ha ve one or two address lines to select inter-

nal registe rs. As these are 8-bit devi ces, special ca re is

required fo r the 16-b it mo des . The addre ss ing sch em e

is selected in such a way that it is common for all

modes. The base address will be an even address

specified by the CSELIO register. (See Section 3.3 for

details on specifying the location of the 8 Kbyte region

for I/O).

The periph eral device’s data bus (D7:D0) is connected

to the contro ller’s dat a bus. Periphe ral address pins A0

and A1 (in some cases, only A0) are connected to A0

and A1 of the controller. For 8-bit mode, address pins

A0 and A1 of the peripheral device (in some case only

A0) can be connected with BA0 and A0 of the

controll er.

The RD control pin of the peripheral is connected to the

OE pin of the controll er . The WR pin o f the peri pheral i s

connec ted to either the WRL or WRH pin of the contro l-

ler, depending on the memory interface mode.

The internal registers of the peripheral device can be

access ed by Table Read and Table Write instructions.

Addresse s for the registers st art with the bas e a dd res s

specified by the CSELIO register, incrementing with an

offset of 02h in 16-bit mode or 01h in 8-bit mode. (See

the Address/Register tables in Figures 2-3 through 2-5

for det ails.) For 1 6-bit Table Wri te operations, t he upper

byte will be dummy data.

FIGURE 2-3: 16-BIT MEMORY MAPPED I/O FOR THE PIC18C601/801 –

PROGRAMMABLE PERIPHERAL DEVICES

PERIPHERAL

LATCH

RD WR

WRH

AD<7:0>

ALE

CSIO

D<7:0>

PIC18C601/801

A<7:0>

WRL

A<1:0>

Interface

Mode WR Conn ected

16-bit, Byte Write WRL

16-bit, Word Write WRH

16-bit, Byte Select WRH

LEGEND

Address Lines

Data Lines

Control Lines

Address 0

CSELIO Base 1 Base + 2 2

Base + 4 3

Base + 6

A<1:0>

Peripheral

MCU

AN778

DS00778A-page 16  2001 Microchip Technology Inc.

FIGURE 2-4: 8-BIT MEMORY MAPPED I/O FOR THE PIC18C801 –

PROGRAMMABLE PERIPHERAL DEVICES

FIGURE 2-5: 8-BIT MEMORY MAPPED I/O FOR THE PIC18C601 –

PROGRAMMABLE PERIPHERAL DEVICES

PERIPHERAL

RD WR

CSIO

D<7:0>

PIC18C801

D<7:0>

WRL

BA0

LEGEND

Address Lines

Data Lines

Control Lines

Address 0

CSELIO Base 1 Base + 2 2 Base + 4 3 Base + 6

Peripheral

MCU

PERIPHERAL

LATCH

RD WR

WRL

AD<7:0>

ALE

CSIO

D<7:0>

PIC18C601

A0 A1

LEGEND

Address Lines

Data Lines

Control Lines

BA0 A0

BA0

Address 0

CSELIO Bas e 1

Base + 2 2

Base + 4 3

Base + 6

Peripheral

MCU

 2001 Microchip Technology Inc. DS00778A-page 17

AN778

3.0 MEMORY MAPPING

PIC18C601/801 microcontrollers are capable of sup-

porting a wide va riety of memorie s and memory config-

urati ons. Users can connect up to two diff erent typ es of

memories in a single system. Different memories can

be enabled or disabled using combinations of the chip

select signals.

While chip select signals are normally generated by

external ly d ec odi ng the address lines, PIC18C601/80 1

devices provide up to two programmable on-board chip

select sign als and on e I/ O ch ip sele ct signal. This min-

imizes the amount of additional external circuitry

required to interface the ex te rnal me mo ry a nd me mory

mapped I/O devices. The PIC18C601 provides CS1

and CSIO, while the PIC18C801 provides CS1, CS2

and CSIO.

When enabled, a chip select signal is asserted when-

ever the CPU accesses the dedicated range of

addresses, specified in the chip select registers,

CSEL2 and CSELIO. If both the CSEL2 and CSELIO

registers are 00h, all of the chip selects are disabled,

and their corresponding pins are configured as I/O. In

addition, when program execution takes place from

internal Boot RAM, all chip selects are configured in

their inactive states. For the PIC18C601, CS1 is always

enabled unless the CSIO signal is active. The CSEL2

be used as a general purpose register.

The chip selects are unaffected by any device

RESETS, except the Power-on Reset. The RESET

value of these registers enable all three chip selects

with CS1 active (= ‘0’), CS 2 inactive (= ‘1’), and CSIO

inactive (= ‘1’) (with the RESET address = 000000h).

Det ails of the operation of the chip select s are prov ided

in the following sections. Figure 3-1 further illustrates

the relationships b etw ee n t he ch ip selects an d th e p r o-

gram memory map.

3.1 CS1

The CS1 signal is active low and inactive high. CS1 is

enabled by writing a value other than 00h into either the

CSEL2 register, or the CSELIO register. If both regis-

ters are programmed to 00h, the CS1 signal is not

enabled and the RF5/CS1 pin is configured as I/O.

The CS1 signal is active for a range of addresses that

are specified in the CSEL2 and CSELIO registers. By

default, it is active for the entire program memory range

from 000000h to 1FDFFh. It will always be active for

the lower 8 Kbytes of program memory. CS1 is active

for all add res se s f or wh ic h C S2 an d C SIO are inactive.

Therefore, if CSEL2 is equal to 20h and CSELIO is

equal to 80h, the CS1 signal will be active for the

addresses that fall between 000000h and 03FFFFh.

When the dev ice cycles throu gh a Power-on Reset, the

CS1 chip select is the only active chip select.

3.2 CS2

The CS2 signal is also active low and inactive high. A

value of 00h in the Chi p Select 2 Reg ister (CSEL2 ) dis-

ables the CS2 signal and configures the RF4/CS2 pin

as I/O.

The program memory range for C S2 is determ ined by

the value contained in CSEL2. An 8-bit value in this

tion of CS2. The 8-bit value is decoded as one of 256

boundaries in the program memory space, each being

8 Kbyte in size. For example, if the value contained in

the CSEL2 register is 128 (80h), then the CS2 signal

will be asserted whenever the address is greater than,

or equal to 8192 x 128, or 1,048,576 (100000h).

When the device cycles through a Power-on Reset,

CS2 becomes inac tiv e.

Note: Because it is the only active chip sele ct sig-

nal on Power-on Reset, CS1 must alwa ys

be connected to one of the external mem-

ory devices .

AN778

DS00778A-page 18  2001 Microchip Technology Inc.

3.3 CSIO

The CSIO si gna l is als o a cti ve low an d inactive high. A

value of 00h in the Chi p Select 2 Reg ister (CSEL2 ) dis-

ables the CSIO output, and configures the RF3/CSIO

pin as I/O.

The I/O ch ip select is active for a fix ed 8 Kbyte add ress

range. The locati on of the I/O c hip se lect is de termine d

by the value contained in the I/O Chip Select register

(CSELIO). The ei ght-bit value is decoded as one of 256

8 Kbyte banks of program memory that, when

address ed , wil l ass ert th e CS IO outp ut. If, for inst anc e,

the value contained in the CSIO register is 128 (80h ),

then the CSIO pin will be asserted for the address

range between and including 8192 x 128 to ((8192 x

128) + 8192), or 100000h to 101FFFh. If the 8 Kbyte

address block overlaps the address range of the CS2

signal, the CSIO signal will be active and the CS2 sig-

nal will be inactive for that 8 Kbyte block of addresses

decoded by the CSELIO register.

When the device cycles through a Power-on Reset,

CSIO becomes inactive.

FIGURE 3-1: EXAMPLE CONFIGURATION ADDRESS MAPS FOR CS1, CS2, AND CSIO

Note: The RESET state of both CSEL2 and

CSELIO registers on Power-on Reset is

FFh. This allows the CS1, CS2 and CSIO

signals to be enabled. The CS1 signal will

be active for all addresses less than

1FE000h, the CSIO signal is active for all

addresses greater than, or equal to

1FE000h, and CS2 is inactive, since it

shares the same address value as CSIO.

This ensures that the chip select signals

are not floating if external memory is

prese nt, and i ts chip enabl e in puts are tied

to the chip selects.

PROGRAM MEMORY

CSEL2 = FFh (DEFAULT)

CSELIO = FFh (DEFAULT)

= CS1 ACTIVE = CS2 ACTIVE = CSIO ACTIVE

000000h

1FFFFFh

PROGRAM MEMORY

CSEL2 = 80h

CSELIO = 00h

000000h

1FFFFFh

PROGR AM MEMORY

CSEL2 = 20h

CSELIO = 80h

000000h

1FFFFFh

100000h

0FFFFFh 100000h

101FFFh

102000h

0FFFFFh

03FFFFh

040000h

= NO CHIP SELECT ACTIVE

INTERNAL EXECUTION IF

PGRM = 1

1FFDFFh

1FFE00h 1FFDFFh

1FFE00h

 2001 Microchip Technology Inc. DS00778A-page 19

AN778

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CSL7 CSL6 CSL5 CSL4 CSL3 CSL2 CSL1 CSL0

bit 7 bit 0

bit 7-0 CSL<7:0>: Chip Select 2 Address Decode bits

XXh = All eight bits are compared to the Most Significant bits PC<20:13> of the program

counter. If PC<20:13> ≥ CSL<7:0> register, then the CS2 signal is low.

If PC<20:13> < CSL<7:0>, CS2 is high.

00h = CS2

is in active

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

CSIO7 CSIO6 CSIO5 CSIO4 CSIO3 CSIO2 CSIO1 CSIO0

bit7 bit0

bit 7 CSIO<7:0>: Chip Sel ect I/O Address Decode bits

XXh = All eight bits are compared to the Most Significant bits PC<20:13> of the program

counter. If PC<20:13> = CSIO<7:0>, then the CSIO signal is low. If not, CSIO is high.

00h =CSIO

is inactive

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

AN778

DS00778A-page 20  2001 Microchip Technology Inc.

4.0 MEMORY DEVICES AND

INTERFACES

The PIC1 8C601/801 ROM less devic es are designed to

support a variety of memory devices. A variety of con-

trol signals are provided to facilitate the interface with

many memory chips.

4.1 Memory Devices with x8

Organization

4.1.1 x8 ARRANGEMENT

In this a rrangemen t, address pin s AX:A0 of the control-

ler are connected to address pins AX+1:A1 of the mem-

ory device. Pin BA0 is connected to the A0 pin of

memory. Controller data pins D7:D0 are connected to

memory data lines D7:D0. The controller’s OE pin is

connec ted to the OE pin of the memo ry device, and the

controller’s WRL pin is connec ted to the memory’s WE

pin.

For the PIC18C801, all address and data signals are

directly available at pin. For the PIC18C601, pins

AD7:AD0 are multiplexed; one external latch is

required for de-multiplexing the address and data

busses.

Instructions are fetc hed as two 8-bit bytes. The output

enable (OE) signal will enable one byte of program

memory for a portion of cycle, then the LSb of address

BA0 will change and the second byte will be read to

from the 16-bit instruc ti on word.

External Table Reads and Table Writes are performed

one byte at a time.

Examples of the 8-bit interfaces are provided in

Figure 1-5 (Multiplexed mode) and Figure 1-6

(De-Multiplexed mode).

4.1.2 x16 ARRANGEMENT

For this arran gemen t, two byt e-wide me mor y chips are

used, one each for the LSB and MSB. The controller

address lines AX:A0 are connected to the AX:A0

address lines of both memories. BA0 is left uncon-

nected. The controller data lines are connected to

D7:D0 of one memory device (LSB), and to D15:D8 of

the sec ond devi ce (MSB ). The cont roller OE p in is co n-

nected with the OE pin of both memories. The control-

ler WRL pin is connected to WE of the LSB memory,

while WRH is connected to WE of the MSB memory.

Instructions are fetched as a 16-bit word. The output

enable (O E) signal will enable one byte of both memo-

ries for a portion of cycle to form the 16-bit instruction

word.

External Table Reads are logically performed one byte

at a time, although the memory will read a 16-bit word

externally. The Least Significant bit of the address

internally selects between high and low bytes.

For Table Writes, configure the MEMCON register for

Byte Write mode (MEMCON<1:0>=’00’). During a

TBLWT cycle, the TABLAT data is presented on the

upper and lower byte of the AD bus. The appropriate

WRH or WRL signal is strobe d based on the LSb of th e

TBLPTR.

An example of this interface is provided in Figure 1 -1.

4.2 Memory Devices with x16

Organization

For this arrangement, the controller address pins

AX:A0 are connected to the memory address pins

AX:A0. BA0 is not used, and left unconnected. The

controller data pins D15:D0 are connected to D15:D0

of th e memory d evice. T he contr oller ’s OE control pin

is connected with the OE pin of the memory, and the

controller’s WRH pin is connect ed to the memory’s WE

pin.

Instructions are fetched as a single 16-bit word. The

output enable (OE) signal wi ll enable word from mem-

ory for a po rtion of the cy cle to get the 16 -bit instruct ion

word.

External Table Reads are logically performed one byte

at a time, although the memory will read a 16-bit word

externally. The Least Significant bit of the address will

internally select between high and low bytes.

For Table Write, configure the MEMCON register for

Word Write mode (MEMCON<1:0>=’1x’). During a

TBLWT cycle to an even address (TBLPTR<0> = ‘0’),

the TABLAT data is transferred to a holding latch and

the external address data bus is tri-stated for the data

portion of the bus c yc le . No w rite s ign als are activ ate d.

During a TBLWT cycle to an odd address (TBLPTR<0>

= ‘1’), the TABLAT data is pres ente d on th e upp er by te

of the AD bus (AD15:AD8). The content s of the holdin g

latch are presented on the lower byte of the AD bus

(AD7:AD0). The WRH signal is strobed for each write

cycle and the WRL signal is unused. The BA0 signal

indica tes the LSb of TBLP TR, but it is not used. The UB

and LB control signals are active to select both bytes.

An example of the 16-bit Word Write interface is shown

in Figure 1-4.

Note: The 8-bit memory interfaces require the

use of either faster memory devices, or a

lower controller operating frequency (as

compared to similar 16-bit interfaces).

 2001 Microchip Technology Inc. DS00778A-page 21

AN778

4.3 Memory Devices with

x8/x16 Selectable Organization

The memory devices covered in this section are capa-

ble of supporting both x8 and x16 organization. The

method used for interfacing a device depends on the

organization used. Additionally, the addressing modes

discussed here differ on how the controller address

lines are used to fetch byte or word entities. To distin-

guish t hese, the sc hemes in thi s section wi ll be referred

to as “Basic Byte” and “Ba sic Word”.

4.3.1 “BASIC BY TE ” ADDRESSING

SCHEMES

In this sc heme, all available memory address lines are

used to directly address byte-size data entities .

In general, TSOP56 package JEDEC FLASH devices

fall into the “Basic Byte” category.

4.3.1.1 Byte (8-b it) Mode

The arrangement is similar to the 8-bit modes illus-

trated in Figures 1-5 and 1-6. Address pins AX:A0 for

the controller are connected to address pins AX+1:A1

of memor y. The controller’s BA0 pin is connected to A0

of the memory device. For the PIC18C801, data pins

D7:D0 are connected directly to the data pins of the

memory, providing a “glueless” interface (Figure 4-2).

For the PIC18C601, the low order address and data

signals are multiplexed; controller pins AD7:AD0 are

directly connected t o the memory t o provide dat a, while

an external latch de-multiplexes address pins A7:A0

(Figure 4-1). The controller and memory OE pins are

connected, while the controller WRL pin is connected

to the me mory WR pin.

Instructions are fetched as two 8-bit bytes. The output

enable (OE) signal will enable one byte of program

memory for the first portion of cycle; then the BA0 sig-

nal changes, and the second byte is read to form the

16-bit instruction word. External Table Reads and Table

Writes are performed one byte at a time.

4.3.1.2 Word (16-bit ) Mode

For this arrangement, the controller’s AX:A0 address

pins are connected to address pins AX+1:A1 of mem-

ory. Controller pin BA0 and memory pin A0 are left

unconnected. The controller’s D15:D0 data pins are

connec ted to the mem ory’s D15 :D0 dat a pins. The con-

troller and memory OE pins are connected, while the

controller’s WRH pin is connected to the WE pin of the

memory. The connections for this mode are shown in

Figure 4-3.

For Byte Selec t mode, t he contro ller’s BA0 pin must be

connected to A0 of the memory. The WORD/BYTE pin

of th e memory is connected to an I/O pin on th e control-

ler to enable dynamic Word/Byte mode switching.

Dynamic switching of FLASH devices is not possible if

a program is executing from the same FLASH at the

same time. See Section 1.2.3 for more information.

Instructions are fetched as 16-bit words. The output

enable (O E) si gn al w il l en ab le word from memory fo r a

portion of cycle to fetch the 16-bit instruction word.

External Table Reads and Writes are logically per-

formed one byte at a time, although the memory will

read a 16-bit word externally. The Leas t Significant bit

of the address will internally select between high and

low bytes. Table Writes can be performed in either

Word Write or Byte Select mode. (Refer to Sections

1.2.3 and 1.2.4 for more details.)

FIGURE 4-1: 8-BIT “BASIC BYTE” ADDRESSING SCHEME FOR THE PIC18C601

LATCH

OE WR

A<17:1>

AD<7:0>

A16

AD<15:8>

A<16:0>

ALE

BA0

D<7:0>

A<15:8>

D<7:0>

PIC18C601

WRL

A<7:0>

LEGEND

Address Lines

Data Lines

Control Lines

CS1

WORD/

BYTE

AN778

DS00778A-page 22  2001 Microchip Technology Inc.

FIGURE 4-2: 8-BIT “BASIC BYTE” ADDRESSING SCHEME FOR THE PIC18C801

FIGURE 4-3: 16-BIT “BASIC BYTE” ADDRESSING SCHEME FOR THE PIC18C601/801

OE WR

A<20:1>

AD<7:0>

A<19:16>

AD<15:8>

A<19:0>

BA0

D<7:0>

A<15:8>

PIC18C801

WRL

A<7:0>

D<7:0> D<7:0>

LEGEND

Address Lines

Data Lines

Control Lines

CS1 or CS2(1)

WORD/

BYTE

Note 1: CS2 is available only on the PIC18C801.

LATCH

OE WR

WRH

A<17:1>(1)/

AD<7:0>

AD<15:8>

ALE

D<7:0>

A<15:8>

D<15:8>

D<7:0>

PIC18C601/801

A<7:0>

A16(1)/A<19:16>(2)

Note 1: PIC18C601 devices only.

2: PIC18C801 devices only.

3: CS2 is available only on the PIC18C801.

LEGEND

Address Lines

Data Lines

Control Lines

CS1 or CS2(3)

WORD/

BYTE

VDD

A<20:1>(2)

A16(1)/ A<19:16>(2) A<16:0>(1)/

A<19:0>(2)

 2001 Microchip Technology Inc. DS00778A-page 23

AN778

4.3.2 “BASIC WORD” ADDRESSING

SCHEMES

In this sc heme, all available memory address lines are

used to address word (16-bit) data entities. Function-

ally, one pin (e.g. DQ15) is used as the LSb address

input, and acts as a multi-function pin, depending on

the operation mode (Byte or Word).

In general, TSOP48 package FLASH devices fall into

the “Basic Word” ca tegory.

4.3.2.1 Byte (8-b it) Mode

In this arrangement, controller address pins AX:A0 are

connected to memory address lines AX:A0. Controller

data pins D<7:0> are connected to memory data pins

D7:D0. BA0 is connected to a memory multi-function

pin (e.g., DQ15). The controller and memory OE pins

are connected, while the controller WRL pin is con-

nected to the memory’s WE pin.

For the PIC18C601, pins AD 7:AD0 are multiplexed, so

one external latch is required for de-multiplexing the

address and data busses (Figure 4-4). For the

PIC18C801, data is directly available at pin (Figure 4-5).

Instructions are fetc hed as two 8-bit bytes. The output

enable (OE) signal will enable one byte of program

memory for a portion of cycle; then the BA0 signal will

change state for the LSb of address, and the second

byte will be read to from the 16-bit instruction word.

External Table Reads and Table Writes are performed

one byte at a time.

4.3.2.2 Word (16-bit ) Mode

For this arrangement, controller address pins AX:A0

are connected to memory address pins AX:0. BA0 is

left unconnected. The control ler data pin s D15:D0 pin s

are connected to memory data pins D15:D0. The con-

troller and memory OE pi ns ar e c onn ec ted, wh il e co n-

troller pin WRH is connected to the memory’s W E pin.

The connections for this mode are shown in Figure 4-6.

Instructions are fetched as one 16-bit word. The output

enable (OE) signal will enable word from memory for a

portion of the cycle to get the 16-bit instruction word.

Externa l Table Re ad s and W rites are l ogic ally p erform ed

one byte at a time, although the memory will read a 16-bit

word externally. The Least Significant bit of the address

will in te rna ll y s el ec t b et w ee n h ig h an d l ow by te s.

For Byte Select mode, the controller’s BA0 pin must be

connected to pin D15/A1 of the memory. The

WORD/BYTE pin of the memory is connected to an I/O

pin on the controller to enable dynamic Word/Byte mode

switching. Dynamic switching of FLASH devices is not

possible if a program is executing from the same FLASH

at the same time. See Section 1.2.3 for more in formation.

Table Writes can be performed in either Word Write or

Byte Select mode. (Refer to Sections 1.2.3 and 1.2.4

for more de tails.)

FIGURE 4-4: 8-BIT “BASIC WORD” ADDRESSING SCHEME FOR THE PIC18C601

LATCH OE WR

A<16:0>

AD<7:0>

A16

AD<15:8>

A<16:0>

ALE

BA0

D15/A1

D<7:0>

A<15:8>

D<7:0>

PIC18C601

WRL

A<7:0>

LEGEND

Address Lines

Data Lines

Control Lines

CS1

WORD/

BYTE

AN778

DS00778A-page 24  2001 Microchip Technology Inc.

FIGURE 4-5: 8-BIT “BASIC WORD” ADDRESSING SCHEME FOR THE PIC18C801

FIGURE 4-6: 16-BIT “BASIC WORD” ADDRESSING SCHEME FOR THE PIC18C601/801

OE WR

A<19:0>

AD<7:0>

A<19:16>

AD<15:8>

A<19:0>

BA0

D15/A1

D<7:0>

A<15:8>

PIC18C801

WRL

A<7:0>

D<7:0> D<7:0>

LEGEND

Address Lines

Data Lines

Control Lines

WORD/

BYTE

LATCH

OE WR

WRH

A<16:0>(1)/

AD<7:0>

AD<15:8>

ALE

D15/A1

D<7:0>

A<15:8>

D<14:8>

D<7:0>

PIC18C601/801

A<7:0>

D15

LEGEND

Address Lines

Data Lines

Control Lines

Note 1: PIC18C601 devices only.

2: PIC18C801 devices only.

3: CS2 is available only on the PIC18C801.

A16/A<19:16>(2)

CS1 or CS2(3)

A<19:0>(2)

A16(1)/ A<19:16>(2)

WORD/

BYTE

VDD

A<16:0>(1)/

A<19:0>(2)

 2001 Microchip Technology Inc. DS00778A-page 25

AN778

5.0 MEMORY T IMING

CONSIDERATIONS

Instruction fetching depends on the processor speed,

so memory used must provide data output at that

speed. This requires consideration on selection of

memory for requ ired ac ce ss tim e. The memory a cc es s

time is dependent on main oscillator frequency and

External Interface mode. The 8-bit mode requires

either a faster memory or a lower processor operating

frequency than is available in 16-bit mode.

Most of the p r ogr am m emory t im ing c ha rac teri sti cs a re

defined relative to the instruction cycle period (TCY).

This period equals four times the input oscillator

tim e-b as e pe ri od ( TOSC), or one-fourth of the oscillator

frequency (FOSC):

TCY = 4/FOSC = 4 * TOSC

For a data read operation, it is apparent that address

access time for the memory (address to output delay,

or tACC) must be less than the controller’s TACC (addres s

valid to data valid delay). However, it is also necessary

to consider the propagation delay of the external latch,

or tPROP. Depending on the choice of TTL technology,

tPROP varie s from 5 ns to 40 ns. For 16-bit modes, the

memory access time may be expressed by the relation-

ship: tACC < TACC – tPROP

For 8-bit mode, the BA0 signal toggles within the OE

period to fetch word instruction. Therefore, memory

devices for 8-bit mode systems should supply data in

half the time of 16-bit mode systems. The memory

acces s time for 8-bi t mode is expre ssed by the rela tion-

ship: tACC < (TACC – tPROP) / 2

Another consideration is the memory device’s tOE, or

OE to output delay. This must be less than the micro-

controller’s TOE (time from OE falling edg e to data vali d)

of 0.5TCY-25 ns. The OE pulse w idth is fixed, so if tOE is

longer than TOE, it will not meet the requirement for the

minimum data setup time of 20 ns.

In mathematical terms, this means:

tOE < TOE, or tOE < 0.5TCY-25 ns

After establishing that the controller can successfully

access the memory, it ’s still necessary to compare the

memor y device’s data hold (tOH) and float (tDF) specifi-

cations with the controller’s ToeH2adD specification

(time from OE low-to-high transition to AD driven).

Although access time is the main criteria for determin-

ing device compatibility, the data float time (also occa-

sionally referred to as the un-access time) can’t be

ignored. If the m emory dev ic e ou tpu t is unable to go to

float in this interval, a bus contention situation will

result, in which the next cycle address driven by the

CPU will coll ide with the remnant s of the prev ious cycle

memory output. So mathematically,

tDF < ToeH2adD

Finally, the external latch used for de-multiplexing the

addr es s/d ata buss es mu st sat is fy so me o f its o wn t i m-

ing requirements:

•It must be able to operate within the ALE pulse

width interval of 0.25TCY;

•The address must set in the latch within the latch

address setup ti me. Thi s is de fined as the int erval

from address out to the ALE trailing edge, or

0.25TCY-10 ns;

•The address should latch when the ALE signal

goes low; and

•Any additional address hold time following the

ALE trailing edge should be less than the time

from the trailin g edge to the addres s out invali d

time of 5 ns.

Table 5-1 lists approximate memory timing require-

ment s for some typical oscillator frequencies. Normally ,

if access time requirements are met, all other require-

ments will match.

Detailed timing diagrams and requirements follow on

the next two pages. Figure 5-1 and Table 5-2 provide

information on 16-bit timing operations, while

Figur e 5-2 and Table 5-3 provide the s am e info rma tio n

for 8-bit operations.

TABLE 5-1: SELECTED MEMORY TIMING REQUIREMENTS AT VARIOUS

OSCILLATOR FREQUENCIES

Oscillator

Frequency tACC*

(16-bit mode) tACC*

(8-bit mode) tOE tDF

TadV2aIL

Address Setup

Time

4 MHz <715 ns <360 ns <475 ns <120 ns <240 ns

10 MHz <265 ns <130 ns <175 ns <45 ns <90 ns

16 MHz <150 ns <75 ns <100 ns <25 ns <50 ns

20 MHz <115 ns <60 ns <75 ns <20 ns <40 ns

25 MHz <85 ns <40 ns <55 ns <15 ns <30 ns

*Propagation delay tPROP is assumed to be 10 ns.

AN778

DS00778A-page 26  2001 Microchip Technology Inc.

FIGURE 5-1: PROGRAM MEMORY FETCH TIMING DIAGRAM (16-BIT)

TABLE 5-2: CLKOUT AND I/O TIMING REQUIREMENTS (16-BIT)

Q1 Q2 Q3 Q4 Q1 Q2

OSC1

ALE

Address Data from External

164

166

160

165

161

151 162

163

AD<15:0>

167 168

Address

150

A<19:16> Address

169

CS1

CS2

or CSIO

171

171A

155

Param

No Symbol Characteristics Min Typ Max Units

150 TadV2alL Address out valid to ALE↓ (address set up time) 0. 25TCY-10 ——ns

151 TalL2adl ALE↓ to address out invalid (address hold time) 5 ——ns

155 TalL2oeL ALE ↓ to OE ↓10 0.125TCY —ns

160 TadZ2oeL AD high-Z to OE ↓ (bus release to OE)0——ns

161 ToeH2adD OE ↑ to AD driven 0.125TCY-5 ——ns

162 TadV2oeH LS Data valid before OE ↑ ( data setup time) 20 ——ns

163 ToeH2adl OE ↑ to data in invalid (data hold time) 0 ——ns

164 TalH2alL A LE pulse width —0.25TCY —ns

165 ToeL2oeH OE pulse width 0.5TCY-5 0.5TCY —ns

166 TalH2alH ALE↑ to ALE ↑ (cycle t ime) —TCY —ns

167 TACC Address valid to data valid 0.75TCY-25 ——ns

168 TOE OE ↓ to data valid ——0.5TCY-25 ns

169 TalL2oeH ALE ↓ to OE ↑0.625TCY-10 —0.625TCY+10 ns

171 TalH2csL Chip select active to ALE ↓0.25TCY-20 ——ns

171A TubL2oeH AD valid to chip select active ——10 ns

 2001 Microchip Technology Inc. DS00778A-page 27

AN778

FIGURE 5-2: PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT)

TABLE 5-3: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT)

Q1 Q2 Q3 Q4 Q1 Q2

OSC1

ALE

Address Data

170

161

162

163

AD<7:0> Address

Address

A<19:8> Address

162A

BA0

Data

170A

CS1

CS2

or CSIO

151

150

166

Param

No Symbol Characteristics Min Typ Max Units

150 TadV2alL Address out valid to ALE ↓ (address setup time) 0 .25TCY-10 ——ns

151 Ta lL2adl ALE ↓ to address out invalid (address hold time) 5 ——ns

161 ToeH2adD OE ↑ to AD driven 0.125TCY-5 ——ns

162 TadV2oeH LS Data valid before O E ↑ (data setup time) 20 ——ns

162A TadV2oeH MS Data valid before OE ↑ (data setup tim e ) 0.25TCY+20 ——ns

163 ToeH2adl OE ↑ to data in invalid (data hold time) 0 ——ns

166 TalH2alH ALE ↑ to ALE ↑ (cycle time) —TCY —ns

170 TubH2oeH BA0 = 0 valid before OE ↑0.25TCY-10 ——ns

170A TubL2oeH BA0 = 1 valid before OE ↑0.5TCY-10 ——ns

AN778

DS00778A-page 28  2001 Microchip Technology Inc.

SUMMARY

The PIC18C601/801 family of devices provide a flexi-

ble external memory interface to support a variety of

embedded systems requirements for cost effective

implem ent ation w ith few externa l comp onent s. A mul ti-

tude of control signals and interface modes make it

possible to use a v arie t y of me mo ry dev ic es w it h ease.

The same interface also provides the ability to use

memory mapped I/O with a number of peripheral

devices.

 2001 Microchip Technology Inc. DS00778A-page 29

AN778

APPENDIX A: SUMMARY OF MEMORY DEVICES(1)

Manufacturer Part ID Prog ramm ing

Algor ithm Family (2) Organization Bas ic Byte/W ord

Addressing(4) Remarks

AMD 29F series A x8

29F series A x16

29F series A x8/x16 Byte

ATMEL 29 series B(3) x8 Sector

Programming

29 series B(3) x16 Sector

Programming

49 series B x8

49 series B x16

49 series B x8/x16 Byte

INTEL Boot Block C x8/x16 Byte

Strata FLASH/

FLASH File Cx8

Strata FLASH/

FLASH File C x8/x16 Word

SHARP 28F series C x8

28F series C x16

28F series C x8/x16 Word

ST 29F series A x8

29F series A x16

29F series A x8/x16 Byte

Samsung FLASH products in this family have multiplexed address/data/command lines and are incompatible

with PIC 18C6 01/ 801 de vice s.

Catalyst Boot Block

FLASH Cx8

Bulk Erase

FLASH

(5) x8

x16

Hyundai 29F series A x8 x

29F series A x8/x16 Byte

Micron Boot Block C x8

Boot Block C x8/x16 Byte

Even

Sectored Cx8

Even

Sectored C x8/x16 Word

SST 39F series B x8

29EE series B(3) x8 Sector

Programming

NexFlash 29F series B x8

Note 1: This listing is provided only as an example of typical memory devices available. It is not meant to be

exhaustive.

2: Detail s of each programming algorithm family are provided in Appendix B.

3: For these dev ices, use rs must pr ovide all da ta in the s ector. The dev ice will firs t erase the enti re sect or , then

program it. These devices do not support Sector Erase commands.

4: Applicable only to x8/x16 selectable devices.

5: These devices have a unique set of programming algorithms. They are omitted for the sake of brevity.

AN778

DS00778A-page 30  2001 Microchip Technology Inc.

APPENDIX B: PROGRAMMING ALGORITHMS FOR REPRESENT ATIVE

MEMORY DEVICES(1)

Command Program

Algorithm

Bus Cycles

Cycles

Needed First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read mode/

RESET A1XF0

——————————

B1XF0

——————————

C1XFF

——————————

Read

Mfg. ID A 4 555 AA 2AA 55 555 90 X00 01 ————

B 4 5555 AA 2AAA 55 5555 90 XX00 01 ————

C 2 X 90 (IA) ( ID) — — — —————

Read

Device ID A 4 555 AA 2AA 55 555 90 X01 AD ————

B 4 5555 AA 2AAA 55 5555 90 XX01 20 ————

C 2 X 90 (IA) ( ID) — — — —————

Write A 4 555 AA 2AA 55 555 A0 (WA) (WD) ————

B 4 5555 AA 2AAA 55 555 A0 (WA) (WD) ————

C 2 (WA) 40 (W A) (WD) — — — —————

Block Erase A 6 555 AA 2AA 55 555 80 555 AA 2AA 55 (BA) 30

B 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 (BA) 30

C 2 (BA) 20 (BA) D0 — — — — ————

Erase

Suspend A1XB0

——————————

B (2)

C1XB0

——————————

Erase Resume A 1 X30 ——————————

B (2)

XD0 ——————————

Chip Erase A 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

B 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

C2X30XD0

— — — — ————

Sector

Protect Verif y A 4 555 AA 2AA 55 555 90 (SGA) 00/01 ————

B 4 5555 AA 2AAA 55 5555 90 (SGA) 00/01 ————

C (2)

Legend: WA = Writ e Address, WD = Write Data, IA = Identifier Address, ID = Identifier Data

BA = Block Address, SGA = Sector Group Addres s

Note 1: The information provided in this table is for reference only, and is not meant to be a comprehensive description of the

device programming algorithm s. For complete information, please refer to the manufacturer ’s data sheet.

2: Instruction unimplemented in this programming algorithm family.

 2001 Microchip Technology Inc. DS00778A - page 31

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or oth er intellectual property rights arising from such

use or otherwise. Use of Microchip’s product s as critical com-

ponents in lif e support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, PIC, PICmicro,

PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL,

MPLAB and The Embedded Control Solutions Company are reg-

istered trademarks of Micr ochip Techno logy Incorp orated in the

U.S.A. and other countries.

Total Endurance, ICSP, In-Circuit S erial Programming, Filter-

Lab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,

MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC,

Migratable Memory, FanSense, ECONOMONITOR, Select

Mode and microPort are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Term Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and T empe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside t he operating specifications contained in the data sheet.

The person doing so may be engaged in th eft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

DS00778A-page 32  2001 Microchip Technology Inc.

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Tel: 45 4420 9895 Fax: 45 4420 9910

France

Arizona Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Et age

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Germany - Analog

Lochhamer Strasse 13

D-82152 Martinsried, Germany

Tel: 49-89-895650-0 Fax: 49-89-895650-22

Italy

Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berksh ire, E ngla nd RG 41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

06/01/01

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