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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
A buffered output-enable (1 OE or 2 OE) input can be used to place the outputs of the corresponding 10-bit latch
SN74ALVCH1684120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
•Member of the Texas Instruments Widebus™Family
•EPIC™ (Enhanced-Performance ImplantedCMOS) Submicron Process•ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)•Latch-Up Performance Exceeds 250 mA PerJESD 17•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Package Options Include Plastic 300-milShrink Small-Outline (DL) and Thin ShrinkSmall-Outline (DGG) Packages
This 20-bit bus-interface D-type latch is designed for1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16841 features 3-state outputsdesigned specifically for driving highly capacitive orrelatively low-impedance loads. This device isparticularly suitable for implementing buffer registers,unidirectional bus drivers, and working registers.
The SN74ALVCH16841 can be used as two 10-bitlatches or one 20-bit latch. The 20 latches aretransparent D-type latches. The device hasnoninverting data (D) inputs and provides true data atits outputs. While the latch-enable (1LE or 2LE) inputis high, the Q outputs of the corresponding 10-bitlatch follow the D inputs. When LE is taken low, the Qoutputs are latched at the levels set up at the Dinputs.
in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16841 is characterized for operation from -40 °C to 85 °C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1Q1
2
1Q2
3
1Q3
5
1Q4
6
1Q5
8
1D
55
1D1 54
1D2 52
1D3 51
1D4 49
1D5 48
1D6 47
1D7 45
1D8 44
1D9 43
1D10
1Q6
9
1Q7
10
1Q8
12
1Q9
13
1Q10
14
3D
42
2D1 41
2D2 40
2D3 38
2D4 37
2D5
2Q1
15
2Q2
16
2Q3
17
2Q4
19
2Q5
20
36
2D6 34
2D7 33
2D8 31
2D9 30
2D10
2Q6
21
2Q7
23
2Q8
24
2Q9
26
2Q10
27
EN2
1
C1
56
1LE
EN4
28
C3
29
2LE
1OE
2OE
2
4
SN74ALVCH16841
20-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
FUNCTION TABLE(each 10-bit latch)
INPUTS
OUTPUT
QOE LE D
L H H HL H L LL L X Q
0
H X X Z
LOGIC SYMBOL
(1)
2
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1OE
To Nine Other Channels
1
56
55 2
1LE
1D1
C1
1D 1Q1
2OE
To Nine Other Channels
28
29
42 15
2LE
2D1
C1
1D 2Q1
ABSOLUTE MAXIMUM RATINGS
(1)
SN74ALVCH1684120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 VV
I
Input voltage range
(2)
-0.5 4.6 VV
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 -50 mAI
OK
Output clamp current V
O
< 0 -50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 81θ
JA
Package thermal impedance
(4)
°C/WDL package 74T
stg
Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51.
3
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RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCH16841
20-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 VV
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 V
CC
VV
O
Output voltage 0 V
CC
VV
CC
= 1.65 V -4V
CC
= 2.3 V -12I
OH
High-level output current mAV
CC
= 2.7 V -12V
CC
= 3 V -24V
CC
= 1.65 V 4V
CC
= 2.3 V 12I
OL
Low-level output current mAV
CC
= 2.7 V 12V
CC
= 3 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature -40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
SN74ALVCH1684120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= -100 µA 1.65 V to 3.6 V V
CC
- 0.2I
OH
= -4 mA 1.65 V 1.2I
OH
= -6 mA 2.3 V 2V
OH
2.3 V 1.7 VI
OH
= -12 mA 2.7 V 2.23 V 2.4I
OH
= -24 mA 3 V 2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45I
OL
= 6 mA 2.3 V 0.4V
OL
V2.3 V 0.7I
OL
= 12 mA
2.7 V 0.4I
OL
= 24 mA 3 V 0.55I
I
V
I
= V
CC
or GND 3.6 V ±5µAV
I
= 0.58 V 1.65 V 25V
I
= 1.07 V 1.65 V -25V
I
= 0.7 V 2.3 V 45I
I(hold)
V
I
= 1.7 V 2.3 V -45 µAV
I
= 0.8 V 3 V 75V
I
= 2 V 3 V -75V
I
= 0 to 3.6 V
(2)
3.6 V ±500I
OZ
V
O
= V
CC
or GND 3.6 V ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 40 µA∆I
CC
One input at V
CC
- 0.6 V, Other inputs at V
CC
or GND 3 V to 3.6 V 750 µAControl inputs 4.5C
i
V
I
= V
CC
or GND 3.3 V pFData inputs 6.5C
o
Outputs V
O
= V
CC
or GND 3.3 V 7 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state toanother.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 V±0.2 V ±0.3 V
UNITMIN MAX MIN MAX MIN MAX MIN MAX
t
w
Pulse duration, LE high or low
(1)
3.3 3.3 3.3 nst
su
Setup time, data before LE ↑
(1)
0.9 0.7 1.1 nst
h
Hold time, data after LE ↑
(1)
1.2 1.5 1.1 ns
(1) This information was not available at the time of publication.
5
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SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74ALVCH16841
20-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX
D
(1)
1 5 4.7 1.2 3.9t
pd
Q nsLE
(1)
1 5.6 5.1 1 4.3t
en
OE Q
(1)
1 6.2 6 1 4.9 nst
dis
OE Q
(1)
1.1 5.3 4.3 1.3 4.1 ns
(1) This information was not available at the time of publication.
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
Outputs enabled
(1)
12 20Power dissipationC
pd
C
L
= 50 pF, f = 10 MHz pFcapacitance
Outputs disabled
(1)
1 3
(1) This information was not available at the time of publication.
6
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PARAMETER MEASUREMENT INFORMATION
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74ALVCH1684120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
V
CC
= 1.8 V
Figure 1. Load Circuit and Voltage Waveforms
7
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PARAMETER MEASUREMENT INFORMATION
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74ALVCH16841
20-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
V
CC
= 2.5 V ±0.2 V
Figure 2. Load Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
0 V
1.5 V 2.7 V
0 V
0 V
2.7 V
0 V
Input
2.7 V 2.7 V
3 V
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
1.5 V 1.5 V
tw
th
tsu
1.5 V 1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
SN74ALVCH1684120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SCES043E – JULY 1995 – REVISED SEPTEMBER 2004
V
CC
= 2.7 V AND 3.3 V ±0.3 V
Figure 3. Load Circuit and Voltage Waveforms
9
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74ALVCH16841DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16841DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16841DLG4 ACTIVE SSOP DL 56 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74ALVCH16841DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16841DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16841DL ACTIVE SSOP DL 56 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVCH16841DLR ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALVCH16841DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74ALVCH16841DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVCH16841DGGR TSSOP DGG 56 2000 346.0 346.0 41.0
SN74ALVCH16841DLR SSOP DL 56 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
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