DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT240
Octal buffer/line driver; 3-state;
inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state;
inverting 74HC/HCT240
FEATURES
•Output capability: bus driver
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT240 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT240 are octal inverting buffer/line drivers
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high impedance
OFF-state. The “240” is identical to the “244” but has
inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× VCC2× fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay
1An to 1Yn;
2An to 2Yn
CL= 15 pF; VCC =5 V99ns
C
Iinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per buffer notes 1 and 2 30 30 pF
December 1990 3
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state; inverting 74HC/HCT240
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
11
OE output enable input (active LOW)
2, 4, 6, 8 1A0 to 1A3data inputs
3, 5, 7, 9 2Y0 to 2Y3bus outputs
10 GND ground (0 V)
17, 15, 13, 11 2A0 to 2A3data inputs
18, 16, 14, 12 1Y0 to 1Y3bus outputs
19 2OE output enable input (active LOW)
20 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state; inverting 74HC/HCT240
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
INPUTS OUTPUT
nOE nAnnYn
L
L
H
L
H
X
H
L
Z
December 1990 5
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state; inverting 74HC/HCT240
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
1An to 1Yn;
2An to 2Yn
30
11
9
100
20
17
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.5
tPZH/ tPZL 3-state output enable time
1OE to 1Yn;
2OE to 2Yn
39
14
11
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.6
tPHZ/ tPLZ 3-state output disable time
1OE to 1Yn;
2OE to 2Yn
41
15
12
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.6
tTHL/ tTLH output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.5
December 1990 6
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state; inverting 74HC/HCT240
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
IICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
1An
2An
1OE
2OE
1.50
1.50
0.70
0.70
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HCT UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
1An to 1Yn;
2An to 2Yn
11 20 25 30 ns 4.5 Fig.5
tPZH/ tPZL 3-state output enable time
1OE to 1Yn;
2OE to 2Yn
13 30 38 45 ns 4.5 Fig.6
tPHZ/ tPLZ 3-state output disable time
1OE to 1Yn;
2OE to 2Yn
13 25 31 38 ns 4.5 Fig.6
tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.5
December 1990 7
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state; inverting 74HC/HCT240
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.5 Waveforms showing the input (1An, 2An) to output (1Yn, 2Yn) propagation delays and the output transition
times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.6 Waveforms showing the 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
