== PRELIMINARY M=i MX29F1611 sae 16N-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM FEATURES * 5V+5% write, erase and read * Low VCC write inhibit is equal to or less than 3.2V * JEDEC-standard EEPROM commands * Software and hardware data protection Endurance: 10,000 cycles * Page program operation * Fast access time: 100/120/150ns - Internal address and data latches for 128 bytes/64 * Fast pagemode access time: 50/60/70ns words per page * Page access depth: 16 bytes/8 words, page address - Page programming time: 5ms typical AO, A1, A2 - Byte programming time: 39us in average * Sector erase architecture + Lowpower dissipation - 16 equal sectors of 128k bytes each - 80mA active current - Sector erase time: 150ms typical - 100uA standby current * Auto Erase and Auto Program Algorithms * CMOS inputs and outputs - Automatically erases any one of the sectors or the * Two independently Protected sectors whole chip with Erase Suspend capability * Industry standard surface mount packaging - Automatically programs and verifies data at - 44 lead SOP specified addresses * Status Register feature for detection of program or erase cycle completion GENERAL DESCRIPTION The MX29F 1611 is a 16-mega bit Pagemode Flash To allow for simple in-system reprogrammability, the memory organized as either 1M wordx16 or 2M bytex8. MX29F 1611 does not require high input voltages for The MX29F 1611 includes 16-128KB(131,072 Bytes) programming. Five-volt-only commands determine the blocks or 16-64KW(65,536 Words)blocks. MXICs Flash operation of the device. Reading data out of the device is memories offer the most cost-effective and reliable read/ similar to reading from an EPROM. write non-volatile random access memory and fast page mode access. The MX29F 1611 ispackaged 44-pin SOP. MXIC Flash technology reliably stores memory contents Itis designed to be reprogrammed and erased in-system or even after 10,000 cycles. The MXIC's cell is designed to in-standard EPROMprogrammers. optimize the erase and programming mechanisms. tn addition, the combination of advanced tunnel oxide The standard MX29F 1611 offers access times as fast as processing and low internal electric fields for erase and 100ns,allowing operation of high-speed microprocessors programming operations produces reliable cycling. The without wait. To eliminate bus contention, the MX29F 1611 MX29F 1611 uses a 5V + 5% VCC supply to perform the has separate chip enable CE, output enable (OE), andwrite Auto Erase and Auto Program algorithms. enable (WE) controls. The highest degree of latch-up protection is achieved with MXICs Flash memories augment EPROM functionality MXICs proprietary non-epi process. Latch-up protectionis with in-circuit electrical erasure and programming. The proved for stresses up to 100 milliamps on address and MX29F 1611 uses a command register to manage this data pin from -1V to VCC +1V. functionality. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-1M=Ic Mx29F 1617 om PIN CONFIGURATIONS PIN DESCRIPTION 44 SOP(500mil) SYMBOL PIN NAME WE 44 we . ag lS aa | Ate AO - Ai9 Address Input AI? 3 42 Ag av | 4 a1 Ag Q0-Q14 Data Input/Output AB 5 40 A10 AS 6 39 Ait a (| 7 3a | At2 QI5/A - 1 Q15(Word mode)/LSB addr.(Byte mode) A3 8 37 A13 _ A2 9 = 36 Al4 . At 0 8 os | ats CE Chip Enable input AQ i 34 A16__ ce | 12 SN 33 | BYTE OE Output Enable Input eno | 13 S 32 | GND 4 31 QI15/A-1 wr . ool is oar WE Write Enable input Qs 16 29 aia __ ai | 7 28] 96 WP Sector Write Protect Input Qg 18 27 Q13 a2 19 26 Os porn J aio | 20 25 | a2 BYTE Word/Byte Selection Input Qs 21 24 Qa an | 2 23} vee VCC Power Supply GND Ground Pin P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-2M= Gc MxX29F1611 ae BLOCK DIAGRAM i | CONTROL | PROGRAMERASE | WRITE INPUT /i _ STATE HIGH VOLTAGE \eo | MACHINE Ty | (WSM) Z | f COMMAND INTERFACE | REGISTER | MX29F1611 m | ADDRESS 8 FLASH oO ars LATCH | > 5 ARRAY ARRAY 15/A-1 i ne SOURCE | AO-ATS AND x - HV COMMAND go BUFFER | mR DATA | =) | YPASS GATE DECODER D i T t N oe 7 a a tt SENSE] | pen ; DATA |e. i | AMPLIFIER Hy |* COMMAND Le: C DATA LATCH | "y > i a. ~. PAGE [ PROGRAM DATA LATCH | I \ 7 AVA ] No po Q0-015/A-1 ) |" BUFFER 9 | P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-3M=Iic MxX29F1611 Table1.PIN DESCRIPTIONS SYMBOL TYPE AQ -A19 INPUT NAME AND FUNCTION ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Q8 -Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled Qi S/A -1 INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB ADDRESS(BYTE = LOW) CE INPUT CHIP ENABLE INPUTS: Activate the devices control logic, Input buffers, decoders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low toselect the device. OE INPUT OUTPUT ENABLES: Gates the devices data through the output buffers during a read cycle OE is active low. WE INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active low. WP INPUT WRITE PROTECT: Top or Bottom sector can be protected by writing a non- volatile protect-bit for each sector. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. The WP input buffer is disabled when PWD transitions low(deep power-down mode). BYTE INPUT BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or output on QO-7 and Q8-14 float. AddressQ15/A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/A-1 input buffer. Address AO, then becomes the lowest order address. Vcc DEVICE POWER SUPPLY(5V+ 5%) GND GROUND PIN: PM0440 REV. 1.6, JUL. 16, 1998 27-4M=Iic MxXxX29F1611 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU . Alf bus cycles to or from the flash memory conform fo standard microprocessor bus cycles. Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH) Mode Notes | CE | OE | WE | AO | A1 | AS |} Q0-Q7 | @8-Q14 | Q15/A-1 Read 1 VIL VIL VIH xX x x DOUT DOUT DOUT Output Disable 1 VIL VIH VIH x x x HighZ HighZ HighZ Standby 1 VIH X x xX x xX HighZ HighZ HighZ Deep Power-Down 1 x Xx x X X X HighZ High Z HighZ Manufacturer iD 2,4 Vit VIL VIH VIL Vit VID C2H OOH 0B Device ID 2,4 VIL VIL VIH VIH VIL VID F7H 00H 0B Write 1,3 VIL VIH VIL xX x X DIN DIN DIN Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL) Mode Notes} CE | OE | WE | AO | A1 | AQ | Q0-Q7 | @8-Q14 | QI15/A-1 Read 1 VIL VIL VIH xX Xx x DOUT DOUT VIL/VIH Output Disable 1 VIL VIH VIH x x xX HighZ High Z X Standby 1 VIH x xX x x Xx HighZ HighZ x Deep Power-Down 1 X xX Xx x X x HighZ HighZ X Manufacturer ID 2,4 VIL VIL VIH VIL VIL VID C2H High Z VIL Device iD 2,4 VIL VIL VIH VIH VIL VID F7H HighZ VIL Write 1,3 VIL VIH VIL x x x DIN HighZ VILMVIH NOTES: 1. X can be VIH or VIL for address or control pins. 2. AQ and At at VIL provide manufacturer ID codes. AQ at VIH and A1 at VIL provide device ID codes. AO at VIL, A1 at VIH and with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4) 3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence. 4. VID = 11.5V- 12.5V. 5. Q15/A-1 = VIL, QO - Q7 =D0-D7 out. Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out. P/N: PMO0440 REV. 1.6, JUL. 16, 1998 27-5WRITE OPERATIONS Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. Inthe event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control TABLE 3. COMMAND DEFINITIONS MxX29F1611 the program sequences and the CIR will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash family command. Command Read/ | Silicon [Page/Byte}] Chip | Sector | Erase Erase Read Clear Sequence Reset | ID Read] Program | Erase | Erase [Suspend | Resume j Status Reg. [ Status Reg. Bus Write 4 4 4 6 3 3 4 3 Cycles Req'd First Bus Addr 15555H | 5555H | 5555H_ |5555H | 5555H | 5555H_ | 5555H 5555H 5555H Write Cycle Data | AAH AAH AAH AAH AAH AAH AAH AAH AAH Second Bus Addr | 2AAAH f 2AAAH J 2AAAH [2AAAH | 2AAAH | 2AAAH J 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H 55H 55H 55H 55H 55H Third Bus Addr _5555H | 5555H {| 5555H {5555H | 5555H | 5555H_ | 5555H 9955H 5959H Write Cycle Data FOH 90H AOH 80H 80H BOH DOH 70H 50H Fourth Bus Addr RA} OOH/01H PA 5555H | 5555H xX Read/Write Cycle | Data RD |[C2H/F7HE PD AAH AAH SRD Fifth Bus Addr 2AAAH | 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr 5555H |_ SA Write Cycle Data 10H 30H P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-6M> Gc MxX29F1611 a COMMAND DEFINITIONS(continue Table 3.) Command Sector Sector Verify Sector ] Sleep Abort Sequence Protection Unprotect Protect Bus Write 6 6 4 3 3 Cycles Req'd First Bus Addr 5555H 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH | 2AAAH Write Cycle Data 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H Write Cycle Data 60H 60H 90H COH EOH Fourth Bus Addr 5555H 5555H * ReadMrite Cycle Data AAH AAH C2H* Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr SA** SA Write Cycle Data 20H 40H Notes: 1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AQ to A14. 2. Bus operations are defined in Fable 2. 3. RA = Address of the memory location to be read. _ PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A16 -- A19 will uniquely select any sector. 4, RD = Data read from location RA during read operation. _ PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. SRD = Data read from status register. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care. * Refer to Table 4, Figure 12. ** Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18,A17,A16) = O000B or 1111B is valid. an P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-7Mic DEVICE OPERATION SILICON ID READ The Silicon 1D Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address AO from VIL to VIH. All addresses are don't cares except AO and A1. MxXxX29F1611 The manufacturer and device codes may also be read via the command register, for instances when the MX29F 161 1 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is . ilustrated in Table 3. Byte 0 (A0=VIL) represents the manfacturers code (MXIC=C2H) and byte 1 (AO=VIH) the device identifier code (MX29F 161 1=F7H). To terminate the operation, it is necessary to write the read/ reset command sequence into the CIR. Table 4. MX29F1611 Silion ID Codes and Verify Sector Protect Code Type Aig |Aig|Aiz|Aiet A: | Ap | Code(HEX) |DQ,)DQ,|/DQ,;DQ,;DQ,|DQ,|DQ,|/Da Manufacturer Code X 1X] xX] xX [VILE VIL C2H* 1 1 0 0 0 0 1 0 MX29F1611 Device Code| X | X | X | X | VIL|VIH F7H* 1 1 1 1 0 1 1 1 Verify Sector Protect Sector Address*** | VIH} VIL C2H** 1 1 0 0 0 0 1 0 * MX29F1611 Manufacturer Code = C2H, Device Code = F7H when BYTE = VIL MX29F 1611 Manufacturer Code = 00C2H, Device Code = 00F7H when BYTE = VIH * Outputs C2H at protected sector address, 0OH at unprotected scetor address. *** Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16) = OOOOB or 1111B P/N: PM0440 27-8 REV. 1.6, JUL. 16, 1998Mic READ/RESET COMMAND The read or reset operation is initiated by writing the read/ resat command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer tothe AC Read Characteristics and Waveforms for the specific timing parameters. The MX29F 1611 is accessed like an EPROM. When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever GE or OE is high. This dual line control gives designers flexibility in preventing bus contention. Note that the read/reset command is not valid when program or erase is in progress. PAGE READ The MX29F 1611 offers fast page mode read feature. The users can take the access time advantage if keeping CE, OE at low and the same page address (A3~A19 unchanged). Please refer to Figure 5-2 for detailed timing waveform. The system performance could be enhanced by initiating 1 normal read and 7 fast page reads(for word mode A0~A2) or 15 fast page reads(for byte mode altering A-1~A2). PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock write cycles. These are followed by writing the page program command- AOH. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSW)}, no data will be written to the device. MxX29F1611 After three-cycte command sequence is given, a byte (word) load is performed by applying a iow pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below. BYTE-WIDE LOAD/WORD-WIDE LOAD Byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. A byte ioad(word load) is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide load is determined(Byte = VIL or VIHis latched) on the falling edge of the WE(or CE) during the 3rd command write cycle. PROGRAM Any page to be programmed should have the page in the erased state first, i.e. performing sector rase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte(word) of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte(word) thatis not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte(word) has been loaded into the device, successive bytes(words) are entered in the same manner. Each new byte(word) to be programmed must have its high to low transition on WE (or CE) within 30us of the low to high transition of WE (or CE) of the preceding byte(word). A6 to A19 specify the page address, i.e., the device is page- aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of WE or CE. A-1 to A5 specify the byte address within the page, AO to A5 specify the word address withih the page. P/N: PM0440 27-9 REV. 1.6, JUL. 16, 1998MI The byte(word) may be loaded in any order; sequential loading is not required. Ifa high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on DQ7 is 1 at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 1,7,8) CHIP ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H. Chip erase does not require the user to program the device prior to erase. The automatic erase begins on the rising edge of the last WE pulse in the command sequence andterminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 2,7,9) Table 5. MX29F 1611 Sector Address Tabie (Byte-Wide Mode) A19|A18\A17| A16/| Address Range[A19, -1] SAO |0| 0); 0 0 000000H--01FFFFH SA1 0 0; 0 1 020000H--0O3FFFFH SA2 | 0 | 0 1 0 040000H--O5FFFFH SA3 | 0 | 0 1 1 O60000H--07FFFFH SA4 | 0 1 0 0 O80000H--O9FFFFH SA15) 1 1 1 1 1EQOO00H--1FFFFFH MX29F1611 SECTOR ERASE Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set- up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3, 6 and Figure 3,4,7,9)) ERASE SUSPEND This command only has meaning while the the WSM is executing SECTOR or CHIP erase operation, and therefore will only be responded to during SECTOR or CHIP erase operation. After this command has been executed, the CIR will initiate the WSM to suspend erase operations, and then return to Read Status Register mode. The WSM will set the DQ6 bit to a1". Once the WSM has reached the Suspend state,the WSM will set the DQ7 bit toa "1", At this time, WSM allows the CIR to respond to the Read Array, Read Status Register, Abort and Erase Resume commands only. In this mode, the CIR will not resopnd to any other comands. The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input control pins. ERASE RESUME This command will cause the CIR to clear the suspend state and set the DQ6 to a0, but only ifan Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-10Mic READ STATUS REGISTER The MXiCs16 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. The status register bits are output on DQ2 - DQ7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode forthe MX29F 161 1. Inthe word-wide mode the upper byte, DQ(8:15) is set to OOH during a Read Status command. Inthe byte-wide mode, DQ(8:14) are tri-stated and DQ15/A-1 retains the low order address function. DQ0- DQ1 is set to OH in either x8 or x16 mode. it should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fail or Program fail status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29F 1611 automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program or Read Status Command write cycle. The default state of the Status Register after powerup and return from deep power-down mode is (DQ7, DQ6, DQ5, DQ4) = 1000B. DQ3 = 0 or 1 depends on sector-protect status, can not be changed by Clear Status Register Command or Write State Machine. DQ@2 =0 or 1 depends on Sleep status, During Sleep mode or Abort mode DQ@2 is set to "1"; DQ2 is reset to "0" by Read Array command. MX29F1611 CLEAR STATUS REGISTER The Eraes fail status bit (DQ5) and Program fail status bit (DQ4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-11M=Ic MxX29F1611 TABLE 6. MX29F1611 STATUS REGISTER STATUS NOTES | 0Q@7 | DQ6 | DQS5 | DQ4/|DQ3; DA2 IN PROGRESS PROGRAM 1,2, 6,7 0 0 0 0 0/1 0/1 ERASE 1,3, 6,7 0 0 0 0 oO 0/1 SUSPEND (NOT COMPLETE) 1,4, 6,7 0 1 0 0 of o/4 (COMPLETE) 1 1 0 0 of 0/4 COMPLETE PROGRAM 1,2, 6,7 1 0 0 0 o/1 0A ERASE 1,3, 6,7 1 0 0 0 oO 0/1 FAIL PROGRAM 1,5, 6,7 1 0 0 1 oO 0/1 ERASE 1,5, 6,7 1 0 1 0 oO 0/1 AFTER CLEARING STATUS REGISTER 6,7 1 0 0 0 0/1 * NOTES: -1.DQ7 : WRITE STATE MACHINE STATUS 1 = READY, 0 = BUSY DQ6 : ERASE SUSPEND STATUS 1 = SUSPEND, 0 = NO SUSPEND DQS5 : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE DQ4 : PROGRAM FAIL STATUS. 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM DQ3 : SECTOR-PROTECT STATUS 1 = SECTOR 0 ORVAND 15 PROTECTED 0 = NONE OF SECTOR PROTECTED DQ2: SLEEP STATUS 1 = DEVICE IN SLEEP STATUS 0 = DEVICE NOT IN SLEEP STATUS DQ1 - 0 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register. . PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode. . ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode. . SUSPEND STATUS is for both Sector and Chip Erase mode . . FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively. . DQ3 = 0 ort depends on Sector-Protect Status. . DQ2 = G or 1 depends on whether device is in the Sleep mode or not . Once in the Sleep mode, DQ2 is set to "1", and is reset by read array command only.- rN OOP ON P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-12M=Ic a HARDWARE SECTOR PROTECTION The MX29F 1611 features sector protection. This feature will disable both program and erase operations in either the top or the bottom sector (0 or 15). The sector protection feature is enabled using system software by the user(Refer to table 3). The device is shipped with both sectors unprotected. Alternatively, MXIC may protect sectors in the factory prior to shipping the device. SECTOR PROTECTION To activate this mode, a six-bus cycle operation is required. There are two unlock write cycles. These are followed by writing the set-up command. Two more unlock write cycles are then followed by the Lock Sector command - 20H, Sector address is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is 1 at which time the device stays at the read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence (Refer to table 3,6 and Figure 10,12 ). VERIFY SECTOR PROTECT To verify the Protect status of the Top and the Bottom sector, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from address XXX0H retrieves the Manufacturer code of C2H. Aread cycle from XXX1H returns the Device code F7H. A read cycle from appropriate address returns information as to which sectors are protected. To terminate the operation, it is necessary to write the read/reset command sequence into the CIR. (Refer to table 3,4 and Figure 12) A few retries are required if Protect status can not be verified successfully after each operation. SECTOR UNPROTECT itis also possible to unprotect the sector , same as the first five write command cycles in activating sector protection MX29F1611 mode followed by the Unprotect Sector command - 40H, the automatic Unprotect operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is 1 at which time the device stays at the read status register mode.(Refer to table 3,6 and Figure 11,12) The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. Either Protect or Unprotect sector mode is accomplished by keeping WP high, i.e. protect-bit status can only be changed with a valid command sequence and WP at high. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. Protect-bit status will not be changed during chip/sector erase operations. With WP at VIL, only unprotected sectors can be programmed or erased. SLEEP MODE The MX29F 1611 features two software controlled low- power modes : Sleep and Abort modes. Sleep mode is allowed during any current operations except that once Suspend command is issued, Sleep command is ignored. Abort mode is excuted only during Page Program and Chip/ Sector Erase mode. To activate Sleep mode, a three-bus cycle operation is required. The COH command (Refer to table 3) puts the device inthe Sleep mode. Once in the Sleep mode and with CMOS input level applied, the current of the device is 100uUA. The Sleep command allows the device to COMPLETE current operations before going into Sleep mode. Once current operation is done, device stays at read status ragister mode. The status registers are not reset during sleep command. Program or erase fail bit may have been set if during program/erase mode the device retry exceeds maximum count. During Sleep mode, the status registers, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Writing the Read Array command wakes up the device out of sleep mode. DQ2 is reset to "0" and Device returns to standby current level. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-13M= SG MX29F1611 ABORT MODE To activate Abort mode, a three-bus cycle operation is required. The EOH command (Refer to table 3) only stops Page program or Sector /Chip erase operation currently in progress and puts the device in Sleep mode. But unlike the sleep command, the program or erase operation will not be completed. Since the data in some page/sectors is no longer valid due to an incomplete program or erase operation, the program fail (DQ4) or erase fail (DQ5)bit will be set. After the abort command is executed and with CMOS input level applied, the device current is reduced fo the same level as in sleep modes. During Abort mode, the status registers, Silicon iD codes remain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Similar to the sleep mode, A read array command MUST be written to bring the device out of the abort state without incurring any wake up latency. Note that once device is waken up, Clear status register mode is required before a program or erase operation can be executed. DATA PROTECTION The MX29F 1611 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to ihe read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 10ns (typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a lagical zero while OE is a logical one. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-14Mic Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART OT START Y MxX29F1611 Write Data AAH Address 5555H ! Write Data 55H Address 2AAAH oe Write Data AOH Address 5555H + | Write Program Data/Address Loading End? YES Wait 100us i Read Status Register Y <a YES = YES Page Program Completed Y To Continue Other Operations, Do Clear S.R. Mode First Program another page? NO Operation Done, Device Stays At Read S.R. Mode Note : S.R. Stands for Status Register P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-15M=I MX29F1611 Figure 2. AUTOMATIC CHIP ERASE FLOW CHART Write Data AAH Address 5555H Y Write Data 55H Address 2AAAH { Write Data 8OH Address 5555H y Write Data AAH Address 5555H Y Write Data 55H Address 2AAAH Write Data 10H Address 5555H Read Status Register YES To Execute Suspend Mode ? Erase Suspend Flow (Figure 4.) YES y NO YES Chip Erase Completed { Erase Error ) y 1 Operation Done, To Continue Other Device Stays at Operations, Do Clear Read S.R. Mode $.R. Mode First P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-16M=I5 MxX29F1611 a, Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART START y Write Data AAH Address 5555H ' Write Data 55H Address 2AAAH ! Write Data 80H Address 5555H Y Write Data AAH Address 5555H Y Write Data 55H Address 2AAAH YY Write Data 30H Sector Address Read Status Register To Execute Suspend Erase ? Erase Suspend Flow (Figure 4.) <> YES Sector Erase Compieted ' Operation Done. Device Stays at Read S.R. Mode S.R. Mode First Erase Error AJ To Continue Other Operations, Do Clear P/N: PMO440 REV. 1.6, JUL. 16, 1998 27-17= MxXxX29F1611 Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART START Write Data AAH Address 55551 Write Data SSH Address 2AAAH 1 Write Data BOH Address 5555H Y Read Status Register + NO <a YES y NO NO YES Yes 1 1 __Bmserancomstes ne competes C _ fee ener _ } Y Y Operation Done, Device Stays at Read SR, Mode To Continue Other Operations, Do Clear S.R. Mode First Write Data AAH Address 5555H y Write Data 55H Address 2AAAH Y Write Data FOH Address 5555H Read Array | Reading End ? YES x Write Data AAH Address 5555 Write Data SSH Address 2AAAM | y Write Data DOH Address 55S5H Continue Erase P/N: PMO440 REV. 1.6, JUL. 16, 1998 27-18M=I MxX29F1611 ee ELECTRICAL SPECIFICATIONS NOTICE: han th tresses greater than those listed under ABSOLUTE ABSOLUTE MAXIMUM RATINGS MAXIMUM RATINGS may cause permanent damage to the RATING VALUE device. This is stress rating only and functional operational Ambient Operating Temperature OCto70C sections of this specification is not implied. Exposure to ~ - absolute maximum rating conditions for extended period may Storage Temperature -65 Cto 125 C affect reliability. Applied Input Voltage -0.5V to 7.0V NOTICE: #2 Specifications contained within the following tables are subject Applied Output Voltage -0.5V to 7.0V to change. VCC to Ground Potential -0.5V to 7.0V Ag -0.5V to 13.5V CAPACITANCE TA =25 C, f= 1.0 MHz SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 14 pF VIN = 0V COUT Quitput Capacitance 16 pF VOUT = 0V SWITCHING TEST CIRCUITS DEVICE 1.8K ohm UNDER VA oO +5 TEST DIODES = IN3064 OR EQUIVALENT CL. = 100 pF Including jig capacitance SWITCHING TEST WAVEFORMS Vec ~/- ~ 2.0V v > o.av TEST POINTS ov INPUT QUTPUT AC TESTING: Inputs are driven at Vcc for a logic "1" and OV for a logic "0". Input pulse rise and fall times are < 10ns. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-19M=I : MX29F1611 Tn DC CHARACTERISTICS =0 Cto70 C, VCC =5V:5% SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS He Input Load 1 10 uA VCC = VCC Max Current VIN = VCC or GND [LO Output Leakage 1 10 uA VCC = VCC Max Current VIN = VCC or GND ISB1 VCC Standby 1 50 100 uA VCC = CC Max Current(CMOS) CE = VCC + 0.2V Icc1 VCC Read 1 80 120 mA VCC = VCC Max Current CMOS: CE = GND + 0.2V BYTE = GND + 0.2V or VCC + 0.2V Inputs = GND + 0.2V or VCC + 0.2V f = 10MHz, IOUT = 0 mA IcC2 VCC Read 1 60 100 mA VCC = VCC Max, Current CMOS: CE = GND + 0.2V BYTE = VCC + 0.2V or GND + 0.2V Inputs = GND + 0.2V or VCC + 0.2V TTL: CE = VIL, BYTE = ViH or VIL Inputs = VIL or VIH, f = 5MHz, IOUT = OmA ICC3 VCC Erase 1,2 5 10 mA CE = VIH Suspend Current BLack Erase Suspended ICC4 VCC Program 1 30 50 mA Program in Progress Current Iccs VCC Erase Current 1 30 50 mA Erase in Progress VIL Input Low Voltage 3 -0.3 0.1 Vv VIH Input High Voltage 4 4.0 VCC+0.3 V VOL Output Low Voltage 0.45 Vv IOL = 2.1mA VOH Output High Voltage 2.4 Vv IOH = -400uUA NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25 C. These currents are valid for all product versions (package and speeds). 2. ICC3 is specified with the device de-selected. |f the device is read while in erase suspend mode, current draw is the sum of ICC3 and ICC 1/2. 3. VIL min. = -1.0V for pulse width is equal to or less than SOns. VIL min. = -2.0V for pulse width is equal to or less than 20ns. 4. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-20M=IiGc MxX29F1611 AC CHARACTERISTICS READ OPERATIONS 29F1611-10 29F1611-12 29F1611-15 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT ONDITIONS tACC Address to Output Delay 100 120 150 ns CE=OE=VIL tPA Page Mode Access Time 50 60 70 ns CE= OE = VIL tCE CE to Output Delay 100 120 150 ns OE=VIL tOE OE to Output Delay gg 60 70 ns CE=VIL iDF OE High to Output Delay 0 55 0 55 0 55 ns CE=VIL tOH Address to Output hold 0 0 0 ns CE=OES=VIL tBACG BYTE to Output Delay 100 120 150 ns CE=OE=VIL tBHZ BYTE Low to Output in High Z 55 55 70 ns CE=VIL TEST CONDITIONS: NOTE: + Input pulse levels: OV/Vcc 1. tDF is defined as the time at which the output achieves the * Input rise and fall times: 10ns open circuit condition and data is no longer driven. * Outputload: 1 TTL gate+100pF (Including scope and jig) * Reference levels for measuring timing: 0.8V, 2.0V P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-2)M=Iic MX29F1611 Figure 5-1. NORMAL READ TIMING WAVEFORMS Device and Standby Outputs Enabled Standby Vee Power-up address selection Data valid Vec Power-down ADDRESSES ADDRESSES STABLE CE = VIL or 1DF ~- VIH i - WE VIL #(tob y \ ~ tCE = : 10H -~ VOH nen? HIGH Z DATA OUT s i Data out valid 5 VOL \ ~ tACC ~ 5.0V vcc / GND NOTE: 1. For real world application, BYTE pin should be either static high(word mode) or static low(byte mode); dynamic switching of BYTE pin is not recommended. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-22=i: MX29F16141 an Figure 5-2. PAGE READ TIMING WAVEFORMS A3~A19 VALID ADDRESS A0~A2(Word mode} | A-1~A2(Byte mode) x ) ( <a - tACC CE | | | ! ! at - OE : \ * tPA [* tPA >| tPA f{ ~ | >| at | Hs tOE* <> {tDF DATA OUT + \ . -\ Figure 6. BYTE TIMING WAVEFORMS VI VIL CE VIL = VIL OE IDF ~a ~ 1BACC = - VIH ~~ ~ 10E ave vt a 1CE ~ wm 10H 4 VOH wiahz HIGH Z DATA(DQ0-DQ7) tf ( Data Output X ata ouput pp} vou tACC = tBHZ ~<a ~ VOH IGH Z VOL _| PIN: PM0440 REV. 1.6, JUL. 16, 1998 27-23M=Ic MxX29F1611 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS 29F1611-10 29F1611-12 29F 1611-15 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT twc Write Cycle Time 100 120 150 ns tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 45 50 60 ns DS Data Setup Time 45 50 60 ns tDH Data Hold Time 10 10 10 ns tOES Output Enable Setup Time 0 0 0 ns tCES CE Setup Time 0 0 i) ns tGHWL Read Recover TimeBefore Write 0 0 0 tCs CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns twP Write Pulse Width 45 50 60 ns tWPH Write Pulse Width High 50 50 50 ns tBALC Byte(Word) Address Load Cycle 0.3 30 0.3 30 0.3 30 us tBAL Byte(Word) Address Load Time 100 100 100 us tSRA Status Register Access Time 100 120 150 ns tCESR CE Setup before S.R. Read 100 100 100 ns tVCS VCC Setup Time 2 2 2 us P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-24M=Iic. MxX29F1611 Figure 7. COMMAND WRITE TIMING WAVEFORMS CE tCH \ YON tOES . er ts OE = ~ we : < - WE em NY wer \ - ~~ twP <_ ~ ADDRESSES 10S 10H - _? - (D/Q) VCC wes <-_ > NOTE: 1. BYTE pin is treated as address pin All timing specifications for BYTE pin are the same as those for address pin. 2. BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application BYTE pin should be either static high(word mode) or static tow(byte mode). PIN: PM0440 REV. 1.6, JUL. 16, 1998 27-25vic _ Mx29F1611 Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS 4 Word offset ast Word A0~AS 55H AAH 5SH Address ae Low/High Last Low/High - Ad Byte Select Byte Select (byte mode only) AB~A14 x 55H x 2AH x 55H x Page Address H tAS Al e twe {BALC {BAL twPOIWPH =~ > <P NIN IN IN INOS {CES =a / NS DS ap (OH ~ 1 {SRA ~ DATA AAH 55H AOH Write a Write SRD NOTE: 1.Please refer to page 9 for detail page program operation. P/N: PM0440 : , REV. 1.6, JUL. 16, 1998 27-26=I MxX29F1611 Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS A0~A14 */5555H tAS {AH =a ~< - A1S A16~A19 tCESR . _ > NIN IN IN INS NS NS we fWPH > E we ~ Ices i ce _/ Vf 1DS ate tOH ~ _ tSRA , iat DATA ' AAH 55H 80H AAH 55H 30H/10H (spp ) NOTES: 1."*" means don't care" in this diagram. 2."SA" means "Sector Adddress. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-27Mic Figure 10. SECTOR PROTECTION ALGORITHM MxX29F1611 1 Write Data AAH Adidress 5555H ' Write Data 5SH Address 2AAAH Write Data 60H Address 5555H y Write Data AAH Address S555H Write Data 55H Address 2AAAH Increment PLSCNT, To Protect Sector Again t Hy Write Data 20H, Sector Address Y Read Status Register ' NO YES NO y Protect Sector YES Operation Terminated NO Device Failed To Verify Protect Verity Protect Status Flow Data Status 7 (Figure 12) = C2H? NO t YES Device Stays at Read S.R. Mode Sector Protacted,Operation Done, Device Stays at Verify Sector Protect Mode NOTE : *Only the Top or the Bottom Sector Address is vaild in this feature. i.e. Sector Address = (A19,A18,A17,A16) = O000B or 1111B ; PMO440 REV. 1.6, JUL. 16, 1998 27-28Mic TN Figure 11. SECTOR UNPROTECT ALGORITHM MxX29F1611 START, PLSCNT=0 ms Write Data AAH Address 5555H ' Write Data 5SH Address 2AAAH 1 Write Data 60H Address 5555H y Write Data AAH Address 5555H Y Write Data 55H Address 2AAAH Write Data 40H, Sector Address Y Read Status Register YES Unprotect Sector Operation Terminated To Verify Protect Status ? Verity Protect Status Flow (Figure 12) NO Device Stays at Read S.R. Mode NOTE : | *Only the Top or the Bottom Sector Address is vaild in this feature. i.e. Sector Address = (A19,A18,A17,A16) = OOOOB or 1111B Increment PLSCNT, To Unprotect Sector Again i Data = 00H ? 1 YES YES Device Failed Sector Unprotected,Operation Dane, Device Stays at Verity Sector Protect Mode P/N: PM0440 27-29 REV. 1.6, JUL. 16, 998M=| MxX29F1611 Figure 12. VERIFY SECTOR PROTECT FLOW CHART START Yr Write Data AAH, Address 5555H | f Write Data 55H, Address 2AAAH ! Write Data 90H, Address 5555H Y Ptoect Status Read* * 1. Protect Status: Data Outputs C2H as Protected Sector Verified Code. Data Outputs 00H as Unprotected Sector Verified Code. 2. Sepecified address will be either {(A19,A18,A17,A16,A1,A0) = (000010) or (111110), the rest of the address pins are don't care. 3. Silicon ID and Test Row lock status can be read via this Flow Chart. Refer to Table 4. P/N: PM0440 27-30 REV. 1.6, JUL. 16, 1998| | MX29F1614 Figure 13. COMMAND WRITE TIMING WAVEFORMS (Alternate CE Controlled) WE (\ .- | 7 OE = ~ tw CE _ GHW {CPH NN = - ADDRESSES 1iDS 1DH ? ~ ~ ~ (D/Q) Vcc _S wes > ? NOTE: 1. BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address gin. 2. BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world applicaton, BYTE oin should be either static high(word mode) or static low(byte mode). P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-31MEIC Mx29F16141 a Figure 14. AUTOMATIC PAGE: PROGRAM TIMING WAVEFORM(Alternate CE Controlled) Word offset it Word a z eee Po ca ow/Higl ((Byte Mode Only) AG~A14 55H 2AH 55H Xx Page Address Ga 1AS AH _ - ~ two tBALC ~ VN NDS | ae aa BAL NN NI NS NS NS NS [\ = Oe _/ . \ f/f 0S oH => : ~~ ~< 1SRA a oAtA (oat) (oon CE Daia Data NOTE: 1.Please refer to page 9 for detait page program operation. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-32M=Iic. MxX29F1614 ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. | MAX. (Note 1) | UNITS Chip/Sector Erase Time : 100 (Note 2) ms Page Programming Time 5 (Note 3) ms Chip Programming Time 80 150 sec Erase/Program Cycles 10,000 Cycles Byte Program Time 39 us *Note 1: MAX values are all evaluated with polling the status in stead of internal state machine time out. Note 2: The IC internal state machine is set 2000 ms as maximum chip/sector erase time out. Note 3: We set 60 ms as production test condition, whereas, the IC internal state machine is set 150 ms as maximum programming time out. LATCHUP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voitage with respect to GND on all I/O pins -1.0V Vec + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. P/N: PM0440 REV. 1.6, JUL. 16, 1998 27-33Mic Mx2eF1644 Revision History o . Rev. # Description Date 1.1 Write-Erase cycles change from 1,000/10,000 to 100,000. 10/29/1997 1.2 Programming Performance table updated again 03/19/1998 1.3 Write-Erase cycles change from 100,000to 10,000 04/09/1998 1.4 Correct Page Pregramming waveform and delete RY/BY,PWD wafewaves on Page 26 & 04/10/1998 . Page 32 respetively 1.5 VIL MAX. 0.1-->0.4 ; VIH MIN. 4-->3.5 07/13/1998 1.6 VIL MAX. 0.4-->0.1 ; VIH MIN. 3.5-->4 07/16/1998 P/N: PMO440 REV. 1.6, JUL. 16, 1998 27-34