Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-50
0278I—06/03/03
Block Diagram
Frequency Timing Generator for Pentium II Systems
Pin Configuration
• Generates the following system clocks:
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free
running).
- 2 REF clks (3.3V) at 14.318MHz.
• Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
• Supports Spread Spectrum modulation for CPU and
PCI clocks, 0.5% down spread
• Efficient Power management scheme through stop
clocks and power down modes.
• Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
• 28-pin (209 mil) SSOP package
The ICS9248-50
ICS9248-50
Power Groups
28-Pin SSOP
2
ICS9248-50
0278I—06/03/03
Pin Descriptions
Pin number Pin name Type Description
1 GNDREF Power Ground for 14.318 MHz reference clock outputs
2 X1 Input 14.318 MHz cr
y
stal input
3 X2 Output 14.318 MHz crystal output
4 PCICLK_F Output 3.3 V free runnin
g
PCI clock output, will not be stopped b
y
the PCI_STOP#
5,6,9,10,11 PCICLK (1:5) Output 3.3 V PCI clock outputs,
g
eneratin
g
timin
g
requirements for Pentium IIä
7 GNDPCI Power Ground for PCI clock outputs
8 VDDPCI Power 3.3 V power for the PCI clock outputs
12 VDD48 Power 3.3 V power for 48/24 MHz clocks
13 48 MHz Output 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
14 TS#/48/24MHz Output 3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for
testin
g
, active hi
g
h = normal operation
15 GND48 Power Ground for 48/24 MHz clocks
16 SEL 100/66# Input
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selected cases.
17 PD# Input
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
18 CPU_STOP# Input
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
19 VDD Power Isolated 3.3 V power for core
20 PCI-Stop# Input Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
21 GND Power Isolated
g
round for core
22 GNDL Power Ground for CPU clock outputs
23,24 CPUCLK(1:0) Output 2.5 V CPU clock outputs
25 VDDL Power 2.5 V power for CPU clock outputs
26 REF1/SPREAD# Output
3.3 V 14.318 MHz reference clock output and power-on spread spectrum enable
option. Active low = spread spectrum clocking enable. Active high = spread
spectrum clocking disable.
27 REF0/SEL48# Output 3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
28 VDDREF Power 3.3 V power for 14.318 MHz reference clock outputs.
3
ICS9248-50
0278I—06/03/03
Select Functions
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10 edoMtseT
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1- )devreseR(
11 ICP3.33,UPCzHM001evitcA
Power Management
ICS9248-50 Power Management Requirements
Clock Enable Configuration
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
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10 1 zHM6.66/001woLzHM3.33gninnuRgninnuRgninnuR
111 zHM6.66/001zHM3.33zHM3.33gninnuRgninnu
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4
ICS9248-50
0278I—06/03/03
PCI_STOP# Timing Diagram
ICS9248-50
ICS9248-50
CPU_STOP# Timing Diagram
ICS9248-50
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
5
ICS9248-50
0278I—06/03/03
PD# Timing Diagram
ICS9248-50
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
6
ICS9248-50
0278I—06/03/03
Absolute Maximum Ratings
DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 0°C to +115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD + 0.3 V
Input Low Voltage VIL VSS - 0.3 0.8 V
Input High Current IIH VIN
= VDD 0.1 5 mA
Input Low Current IIL1 VIN
= 0 V; Inputs with no pull-up resistors -5 2.0 mA
Input Low Current IIL2 VIN
= 0 V; Inputs with pull-up resistors -200 -100 mA
IDD3.3OP66 CL = 0 pF; Select @ 66MHz 60 180 mA
IDD3.3OP100 CL = 0 pF; Select @ 100MHz 66 180 mA
IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz 16 72 mA
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz 23 100 mA
Power Down
Suppl
y
Current IDD3.3PD CL = 0 pF; With input address to Vdd or GND 70 600 mA
Input frequency FiVD
D
= 3.3 V; 11 14.318 16 MHz
Input Capacitance1CIN Logic Inputs 5 pF
CINX X1 & X2 pins 27 36 45 pF
Transition Time1Ttrans To 1st crossing of target Freq. 3 ms
Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3 ms
Skew1TCPU-PCI VT = 1.5 V; VTL = 1.25 V 1.5 3 4 ns
Operating
Supply Current
7
ICS9248-50
0278I—06/03/03
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH2B IOH = -12.0 mA 1.8 2.3 V
Output Low Voltage VOL2B IOL = 12 mA 0.31 0.4 V
Output High Current IOH2B VOH = 1.7 V -27 mA
Output Low Current IOL2B VOL = 0.7 V 27 mA
Rise Time tr2B1VOL = 0.4 V, VOH = 2.0 V 0.4 1.15 1.6 ns
Fall Time tf2B1VOH = 2.0 V, VOL = 0.4 V 0.4 1.4 1.6 ns
Duty Cycle dt2B1V
T
= 1.25 V 44 48 55 %
Skew tsk2B1V
T
= 1.25 V 134 175 ps
Jitter period(norm) V
T
= 1.25 V; 100MHz 10 10 10.5 ns
Jitter t
c
c-c
c2B1V
T
= 1.25 V 186 200 ps
Jitter, Absolute tjabs2B1VT = 1.25 V -250 150 +250 ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF/48MHz/24MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH5 IOH = -12 mA 2.6 3.1 V
Output Low Voltage VOL5 IOL = 9 mA 0.17 0.4 V
Output High Current IOH5 VOH = 2.0 V -44 -22 mA
Output Low Current IOL5 VOL = 0.8 V 16 42 mA
Rise Time1tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 4 ns
Fall Time1tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 4 ns
Duty Cycle1dt5 V
T
= 1.5 V 45 53 55 %
t
j
1s5 V
T
= 1.5 V, REF 185 250 ps
t
j
abs5 V
T
= 1.5 V, REF 385 800 ps
t
j
1s5 V
T
= 1.5 V, 48 MHz 169 250 ps
tjabs5 VT = 1.5 V, 48 MHz 469 800 ps
Jitter1
Jitter1
8
ICS9248-50
0278I—06/03/03
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH1 IOH = -18 mA 2.1 3.3 V
Output Low Voltage VOL1 IOL = 9.4 mA 0.1 0.4 V
Output High Current IOH1 VOH = 2.0 V -22 mA
Output Low Current IOL1 VOL = 0.8 V 16 57 mA
Rise Time1tr1 VOL = 0.4 V, VOH = 2.4 V 1.6 2 ns
Fall Time1tf1 VOH = 2.4 V, VOL = 0.4 V 1.8 2 ns
Duty Cycle1dt1 V
T
= 1.5 V 45 50 55 %
Skew1tsk1 V
T
= 1.5 V 222 500 ps
t
j
c
y
c-c
y
cV
T
= 1.5 V 186 500 ps
t
j
1s V
T
= 1.5 V 52 150 ps
tjabs VT = 1.5 V 200 500 ps
1Guaranteed by design, not 100% tested in production.
Jitter1
9
ICS9248-50
0278I—06/03/03
General Layout Precautions:
Notes:
Capacitor Values:
10
ICS9248-50
0278I—06/03/03
Ordering Information
9248yF-50-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
XXXX y F - PPP - T
MIN MAX MIN MAX
A - 2.00 - .079
A1 0.05 - .002 -
A2 1.65 1.85 .065 .073
b 0.22 0.38 .009 .015
c 0.09 0.25 .0035 .010
D
E 7.40 8.20 .291 .323
E1 5.00 5.60 .197 .220
e
L 0.55 0.95 .022 .037
N
α0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
82.70
3.30 .106 .130
14 5.90 6.50 .232 .256
16 5.90 6.50 .232 .256
18 6.90 7.50 .271 .295
20 6.90 7.50 .271 .295
22 7.90 8.50 .311 .335
24 7.90 8.50 .311 .335
28 9.90 10.50 .390 .413
30 9.90 10.50 .390 .413
38 12.30 12.90 .484 .508
MO-150 JEDEC
Doc.# 10-0033 6/1/00 Rev B
ND mm. D (inch)
SEE VARIATIONS
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS In Inches
COMMON DIMENSIONS
SEE VARIATIONS
0.65 BASIC 0.0256 BASIC