MC54HC4040AN - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 1

 Motorola, Inc. 1995

10/95

  



High–Performance Silicon–Gate CMOS

The MC54/74C4040A is identical in pinout to the standard CMOS

MC14040. The device inputs are compatible with standard CMOS out-

puts; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of 12 master–slave flip–flops. The output of each

flip–flop feeds the next and the frequency at each output is half of that of

the preceding one. The state counter advances on the negative–going

edge of the Clock input. Reset is asynchronous and active–high.

State changes of the Q outputs do not occur simultaneously because of

internal ripple delays. Therefore, decoded output signals are subject to

decoding spikes and may have to be gated with the Clock of the

HC4040A for some designs.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With JEDEC Standard No. 7A Requirements

•Chip Complexity: 398 FETs or 99.5 Equivalent Gates

LOGIC DIAGRAM

Q10

Clock 10

Reset 11 Pin 16 = VCC

Pin 8 = GND

1516 14 13 12 11 10

21 34567

VCC 9

Q11 Q10 Q8 Q9 Reset Clock Q1

Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND

Pinout: 16–Lead Plastic Package

(Top View)

Q11

Q12



FUNCTION TABLE

Clock Reset Output State

No Charge

Advance to Next State

All Outputs Are Low

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXXAJ

MC74HCXXXXAN

MC74HCXXXXAD

MC74HCXXXXADT

Ceramic

Plastic

SOIC

TSSOP

16 DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

MC54/74HC4040A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature Range

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

Ceramic DIP

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

TSSOP Package: – 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

600

500

400

ÎÎÎ

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Condition

VCC

Guaranteed Limit

Unit

Symbol

Parameter

Condition

VCC

–55 to 25°C≤85°C≤125°C

Unit

VIH Minimum High–Level Input Voltage Vout = 0.1V or VCC –0.1V

|Iout| ≤ 20µA2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

VIL Maximum Low–Level Input Voltage Vout = 0.1V or VCC – 0.1V

|Iout| ≤ 20µA2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

VOH Minimum High–Level Output

Voltage Vin = VIH or VIL

|Iout| ≤ 20µA2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low–Level Output

Voltage Vin = VIH or VIL

|Iout| ≤ 20µA2.0

4.5

6.0

0.1

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC4040A

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Unit

Guaranteed Limit

VCC

ConditionParameter

Symbol Unit≤125°C≤85°C–55 to 25°C

VCC

ConditionParameter

Vin = VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

ICC Maximum Quiescent Supply

Current (per Package) Vin = VCC or GND

Iout = 0µA6.0 4 40 160 µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

VCC

Guaranteed Limit

Unit

Symbol

Parameter

VCC

–55 to 25°C≤85°C≤125°C

Unit

fmax Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4) 2.0

3.0

4.5

6.0

9.0

8.0

MHz

tPLH,

tPHL Maximum Propagation Delay, Clock to Q1*

(Figures 1 and 4) 2.0

3.0

4.5

6.0

106

115

tPHL Maximum Propagation Delay, Reset to Any Q

(Figures 2 and 4) 2.0

3.0

4.5

6.0

tPLH,

tPHL Maximum Propagation Delay, Qn to Qn+1

(Figures 3 and 4) 2.0

3.0

4.5

6.0

tTLH,

tTHL Maximum Output Transition Time, Any Output

(Figures 1 and 4) 2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance 10 10 10 pF

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns

VCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0V: tP = [24.4 + 12 (n–1)] ns

CPD

Power Dissipation Capacitance (Per Package)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC4040A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Symbol

Parameter

VCC

Guaranteed Limit

Unit

Symbol

Parameter

VCC

–55 to 25°C≤85°C≤125°C

Unit

trec Minimum Recovery Time, Reset Inactive to Clock

(Figure 2) 2.0

3.0

4.5

6.0

twMinimum Pulse Width, Clock

(Figure 1) 2.0

3.0

4.5

6.0

twMinimum Pulse Width, Reset

(Figure 2) 2.0

3.0

4.5

6.0

tr, tfMaximum Input Rise and Fall Times

(Figure 1) 2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

PIN DESCRIPTIONS

INPUTS

Clock (Pin 10)

Negative–edge triggering clock input. A high–to–low tran-

sition on this input advances the state of the counter.

Reset (Pin 11)

Active–high reset. A high level applied to this input asynch-

ronously resets the counter to its zero state, thus forcing all Q

outputs low.

OUTPUTS

Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)

Active–high outputs. Each Qn output divides the Clock

input frequency by 2N.

SWITCHING WAVEFORMS

Clock

VCC

GND

90%

50%

10%

90%

50%

10%

tPHL

1/fMAX

tPLH

tTLH tTHL

Clock VCC

GND

trec

50%

Figure 1. Figure 2.

Reset VCC

GND

50%

Any Q 50%

tPHL

MC54/74HC4040A

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

SWITCHING WAVEFORMS (continued)

50%

Qn VCC

GND

50%

Qn+1

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Figure 4. Test Circuit

tPLH tPHL

Figure 5. Expanded Logic Diagram

Clock 10 C

Reset 11

Q19

Q27Q36Q10

14 Q11

15 Q12

Q4 = Pin 5

Q5 = Pin 3

Q6 = Pin 2

Q7 = Pin 4

Q8 = Pin 13

Q9 = Pin 12

VCC = Pin 16

GND = Pin 8

MC54/74HC4040A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

Clock

Reset

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

Q10

Q11

Figure 6. Timing Diagram

Q12

APPLICATIONS INFORMATION

Time–Base Generator

A 60Hz sinewave obtained through a 1.0 Megohm resistor

connected directly to a standard 120 Vac power line is

applied to the input of the MC54/74HC14A, Schmitt-trigger

inverter. The HC14A squares–up the input waveform and

feeds the HC4040A. Selecting outputs Q5, Q10, Q11, and

Q12 causes a reset every 3600 clocks. The HC20 decodes

the counter outputs, produces a single (narrow) output pulse,

and resets the binary counter . The resulting output frequency

is 1.0 pulse/minute.

HC4040A

Figure 7. Time–Base Generator

Clock Q5

Q10

Q11

Q12

VCC

1/2

HC20 1/2

HC20 6

1/6 of HC14A

≥

20pF

1.0M

1.0 Pulse/Minute

Output

VCC

120Vac

60Hz

MC54/74HC4040A

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10

—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0.51 15

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM 0.750

0.240

—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

0.020 15

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE

THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

D 16 PL

–T

–

SEATING

PLANE

J 16 PL

0.25 (0.010) T A

MS0.25 (0.010) T B

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

1 8

916

HGD 16 PL

–T

–

SEATING

PLANE

KJM

T A0.25 (0.010) M M

0.25 (0.010) T B A

MS S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

9.80

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

D16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HC4040A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C––– 1.20 ––– 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH OR

GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER

SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT

DATUM PLANE –W–.

_ _ _ _

SECTION N–N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉ

DETAIL E

2X L/2

–U–

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

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MC54/74HC4040A/D

*MC54/74HC4040A/D*

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