19-4575; Rev 0; 4/09 KIT ATION EVALU E L B AVAILA Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver Features Single +3.3V Supply Operation The MAX4952A dual-channel redriver is designed to redrive one full lane of SAS or SATA signals up to 6.0GT/s (gigatransfers per second) and operates from a single +3.3V supply. The MAX4952A features independent input equalization and output preemphasis. The MAX4952A enhances signal integrity at the receiver by equalizing the signal at the input and establishing preemphasis at the output of the device. SAS and SATA OOB (Out-of-Band) signaling is supported using high-speed amplitude detection on the inputs and squelch on the corresponding outputs. Inputs and outputs are all internally 50 terminated and must be AC-coupled to the SAS/SATA controller IC and SAS/SATA device. The MAX4952A is available in a small 28-pin, 3.5mm x 5.5mm TQFN package with flowthrough traces for ease of layout. This device is specified over the 0C to +70C operating temperature range. SAS Gen I/II Up to 6.0GT/s Excellent Return Loss 8dB at 3.0GT/s Supports SAS/SATA OOB (Out-of-Band) Signaling Very Fast Entry and Exit Time 5ns (typ) Internal Input/Output 50 Termination Resistors Selectable Input Equalization 0, 3dB Standard 1000mVP-P (typ) Output Selectable Output Preemphasis 0, 3dB Inline Signal Traces for Flowthrough Layout Space-Saving, 3.5mm x 5.5mm TQFN Package Applications Ordering Information Servers Data Storage/Work Stations Docking Stations PART TEMP RANGE PIN-PACKAGE MAX4952ACTI+ 0C to +70C 28 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration MODE VCC GND IN1M IN1P GND OUT0M OUT0P GND VCC TOP VIEW 24 23 22 21 20 19 18 17 16 15 14 PE1 GND 25 13 EQ1 GND 26 MAX4952A GND 27 12 PE0 GND 28 IN0M 7 8 9 10 EN IN0P 6 VCC VCC 5 GND 4 OUT1M 3 OUT1P 2 11 EQ0 GND 1 GND *EP TQFN *CONNECT EXPOSED PAD (EP) TO GND. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX4952A General Description MAX4952A Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VCC ........................................................................-0.3V to +4.0V All Other Pins..............................................-0.3V to (VCC + 0.3V) Continuous Current (PE_, EQ_, MODE)............................15mA Peak Current (for 10kHz, 1% duty cycle) (IN__, OUT__) .............................................................100mA Continuous Power Dissipation (TA = +70C) 28-Pin TQFN (derate 28.6mW/C above +70C) .......2286mW Junction-to-Case Thermal Resistance (JC) (Note 1) 28-Pin TQFN................................................................2.7C/W Junction-to-Ambient Thermal Resistance (JA) (Note 1) 28-Pin TQFN.................................................................35C/W Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-55C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, CCOUPLE = 12nF, RL = 50, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL Operating Power-Supply Range VCC Operating Supply Current ICC Standby Supply Current I STBY CONDITIONS MIN TYP 3.0 MAX UNITS 3.6 V EQ_ = PE_ = GND 140 175 EQ_ = PE_ = VCC 175 220 16 20 mA EN = GND mA Input Termination RRX-SE Single-ended to VCC 42.5 57.5 Output Termination RTX-SE Single-ended to VCC 42.5 57.5 AC PERFORMANCE Differential Input Return Loss (Note 3) Common-Mode Input Return Loss (Note 3) Differential Output Return Loss (Note 3) Common-Mode Output Return Loss (Note 3) Differential Input Voltage Input Equalization Differential Output Voltage Output Preemphasis Propagation Delay Output Transition Time 2 SDD11 SCC11 SDD22 SCC22 VIN-DIFF EQ VOUT-DIFF 0.1GHz f 0.3GHz -10 0.3GHz f 3.0GHz -7.9 3.0GHz f 6.0GHz 0 0.1GHz f 0.3GHz -6 0.3GHz f 3.0GHz -5 3.0GHz f 6.0GHz 0 0.1GHz f 0.3GHz -10 0.3GHz f 3.0GHz -7.9 3.0GHz f 6.0GHz 0 0.1GHz f 0.3GHz -6 0.3GHz f 3.0GHz -5 3.0GHz f 6.0GHz 0 dB dB dB SAS 1.5, 3.0, or 6.0GT/s MODE = GND 275 1600 SATA 1.5, 3.0, or 6.0GT/s MODE = VCC 225 1600 EQ_ = VCC (Note 4) f = 750MHz, PE_ = GND PE PE_ = VCC, Figure 1 t PD PE_ = EQ_ = GND TTX-RF dB PE_ = GND, 20% to 80% 3 800 mVP-P dB 1200 mVP-P 3 dB 300 ps 30 _______________________________________________________________________________________ ps Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver (VCC = +3.0V to +3.6V, CCOUPLE = 12nF, RL = 50, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL Differential Output Skew Same Pair TSK CONDITIONS MIN Deterministic Jitter TDJ K28.5 pattern, 6.0GT/s, PE_ = EQ_ = GND (Note 3) Random Jitter TRJ D10.2 pattern, 6.0GT/s, PE_ = EQ_ = GND TYP MAX 10 UNITS ps 20 psP-P 1.5 psRMS MODE = GND, f = 0.75GHz 120 220 MODE = VCC, f = 0.75GHz 50 150 mVP-P OOB Squelch Threshold VSQ-DIFF OOB Squelch Entry Time T OOB,SQ f = 0.75GHz (Note 3) 5 ns OOB Squelch Exit Time T OOB,EX f = 0.75GHz (Note 3) 9 ns OOB Differential Offset Delta VOOB,DIFF Difference between OOB and active-mode output offset -50 +50 mV OOB Common-Mode Offset Delta VOOB,CM Difference between OOB and active-mode output common-mode voltage -30 +30 mV OOB Output Disable VOOB,OUT OOB disabled output level 30 mVP-P CONTROL LOGIC INPUTS Input Logic-High VIH Input Logic-Low 1.4 V VIL Input Logic Hysteresis VHYST Input Leakage Current I IN 0.6 75 VCC = +3.3V, VIN = +0.5V or +1.5V -50 V mV +50 A Note 2: All devices are 100% production tested at TA = +70C. All temperature limits are guaranteed by design. Note 3: Guaranteed by design. Note 4: EQ (input equalization) as employed in this device refers to the equivalent of adding preemphasis before the input. For example, input EQ of 3dB would show the same waveform as output PE of 3dB (see Figure 1). Timing Diagram VLOW_P-P VHIGH_P-P VHIGH_P-P PE(dB) = 20log V LOW_P-P Figure 1. Output Preemphasis _______________________________________________________________________________________ 3 MAX4952A ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +3.3V, TA = +25C, all eye diagrams measured using K28.5 pattern.) VIN = 275mVP-P, 1.5Gbps, PE = 0, EQ = 0 VIN = 275mVP-P, 3Gbps, PE = 0, EQ = 0 VIN = 275mVP-P, 6Gbps, PE = 0, EQ = 0 MAX4952A toc02 400 200 0 -200 -400 400 200 0 -200 -400 MAX4952A toc03 600 EYE DIAGRAM VOLTAGE (200mV/div) EYE DIAGRAM VOLTAGE (200mV/div) MAX4952A toc01 EYE DIAGRAM VOLTAGE (200mV/div) 400 200 0 -200 -400 -600 -400 -200 0 200 400 -200 200ps/div -100 0 100 200 400 200 0 -200 -400 -600 MAX4952A toc05 800 EYE DIAGRAM VOLTAGE (200mV/div) 600 0 VIN = 275mVP-P, 3Gbps, PE = 1, EQ = 0 MAX4952A toc04 -800 600 400 200 0 -200 -400 -600 -800 -400 -200 0 200 400 -200 -100 200ps/div 0 100 200 100ps/div VIN = 275mVP-P, 6Gbps, PE = 1, EQ = 0 VIN = 1600mVP-P, 1.5Gbps, PE = 0, EQ = 0 MAX4952A toc06 800 400 200 0 -200 -400 -600 MAX4952A toc07 600 EYE DIAGRAM VOLTAGE (200mV/div) 600 -800 400 200 0 -200 -400 -600 -100 -50 0 50ps/div 4 -50 50ps/div VIN = 275mVP-P, 1.5Gbps, PE = 1, EQ = 0 EYE DIAGRAM VOLTAGE (200mV/div) -100 100ps/div 800 EYE DIAGRAM VOLTAGE (200mV/div) MAX4952A Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver 50 100 -400 -200 0 200 400 200ps/div _______________________________________________________________________________________ 50 100 Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver VIN = 1600mVP-P, 3Gbps, PE = 0, EQ = 0 0 -200 -400 -600 400 200 0 -200 -400 -100 0 100 200 -100 100ps/div 400 200 0 -200 -400 -600 -50 0 50 -400 100 -200 VIN = 1600mVP-P, 3Gbps, PE = 1, EQ = 0 200 0 -200 -400 -600 400 MAX4952A toc12 800 EYE DIAGRAM VOLTAGE (200mV/div) 400 200 VIN = 1600mVP-P, 6Gbps, PE = 1, EQ = 0 MAX4952A toc11 600 0 200ps/div 50ps/div 800 EYE DIAGRAM VOLTAGE (200mV/div) 600 -800 -600 -800 600 400 200 0 -200 -400 -600 -800 -200 -100 0 100 200 -100 -50 100ps/div VIN = 500mVP-P WITH 20in FR4 STRIPLINE, 3GT/s, PE = 0, EQ = 0 600 400 200 0 -200 -400 -600 -200 -100 0 100ps/div 50 100 VIN = 500mVP-P WITH 20in FR4 STRIPLINE, 6GT/s, PE = 0, EQ = 0 MAX4952A toc13 -300 0 50ps/div MAX4952A toc14 EYE DIAGRAM VOLTAGE (200mV/div) -200 MAX4952A toc10 800 EYE DIAGRAM VOLTAGE (200mV/div) EYE DIAGRAM VOLTAGE (200mV/div) 200 EYE DIAGRAM VOLTAGE (200mV/div) EYE DIAGRAM VOLTAGE (200mV/div) MAX4952A toc09 600 400 VIN = 1600mVP-P, 1.5Gbps, PE = 1, EQ = 0 VIN = 1600mVP-P, 6Gbps, PE = 0, EQ = 0 MAX4952A toc08 600 100 200 300 600 400 200 0 -200 -400 -600 -150 -100 -50 0 50 100 150 50ps/div _______________________________________________________________________________________ 5 MAX4952A Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25C, all eye diagrams measured using K28.5 pattern.) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25C, all eye diagrams measured using K28.5 pattern.) VIN = 500mVP-P WITH 20in FR4 STRIPLINE, 3GT/s, PE = 0, EQ = 1 VIN = 500mVP-P WITH 20in FR4 STRIPLINE, 6GT/s, PE = 0, EQ = 1 600 MAX4952A toc16 EYE DIAGRAM VOLTAGE (200mV/div) EYE DIAGRAM VOLTAGE (200mV/div) MAX4952A toc15 400 200 0 -200 -400 -600 -300 -200 -100 0 100 200 600 400 200 0 -200 -400 -600 300 -150 -50 50 100 150 VIN = 275mVP-P, 3GT/s, PE = 0, EQ = 0, OUTPUT AFTER 20in FR4 STRIPLINE VIN = 275mVP-P, 6GT/s, PE = 0, EQ = 0, OUTPUT AFTER 20in FR4 STRIPLINE MAX4952A toc18 500 400 300 200 100 0 -100 -200 -300 -400 -500 -300 -200 -100 0 100 200 500 400 300 200 100 0 -100 -200 -300 -400 -500 300 -150 -100 -50 100ps/div EYE DIAGRAM VOLTAGE (100mV/div) 400 300 200 100 0 -100 -200 -300 -400 -500 -100 0 100ps/div 100 150 MAX4952A toc20 500 -200 50 VIN = 275mVP-P, 6GT/s, PE = 1, EQ = 0, OUTPUT AFTER 20in FR4 STRIPLINE MAX4952A toc19 -300 0 50ps/div VIN = 275mVP-P, 3GT/s, PE = 1, EQ = 0, OUTPUT AFTER 20in FR4 STRIPLINE 6 0 50ps/div EYE DIAGRAM VOLTAGE (100mV/div) EYE DIAGRAM VOLTAGE (100mV/div) -100 100ps/div MAX4952A toc17 EYE DIAGRAM VOLTAGE (100mV/div) MAX4952A Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver 100 200 300 500 400 300 200 100 0 -100 -200 -300 -400 -500 -150 -100 -50 0 50 100 50ps/div _______________________________________________________________________________________ 150 Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver PIN NAME FUNCTION 1, 9, 16, 24 VCC Positive Supply Voltage Input. Bypass VCC to GND with 2.2F and 0.01F capacitors in parallel as close as possible to the device, recommended on each VCC pin. 2, 5, 8, 17, 20, 23, 25-28 GND Ground 3 IN0P Noninverting Input 0 4 IN0M Inverting Input 0 6 OUT1P 7 OUT1M Noninverting Output 1 Inverting Output 1 10 EN Active-High Enable Input. Drive EN low to put device in standby mode. Drive EN high for normal operation. EN is internally pulled down. 11 EQ0 Channel 0 Input Equalizer Logic Input. EQ0 is internally pulled down. 12 PE0 Channel 0 Output Preemphasis Logic Input. PE0 is internally pulled down. 13 EQ1 Channel 1 Input Equalizer Logic Input. EQ1 is internally pulled down. 14 PE1 Channel 1 Output Preemphasis Logic Input. PE1 is internally pulled down. 15 MODE OOB Threshold Logic Input. MODE is internally pulled down. 18 IN1M Inverting Input 1 19 IN1P Noninverting Input 1 21 OUT0M Inverting Output 0 22 OUT0P Noninverting Output 0 -- EP Exposed Pad. Internally connected to GND. EP must be electrically connected to a ground plane for proper thermal and electrical operation. Do not use EP as the sole ground connection. _______________________________________________________________________________________ 7 MAX4952A Pin Description Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver MAX4952A Functional Diagram VCC MAX4952A VCC VCC 50 50 50 50 IN0P OUT0P IN0M OUT0M VCC VCC 50 50 50 50 OUT1M IN1M OUT1P IN1P CONTROL LOGIC EN GND EQ0 PE0 EQ1 MODE PE1 Typical Application Circuit MIDPLANE SAS CONTROLLER SAS/SATA HDD 18in SAS CABLE 20in BOARD TRACES CONNECTORS 8 MAINBOARD MAX4952A 8in BOARD TRACES _______________________________________________________________________________________ Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver The MAX4952A consists of two identical redrivers with input equalization and output preemphasis useful for SAS or SATA signals up to 6.0GT/s. Input/Output Terminations Inputs and outputs are internally 50 terminated to VCC (see the Functional Diagram) and must be AC-coupled using 12nF (max) capacitors to the SAS/SATA controller IC and SAS/SATA device for proper operation. Enable Input (EN) The MAX4952A features an active-high enable input (EN). EN has an internal pulldown resistor of 70k (typ). When EN is driven low or left unconnected, the MAX4952A enters low-power standby mode and the redrivers are disabled. Drive EN high for normal operation. Out-of-Band Threshold Selector (MODE) The MAX4952A provides full OOB signal support through high-speed amplitude detection circuitry. OOB differential input signals less than the internal OOB threshold (V SQ-DIFF ) are detected as OFF and not passed to the output. This prevents the system from responding to unwanted noise. OOB differential input signals higher than VSQ-DIFF are detected as ON and passed to the output, allowing OOB signals to transmit through the MAX4952A. The logic level of the MODE input sets VSQ-DIFF for either SAS or SATA OOB signals (see Table 1). MODE has an internal pulldown resistor of 70k (typ). Table 1. Out-of-Band Logic Threshold (MODE) MODE OOB MODE 0 SAS 1 SATA Input Equalization (EQ0, EQ1) The MAX4952A features control logic inputs (EQ0, EQ1) to enable input equalization on either channel, providing 3dB of boost (see Note 4 in the Electrical Characteristics table). Drive EQ0 or EQ1 high to enable input equalization on channel 0 or channel 1. Drive EQ0 or EQ1 low to disable input equalization on channel 0 or channel 1 (see Table 2). EQ0 and EQ1 have internal pulldown resistors of 70k (typ). Table 2. Input Equalization (EQ0, EQ1) EQ1 EQ0 CHANNEL 1 (dB) CHANNEL 0 (dB) 0 0 0 0 0 1 0 3 (typ) 1 0 3 (typ) 0 1 1 3 (typ) 3 (typ) Output Preemphasis (PE0, PE1) The MAX4952A features control logic inputs (PE0, PE1) to enable output preemphasis on either channel, providing 3dB of boost. The MAX4952A uses true preemphasis, so the transition signal is increased after a changing bit, thus increasing the total energy content of the signal when employed. Drive PE0 or PE1 high to enable output preemphasis on channel 0 or channel 1. Drive PE0 or PE1 low to disable output preemphasis on channel 0 or channel 1 (see Table 3). PE0 and PE1 have internal pulldown resistors of 70k (typ). Table 3. Output Preemphasis (PE0, PE1) PE1 PE0 CHANNEL 1 (dB) CHANNEL 0 (dB) 0 0 0 0 0 1 0 3 (typ) 1 0 3 (typ) 0 1 1 3 (typ) 3 (typ) _______________________________________________________________________________________ 9 MAX4952A Detailed Description MAX4952A Dual Equalized 1.5/3.0/6.0 GT/s SAS/SATA Redriver Applications Information Exposed Pad Package The exposed pad, 28-pin TQFN package incorporates features that provide a very low thermal resistance path for heat removal from the IC. The exposed pad on the MAX4952A must be soldered to GND for proper thermal and electrical performance. For more information on exposed pad packages, refer to Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages. Power-Supply Sequencing Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the device. Proper power-supply sequencing is recommended for all devices. Always apply VCC before applying signals, especially if the signal is not current limited. Chip Information PROCESS: BiCMOS Package Information Layout Use controlled-impedance transmission lines to interface with high-speed inputs and outputs of the MAX4952A. Place power-supply 2.2F and 0.01F bypass capacitors as close as possible to VCC, recommended on each VCC pin. For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 TQFN T283555-1 21-0184 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.