MAX4952ACTI+T - Maxim Integrated

General Description

The MAX4952A dual-channel redriver is designed to

redrive one full lane of SAS or SATA signals up to

6.0GT/s (gigatransfers per second) and operates from

a single +3.3V supply.

The MAX4952A features independent input equalization

and output preemphasis. The MAX4952A enhances sig-

nal integrity at the receiver by equalizing the signal at

the input and establishing preemphasis at the output of

the device. SAS and SATA OOB (Out-of-Band) signaling

is supported using high-speed amplitude detection

on the inputs and squelch on the corresponding outputs.

Inputs and outputs are all internally 50Ωterminated and

must be AC-coupled to the SAS/SATA controller IC and

SAS/SATA device.

The MAX4952A is available in a small 28-pin, 3.5mm x

5.5mm TQFN package with flowthrough traces for ease

of layout. This device is specified over the 0°C to +70°C

operating temperature range.

Applications

Servers

Data Storage/Work Stations

Docking Stations

Features

♦Single +3.3V Supply Operation

♦SAS Gen I/II Up to 6.0GT/s

♦Excellent Return Loss

8dB at 3.0GT/s

♦Supports SAS/SATA OOB (Out-of-Band) Signaling

Very Fast Entry and Exit Time

5ns (typ)

♦Internal Input/Output 50ΩTermination Resistors

♦Selectable Input Equalization

0, 3dB

♦Standard 1000mVP-P (typ) Output

♦Selectable Output Preemphasis

0, 3dB

♦Inline Signal Traces for Flowthrough Layout

♦Space-Saving, 3.5mm x 5.5mm TQFN Package

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

________________________________________________________________

Maxim Integrated Products

TOP VIEW

MAX4952A

TQFN

*EP

EQ0

PE0

EQ1

PE1

GND

12345678910

24 23 22 21 20 19

*CONNECT EXPOSED PAD (EP) TO GND.

18 17 16 15

VCC

GND

OUT1M

OUT1P

GND

IN0M

IN0P

GND

VCC

GND

IN1M

IN1P

MODE

GND

OUT0M

OUT0P

GND

VCC

Pin Configuration

19-4575; Rev 0; 4/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX4952ACTI+ 0°C to +70°C 28 TQFN-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.6V, CCOUPLE = 12nF, RL= 50Ω, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V,

TA= +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

(Voltages referenced to GND.)

VCC ........................................................................-0.3V to +4.0V

All Other Pins..............................................-0.3V to (VCC + 0.3V)

Continuous Current (PE_, EQ_, MODE)............................±15mA

Peak Current (for 10kHz, 1% duty cycle)

(IN__, OUT__) .............................................................±100mA

Continuous Power Dissipation (TA= +70°C)

28-Pin TQFN (derate 28.6mW/°C above +70°C) .......2286mW

Junction-to-Case Thermal Resistance (θJC) (Note 1)

28-Pin TQFN................................................................2.7°C/W

Junction-to-Ambient Thermal Resistance (θJA) (Note 1)

28-Pin TQFN.................................................................35°C/W

Operating Temperature Range...............................0°C to +70°C

Storage Temperature Range .............................-55°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Power-Supply Range VCC 3.0 3.6 V

EQ_ = PE_ = GND 140 175

Operating Supply Current ICC EQ_ = PE_ = VCC 175 220

Standby Supply Current ISTBY EN = GND 16 20 mA

Input Termination RRX-SE Single-ended to VCC 42.5 57.5 

Output Termination RTX-SE Single-ended to VCC 42.5 57.5 

AC PERFORMANCE

0.1GHz  f  0.3GHz -10

0.3GHz  f  3.0GHz -7.9

Differential Input Return Loss

(Note 3) SDD11

3.0GHz  f  6.0GHz 0

0.1GHz  f  0.3GHz -6

0.3GHz  f  3.0GHz -5

Common-Mode Input Return

Loss (Note 3) SCC11

3.0GHz  f  6.0GHz 0

0.1GHz  f  0.3GHz -10

0.3GHz  f  3.0GHz -7.9

Differential Output Return Loss

(Note 3) SDD22

3.0GHz  f  6.0GHz 0

0.1GHz  f  0.3GHz -6

0.3GHz  f  3.0GHz -5

Common-Mode Output Return

Loss (Note 3) SCC22

3.0GHz  f  6.0GHz 0

SAS 1.5, 3.0, or 6.0GT/s MODE = GND 275 1600

Differential Input Voltage VIN-DIFF SATA 1.5, 3.0, or 6.0GT/s MODE = VCC 225 1600

mVP-P

Input Equalization EQ EQ_ = VCC (Note 4) 3 dB

Differential Output Voltage VOUT-DIFF f = 750MHz, PE_ = GND 800 1200 mVP-P

Output Preemphasis PE PE_ = VCC, Figure 1 3 dB

Propagation Delay tPD PE_ = EQ_ = GND 300 ps

Output Transition Time TTX-RF PE_ = GND, 20% to 80% 30 ps

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.6V, CCOUPLE = 12nF, RL= 50Ω, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V,

TA= +25°C.) (Note 2)

Note 2: All devices are 100% production tested at TA= +70°C. All temperature limits are guaranteed by design.

Note 3: Guaranteed by design.

Note 4: EQ (input equalization) as employed in this device refers to the equivalent of adding preemphasis before the input. For

example, input EQ of 3dB would show the same waveform as output PE of 3dB (see Figure 1).

Timing Diagram

VLOW_P-P VHIGH_P-P

PE(dB) = 20log VHIGH_P-P

VLOW_P-P

⎛

⎝

⎜

⎡

⎣

⎢

⎛

⎝

⎜

⎡

⎣

⎢

Figure 1. Output Preemphasis

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Output Skew Same Pair T

10 ps

Deterministic Jitter T

K28.5 pattern, 6.0GT/s, PE_ = EQ_ = GND

(Note 3) 20 ps

P-P

Random Jitter T

D10.2 pattern, 6.0GT/s, PE_ = EQ_ = GND 1.5 ps

RMS

MODE = GND, f = 0.75GHz 120 220

OOB Squelch Threshold V

SQ-DIFF

MODE = V

, f = 0.75GHz 50 150 mV

P-P

OOB Squelch Entry Time T

OOB,SQ

f = 0.75GHz (Note 3) 5 ns

OOB Squelch Exit Time T

OOB,EX

f = 0.75GHz (Note 3) 9 ns

OOB Differential Offset Delta V

OOB,DIFF

Difference between OOB and active-mode

output offset -50 +50 mV

OOB Common-Mode Offset

Delta V

OOB,CM

Difference between OOB and active-mode

output common-mode voltage -30 +30 mV

OOB Output Di sable V

OOB,OUT

OOB disabled output level 30 mV

P-P

CONTROL LOGIC INPUTS

Input Logic-High V

1.4 V

Input Logic-Low V

0.6 V

Input Logic Hysteresis V

HYST

75 mV

Input Leakage Current I

= +3.3V, V

= +0.5V or +1.5V -50 +50 μA

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

4 _______________________________________________________________________________________

VIN = 275mVP-P, 1.5Gbps, PE = 0, EQ = 0

200ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

4002000-200-400

-400

-200

200

400

MAX4952A toc01

VIN = 275mVP-P, 3Gbps, PE = 0, EQ = 0

100ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

2001000-100-200

-400

-200

200

400

MAX4952A toc02

VIN = 275mVP-P, 6Gbps, PE = 0, EQ = 0

50ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

100500-50-100

-400

-200

200

400

MAX4952A toc03

600

-600

VIN = 275mVP-P, 1.5Gbps, PE = 1, EQ = 0

200ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

400200-400 -200 0

-600

-400

-200

200

400

600

800

-800

MAX4952A toc04

VIN = 275mVP-P, 3Gbps, PE = 1, EQ = 0

100ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

200100-200 -100 0

-600

-400

-200

200

400

600

800

-800

MAX4952A toc05

VIN = 275mVP-P, 6Gbps, PE = 1, EQ = 0

50ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

10050-100 -50 0

-600

-400

-200

200

400

600

800

-800

MAX4952A toc06

Typical Operating Characteristics

(VCC = +3.3V, TA= +25°C, all eye diagrams measured using K28.5 pattern.)

VIN = 1600mVP-P, 1.5Gbps, PE = 0, EQ = 0

200ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

4002000-200-400

-400

-200

200

400

MAX4952A toc07

600

-600

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

_______________________________________________________________________________________ 5

Typical Operating Characteristics (continued)

(VCC = +3.3V, TA= +25°C, all eye diagrams measured using K28.5 pattern.)

VIN = 1600mVP-P, 3Gbps, PE = 0, EQ = 0

100ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

2001000-100-200

-400

-200

200

400

MAX4952A toc08

600

-600

VIN = 1600mVP-P, 6Gbps, PE = 0, EQ = 0

50ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

100500-50-100

-400

-200

200

400

MAX4952A toc09

600

-600

VIN = 1600mVP-P, 1.5Gbps, PE = 1, EQ = 0

200ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

400200-400 -200 0

-600

-400

-200

200

400

600

800

-800

MAX4952A toc10

VIN = 1600mVP-P, 3Gbps, PE = 1, EQ = 0

100ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

200100-200 -100 0

-600

-400

-200

200

400

600

800

-800

MAX4952A toc11

VIN = 1600mVP-P, 6Gbps, PE = 1, EQ = 0

50ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

10050-100 -50 0

-600

-400

-200

200

400

600

800

-800

MAX4952A toc12

VIN = 500mVP-P WITH 20in FR4 STRIPLINE,

3GT/s, PE = 0, EQ = 0

100ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

200100-200 -100 0

-600

-400

-200

200

400

600

MAX4952A toc13

-300 300

VIN = 500mVP-P WITH 20in FR4 STRIPLINE,

6GT/s, PE = 0, EQ = 0

50ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

10050-100 -50 0

-600

-400

-200

200

400

600

MAX4952A toc14

-150 150

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VCC = +3.3V, TA= +25°C, all eye diagrams measured using K28.5 pattern.)

VIN = 500mVP-P WITH 20in FR4 STRIPLINE,

3GT/s, PE = 0, EQ = 1

100ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

200100-200 -100 0

-600

-400

-200

200

400

600

MAX4952A toc15

-300 300

VIN = 500mVP-P WITH 20in FR4 STRIPLINE,

6GT/s, PE = 0, EQ = 1

50ps/div

EYE DIAGRAM VOLTAGE (200mV/div)

10050-100 -50 0

-600

-400

-200

200

400

600

MAX4952A toc16

-150 150

VIN = 275mVP-P, 3GT/s, PE = 0, EQ = 0,

OUTPUT AFTER 20in FR4 STRIPLINE

100ps/div

EYE DIAGRAM VOLTAGE (100mV/div)

2001000-100-200

-500

-400

-300

-200

-100

100

200

300

400

500

-300 300

MAX4952A toc17

VIN = 275mVP-P, 6GT/s, PE = 0, EQ = 0,

OUTPUT AFTER 20in FR4 STRIPLINE

50ps/div

EYE DIAGRAM VOLTAGE (100mV/div)

100500-50-100

-500

-400

-300

-200

-100

100

200

300

400

500

-150 150

MAX4952A toc18

VIN = 275mVP-P, 3GT/s, PE = 1, EQ = 0,

OUTPUT AFTER 20in FR4 STRIPLINE

100ps/div

EYE DIAGRAM VOLTAGE (100mV/div)

2001000-100-200

-500

-400

-300

-200

-100

100

200

300

400

500

-300 300

MAX4952A toc19

VIN = 275mVP-P, 6GT/s, PE = 1, EQ = 0,

OUTPUT AFTER 20in FR4 STRIPLINE

50ps/div

EYE DIAGRAM VOLTAGE (100mV/div)

100500-50-100

-500

-400

-300

-200

-100

100

200

300

400

500

-150 150

MAX4952A toc20

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

_______________________________________________________________________________________ 7

Pin Description

PIN NAME FUNCTION

1, 9, 16, 24 VCC Positive Supply Voltage Input. Bypass VCC to GND with 2.2µF and 0.01µF capacitors in parallel as

close as possible to the device, recommended on each VCC pin.

2, 5, 8,

17, 20, 23,

25–28

GND Ground

3 IN0P Noninverting Input 0

4 IN0M Inverting Input 0

6 OUT1P Noninverting Output 1

7 OUT1M Inverting Output 1

10 EN Active-High Enable Input. Drive EN low to put device in standby mode. Drive EN high for normal

operation. EN is internally pulled down.

11 EQ0 Channel 0 Input Equalizer Logic Input. EQ0 is internally pulled down.

12 PE0 Channel 0 Output Preemphasis Logic Input. PE0 is internally pulled down.

13 EQ1 Channel 1 Input Equalizer Logic Input. EQ1 is internally pulled down.

14 PE1 Channel 1 Output Preemphasis Logic Input. PE1 is internally pulled down.

15 MODE OOB Threshold Logic Input. MODE is internally pulled down.

18 IN1M Inverting Input 1

19 IN1P Noninverting Input 1

21 OUT0M Inverting Output 0

22 OUT0P Noninverting Output 0

—EP

Exposed Pad. Internally connected to GND. EP must be electrically connected to a ground plane for

proper thermal and electrical operation. Do not use EP as the sole ground connection.

MAX4952A

50Ω

VCC

50Ω50Ω

VCC

50Ω

IN0P

IN0M

OUT0P

OUT0M

50Ω

VCC

50Ω50Ω

VCC

50Ω

OUT1M

OUT1P

IN1M

IN1P

CONTROL LOGIC

EN MODE

EQ0 PE0 EQ1 PE1

GND

VCC

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

8 _______________________________________________________________________________________

Functional Diagram

Typical Application Circuit

MAINBOARDMIDPLANE

CONNECTORS

8in BOARD

TRACES

20in BOARD

TRACES

18in SAS

CABLE

SAS

CONTROLLER

SAS/SATA

HDD

MAX4952A

Detailed Description

The MAX4952A consists of two identical redrivers with

input equalization and output preemphasis useful for

SAS or SATA signals up to 6.0GT/s.

Input/Output Terminations

Inputs and outputs are internally 50Ωterminated to VCC

(see the

Functional Diagram

) and must be AC-coupled

using 12nF (max) capacitors to the SAS/SATA controller

IC and SAS/SATA device for proper operation.

Enable Input (EN)

The MAX4952A features an active-high enable input

(EN). EN has an internal pulldown resistor of 70kΩ

(typ). When EN is driven low or left unconnected, the

MAX4952A enters low-power standby mode and the

redrivers are disabled. Drive EN high for normal

operation.

Out-of-Band Threshold Selector (MODE)

The MAX4952A provides full OOB signal support

through high-speed amplitude detection circuitry. OOB

differential input signals less than the internal OOB

threshold (VSQ-DIFF) are detected as OFF and not

passed to the output. This prevents the system from

responding to unwanted noise. OOB differential input

signals higher than VSQ-DIFF are detected as ON and

passed to the output, allowing OOB signals to transmit

through the MAX4952A. The logic level of the MODE

input sets VSQ-DIFF for either SAS or SATA OOB signals

(see Table 1). MODE has an internal pulldown resistor

of 70kΩ(typ).

Input Equalization (EQ0, EQ1)

The MAX4952A features control logic inputs (EQ0,

EQ1) to enable input equalization on either channel,

providing 3dB of boost (see Note 4 in the

Electrical

Characteristics

table). Drive EQ0 or EQ1 high to enable

input equalization on channel 0 or channel 1. Drive EQ0

or EQ1 low to disable input equalization on channel 0 or

channel 1 (see Table 2). EQ0 and EQ1 have internal

pulldown resistors of 70kΩ(typ).

Output Preemphasis (PE0, PE1)

The MAX4952A features control logic inputs (PE0, PE1)

to enable output preemphasis on either channel, pro-

viding 3dB of boost. The MAX4952A uses true preem-

phasis, so the transition signal is increased after a

changing bit, thus increasing the total energy content of

the signal when employed. Drive PE0 or PE1 high to

enable output preemphasis on channel 0 or channel 1.

Drive PE0 or PE1 low to disable output preemphasis on

channel 0 or channel 1 (see Table 3). PE0 and PE1

have internal pulldown resistors of 70kΩ(typ).

MODE OOB MODE

0 SAS

1 SATA

Table 1. Out-of-Band Logic Threshold

(MODE)

EQ1 EQ0 CHANNEL 1

(dB)

CHANNEL 0

(dB)

0 0 0 0

0 1 0 3 (typ)

1 0 3 (typ) 0

1 1 3 (typ) 3 (typ)

Table 2. Input Equalization (EQ0, EQ1)

PE1 PE0 CHANNEL 1

(dB)

CHANNEL 0

(dB)

0 0 0 0

0 1 0 3 (typ)

1 0 3 (typ) 0

1 1 3 (typ) 3 (typ)

Table 3. Output Preemphasis (PE0, PE1)

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

_______________________________________________________________________________________ 9

MAX4952A

Dual Equalized 1.5/3.0/6.0 GT/s

SAS/SATA Redriver

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Applications Information

Exposed Pad Package

The exposed pad, 28-pin TQFN package incorporates

features that provide a very low thermal resistance path

for heat removal from the IC. The exposed pad on the

MAX4952A must be soldered to GND for proper thermal

and electrical performance. For more information on

exposed pad packages, refer to Maxim Application

Note HFAN-08.1:

Thermal Considerations of QFN and

Other Exposed-Paddle Packages

Layout

Use controlled-impedance transmission lines to inter-

face with high-speed inputs and outputs of the

MAX4952A. Place power-supply 2.2µF and 0.01µF

bypass capacitors as close as possible to VCC, recom-

mended on each VCC pin.

Power-Supply Sequencing

Caution: Do not exceed the absolute maximum rat-

ings because stresses beyond the listed ratings

may cause permanent damage to the device.

Proper power-supply sequencing is recommended for

all devices. Always apply VCC before applying signals,

especially if the signal is not current limited.

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns, go

to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TQFN T283555-1 21-0184