Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but th ere is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regar ding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various
means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams,
charts, programs, and algorithms, please be sure to evaluate all information as a total system before
making a final decision on the applicability of the information and products. Renesas Technology
Corpo r ation assumes no respon sibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be
exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products
contained therein.
HN58C1001 Series
1M EEPROM (128-kword × 8-bit)
Ready/Busy and RES function
ADE-203-028G (Z)
Rev. 7.0
Oct. 31, 1997
Description
The Hitachi HN58C1001 is a electrically erasable and programmable ROM organized as 131072-word × 8-
bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming
function to make the write operations faster.
Features
• Single supply: 5.0 V ± 10%
• Access time: 150 ns (max)
• Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic byte write: 10 ms (max)
• Automatic page write (128 bytes): 10 ms (max)
• Data polling and RDY/Busy
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 104 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin
HN58C1001 Series
2
Ordering Information
Type No. Access time Package
HN58C1001P-15 150 ns 600 mil 32-pin plastic DIP (DP-32)
HN58C1001FP-15 150 ns 525 mil 32-pin plastic SOP (FP-32D)
HN58C1001T-15 150 ns 8 × 14 mm 32-pin plastic TSOP (TFP-32DA)
Pin Arrangement
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
OE
A4
A5
A6
A7
A12
A14
A16
RDY/Busy
VCC
A15
RES
WE
A13
A8
A9
A11
(Top view)
HN58C1001T Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
RES
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/Busy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58C1001P/FP Series
Pin Description
Pin name Function
A0 to A16 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy Ready busy
RES Reset
HN58C1001 Series
3
Block Diagram
V
V
OE
CE
A6
A0
A7
A16
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/Bus
y
RES
to
to
to
Operation Table
Operation CE OE WE RES RDY/Busy I/O
Read VIL VIL VIH VH*1High-Z Dout
Standby VIH ×*2×× High-Z High-Z
Write VIL VIH VIL VHHigh-Z to VOL Din
Deselect VIL VIH VIH VHHigh-Z High-Z
Write Inhibit ××VIH ×——
×VIL ×× ——
Data Polling VIL VIL VIH VHVOL Dout (I/O7)
Program reset ×××VIL High-Z High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2. × : Don’t care
HN58C1001 Series
4
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS VCC –0.6 to +7.0 V
Input voltage relative to VSS Vin –0.5*1 to +7.0 V
Operating temperature range*2Topr 0 to + 7 0 °C
Storage temperature range Tstg –55 to +125 °C
Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 000V
Input voltage VIL –0.3*1— 0.8 V
VIH 2.2 — VCC + 0.3 V
VHVcc – 0.5 — VCC + 1.0 V
Operating temperature Topr 0 — 70 °C
Note: 1. VIL (min): –1.0 V for pulse width ≤ 50 ns
DC Characteristics (Ta = 0 to +70 °C, VCC = 5.0V ± 10%)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI ——2*
1µAV
CC = 5.5 V, Vin =5.5 V
Output leakage current ILO ——2 µAV
CC = 5.5 V, Vout = 5.5/0.4 V
Standby VCC current ICC1 ——20µACE = VCC
ICC2 ——1 mACE = VIH
Operating VCC current ICC3 — — 15 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs at VCC = 5.5 V
— — 50 mA Iout = 0 mA, Duty = 100%,
Cycle = 150 ns at VCC = 5.5 V
Output low voltage VOL — — 0.4 V IOL = 2.1 mA
Output high voltage VOH 2.4 — — V IOH = –400 µA
Notes: 1. ILI on RES: 100 µA (max)
HN58C1001 Series
5
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1Cin — — 6 pF Vin = 0 V
Output capacitance*1Cout — — 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70 °C, VCC = 5.0 V ± 10%)
Test Conditions
• Input pulse levels: 0.4 V to 2.4 V
0 V to VCC (RES pin)
• Input rise and fall time: ≤ 20 ns
• Output load: 1TTL Gate +100 pF
• Reference levels for measuring timing: 0.8 V, 2.0 V
Read Cycle
HN58C1001-15
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC — 150 ns CE = OE = VIL, WE = VIH
CE to output delay tCE — 150 ns OE = VIL, WE = VIH
OE to output delay tOE 10 75 ns CE = VIL, WE = VIH
Address to output hold tOH 0—nsCE = OE = VIL, WE = VIH
OE (CE) high to output float*1tDF 050nsCE = VIL, WE = VIH
RES low to output float*1 tDFR 0 350 ns CE = OE = VIL, WE = VIH
RES to output delay tRR 0 450 ns CE = OE = VIL, WE = VIH
HN58C1001 Series
6
Write Cycle
Parameter Symbol Min*2Typ Max Unit Test conditions
Address setup time tAS 0 ——ns
Address hold time tAH 150 — — ns
CE to write setup time (WE controlled) tCS 0 ——ns
CE hold time (WE controlled) tCH 0 ——ns
WE to write setup time (CE controlled) tWS 0 ——ns
WE hold time (CE controlled) tWH 0 ——ns
OE to write setup time tOES 0 ——ns
OE hold time tOEH 0 ——ns
Data setup time tDS 100 — — ns
Data hold time tDH 10——ns
WE pulse width (WE controlled) tWP 250 — — ns
CE pulse width (CE controlled) tCW 250 — — ns
Data latch time tDL 300 — — ns
Byte load cycle tBLC 0.55 — 30 µs
Byte load window tBL 100 — — µs
Write cycle time tWC — — 10*3ms
Time to device busy tDB 120 — — ns
Write start time tDW 150*4——ns
Reset protect time tRP 100 — — µs
Reset high time*5tRES 1——µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100% tested.
6. A7 to A16 are page addresses and must be same within the page write operation.
7. See AC read characteristics.
HN58C1001 Series
7
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
tACC
tCE
tOE
tOH
tDF
tRR
tDFR
RES
HN58C1001 Series
8
Byte Write Timing Waveform (1) (WE Controlled)
Address
CE
WE
OE
Din
RDY/Busy
tWC
tCH
tAH
tCS
tAS tWP
tOEH
tBL
tOES
tDS tDH
tDB
tRP
RES
VCC
tRES
High-Z High-Z
tDW
HN58C1001 Series
9
Byte Write Timing Waveform (2) (CE Controlled)
Address
CE
WE
OE
Din
RDY/Busy
tWC
tAH
tWS
tAS
tOEH
tWH
tOES
tDS tDH
tDB
tRP
RES
VCC
tCW
tBL
tDW
tRES
High-Z High-Z
HN58C1001 Series
10
Page Write Timing Waveform (1) (WE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/Busy
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
VCC
tCH
tCS
tWP tDL tBLC
tDS
tDW
High-Z High-Z
*6
HN58C1001 Series
11
Page Write Timing Waveform (2) (CE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/Busy
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
VCC
tWH
tWS
tCW
tDL tBLC
tDS
tDW
High-Z High-Z
*6
HN58C1001 Series
12
Data Polling Timing Waveform
tCE
tOEH
tWC
tDW
tOES
Address
CE
WE
OE
I/O7
tOE
Din X
An An
Dout XDout X
*7
*7
HN58C1001 Series
13
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.
Notes: 1. I/O6 beginning state is “1”.
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any location can be used, but the address must be fixed.
Toggle bit Waveform
WE
tOES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
tOE
tCE
tDW
tWC
tOEH
*1 *2 *2
Address
*3
*3
*4
Din
HN58C1001 Series
14
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data
5555
AA
AAAA or
2AAA
55
5555
A0
tBLC tWC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
tWC
CC Normal active
mode
5555
AA
AAAA
or
2AAA
55
5555
80
5555
AA
AAAA
or
2AAA
55
5555
20
HN58C1001 Series
15
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
Data Polling
Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.
RDY/Busy Signal
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write signal. At the end of write cycle,
the RDY/Busy signal changes state to high impedance.
RES Signal
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn’t provide
a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit Read inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
HN58C1001 Series
16
Write/Erase Endurance and Data Retention Time
The endurance is 104 cycles in case of the page programming and 10 3 cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is page-
programmed less than 104 cycles.
Data Protection
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns
or less in program mode.
Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
HN58C1001 Series
17
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the
EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET
signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
(1) Protection by RES
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s
RES pin. RES should be kept VSS level during VCC on/off.
The EEPROM brakes off programming operation when RES becomes low, programming operation doesn’t
finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.
VCC
RES
WE
or CE 100 µs min 10 ms min
1 µs min
Program inhibit Program inhibit
HN58C1001 Series
18
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is
enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is
input. To program data in the SDP enable mode, 3 bytes code must be input before write data.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
5555
↓
AAAA or 2AAA
↓
5555
↓
Write address Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can note be written.
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
5555
↓
AAAA or 2AAA
↓
5555
↓
5555
↓
AAAA or 2AAA
↓
5555
The software data protection is not enabled at the shipment.
Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence of
software data protection. If there are any questions , please contact with Hitachi sales offices.
HN58C1001 Series
19
Package Dimensions
HN58C1001P Series (DP-32)
0.51 Min
2.54 Min 5.08 Max
0.25+ 0.11
– 0.05
2.54 ± 0.25 0.48 ± 0.10 0° – 15°
41.90
42.50 Max
13.4
13.7 Max
15.24
32 17
116
2.30 Max 1.20
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
DP-32
—
Conforms
5.1 g
Unit: mm
HN58C1001 Series
20
Package Dimensions (cont.)
HN58C1001FP Series (FP-32D)
0.15 M
0.40 ± 0.08
20.45
1.00 Max
1.27
11.30
1.42
3.00 Max
0.22 ± 0.05
20.95 Max
32 17
116
0° – 8°
0.80 ± 0.20
14.14 ± 0.30
0.10
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-32D
Conforms
—
1.3 g
0.38 ± 0.06
+ 0.12
– 0.10
0.15
0.20 ± 0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58C1001 Series
21
Package Dimensions (cont.)
HN58C1001T Series (TFP-32DA)
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TFP-32DA
Conforms
Conforms
0.26 g
0.10
0.08 M
0.50
8.00
0.22 ± 0.08
14.00 ± 0.20
1.20 Max
12.40
32
116
17
0.17 ± 0.05
0.13 ± 0.05
0° – 5°
8.20 Max
0.45 Max
0.50 ± 0.10
0.80
0.20 ± 0.06
0.125 ± 0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58C1001 Series
22
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Cop
y
ri
g
ht © Hitachi, Ltd., 1997. All ri
g
hts reserved. Printed in Japan.
