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FEATURES
0.25µm, five-layer metal, ViaLinkTM epitaxial CMOS
process for smallest die sizes
One-time programmable, ViaLink technology for
personalization
150 MHz 16-bit counters, 150 MHz datapaths, 60+ MHz
FIFOs
2.5V core supply voltage, 3.3V I/O supply voltag e
Up to 320,000 usable system gates (non-volatile)
I/Os
- Interfaces with 3.3 volt
- PCI compliant with 3.3 volt
- Full JTAG 11 49.1 com pliant
- Registered I/O cells with individually controlled enables
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Test Method 1019
- Total-dose: 300 krad(Si)
- SEL Immune: >120MeV-cm2/mg
- LETTH (0.25) MeV-cm2/mg:
>42 logic cell flip flops
>64 for embedded SRAM
- Saturated Cross Section (cm 2) p er bit
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
Up to 24 dual-port RadHard SRAM modules, organized in
user-configurable 2,304 bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and initialized RAM
functions
100% routable with 100% utilization and 100% user fixed
I/O
Variable-grain logic cells provide high performance an d
100% utilization
Comprehensi ve design tools include high quality Verilog/
VHDL synthesis and simulation
QuickLogic IP available for microcontrollers, DRAM
controllers, USART and PCI
Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, and
484 CLGA
Standard Microcircuit Drawing 5962-04229
- QML Q and V compliant part
INTRODUCTION
The RadHard Eclipse Field Programmable Gate Array Family
(FPGA) offers up to 320,000 usable system gates including
Dual-Port RadHard SRAM modules. It is fabricated on 0.25µm
five-layer metal ViaLink CMOS process and contains a
maximum of 1,536 logic cells and 24 dual-port RadHard SRAM
modules (see Figure 1 Block Diagram). Each RAM module has
2,304 RAM bits, for a maximum total of 55,300 bits. Please
reference product family comparison chart on page 2.
RAM modules are Dual Port (one asynchronous/synchronous
read port, one write port) and can be configured into one of four
modes (see Figure 2). The RadHard Eclipse FPGA is available
in a 208-pin Cerquad Flatpack, allowing access to 99
bidirectional signal I/O, 1 dedicated clock, 8 programmable
clocks and 16 high drive inputs. Other package options include
a 288 CQFP, 484 CCGA and a 484 CLGA.
Designers can cascade multiple RAM modules to increase the
depth or width allowed in single modules by connecting
corresponding address lines together and dividing the words
between modules (see Figure 3). This approach allows a variety
of address depths and word widths to be tail o red to a specific
application.
Aeroflex uses QuickLogic Corporation’s licensed ESP
(Embedded Standard Products) technology. QuickLogic is a
pioneer in the FPGA semiconductor and software tools field.
Standard Products
RadHard Eclipse FPGA Family (6250 and 6325)
Advanced Data Sheet
July 2005
www.aeroflex.com/RadHardFPGA