LTC6601IUF-1#TRPBF - Linear Technology

LTC6601-1

66011f

FEATURES

APPLICATIONS

DESCRIPTION

Low Noise, 0.5% Tolerance,

5MHz to 28MHz, Pin Conﬁ gurable

Filter/ADC Driver

The LTC

6601-1 is a very easy-to-use fully differential

2nd order active RC ﬁ lter and driver. On-chip resistors,

capacitors, and ampliﬁ er bandwidth are trimmed to provide

consistent and repeatable ﬁ lter characteristics.

The ﬁ lter characteristics are pin-strap conﬁ gurable. Cutoff

frequencies range from 5MHz to 28MHz. Gain is pin-strap

programmable between –17dB and +17dB.

A three-state BIAS pin is provided to adjust ampliﬁ er

power consumption. Select between high performance,

low power (50% power reduction), and standby modes

with the BIAS pin.

The LTC6601-1 is available in a compact 4mm × 4mm

16-pin leadless QFN package.

19MHz, 2nd Order Lowpass Filter. Gain = 6dB

n Pin Conﬁ gurable Gain and Filter Response

Up to 28MHz

n Few External Components Required

n Resistors Trimmed to 0.5% Typical

n Capacitors Trimmed to 0.5% Typical

n Very Low Noise: 80dB S/N in 100MHz Bandwidth

n Very Low Distortion (2VP-P):

1MHz: –100dBc 2nd, –123dBc 3rd

10MHz: –72dBc 2nd, –103dBc 3rd

n Adjustable Output Common Mode Voltage

n Rail-to-Rail Output Swing

n Power Conﬁ gurability and Low Power Shutdown

n Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package

n Differential Input A/D Converter Driver

n Antialiasing/Reconstruction Filter

n Single-Ended to Differential Conversion/Ampliﬁ cation

n Low Voltage, Low Noise, Differential Signal

Processing

n Common Mode Voltage Translation

Frequency Response

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6271719.

TYPICAL APPLICATION

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VIN

0.1µF

66011 TA01a

–

0.1µF

–

VOUT

–

FREQUENCY (MHz)

GAIN (dB)

66011 TA01b

–10

–15

–20

–25

–5

–30 1 10 100

LTC6601-1

66011f

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (V+ to V–) ...............................5.5V

Input Voltage (Any Pin) (Note 2) ..V+ + 0.3V to V– –0.3V

Input Current (VOCM, BIAS) ..................................±10mA

Input Current (Pins 1, 5) (Note 2) ........................±20mA

Input Current (Pins 2, 4) (Note 2) ........................±30mA

Input Current (Pins 6, 20) (Note 2) ......................±15mA

Input Current (Pins 7, 8, 9, 10, 16, 17, 18, 19)

(Note 2) ................................................................±10mA

Output Short-Circuit Duration (Note 3) ............ Indeﬁ nite

Operating Temperature Range (Note 4)....–40°C to 85°C

Speciﬁ ed Temperature Range (Note 5) ....–40°C to 85°C

Junction Temperature ...........................................150°C

Storage Temperature Range ...................–65°C to 150°C

(Note 1)

20 19 18 17 16

6 7 8

TOP VIEW

UF PACKAGE

20-LEAD (4mm s 4mm) PLASTIC QFN

9 10

IN2+

IN1+

BIAS

IN1–

IN2–

OUT–

V+

V–

VOCM

OUT+

IN4+

IN4–

TJMAX = 150°C, θJA = 37°C/W, θJC = 2°C/W

EXPOSED PAD (PIN 21) IS V–, MUST BE SOLDERED TO PCB

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6601CUF-1#PBF

LTC6601IUF-1#PBF

LTC6601CUF-1#TRPBF

LTC6601IUF-1#TRPBF

66011

20-Lead (4mm × 4mm) Plastic QFN

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ORDER INFORMATION

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOSDIFF (Note 6) Ampliﬁ er Differential Offset Voltage (Input

Referred) VS = 2.7V to 5.25V, BIAS = V+

BIAS = Floating

±0.25

±0.25 ±1

±1.5 mV

ΔVOSDIFF/ΔT

(Note 6)

Ampiﬁ er Differential Offset Voltage Drift

(Input Referred) VS = 2.7V to 5.25V 1 µV/°C

RIN (Note 14) Input Resistance, BIAS = V+

Single Ended Input Resistance, Pin 2 or Pin 4

Differential Input Resistance VS = 3V

VS = 3V 133

200 



DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+ = 3V, V– = 0V, VINCM = VOCM = mid-supply, BIAS tied to V+ or ﬂ oating,

ILOAD = 0, RBAL = 100k. The ﬁ lter is conﬁ gured for a gain of 1 unless otherwise noted. VS is deﬁ ned as (V+ – V–). VOUTCM is deﬁ ned as

(VOUT+ + VOUT–)/2. VINCM is deﬁ ned as (VINP + VINM)/2. VOUTDIFF is deﬁ ned as (VOUT+ – VOUT–). VINDIFF is deﬁ ned as (VINP – VINM). See

Figure 1.

LTC6601-1

66011f

DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+ = 3V, V– = 0V, VINCM = VOCM = mid-supply, BIAS tied to V+ or ﬂ oating,

ILOAD = 0, RBAL = 100k. The ﬁ lter is conﬁ gured for a gain of 1 unless otherwise noted. VS is deﬁ ned as (V+ – V–). VOUTCM is deﬁ ned as

(VOUT+ + VOUT–)/2. VINCM is deﬁ ned as (VINP + VINM)/2. VOUTDIFF is deﬁ ned as (VOUT+ – VOUT–). VINDIFF is deﬁ ned as (VINP – VINM). See

Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ΔRIN (Note 14) Input Resistance Match, BIAS = V+

Single Ended Input Resistance, Pin 2 or Pin 4 VS = 3V l±0.25 

IB (Note 7) Internal Ampliﬁ er Input Bias VS = 2.7V to 5V BIAS = V+

BIAS = Floating

–50

–25 –25

–12.5 0

0µA

µA

IOS (Note 7) Internal Ampliﬁ er Input Offset VS = 2.7V to 5V BIAS = V+

BIAS = Floating

±1

±1 ±10

±5 µA

µA

VINCM (Note 8) Input Signal Common Mode Range

(VINP + VINM)/2

BIAS = V+, VOCM = 1.5V

BIAS = V+, VOCM = 2.5V VS = 3V

VS = 5V

01.7

4.7 V

BIAS Pin Floating, VOCM = 1.5V

BIAS Pin Floating, VOCM = 2.5V VS = 3V

VS = 5V

01.8

4.8 V

CMRRI

(Notes 9, 14) Input Common Mode Rejection Ratio

(Ampliﬁ er Input Referred) ΔVINCM/ΔVOSDIFF

ΔVINCM = 2.5V VS = 5V 74 dB

CMRRO

(Notes 9, 14) Output Common Mode Rejection Ratio

(Ampliﬁ er Input Referred) ΔVOCM/ΔVOSDIFF

ΔVOCM = 1V VS = 5V 70 dB

PSRR (Note 10) Power Supply Rejection Ratio

(Ampliﬁ er Input Referred) ΔVS/ΔVOSDIFF

BIAS = V+

BIAS Pin Floating VS = 2.7V to 5V

VS = 2.7V to 5V

60 95

95 dB

PSRRCM (Note 10) Common Mode Power Supply Rejection Ratio

(ΔVS/ΔVOSCM)V

S = 2.7V to 5V l46 60 dB

gcm Common Mode Gain (ΔVOUTCM/ΔVOCM)

ΔVOCM = 2V VS = 5V 1 V/V

Common Mode Gain Error = 100 • (gcm – 1)

ΔVOCM = 2V VS = 5V l±0.1 ±0.3 %

BAL Output Balance (ΔVOUTCM/ΔVOUTDIFF)

Single-Ended Input

Differential Input

ΔVOUTDIFF = 2V

VS = 5V

–62

–63 –40

–40 dB

VOSCM Common Mode Offset Voltage

(VOUTCM – VOCM)VS = 2.7V to 5V BIAS = V+

VS = 2.7V to 5V BIAS = Floating

±5

±8 ±15

±20 mV

ΔVOSCM/ΔTCommon Mode Offset Voltage Drift

(VOUTCM – VOCM)VS = 2.7V to 5V BIAS = V+

VS = 2.7V to 5V BIAS = Floating

20 µV/°C

µV/°C

VOUTCMR (Note 8) Output Signal Common Mode Range

(Voltage Range for the VOCM Pin) VS = 3V BIAS = V+

VS = 5V BIAS = V+

VS = 3V BIAS Pin Floating

VS = 5V BIAS Pin Floating

1.1

1.7

1.8

RINVOCM Input Resistance, VOCM Pin VS = 3V l12.5 18 23.5 kΩ

VMID Voltage at the VOCM PIn VS = 3V l1.475 1.5 1.525 V

LTC6601-1

66011f

DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+ = 3V, V– = 0V, VINCM = VOCM = mid-supply, BIAS tied to V+ or ﬂ oating,

ILOAD = 0, RBAL = 100k. The ﬁ lter is conﬁ gured for a gain of 1 unless otherwise noted. VS is deﬁ ned as (V+ – V–). VOUTCM is deﬁ ned as

(VOUT+ + VOUT–)/2. VINCM is deﬁ ned as (VINP + VINM)/2. VOUTDIFF is deﬁ ned as (VOUT+ – VOUT–). VINDIFF is deﬁ ned as (VINP – VINM). See

Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT Output Voltage, High, Either Output Pin

(Note 11) VS = 3V, IL = 0mA BIAS = V+

VS = 3V, IL = –5mA BIAS = V+

VS = 3V, IL = –20mA BIAS = V+

VS = 5V, IL = 0mA BIAS = V+

VS = 5V, IL = –5mA BIAS = V+

VS = 5V, IL = –20mA BIAS = V+

245

285

415

350

390

550

450

525

750

625

700

1000

VS = 3V, IL = 0mA, BIAS Pin Floating

VS = 3V, IL = –5mA, BIAS Pin Floating

VS = 3V, IL = –20mA, BIAS Pin Floating

VS = 5V, IL = 0mA, BIAS Pin Floating

VS = 5V, IL = –5mA, BIAS Pin Floating

VS = 5V, IL = –20mA, BIAS Pin Floating

240

290

470

370

430

650

450

525

850

675

775

1100

Output Voltage, Low, Either Output Pin

(Note 11) VS = 3V, IL = 0mA BIAS = V+

VS = 3V, IL = 5mA BIAS = V+

VS = 3V, IL = 20mA BIAS = V+

VS = 5V, IL = 0mA BIAS = V+

VS = 5V, IL = 5mA BIAS = V+

VS = 5V, IL = 20mA BIAS = V+

120

135

195

175

200

270

225

250

350

325

360

475

VS = 3V, IL = 0mA, BIAS Pin Floating

VS = 3V, IL = 5mA, BIAS Pin Floating

VS = 3V, IL = 20mA, BIAS Pin Floating

VS = 5V, IL = 0mA, BIAS Pin Floating

VS = 5V, IL = 5mA, BIAS Pin Floating

VS = 5V, IL = 20mA, BIAS Pin Floating

110

120

170

150

170

225

200

225

300

270

300

400

ISC Output Short-Circuit Current,

Either Output Pin (Note 12) VS = 3V

VS = 5V

±45

±60 ±65

±90 mA

VSSupply Voltage Range l2.7 5.25 V

ISSupply Current, BIAS Pin Tied to V+VS = 2.7V

VS = 3V

VS = 5V

32.9

33.1

33.9

43.5

Supply Current, BIAS Pin Floating VS = 2.7V

VS = 3V

VS = 5V

16.0

16.2

16.9

25.5

26.5

ISHDN Supply Current, BIAS Pin Tied to V–VS = 2.7V

VS = 3V

VS = 5V

0.34

0.35

0.55

0.9

1.6

VBIASSD BIAS Input Pin Range for Shutdown VS = 2.7V to 5V lV–V– + 0.4 V

VBIASLP (Note 13) BIAS Input for Half Power Operation VS = 2.7V to 5V lV– + 1.0 V– + 1.5 V

VBIASHP BIAS Input for High Performance Operation VS = 2.7V to 5V lV– + 2.3 V+V

RBIAS BIAS Input Resistance VS = 2.7V to 5V l100 150 200 kΩ

VBIAS BIAS Float Voltage VS = 2.7V to 5V lV– + 1.05 V– + 1.12 V– + 1.25 V

tON Turn-On Time VS = 3V, VSHDN = 0.25V to 3V 400 ns

tOFF Turn-Off Time VS = 3V, VSHDN = 3V to 0.25V 400 ns

LTC6601-1

66011f

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. V+ = 3V, V– = 0V, VINCM = VOCM = mid-supply, VBIAS is tied to V+ or

ﬂ oating, unless otherwise noted. (See Figure 2 for the AC test conﬁ guration.) VS is deﬁ ned as (V+ – V–). VOUTCM is deﬁ ned as (VOUT+ +

VOUT–)/2. VICM is deﬁ ned as (VINP + VINM)/2. VOUTDIFF is deﬁ ned as (VOUT+ – VOUT–). VINDIFF is deﬁ ned as (VINP – VINM).

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

GAIN Filter Gain, See Figure 2,

BIAS Pin Tied to V+,

AC Gain Measurements Relative to 1MHz

ΔVIN = ±0.25V, fTEST = DC (Note 14)

VIN = 600mVP-P, fTEST = 1MHz

VIN = 600mVP-P, fTEST = 2MHz

VIN = 600mVP-P, fTEST = 5MHz

VIN = 600mVP-P, fTEST = 10MHz

VIN = 600mVP-P, fTEST = 14.45MHz

VIN = 600mVP-P, fTEST = 20MHz

VIN = 600mVP-P, fTEST = 50MHz

–0.25

–0.08

–0.01

–0.54

–2.75

–7.14

–23.70

±0.05

0.02

0.11

–0.34

–2.35

–6.24

–21.70

0.25

0.12

0.23

–0.14

–1.95

–5.34

–19.70

PHASE Filter Phase, See Figure 2,

BIAS Pin Tied to V+ΔVIN = ±0.25V, fTEST = DC

VIN = 600mVP-P, fTEST = 1MHz

VIN = 600mVP-P, fTEST = 2MHz

VIN = 600mVP-P, fTEST = 5MHz

VIN = 600mVP-P, fTEST = 10MHz

VIN = 600mVP-P, fTEST = 14.45MHz

VIN = 600mVP-P, fTEST = 20MHz

VIN = 600mVP-P, fTEST = 50MHz

–6.0

–12.0

–30.7

–67.6

–100.1

–127.3

–5.4

–10.8

–28.2

–62.6

–94.1

–122.3

–169.3

–4.8

–9.6

–25.7

–57.6

–88.1

–117.3

Deg

NOISE Wide Band Output Noise, 14.45MHz Cutoff,

BIAS Pin Tied to V+BW = 100MHz

BW = 20MHz 71

54 µVRMS

µVRMS

SNR BIAS Pin Tied to V+BW = 100MHz

BW = 20MHz 80

82.3 dB

DISTORTION VIN = 2VP-P

, 10MHz, BIAS Pin Tied to V+ HD2, Single-Ended Input

HD3, Single-Ended Input

HD2, Differential Input

HD3, Differential Input

–70

–103

–72

–103

dBc

fO TC Cutoff Frequency Temperature Coefﬁ cient –120 ppm/°C

GAIN Filter Gain, See Figure 2,

BIAS Pin Floating (Remaining AC

Measurements Relative to 1MHz)

ΔVIN = ±0.25V, fTEST = DC (Note 14)

VIN = 600mVP-P, fTEST = 1MHz

VIN = 600mVP-P, fTEST = 2MHz

VIN = 600mVP-P, fTEST = 5MHz

VIN = 600mVP-P, fTEST = 10MHz

VIN = 600mVP-P, fTEST = 14.45MHz

VIN = 600mVP-P, fTEST = 20MHz

VIN = 600mVP-P, fTEST = 50MHz

–0.25

–0.08

–0.01

–0.54

–2.90

–7.43

–23.90

±0.05

0.02

0.11

–0.34

–2.50

–6.53

–21.90

0.25

0.12

0.23

–0.14

–2.10

–5.63

–19.90

PHASE Filter Phase, See Figure 2,

BIAS Pin Floating ΔVIN = ±0.25V, fTEST = DC

VIN = 600mVP-P, fTEST = 1MHz

VIN = 600mVP-P, fTEST = 2MHz

VIN = 600mVP-P, fTEST = 5MHz

VIN = 600mVP-P, fTEST = 10MHz

VIN = 600mVP-P, fTEST = 14.45MHz

VIN = 600mVP-P, fTEST = 20MHz

VIN = 600mVP-P, fTEST = 50MHz

–6.0

–12.4

–31.8

–70.2

–103.5

–130.1

–5.5

–11.2

–29.3

–65.2

–97.5

–125.1

–173.6

–4.8

–10.0

–26.8

–60.2

–91.5

–120.1

Deg

NOISE Output Noise, See Figure 2,

BIAS Pin Floating BW = 100MHz

BW = 20MHz 78

58 µVRMS

µVRMS

SNR BIAS Pin Floating BW = 100MHz

BW = 20MHz 79

81.7 dB

Distortion VIN = 2VP-P

, 10MHz, BIAS Pin Floating HD2, Single-Ended Input

HD3, Single-Ended Input

HD2, Differential Input

HD3, Differential Input

–64

–71

–70

–72

dBc

fO TC Cutoff Frequency Temperature Coefﬁ cient –120 ppm/°C

LTC6601-1

66011f

Note 1: Stresses beyond those listed under the Absolute Maximum

Ratings may cause permanent damage to the device. Exposure to any

Absolute Maximum Rating condition for extended periods may affect

device reliability and lifetime.

Note 2: All pins are protected by steering diodes to either supply. If any

pin is driven beyond the part’s supply voltage, the excess input current

(current in excess of what it takes to drive that pin to the supply rail)

should be limited to less than 10mA.

Note 3: A heat sink may be required to keep the junction temperature

below the Absolute Maximum Rating when the output is shorted

indeﬁ nitely. Long-term application of output currents in excess of the

Absolute Maximum Ratings may impair the life of the device.

Note 4: The LTC6601C/LTC6601I are guaranteed functional over the

operating temperature range –40°C to 85°C.

Note 5: The LTC6601C is guaranteed to meet speciﬁ ed performance from

0°C to 70°C. The LTC6601C is designed, characterized, and expected

to meet speciﬁ ed performance from –40°C to 85°C but is not tested or

QA sampled at these temperatures. The LTC6601I is guaranteed to meet

speciﬁ ed performance from –40°C to 85°C.

Note 6: Output referred voltage offset is a function of the low frequency

gain of the LTC6601. To determine output referred voltage offset, or output

voltage offset drift, multiply this speciﬁ cation by the noise gain (1 + GAIN).

See Applications Information for more details.

Note 7: Input bias current is deﬁ ned as the average of the currents

ﬂ owing into the noninverting and inverting inputs of the internal ampliﬁ er

and is calculated from measurements made at the pins of the IC. Input

offset current is deﬁ ned as the difference of the currents ﬂ owing into the

noninverting and inverting inputs of the internal ampliﬁ er and is calculated

from measurements made at the pins of the IC.

Note 8: Input common mode range is tested using the test circuit of

Figure 1 by measuring the differential DC gain with VICM = mid-supply, and

with VICM at the input common mode range limits listed in the Electrical

Characteristics table, verifying the differential gain has not deviated from

the mid-supply common mode input case by more than 1%, and the

common mode offset (VOCMOS) has not deviated from the mid-supply

common mode offset by more than ±10mV.

The voltage range for the output common mode range is tested using the

test circuit of Figure 1 by measuring the differential DC gain with VOCM =

mid-supply, and again with a voltage set on the VOCM pin at the Electrical

Characteristics table limits, checking the differential gain has not deviated

from the mid-supply common mode input case by more than 1%, and that

the common mode offset (VOCMOS) has not deviated by more than ±10mV

from the mid-supply case.

Note 9: Input CMRR is deﬁ ned as the ratio of the change in the input

common mode voltage at the ampliﬁ er input to the change in differential

input referred voltage offset. Output CMRR is deﬁ ned as the ratio of the

change in the voltage at the VOCM pin to the change in differential input

referred voltage offset.

Note 10: Power supply rejection (PSRR) is deﬁ ned as the ratio of the

change in supply voltage to the change in differential input referred voltage

offset. Common mode power supply rejection (PSRRCM) is deﬁ ned as the

ratio of the change in supply voltage to the change in the common mode

offset, VOUTCM/VOCM.

Note 11: Output swings are measured as differences between the output

and the respective power supply rail.

Note 12: Extended operation with the output shorted may cause junction

temperatures to exceed the 150°C limit and is not recommended.

Note 13: Floating the BIAS pin will reliably place the part into the half-

power mode. The pin does not have to be driven. Care should be taken,

however, to prevent external leakage currents in or out of this pin from

pulling the pin into an undesired state.

Note 14: The variable contact resistance of the high speed test equipment

limits the accuracy of this test. These parameters only show a typical

value, or conservative minimum and maximum value.

ELECTRICAL CHARACTERISTICS

LTC6601-1

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

High Performance Supply Current

vs Temperature and

Supply Voltage

Shutdown Supply Current

vs Temperature and

Supply Voltage

Supply Current vs Bias Pin

Voltage and Temperature

Shutdown Supply Current

vs Supply Voltage and Temperature Low Power Mode Supply Current

vs Supply Voltage and Temperature

High Performance Supply Current

vs Supply Voltage and Temperature

Low Power Supply Current

vs Temperature and

Supply Voltage

High Performance Mode

Differential VOS vs Temperature

Low Power Mode Differential VOS

vs Temperature

TEMPERATURE (°C)

–50

ICC (mA)

18.0

17.5

15.5

16.0

16.5

17.0

15.0 500 100

66011 G01

12525–25 75

VINCM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

2.7V

TEMPERATURE (°C)

–50

ICC (mA)

30 500 100

66011 G02

12525–25 75

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

2.7V

TEMPERATURE (°C)

–50

ICC (mA)

0.8

0.7

0.2

0.4

0.5

0.6

0.3

0.1

0500 100

66011 G03

12525–25 75

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V–

3V 2.7V

BIAS PIN VOLTAGE WITH RESPECT TO V– (V)

ICC (mA)

01.50.5 2.5

66011 G04

312

VINCM = VOCM = MID-SUPPLY

VS = 3V

–40°C

25°C

125°C

SUPPLY VOLTAGE (V)

ICC (mA)

0.01

0.1

0.001 31

66011 G05

524

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V–

–40°C

25°C

125°C

SUPPLY VOLTAGE (V)

ICC (mA)

100

0.01

0.1

0.001 31

66011 G06

524

VINCM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

–40°C

25°C

125°C

SUPPLY VOLTAGE (V)

ICC (mA)

100

0.01

0.1

0.001 31

66011 G07

524

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

–40°C

25°C

125°C

TEMPERATURE (°C)

–50

VOS INPUT REFERRED (mV)

–0.25

1.00

0.75

0.50

0.25

0.00

–0.75

–0.50

–1.00 25–25

66011 G08

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

5 REPRESENTATIVE UNITS

TEMPERATURE (°C)

–50

VOS INPUT REFERRED (mV)

–0.25

1.00

0.75

0.50

0.25

0.00

–0.75

–0.50

–1.00 25–25

66011 G09

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

5 REPRESENTATIVE UNITS

LTC6601-1

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

Low Power Common Mode VOS

vs Temperature

Internal Ampliﬁ er Input Bias

Current vs Temperature

BIAS Pin Input Resistance

vs Temperature

BIAS Pin Float Voltage

vs Temperature

Filter Input Resistance

vs Temperature

Low Frequency Gain

vs Temperature

High Performance Common Mode

VOS vs Temperature

High Performance Mode

Frequency Response of 12

Possible Filter Conﬁ gurations

Low Power Mode Frequency

Response of 12 Possible Filter

Conﬁ gurations

TEMPERATURE (°C)

–50

VOSCM (mV)

–5

–10 25–25

66011 G10

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

5 REPRESENTATIVE UNITS

TEMPERATURE (°C)

–50

VOSCM (mV)

–5

–15

–10

25–25

66011 G11

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

5 REPRESENTATIVE UNITS

TEMPERATURE (°C)

–50

IBIAS (µA)

–20

–5

–10

–15

–30

–25

25–25

66011 G12

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

LOW POWER MODE

(BIAS PIN FLOATING)

HIGH PERFORMANCE MODE

(BIAS PIN TIED TO V+)

TEMPERATURE (°C)

–50

RESISTANCE ()

200

175

150

100

125

25–25

66011 G13

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

TEMPERATURE (°C)

–50

FLOAT VOLTAGE (V)

1.20

1.15

1.10

1.00

1.05

25–25

66011 G14

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

TEMPERATURE (°C)

–50

RESISTANCE/RNOMINAL (/)

1.0050

1.0025

1.0000

0.9950

0.9975

25–25

66011 G15

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

RNOMINAL = 200 DIFFERENTIAL

RNOMINAL = 133.3 SINGLE-ENDED

SEE FIGURE 1 FOR CONFIGURATION

SINGLE-ENDED

DIFFERENTIAL

TEMPERATURE (°C)

–50

GAIN (V/V)

1.010

1.005

1.000

0.990

0.995

25–25

66011 G16

1250 50 75 100

VS = 3V

VINCM = VOCM = MID-SUPPLY

5 REPRESENTATIVE UNITS

FREQUENCY (MHz)

GAIN (dB)

66011 G17

–10

–20

–300.1 10 1001

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

FREQUENCY (MHz)

GAIN (dB)

66011 G18

–10

–20

–300.1 10 1001

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

LTC6601-1

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

Low Power Mode Gain and Phase

Repeatability of 10 Random Units

High Performance Mode Gain Error

of 10 Random Units Normalized to

1MHz

Low Power Mode Gain Error of

10 Random Units Normalized to

1MHz

High Performance Mode Phase

Error of 10 Random Units

Low Power Mode Phase Error of

10 Random Units

Turn On and Turn Off Transient

Response

High Performance Mode Gain

and Phase Repeatability of 10

Random Units

Pulse Response

FREQUENCY (MHz)

GAIN DEVIATION (dB)

PHASE DEVIATION (DEG)

66011 G19

0.20

0.05

0.10

0.15

–0.10

–0.05

–0.15

–0.20

–2

–1

–3

–4

0.1 10 1001

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

SEE FIGURE 2

MAX – AVERAGE

MIN – AVERAGE

ϕMAX – ϕAVERAGE

ϕMIN – ϕAVERAGE

FREQUENCY (MHz)

GAIN DEVIATION (dB)

PHASE DEVIATION (DEG)

66011 G20

0.20

0.05

0.10

0.15

–0.10

–0.05

–0.15

–0.20

–2

–1

–3

–4

0.1 10 1001

VS = 3V

VINCM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

SEE FIGURE 1

MAX – AVERAGE

MIN – AVERAGE

ϕMAX – ϕAVERAGE

ϕMIN – ϕAVERAGE

FREQUENCY (MHz)

GAIN ERROR (dB)

66011 G21

–3

–2

–1

1 10 100

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

10 RANDOM UNITS PLOTTED

TA = 25°C

+SPECIFICATION

–SPECIFICATION

FREQUENCY (MHz)

GAIN ERROR (dB)

66011 G22

–3

–2

–1

1 10 100

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

10 RANDOM UNITS PLOTTED

TA = 25°C

+SPECIFICATION

–SPECIFICATION

FREQUENCY (MHz)

PHASE ERROR (DEG)

66011 G23

–15

–10

–5

1 10 100

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

10 RANDOM UNITS PLOTTED

TA = 25°C

+SPECIFICATION

–SPECIFICATION

FREQUENCY (MHz)

PHASE ERROR (DEG)

66011 G24

–15

–10

–5

1 10 100

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN FLOATING

10 RANDOM UNITS PLOTTED

TA = 25°C

+SPECIFICATION

–SPECIFICATION

TIME (µs)

VOUTDIFF (V)

VBIAS PIN (V)

–3

–2

–1

–5

–4

1.6

1.4

1.2

1.0

0.8

0.2

0.4

0.6

66011 G25

61345

VS = 5V BIAS PIN

VOUTDIFF

TIME (µs)

VOUTDIFF (V)

–1

–2 2

66011 G26

81 34567

VS = 3V

LTC6601-1

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

Normalized 100 Resistor Trim Normalized 125 Resistor Trim

Differential Output Noise Distortion vs Frequency

% Change of fO vs Temperature Passband Gain and Phase

vs Temperature

Gain Error Relative to 1MHz

vs Temperature

Phase Error vs Temperature

Distortion vs Frequency

FREQUENCY (MHz)

NOISE SPECTRAL DENSITY (nV/√Hz)

INTEGRATED NOISE (µVRMS)

66011 G27

100

0.001 0.01 10 10010.1

VS = 3V

FIGURE 2

INTEGRATED NOISE,

BIAS TIED TO V+

SPECTRAL DENSITY,

BIAS TIED TO V+

SPECTRAL DENSITY,

BIAS PIN FLOATING

INTEGRATED NOISE,

BIAS PIN FLOATING

FREQUENCY (MHz)

HARMONIC (dBc)

66011 G28

–60

–70

–120

–110

–100

–90

–80

–1300.1 10 1001

VS = 5V

VIN = 2VP-P INPUT

VICM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

FIGURE 2

SINGLE ENDED INPUT

DIFFERENTIAL INPUT

HD2

HD3

FREQUENCY (MHz)

HARMONIC (dBc)

66011 G29

–60

–70

–120

–110

–100

–90

–80

–1300.1 10 1001

VS = 5V

VIN = 2VP-P INPUT

VICM = VOCM

= MID-SUPPLY

BIAS PIN FLOATING

FIGURE 2

SINGLE ENDED INPUT

DIFFERENTIAL INPUT

TEMPERATURE (°C)

–50

CHANGE OF fO (%)

0.5

–0.5

–2.0

–1.0

–1.5

25–25

66011 G30

1250 50 75 100

FREQUENCY (MHz)

GAIN (dB)

PHASE (DEG)

66011 G31

0.5

–3.0

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

TEMPERATURES PLOTTED:

–45°C, –10°C, 25°C, 70°C, 95°C, 125°C

110

–2.5

–2.0

–1.5

–1.0

–0.5

–105

–90

–75

–60

–45

–30

–15

GAIN

PHASE

FREQUENCY (MHz)

GAIN ERROR (dB)

66011 G32

–3

–2

–1

1 10 100

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

TEMPERATURES PLOTTED:

–45°C, –10°C, 25°C,

70°C, 95°C, 125°C

+SPECIFICATION

–SPECIFICATION

FREQUENCY (MHz)

PHASE ERROR (dB)

66011 G33

–15

–10

–5

1 10 100

VS = 3V

VICM = VOCM = MID-SUPPLY

BIAS PIN TIED TO V+

TEMPERATURES PLOTTED:

–45°C, –10°C, 25°C,

70°C, 95°C, 125°C

+SPECIFICATION

–SPECIFICATION

NORMALIZED RESISTANCE

0.993

FREQUENCY

900

100

700

500

300

800

600

400

200

01.005

66011 G34

1.0091.0010.997

AVERAGE = 100Ω

STD. DEV = 0.19Ω

NORMALIZED RESISTANCE

0.99

FREQUENCY

1000

100

700

500

300

800

900

600

400

200

01.0061.002

66011 G35

1.010.9980.994

AVERAGE = 125Ω

STD. DEV = 0.22Ω

LTC6601-1

66011f

TYPICAL PERFORMANCE CHARACTERISTICS

Normalized Input 400

Resistor Trim

Normalized Feedback 400

Resistor Trim

Normalized 21.1pF Capacitor Trim

Normalized 33.3pF

Capacitor Trim

Normalized 48.2pF

Capacitor Trim

Normalized 81.5pF

Capacitor Trim

Normalized 10.55pF

Capacitor Trim

Normalized 16.1pF

Capacitor Trim

Normalized 200 Resistor Trim

NORMALIZED RESISTANCE

0.99

FREQUENCY

1000

100

700

500

300

800

900

600

400

200

01.0061.002

66011 G36

1.010.9980.994

AVERAGE = 200Ω

STD. DEV = 0.37Ω

NORMALIZED RESISTANCE

0.99

FREQUENCY

900

100

700

500

300

800

600

400

200

01.0061.002

66011 G37

1.010.9980.994

AVERAGE = 400.01Ω

STD. DEV = 1.0Ω

NORMALIZED RESISTANCE

0.99

FREQUENCY

1000

100

700

500

300

800

900

600

400

200

01.0061.002

66011 G38

1.010.9980.994

AVERAGE = 400.01Ω

STD. DEV = 0.87Ω

NORMALIZED CAPACITANCE

0.984

FREQUENCY

1200

800

1000

600

400

200

01.0091.003

66011 G39

1.0150.9970.990

AVERAGE = 21.1pF

STD. DEV = 0.07pF

NORMALIZED CAPACITANCE

0.988

FREQUENCY

1000

800

700

900

600

500

400

300

200

100

01.0101.005

66011 G40

1.0160.9990.993

AVERAGE = 33.3pF

STD. DEV = 0.09pF

NORMALIZED CAPACITANCE

0.9950.992

FREQUENCY

1200

800

1000

600

400

200

01.0071.004

66011 G41

1.0101.0010.998

AVERAGE = 48.2pF

STD. DEV = 0.08pF

NORMALIZED CAPACITANCE

0.9960.993

FREQUENCY

1000

800

700

500

300

100

900

600

400

200

01.0071.004

66011 G42

1.0101.0020.999

AVERAGE = 81.5pF

STD. DEV = 0.1pF

NORMALIZED CAPACITANCE

0.9910.987

FREQUENCY

400

300

250

150

350

200

100

01.0091.005

66011 G43

1.0141.0000.996

AVERAGE = 10.55pF

STD. DEV = 0.03pF

NORMALIZED CAPACITANCE

0.9950.9920.988

FREQUENCY

350

300

250

150

200

100

01.0101.006

66011 G44

1.0141.0030.999

AVERAGE = 16.1pF

STD. DEV = 0.05pF

LTC6601-1

66011f

PIN FUNCTIONS

IN1+, IN2+, IN4+ (Pins 2, 1, 20): Input to a trimmed 100Ω,

200Ω, 400Ω resistor which feeds a noninverting summing

node. Can accept an input signal, be ﬂ oated or tied to OUT–.

For best performance, stray capacitance should be kept as

low as possible by keeping printed circuit connections as

short and direct as possible. If necessary, strip back the

surrounding ground plane away from these pins.

BIAS (Pin 3): Input to a three-state comparator whose

three states allow the user to tailor ampliﬁ er power. The

pin impedance appears as a 150k resistor whose default

open-circuit potential is 1.15V with respect to the V– power

supply. If BIAS is driven to within 0.4V of the V– supply, the

ampliﬁ er is placed into a low power shutdown, consum-

ing typically 350µA. When BIAS is ﬂ oated, the ampliﬁ er

operates in its low power active state. Forcing the pin 2.3V

above V– places the part into the high performance active

state. See Applications Information for more detail.

IN1–, IN2–, IN4– (Pins 4, 5, 6): Input to a trimmed 100Ω,

200Ω, 400Ω resistor which feeds an inverting summing

node. Can accept an input signal, be ﬂ oated or tied to

OUT+. For best performance, it is highly recommended

that stray capacitance be kept to as low as possible by

keeping printed circuit connections as short and direct

as possible, and if necessary, stripping back nearby sur-

rounding ground plane away from these pins.

C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF, 33.3pF

capacitor which feeds a noninverting summing node.

Typically, either ﬂ oat or tie to OUT–. If either of these

pins is tied to a low impedance source other than OUT–,

a resistance of at least 25Ω should be placed in series.

For best performance, it is highly recommended that stray

capacitance be kept to as low as possible by keeping printed

circuit connections as short and direct as possible, and

if necessary, stripping back nearby surrounding ground

plane away from these pins.

C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF, 21.1pF

capacitor which feeds the ampliﬁ er inverting summing

node. Typically, either ﬂ oat or tie to OUT+. For best per-

formance, it is highly recommended that stray capacitance

be kept to as low as possible by keeping printed circuit

connections as short and direct as possible, and if nec-

essary, stripping back nearby surrounding ground plane

away from these pins.

OUT+, OUT– (Pins 11, 15): Output Pins. Besides driving

the internal feedback network, each pin can drive an ad-

ditional 50Ω to ground with typical short-circuit current

limiting of ±65mA. Capacitive loading of these pins should

be minimized by resistively decoupling the outputs from

the load with at least 25Ω.

VOCM (Pin 12): Output Common Mode Reference Voltage.

The voltage on VOCM sets the output common mode voltage

level (which is deﬁ ned as the average of the voltages on

the OUT+ and OUT– pins). The VOCM pin is the midpoint

of an internal resistive voltage divider between the sup-

plies, developing a (default) mid-supply voltage potential

to maximize output signal swing. The VOCM pin can be

overdriven by an external voltage reference capable of

driving the input impedance presented by the VOCM pin.

The VOCM pin has an input resistance of approximately 18k

to a mid-supply potential. It should be bypassed with a

high quality ceramic bypass capacitor (for instance of X7R

dielectric) of at least 0.01F, (unless using symmetrical

split supplies, then connect directly to a low impedance,

low noise ground plane) to minimize common mode noise

from being converted to differential noise by impedance

mismatches both externally and internally to the IC.

(Refer to the Block Diagram)

LTC6601-1

66011f

V+, V– (Pins 14, 13): Power Supply Pins. It is critical that

close attention be paid to supply bypassing. For single

supply applications (Pin 13 grounded), it is recommended

that a high quality 0.1F surface mount ceramic bypass

capacitor (X7R dielectric for instance) be placed between

Pins 14 and 13, with direct short connections. Pin 13

should be tied directly to a low impedance ground plane

with minimal routing. For dual (split) power supplies, it

is recommended that at least two additional high quality

0.1F ceramic capacitors are used to bypass V+ to ground

and V– to ground, again with minimal routing. For driving

large loads (< 200Ω), additional bypass capacitance may

be added for optimal performance. Keep in mind that small

geometry (e.g., 0603) surface mount ceramic capacitors

have a much lower ESL than do leaded capacitors, and

perform best in high speed applications.

C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF, 21.1pF

capacitor which feeds the ampliﬁ er noninverting sum-

ming node. Typically, either ﬂ oat or tie to OUT–. For best

performance, stray capacitance should be kept as low as

possible by keeping printed circuit connections as short

and direct as possible.If necessary, strip back the sur-

rounding ground plane away from these pins.

C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF, 33.3pF

capacitor which feeds an inverting summing node. Typi-

cally, either ﬂ oat or tie to OUT+. If either of these pins are

tied to a low impedance source other than OUT+, a re-

sistance of at least 25Ω should be placed in series. For

best performance, it is highly recommended that stray

capacitance be kept to as low as possible by keeping printed

circuit connections as short and direct as possible, and if

necessary, stripping back nearby surrounding reference

plane away from these pins.

Exposed Pad (Pin 21): Always tie the underlying Exposed

Pad to V– (Pin 13). If split supplies are used, do not tie

the pad to ground. Tie it to V–.

PIN FUNCTIONS

(Refer to the Block Diagram)

LTC6601-1

66011f

BLOCK DIAGRAM

860

400

48.2pF

125BIAS

125

200

IN2+

IN1+100

21.1pF

10.55pF

21.1pF

48.2pF

10.55pF

81.5pF

33.3pF

C2C1

VOCM

860

36k

OUT+

OUT–

V+

V–

33.3pF

16.1pF

400

IN4+C7

66011 BD

107

IN4–

400

BIAS

100

IN1–

IN2–200

–

60k 180k

180k

V– + 2.3V

LTC6601-1

66011f

TEST CIRCUITS

–

0.1µF

VOUT–

3nF

BIAS

VINP

VINM

0.1µF

V+

25

V–

VOCM

VOUT(CM)

RBAL

66011 F01

20 19 18 17 16

109876

–

VOUT+25

LTC6601-1

Figure 1. DC Test Circuit

–

0.1µF

VOUT–

3nF

BIAS

1µF

COILCRAFT

TTWB-4-B

0.1µF

V+

100

50

V–

VOCM

66011 F02

20 19 18 17 16

109876

VOUT+100

VIN

LTC6601-1

LT6411

–5V

10 11 12

123717

VINP

VINM

Figure 2. AC Test Circuit (Frequency Response Testing)

LTC6601-1

66011f

APPLICATIONS INFORMATION

FUNCTIONAL DESCRIPTION

The LTC6601 is designed to make the implementation of

high frequency fully-differential ﬁ ltering functions very

easy. A very low noise ampliﬁ er is surrounded by 8 precision

matched resistors and 12 precision matched capacitors

so that a myriad of ﬁ lter transfer functions limited only by

possible combinations and imagination can be conﬁ gured

by hard wiring pins. The ampliﬁ er itself is a wide band, low

noise and low distortion fully-differential ampliﬁ er with ac-

curate output phase balancing. It is optimized for driving low

voltage, single-supply, differential input, analog-to-digital

converters (ADCs). The LTC6601’s outputs are capable

of swinging rail-to-rail on supplies as low as 2.7V, which

makes the ampliﬁ er ideal for converting ground referenced,

single-ended signals into VOCM referenced differential

signals. Unlike traditional op amps which have a single

output, the LTC6601 has two outputs to process signals

differentially. This allows for two times the signal swing

in low voltage systems when compared to single-ended

output ampliﬁ ers. The balanced differential nature of the

ampliﬁ er and matched surrounding components provide

even-order harmonic distortion cancellation, and less

susceptibility to common mode noise (like power supply

noise). The LTC6601 can be used as a single-ended input

to differential output ampliﬁ er, or as a differential input to

differential output ampliﬁ er.

Figure 3 shows the basic ﬁ lter architecture. The Laplace

transfer function from VINDIFF to VOUTDIFF is given by the

following generalized equation for a 2nd order lowpass

ﬁ lter:

VOUTDIFF

INDIFF

=Gain

1+s

2πf

O•Q +s2

2πf

()

Both Gain and Q of the ﬁ lter are based on component ratios,

which match and track extremely well over temperature.

The corner frequency of the ﬁ lter is a function of an RC

product. This RC product is trimmed to ±1% (typical) and

is not expected to drift by more than ±1% from nominal

over the entire temperature range –40°C to 85°C. As a

result, fully differential ﬁ lters with tight magnitude, phase

tolerance and repeatability are achieved.

Although Figure 3 implies a differential input, the LTC6601

easily accepts single-ended inputs to either input, and will

faithfully replicate the signal at the output in differential

form.

The LTC6601’s output common mode voltage, deﬁ ned as

the average of the two output voltages, is independent of

the input common mode voltage, and is adjusted by apply-

ing a voltage on the VOCM pin. If the pin is left open, there

is an internal resistive voltage divider, which develops a

Figure 3. Basic Filter Topology and Equations

–

VOUT(DIFF)

66011 F03

VIN(DIFF)

fO=1

2πR2 • R3 • C1 • C2

Q= C2

R2 •1

1+ 1+ GAIN

()

•R3

R2 –C2

GAIN = R2

f3dB =

fO• 6089 • 3568 • Q41788 • Q2+447

()

+1.287 • 105•2•Q

21

()











507.6 • Q

0.2236 • fO• 2.109 • 105• 9.891• 1012 •f

3dB45.486 • 109•f

()

+120 • 5.526 • 109•f

3dB2+3.082 • 106•f

()











16 • fO2• 8.29 • 109•f

3dB2+4.127 • 109•f

()

6.638 • 1010 •f

3dB4

()

LTC6601-1

66011f

APPLICATIONS INFORMATION

potential halfway between the V+ and V– pins. Whenever

this pin is not hard tied to a low impedance ground plane,

a high quality ceramic capacitor should be used to bypass

the VOCM pin to a low impedance ground plane (see Layout

Considerations). The LTC6601’s internal common mode

feedback path forces accurate output phase balancing to

reduce even order harmonics, and centers each individual

output about the potential set by the VOCM pin.

VOUTCM =VOCM =VOUT ++VOUT

–

The outputs (OUT+ and OUT–) of the LTC6601 are capable

of swinging rail-to-rail. They can source or sink up to ap-

proximately 75mA of current. Load capacitances should

be decoupled with at least 25Ω of series resistance from

each output.

The LTC6601 Electrical Characteristics table speciﬁ es an

input referred offset. This speciﬁ cation actually lumps volt-

age offsets due to offset bias currents (IOS), and ampliﬁ er

voltage offset into one speciﬁ cation. To refer this speciﬁ ca-

tion to the output, you simply multiply the speciﬁ cation

by the noise gain the LTC6601 is conﬁ gured in:

OSODIFF = 1 + Gain

where Gain is the closed loop gain in the particular ﬁ lter

application:

Gain =R2

COMPONENT INPUT PIN PROTECTION

All of the LTC6601 pins with the exception of V+ and V– are

protected with steering diodes to either power supply. In

the event that a pin is driven beyond the supply rails, the

excess current should be limited to under 10mA to prevent

damage to the IC.

BIAS Pin

The LTC6601 has a BIAS pin (Pin 3) whose function is to

tailor both performance and power of the LTC6601. The

pin has a Thevenin equivalent impedance of approximately

150kΩ to a voltage source whose potential is 1.15V above

the V– supply. This pin has ﬁ xed logic levels relative to V–

(see the Electrical Characteristics table), and can be driven

by an external source keeping in mind its equivalent input

impedance and equivalent input voltage. If the BIAS pin is

ﬂ oated, care should be taken to control external leakage

currents to this pin to under 1A to prevent putting the

LTC6601 an undesired state.

If BIAS is tied to the positive supply, the LTC6601 dif-

ferential ﬁ lter will be in a fully active state conﬁ gured for

highest performance (lowest noise and lowest distortion).

If the BIAS pin is ﬂ oated or left unconnected, the LTC6601

ﬁ lter will be in a fully active state, with ampliﬁ er currents

reduced and performance scaled back to preserve power

consumption. If the BIAS pin is tied to the most negative

supply (V–), the LTC6601 will be placed into a low power

shutdown mode with ampliﬁ er outputs disabled. In this

state, the LTC6601 draws approximately 350µA.

In low power shutdown, all internal biasing current sources

are shut off, and the output pins, OUT+ and OUT–, will each

appear as open collectors with a non-linear capacitor in

parallel and steering diodes to either supply. The turn-on

and turn-off time constant between states are on the order

of 0.4s. Using this function to wire-OR outputs together

is not recommended.

General Design and Usage

As levels of integration have increased and correspond-

ingly, system supply voltages decreased, there has been

a need for ADCs to process signals differentially in order

to maintain good signal-to-noise ratios. These ADCs are

typically supplied from a single supply voltage which

can be as low as 3V (2.7V min), and will have an optimal

common mode input range near mid-supply. The LTC6601

makes interfacing to these ADCs easy, by providing anti-

alias ﬁ ltering, single-ended to differential conversion and

common mode level shifting (translation). Figure 3 shows

a general application of this. The low frequency gain to

VOUTDIFF from VIN is simply:

VOUTDIFF =VOUT +–V

OUT

–≈R2

R1 •V

INDIFF

The differential output voltage (VOUT+ – VOUT–) is completely

independent of input and output common mode voltages,

or the voltage at the common mode pin. This makes the

LTC6601-1

66011f

LTC6601 ideally suited for pre-ampliﬁ cation, level shift-

ing and conversion of single-ended signals to differential

output signals for driving differential input ADCs.

INPUT IMPEDANCE

Calculating the low frequency input impedance of the

LTC6601 depends on how the inputs are driven (whether

they are driven from a single-ended or a differential

source).

Figure 4 shows a simpliﬁ ed low frequency equivalent

circuit of the LTC6601. For balanced input sources (VINP

= –VINM), the low frequency input impedance is given by

the equation:

INP = RINM = R1

The differential input impedance is simply:

INDIFF = 2 • R1

For single-ended inputs (VINM = 0), the input impedance

actually increases over the balanced differential case due

to the fact the summing node (at the junction of R1, R2

and R3) moves in phase with VINP to bootstrap the input

impedance. Referring to Figure 4 with VINM = 0, the input

impedance looking into either input is:

RINP =RINM

1– 1

2•R2

R1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

Input and Output Common Mode Voltage Range

The input common mode voltage is deﬁ ned as the average

of the two inputs:

INCM =V

INP +V

INM

The lower limit of the input common mode range is dic-

tated by the ESD protection diodes at the input. While it

is possible for the inputs to swing below V–, the diodes

will conduct if the inputs are taken a diode drop below V–.

The upper limit of the input common mode range varies

as a function of the ﬁ lter conﬁ guration (GAIN), VOCM po-

tential, and whether or not the inputs are single-ended or

differential. While it is possible to exceed the upper limit

of the common mode range, doing so will degrade ﬁ lter

linearity. Referring to Figure 4, for linear operation, the

summing junction where R1, R2 and R3 merge together

should be prevented from swinging to within 1.4V of the

V+ power supply.

For the general case, the upper input common mode volt-

age limit should be constrained to:

VOCM •R1

R1+R2 +V

INCM •R2

R1+R2 ≤V+– 1.4V

Or equivalently:

INCM ≤1+R1

⎛

⎝

⎜⎞

⎠

⎟V+−1.4V

()

−R1

R2 •V

OCM

The speciﬁ cations for input common mode range (VINCMR)

are based on these constraints with R1 = R2 = 100, and

VOCM = mid-supply. Substituting the numbers for a single

3V power supply, (V+ = 3V, V– = 0V) with VOCM =1.5V, and

R1 = R2 = 100, into the above equation, the input com-

mon mode range (VINCMR) is between the two limits:

0V ≤ VINCM ≤ 1.7V

which is as is speciﬁ ed for a 3V supply.

APPLICATIONS INFORMATION

–

VOUT–

VOUT+

VOCM

VOUTDIFF

0.1µF

66011 F04

RINP

VINP

VINM R1

–

RINM

Figure 4. Input Impedance

LTC6601-1

66011f

Likewise, substituting the numbers for a single 5V power

supply, (V+ = 5V, V– = 0V) with VOCM = 2.5V, and R1 = R2

= 100, into the above equation, the input common mode

range (VINCMR) is between the two limits:

0V ≤ VINCM ≤ 4.7V

The output common mode voltage is deﬁ ned as the aver-

age of the two outputs:

VOUTCM =VOCM =VOUT ++VOUT

–

The VOCM pin sets this average by an internal common

mode feedback loop which internally forces VOUT+ =

–VOUT–. The output common mode range extends from

1.1 V above V– to 1V below V+. The VOCM pin sits in the

middle of a voltage divider which sets the default mid-

supply open circuit potential.

In single supply applications, where the LTC6601 is used

to interface to an ADC, the optimal common mode input

to the ADC is often determined by the ADC’s reference. If

the ADC makes a reference available for setting the input

common mode voltage, it can be directly tied to the VOCM

pin, but must be capable of driving the input impedance of

the VOCM pin (RVOCM). This impedance can be assumed

to be connected to a mid-supply potential. If an external

reference drives the VOCM pin, it should still be bypassed

with a high quality 0.01F or higher capacitor to a low

impedance ground plane to ﬁ lter any thermal noise and

to prevent common mode signals on this pin from being

inadvertently converted to differential signals.

Noise Considerations

When comparing the LTC6601 noise to other ampliﬁ ers,

be sure to compare similar speciﬁ cations. Competing

devices often specify noise referred to the inputs of the

ampliﬁ er. The input referred voltage noise of the LTC6601-1

is 2.1nV/√Hz. This level is one of the lowest available for

ampliﬁ ers in this speed and power range.

In addition to the noise generated by the ampliﬁ er, the

surrounding feedback resistors also contribute noise. A

noise model is shown in Figure 5. The output spot noise

generated by both the ampliﬁ er and the feedback compo-

nents is governed by the equation:

APPLICATIONS INFORMATION

eno =eni •1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

+2• I

2•R2

2+R32•1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

⎟+2• e

nR1 •R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

+2e

nR3 •1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

+2•e

nR2

Substituting the equation for Johnson noise of a resistor (enR2 = 4kTR), and simplifying:

eno =eni •1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

+2• I

2•R2

2+R32•1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

⎟+8•k•T R2 1+R2

⎛

⎝

⎜⎞

⎠

⎟+R3 1+R2

⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜⎞

⎠

⎟

LTC6601-1

66011f

APPLICATIONS INFORMATION

Table 1 lists the ampliﬁ er input referred noise for the

LTC6601-1. Tables 2 to10 list the noise referred to the input

pins of the IC for common conﬁ gurations of the LTC6601-1.

To determine the spot noise at the output, simply multiply

the noise by the Gain = R2/R1. To estimate the integrated

noise at the output, multiply the noise by the gain, and the

square root of the noise bandwidth. The noise bandwidth

depends on the ﬁ lter conﬁ guration. For Figure 2, the noise

bandwidth is 100MHz, or approximately 7 times the ﬁ lter

bandwidth. Improvements in SNR can be made by adding

an additional RC ﬁ lter at the output to band limit wide band

noise before feeding ADCs. See the section “Interfacing

the LTC6601 to ADC Converters” for more detail.

Table 1. Ampliﬁ er (Input Referred) Noise Characteristics for the

LTC6601-1

BIAS PIN PULLED TO V+BIAS PIN FLOATING

eni

nV/√Hz in

pA/√Hz eni

nV/√Hz in

pA/√Hz

2.1 3 2.6 2.1

LAYOUT CONSIDERATIONS

Because the LTC6601 is a very high speed ampliﬁ er, it is

sensitive to both stray capacitance and stray inductance.

It is critical that close attention be paid to supply bypass-

ing. For single supply applications, it is recommended

that a high quality 0.1F surface mount ceramic bypass

capacitor be placed between Pins 14 and 13 with direct

short connections. Pin 13 and the Exposed Pad, Pin 21,

should be tied directly to a low impedance ground plane

with minimal routing. For dual (split) power supplies, it

is recommended that an additional high quality, 0.1F

ceramic capacitor be used to bypass pin V+ to ground

and V– to ground, again with minimal routing. For driv-

ing large differential loads (<200Ω), additional bypass

capacitance may be needed between V+ and V– for opti-

mal performance. Note that small geometry (e.g., 0603)

surface mount ceramic capacitors have a much higher

self resonant frequency than capacitors with leads, and

perform best in high speed applications.

The VOCM pin should be bypassed to ground with a high

quality ceramic capacitor whose value exceeds 0.01F,

with direct, short connections. In split supply applications,

the VOCM pin can be either bypassed to ground or directly

hardwired to ground. Be careful not to violate the output

common mode range speciﬁ cations for the VOCM pin.

Stray parasitic capacitances to unused component pins

that set up the ﬁ lter’s characteristics, should be kept to an

absolute minimum. This prevents deviations from the ideal

frequency response. An ideal layout technique would be to

remove the solder pads for the unused component pins,

and strip away the ground plane underneath these pins to

lower capacitance to an absolute minimum. Floating unused

component pins which set up the ﬁ lter characteristics will

not reduce the reliability of the LTC6601.

At the output, always keep in mind the differential nature of

the LTC6601, and that it is critical that the load impedances

seen by both outputs (stray or intended), should be as bal-

anced and symmetric as possible. This will help preserve

the natural balance of the LTC6601, which minimizes the

generation of even order harmonics and preserves the

rejection of common mode signals and noise.

–

66011 F05

R3 **

eni2

eno2

enR32

enR22

enR12

In+2

In–2

Figure 5. Differential Noise Model of the LTC6601

LTC6601-1

66011f

APPLICATIONS INFORMATION

INTERFACING THE LTC6601 TO ADC CONVERTERS

The LTC6601’s rail-to-rail differential output and adjustable

output common mode voltage make the LTC6601 ideal

for interfacing to low voltage, single supply, differential

input ADCs. The sampling process of ADCs creates a

sampling transient that is caused by the switching-in

of the ADC sampling capacitor. The switching-in of this

sampling capacitor momentarily “shorts” the output of the

ampliﬁ er as charge is transferred between ampliﬁ er and

sampling capacitor. The ampliﬁ er must recover and settle

from this load transient before this acquisition period has

ended, for a valid representation of the input signal. The

LTC6601 will settle much more quickly from these peri-

odic load impulses than it does from a 2V input step, but

it is a good idea to add an RC network after the outputs

of the LTC6601 to decouple the sampling transient of the

ADC (See Figure 6). The capacitance of the decoupling

network serves to provide the bulk of the charge during

the sampling process, while the two resistors of the ﬁ lter

network are used to dampen and attenuate any transient

induced by the ADC. The ADC’s sampling bandwidth will

often be much greater than that of the LTC6601, so hav-

ing this discrete RC ﬁ lter will give the additional beneﬁ t

of band limiting broadband output noise.

The selection of the RC time constant is trial and error

for a given ADC, but the following guidelines are recom-

mended. Choose an RC pole frequency greater than the

cutoff frequency of the LTC6601. 80MHz RC ﬁ lters are

good for ﬁ ltering broadband noise. Lower frequency RC

ﬁ lters improve SNR at the expense of settling time. The

resistors in the decoupling network should be at least 25Ω.

Too much resistance in the decoupling network leaves

insufﬁ cient settling time and will create a voltage divider

between the dynamic input impedance of the ADC and the

decoupling resistors. Using insufﬁ cient resistance might

prevent proper dampening of the load transient caused by

the sampling process, and prolong the time required for

settling. In 16-bit applications, this will typically require

a minimum of 11 RC time constants. It is recommended

that the capacitor is chosen with low dielectric absorption

(such as a C0G multilayer ceramic capacitor).

–

0.1µF

VOUT–

VOUT+

10nF

BIAS 1µF

VOCM

66011 F06

t = R • (C1 + 2 • C2)

2.2µF

1µF 1µF

3.3V

D15

•

VIN

–

6 7 8 9 10

1617181920

AIN+

AIN–

VCM GND

CONTROL

LTC6601-1

Figure 6. Interfacing the LTC6601 to A/D Converters

LTC6601-1

66011f

APPLICATIONS INFORMATION

A GALLERY OF BASIC FILTER TOPOLOGIES

Tables 2 through 10 list (sorted by Gain) a hundred possible

ﬁ lter topologies that can be easily implemented with the

LTC6601. The tables also list the LTC6601-1 approximate

midband (1MHz) spot noise ein referred to the input re-

sistor, R1 (with the BIAS pin pulled to V+). The gains for

these topologies range from 1V/V to 7V/V. The Qs listed

are within the range of 0.54 and 1.72. The fOs listed are

in the range of 6.96MHz and 22.71MHz, and the –3dB

frequencies listed range from 5.5MHz to 27.5MHz. For

all ﬁ lters listed, R3 = 125Ω. Figures 7 to 10 show how to

pin-strap each ﬁ lter conﬁ guration.

Table 2. Gain of 7 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB (MHz) Q R1 () R2 () C1 (pF) C2 (pF)

ein

(nV/√Hz)V/V dB

7.0 16.902 10.38 7.43 0.539 57.14 400.00 48.2 97.6 3.7

7.0 16.902 9.57 10.36 0.771 57.14 400.00 48.2 114.8 3.7

7.0 16.902 8.96 12.10 1.175 57.14 400.00 48.2 130.9 3.7

7.0 16.902 8.12 7.49 0.656 57.14 400.00 58.75 130.9 3.7

Table 3. Gain of 6 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB (MHz) Q R1 ()R2

()C1

(pF) C2 (pF)

ein

(nV/√Hz)V/V dB

6.0 15.563 10.38 10.03 0.684 66.67 400.00 48.2 97.6 3.8

6.0 15.563 9.57 12.52 1.071 66.67 400.00 48.2 114.8 3.8

6.0 15.563 8.67 7.67 0.634 66.67 400.00 58.75 114.8 3.8

6.0 15.563 8.12 9.59 0.870 66.67 400.00 58.75 130.9 3.8

6.0 15.563 7.47 6.07 0.592 66.67 400.00 69.3 130.9 3.8

Table 4. Gain of 5 Filter Conﬁ gurations

GAIN

fo (MHz) f–3dB (MHz) Q R1 ()R2

() C1 (pF) C2 (pF)

ein

nV/√HzV/V dB

5.0 13.979 11.36 9.67 0.614 80.00 400.00 48.2 81.5 4.0

5.0 13.979 10.38 12.78 0.936 80.00 400.00 48.2 97.6 4.0

5.0 13.979 9.40 7.67 0.594 80.00 400.00 58.75 97.6 4.0

5.0 13.979 8.67 10.07 0.849 80.00 400.00 58.75 114.8 4.0

5.0 13.979 8.12 11.25 1.290 80.00 400.00 58.75 130.9 4.0

5.0 13.979 7.98 6.46 0.591 80.00 400.00 69.3 114.8 4.0

5.0 13.979 7.47 8.16 0.779 80.00 400.00 69.3 130.9 4.0

5.0 13.979 6.96 5.50 0.579 80.00 400.00 79.85 130.9 4.0

LTC6601-1

66011f

Table 5. Gain of 4 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB MHz Q R1 ()R2

() C1 (pF) C2 (pF)

ein

nV/√HzV/V dB

4.0 12.041 11.36 13.05 0.834 100.00 400.00 48.2 81.5 4.2

4.0 12.041 10.38 14.80 1.480 100.00 400.00 48.2 97.6 4.2

4.0 12.041 9.40 10.47 0.799 100.00 400.00 58.75 97.6 4.2

4.0 12.041 8.67 12.00 1.284 100.00 400.00 58.75 114.8 4.2

4.0 12.041 8.65 6.76 0.575 100.00 400.00 69.3 97.6 4.2

4.0 12.041 7.98 8.84 0.794 100.00 400.00 69.3 114.8 4.2

4.0 12.041 7.43 6.09 0.596 100.00 400.00 79.85 114.8 4.2

4.0 12.041 7.47 10.00 1.141 100.00 400.00 69.3 130.9 4.2

4.0 12.041 6.96 7.57 0.775 100.00 400.00 79.85 130.9 4.2

Table 6. Gain of 3 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB (MHz) Q R1 () R2 () C1 (pF) C2 (pF)

ein

(nV/√Hz)V/V dB

3.0 9.542 16.06 12.36 0.568 66.67 200.00 48.2 81.5 4.3

3.0 9.542 14.68 15.74 0.763 66.67 200.00 48.2 97.6 4.3

3.0 9.542 13.53 17.83 1.091 66.67 200.00 48.2 114.8 4.3

3.0 9.542 13.29 9.88 0.554 66.67 200.00 58.75 97.6 4.3

3.0 9.542 12.26 12.39 0.715 66.67 200.00 58.75 114.8 4.3

3.0 9.542 11.36 15.77 1.300 133.33 400.00 48.2 81.5 4.6

3.0 9.542 11.48 14.07 0.928 66.67 200.00 58.75 130.9 4.3

3.0 9.542 11.29 8.34 0.552 66.67 200.00 69.3 114.8 4.3

3.0 9.542 10.29 11.04 0.763 133.33 400.00 58.75 81.5 4.6

3.0 9.542 10.57 10.06 0.674 66.67 200.00 69.3 130.9 4.3

3.0 9.542 9.40 12.85 1.224 133.33 400.00 58.75 97.6 4.6

3.0 9.542 8.65 9.54 0.788 133.33 400.00 69.3 97.6 4.6

3.0 9.542 8.06 6.69 0.601 133.33 400.00 79.85 97.6 4.6

3.0 9.542 7.98 10.88 1.212 133.33 400.00 69.3 114.8 4.6

3.0 9.542 7.43 8.48 0.825 133.33 400.00 79.85 114.8 4.6

3.0 9.542 6.96 9.40 1.172 133.33 400.00 79.85 130.9 4.6

3.0 9.542 9.85 7.13 0.544 66.67 200.00 79.85 130.9 4.3

APPLICATIONS INFORMATION

LTC6601-1

66011f

APPLICATIONS INFORMATION

Table 7. Gain of 2 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB (MHz) Q R1 () R2 () C1 (pF) C2 (pF)

ein

(nV/√Hz)V/V dB

2.0 6.021 16.06 18.95 0.868 100.00 200.00 48.2 81.5 5.0

2.0 6.021 14.55 12.69 0.626 100.00 200.00 58.75 81.5 5.0

2.0 6.021 14.68 20.46 1.323 100.00 200.00 48.2 97.6 5.0

2.0 6.021 13.29 15.34 0.840 100.00 200.00 58.75 97.6 5.0

2.0 6.021 12.24 10.96 0.640 100.00 200.00 69.3 97.6 5.0

2.0 6.021 12.26 16.66 1.200 100.00 200.00 58.75 114.8 5.0

2.0 6.021 11.29 12.98 0.835 100.00 200.00 69.3 114.8 5.0

2.0 6.021 10.29 13.97 1.197 200.00 400.00 58.75 81.5 5.5

2.0 6.021 10.51 9.76 0.660 100.00 200.00 79.85 114.8 5.0

2.0 6.021 10.57 13.97 1.102 100.00 200.00 69.3 130.9 5.0

2.0 6.021 9.47 10.52 0.796 200.00 400.00 69.3 81.5 5.5

2.0 6.021 9.85 11.17 0.819 100.00 200.00 79.85 130.9 5.0

2.0 6.021 8.82 7.55 0.616 200.00 400.00 79.85 81.5 5.5

2.0 6.021 8.65 11.91 1.254 200.00 400.00 69.3 97.6 5.5

2.0 6.021 8.06 9.48 0.864 200.00 400.00 79.85 97.6 5.5

2.0 6.021 7.43 10.40 1.341 200.00 400.00 79.85 114.8 5.5

Table 8. Gain of 1.667 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB MHz Q R1 ()R2

() C1 (pF) C2 (pF)

ein

nV/√HzV/V dB

1.667 4.437 19.67 19.35 0.696 80.00 133.33 48.2 81.5 5.1

1.667 4.437 17.97 22.12 0.934 80.00 133.33 48.2 97.6 5.1

1.667 4.437 16.57 23.16 1.336 80.00 133.33 48.2 114.8 5.1

1.667 4.437 16.28 15.60 0.679 80.00 133.33 58.75 97.6 5.1

1.667 4.437 15.01 17.80 0.875 80.00 133.33 58.75 114.8 5.1

1.667 4.437 14.33 18.58 1.046 80.00 133.33 58.75 126 5.1

1.667 4.437 13.82 13.19 0.676 80.00 133.33 69.3 114.8 5.1

1.667 4.437 12.94 14.77 0.826 80.00 133.33 69.3 130.9 5.1

1.667 4.437 12.06 11.32 0.666 80.00 133.33 79.85 130.9 5.1

LTC6601-1

66011f

Table 9. Gain of 1.333 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB MHz Q R1 ()R2

() C1 (pF) C2 (pF)

ein

nV/√HzV/V dB

1.333 2.499 19.67 22.73 0.841 100.00 133.33 48.2 81.5 5.7

1.333 2.499 17.82 15.77 0.633 100.00 133.33 58.75 81.5 5.7

1.333 2.499 17.97 24.34 1.185 100.00 133.33 48.2 97.6 5.7

1.333 2.499 16.28 18.44 0.818 100.00 133.33 58.75 97.6 5.7

1.333 2.499 14.99 13.58 0.646 100.00 133.33 69.3 97.6 5.7

1.333 2.499 15.01 19.82 1.097 100.00 133.33 58.75 114.8 5.7

1.333 2.499 14.06 20.12 1.506 100.00 133.33 58.75 130.9 5.7

1.333 2.499 13.82 15.61 0.814 100.00 133.33 69.3 114.8 5.7

1.333 2.499 12.88 12.03 0.663 100.00 133.33 79.85 114.8 5.7

1.333 2.499 12.94 16.64 1.025 100.00 133.33 69.3 130.9 5.7

1.333 2.499 12.06 13.45 0.801 100.00 133.33 79.85 130.9 5.7

Table 10. Gain of 1 Filter Conﬁ gurations

GAIN

fO (MHz) f–3dB MHz Q R1 ()R2

() C1 (pF) C2 (pF)

ein

nV/√HzV/V dB

1.0 0.0 22.71 25.40 0.804 100.0 100.0 48.2 81.5 6.4

1.0 0.0 20.75 27.23 1.079 100.0 100.0 48.2 97.6 6.4

1.0 0.0 20.57 17.86 0.623 100.0 100.0 58.75 81.5 6.4

1.0 0.0 19.14 27.50 1.543 100.0 100.0 48.2 114.8 6.4

1.0 0.0 18.80 20.62 0.784 100.0 100.0 58.75 97.6 6.4

1.0 0.0 17.31 15.35 0.634 100.0 100.0 69.3 97.6 6.4

1.0 0.0 17.33 22.15 1.011 100.0 100.0 58.75 114.8 6.4

1.0 0.0 16.23 22.58 1.312 100.0 100.0 58.75 130.9 6.4

1.0 0.0 15.96 17.45 0.781 100.0 100.0 69.3 114.8 6.4

1.0 0.0 14.55 19.09 1.079 200.0 200.0 58.75 81.5 6.9

1.0 0.0 14.87 13.57 0.650 100.0 100.0 79.85 114.8 6.4

1.0 0.0 14.95 18.59 0.954 100.0 100.0 69.3 130.9 6.4

1.0 0.0 13.39 14.90 0.798 200.0 200.0 69.3 81.5 6.9

1.0 0.0 13.92 15.04 0.769 100.0 100.0 79.85 130.9 6.4

1.0 0.0 12.48 11.38 0.650 200.0 200.0 79.85 81.5 6.9

1.0 0.0 12.24 16.25 1.115 200.0 200.0 69.3 97.6 6.9

1.0 0.0 11.40 13.27 0.850 200.0 200.0 79.85 97.6 6.9

1.0 0.0 11.29 16.47 1.715 200.0 200.0 69.3 114.8 6.9

1.0 0.0 10.51 14.17 1.167 200.0 200.0 79.85 114.8 6.9

1.0 0.0 9.47 13.26 1.350 400.0 400.0 69.3 81.5 7.9

1.0 0.0 8.82 10.86 0.935 400.0 400.0 79.85 81.5 7.9

1.0 0.0 8.06 11.57 1.535 400.0 400.0 79.85 97.6 7.9

APPLICATIONS INFORMATION

LTC6601-1

66011f

APPLICATIONS INFORMATION

20 19 18 17 16

6 7 8 9 10

LTC6601-1

57.14W

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

66.66W

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

80

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

100

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

133.33

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

66011 F07

400

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

200

–

Figure 7. Pin-Strap Hookup for a Particular R1

LTC6601-1

66011f

APPLICATIONS INFORMATION

Figure 9. Pin-Strap Hookup for a Particular C1

20 19 18 17 16

6 7 8 9 10

LTC6601-1

100

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

133

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

200

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

400

–

66011 F08

Figure 8. Pin-Strap Hookup for a Particular R2

20 19 18 17 16

6 7 8 9 10

LTC6601-1

48.2pF

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

58.75pF

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

69.3pF

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

79.85pF

–

66011 F09

LTC6601-1

66011f

APPLICATIONS INFORMATION

20 19 18 17 16

6 7 8 9 10

LTC6601-1

81.5pF

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

114.8pF

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

97.6pF

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

130.9pF

–

66011 F10

Figure 10. Pin-Strap Hookup for a Particular C2

LTC6601-1

66011f

APPLICATIONS INFORMATION

Example Filter Conﬁ gurations of Basic 2nd Order

Filters

Figure 11 shows some simpliﬁ ed component hookups of

a selection of ﬁ lters taken from Tables 7, 9 and 10. For

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 0dB

fO = 13.92MHz

Q = 0.769

GAIN = 0dB

fO = 22.71MHz

Q = 0.804

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 6dB

fO = 9.85MHz

Q = 0.819

GAIN = 6dB

fO = 16.06MHz

Q = 0.868

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 2.5dB

fO = 12.06MHz

Q = 0.801

GAIN = 2.5dB

fO = 19.67MHz

Q = 0.841

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

66011 F11

VIN

–

simplicity, VOCM pin bypass and power supply bypass

are not shown.

Figure 11. Basic 2nd Order Filter Conﬁ gurations

LTC6601-1

66011f

Figure 12 shows some simpliﬁ ed component hookups

of a selection of ﬁ lters taken from Tables 4, 5, and 6. For

simplicity, VOCM pin bypass and power supply bypass

are not shown.

APPLICATIONS INFORMATION

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 12dB

fO = 6.96MHz

Q = 0.775

GAIN = 12dB

fO = 11.36MHz

Q = 0.834

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 14dB

fO = 6.96MHz

Q = 0.579

GAIN = 14dB

fO = 11.36MHz

Q = 0.614

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

VIN

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 9.54dB

fO = 9.85MHz

Q = 0.544

GAIN = 9.54dB

fO = 16.06MHz

Q = 0.568

VOUT(DIFF)

VIN

–

66011 F12

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

VIN

–

Figure 12. Basic 2nd Order Filter Conﬁ gurations

LTC6601-1

66011f

APPLICATIONS INFORMATION

COMPLEX FILTER CONFIGURATIONS

A Modiﬁ ed 2nd Order Lowpass Filter Topology

The basic ﬁ lter topology of Figure 3 can be modiﬁ ed as

shown in Figure 13. The Figure 13 circuit includes an

impedance path between the two summing nodes (the

circuit nodes common to resistors R1, R2 and R3). A

resistor and/or a capacitor connection between the sum-

ming nodes provide even more ﬂ exibility, and enhance

the ﬁ lter design options (the fO and Q equations shown

in Figure 13 reduce to equations of Figure 3 if C3 is zero

and R4 is inﬁ nite).

The modiﬁ ed second order ﬁ lter topology provides for

setting the Q value (with R4) without changing the fO

value and increasing the passband gain to greater than

one without changing the Q value (in the Q equation of

Figure 13 the value of Q does not change if the value of

the [1 + GAIN + 2(R2/R4)] denominator factor does not

change). Using R4 to set the Q value allows the option

to design the –3dB frequency (f3dB). If the Q value varies

and the fO value is constant then the f3dB frequency var-

ies in a second order lowpass function (refer to the f3dB

equation of Figure 13).

Figure 14 shows three conﬁ gurations using a capacitor

(C3) and a resistor (R4) between the summing nodes.

The external 49.9Ω resistor isolates the LTC6601 outputs

from driving directly a capacitive load. The three circuits

of Figure 14 have equal fO and Q values and differ only in

the passband gain. The 150Ω R4 resistor sets a Q value

equal to 0.54 for an f3dB = 5MHz for fO = 6.954MHz.

Figures 15 to 17 show additional circuits highlighting the

use of R4 in the modiﬁ ed second order cicuit to set the f3dB

frequency to 7.5MHz, 10MHz and 15MHz respectively.

The design procedure for a speciﬁ ed f3dB frequency is

as follows:

1 Using the chosen C1, C2 and C3 values calculate the

fO value.

2. Using fO of step 1 and the speciﬁ ed f3dB calculate the

Q value.

3. Calculate the R4 value using the Q value of step 3.

4. Calculate the required external resistor REXT value for

the R4 value in step 3. Example, in Figure 14 the Q

value for f3dB = 5MHz is 0.54, the required R4 resistor

is 350Ω, the R4A and R4B resistors are the internal

100Ω and the REXT resistor is 150Ω [REXT = R4 – (R4A

+ R4B)].

Note: The modiﬁ ed second order ﬁ lter topology requires

the use of at least two of the three input resistor pairs (two

of the three 400Ω, 200Ω and 100Ω pairs).

LTC6601-1

66011f

APPLICATIONS INFORMATION

Figure 13. Modiﬁ ed Filter Topology and Equations

–

VOUT(DIFF)

66011 F13

VIN(DIFF)

C3A

C3B

49.9

R4A

REXT

R4B C1

R4 = R4A + R4B + REXT

C3 = C3A || C3B

f3dB =

fO• 6089 • 3568 • Q41788 • Q2+447

()

+1.287 • 105•2•Q

21

()











507.6 • Q

0.2236 • fO• 2.109 • 105• 9.891• 1012 •f

3dB45.486 • 109•f

()

+120 • 5.526 • 109•f

3dB2+3.082 • 106•f

()











16 • fO2• 8.29 • 109•f

3dB2+4.127 • 109•f

()

6.638 • 1010 •f

3dB4

()

R4 =1.25 • 104•C1•Q•R2

559 • C1• R2 •C2 +2•C3









50 • Q • C1• 125 • GAIN +R2 +125

()

C2 • R2

()

VOUT(DIFF)

VIN(DIFF)

=–

GAIN

R2 • R3 • C1• C2 +2•C3

()

S2+R1• R2• 2•R3+R4

()

+R3 • R4

()

+R2 • R3 • R4

R1•R2•R3•R4• C2+2•C3

()

•S+1

R2 • R3 • C1• C2 +2•C3

()

GAIN =–VOUT(DIFF)

VIN(DIFF)

=–R2

fO=1

2••R2•R3•C1•C2+2•C3

()









•C2

C1 +2•C3











1+1+|GAIN|+2• R2









•R3

R2 –C2

LTC6601-1

66011f

Figure 14. Modiﬁ ed Filter Conﬁ guration Using a Capacitor and a Resistor Between Summing Nodes (f–3dB = 5MHz)

APPLICATIONS INFORMATION

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 1

fO = 6.954MHz

Q = 0.54

f–3dB = 5MHz

VOUT(DIFF)

VIN 20

–

150

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 2.3

fO = 6.964MHz

Q = 0.54

f–3dB = 5MHz

VOUT(DIFF)

VIN 20

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 3.3

fO = 6.964MHz

Q = 0.54

f–3dB = 5MHz

VOUT(DIFF)

VIN 20

–

66011 F14a

75

FREQUENCY (Hz)

GAIN (dB)

66011 F14b

–10

–20

–30

–40

–50

–60

100k 100M10M1M

FREQUENCY (Hz)

PHASE (DEG)

GROUP DELAY (ns)

66011 F14c

–30

–60

–90

–120 50

100k 2M 8M 10M6M4M

PHASE

GROUP DELAY

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

LTC6601-1

66011f

APPLICATIONS INFORMATION

Figure 15. Modiﬁ ed Filter Conﬁ guration Using a Resistor Between Summing Nodes (f–3dB = 7.5MHz)

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 1

fO = 7.971MHz

Q = 0.67

f–3dB = 7.5MHz

VOUT(DIFF)

VIN

ZIN(DIFF) = 800 VIN

ZIN(DIFF) = 225

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 3.56

fO = 7.971MHz

Q = 0.67

f–3dB = 7.5MHz

VOUT(DIFF)

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 4.55

fO = 7.971MHz

Q = 0.67

f–3dB = 7.5MHz

VOUT(DIFF)

66011 F15a

–

24.9

12.4

VIN

ZIN(DIFF) = 175.6

12.4

FREQUENCY (Hz)

GAIN (dB)

66011 F15b

–10

–20

–30

–40

–50

–60

100k 100M10M1M

FREQUENCY (Hz)

PHASE (DEG)

GROUP DELAY (ns)

66011 F15c

–30

–60

–90

–120 50

100k 2M 8M 10M6M4M

PHASE

GROUP DELAY

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

LTC6601-1

66011f

APPLICATIONS INFORMATION

Figure 16. Modiﬁ ed Filter Conﬁ guration Using a Resistor Between Summing Nodes (f–3dB = 10MHz)

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 0

fO = 11.27MHz

Q = 0.64

f–3dB = 10MHz

VOUT(DIFF)

VIN

ZIN(DIFF) = 400

VIN

ZIN(DIFF) = 250

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 1.6

fO = 11.27MHz

Q = 0.64

f–3dB = 10MHz

VOUT(DIFF)

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 2.6

fO = 11.27MHz

Q = 0.64

f–3dB = 10MHz

VOUT(DIFF)

–

66011 F16a

49.9

24.9

VIN

ZIN(DIFF) = 164

FREQUENCY (Hz)

GAIN (dB)

66011 F16b

–10

–20

–30

–40

–50

100k 100M10M1M

FREQUENCY (Hz)

PHASE (DEG)

GROUP DELAY (ns)

66011 F16c

–30

–60

–90

–120 50

100k 4M 16M 20M12M8M

PHASE

GROUP DELAY

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

LTC6601-1

66011f

APPLICATIONS INFORMATION

Figure 17. Modiﬁ ed Filter Conﬁ guration Using a Resistor Between Summing Nodes (f–3dB = 15MHz)

20 19 18 17 16

6 7 8 9 10

LTC6601-1

GAIN = 1

fO = 16.04MHz

Q = 0.56

f–3dB = 15MHz

GAIN = 1.6

fO = 16.04MHz

Q = 0.66

f–3dB = 15MHz

VOUT(DIFF)

VIN

ZIN(DIFF) = 400

VIN

ZIN(DIFF) = 250

49.9

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

24.9

–

24.9

GAIN = 2.6

fO = 16.04MHz

Q = 0.66

f–3dB = 15MHz

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

–

66011 F17a

24.9

VIN

ZIN(DIFF) = 164

FREQUENCY (Hz)

GAIN (dB)

66011 F17b

–10

–20

–30

–40

–50

100k 100M10M1M

FREQUENCY (Hz)

PHASE (DEG)

GROUP DELAY (ns)

66011 F17c

–30

–60

–90

–120 50

100k 4M 16M 20M12M8M

PHASE

GROUP DELAY

Gain Magnitude vs Frequency (Gain = 1) Passband Phase and Group Delay

LTC6601-1

66011f

APPLICATIONS INFORMATION

DC1251A Demonstration Board

The DC1251A demonstration circuit contains an LTC6601-1

(DC1251A-A). On a DC1251A the LTC6601-1 programming

pins can be connected through 0603 resistor jumpers. In

addition, optional surface mount capacitors and inductors

at the LTC6601 input and/or output can be installed for

additional ﬁ ltering (a lowpass ﬁ lter up to a 5th order can

be implemented with a DC1251A demonstration circuit).

The DC1251A has SMA connectors for the differential

input and output of the LTC6601-1. An on board 106MHz

lowpass RC ﬁ lters the LTC6601-1 output.

DC12351A Top Silk Screen

LTC6601-1

66011f

APPLICATIONS INFORMATION

LTC6601-X Demonstration Circuit DC1251A

66011 DC

RC3

IN2+

IN1+

BIAS

IN1–

IN2–

OUT

V+

V–

VOCM

OUT

IN3+ C5 C6 C7 C8

20 19 18

LTC6601-1

17 16

678910

IN– C1 C2 C3 C4

RC2

RQ1

20Ω 1% (OPT)

RF1

RF2 RF3 RF4 RF5 RF6

RF7

RF8 RF9 RF10

RF11

RF12

49.9Ω, 1%

C11

1000pF

C10

0.01µF

V+

10pF

C3 (OPT)

C4 (OPT)

C12

0.01µF

VOUT–

VOUT+

EXT

VOCM

GND

(24AQG-VIA)

(24AWG-VIA)

RG2

RG1

RZ1

(OPT)

RIN1

RZ2

RG4

RG5

RG6

RG3

(OPT)

RIN2

VIN+

VIN–

SHDN

V+

JP1

C15

0.1µF

C14

1µF

10V

C13

10µF

10V

V+ IN

2.7V TO 5.5V

GND

(24AWG-VIA)

V+

DC1251A-A LTC6601CUF-1

DC1251A-B LTC6601CUF-2

ASSY U1

BOARD ASSEMBLY

LTC6601-1

66011f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UF Package

20-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1710)

4.00 p 0.10

(4 SIDES)

NOTE:

1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220

VARIATION (WGGD-1)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.38 p 0.10

2019

BOTTOM VIEW—EXPOSED PAD

2.45 p 0.10

(4-SIDES)

0.75 p 0.05 R = 0.115

TYP

0.25 p 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF20) QFN 10-04

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 p0.05

0.25 p0.05

0.50 BSC

2.45 p 0.05

(4 SIDES)

3.10 p 0.05

4.50 p 0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.30 TYP

LTC6601-1

66011f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1108 • PRINTED IN USA

PART NUMBER DESCRIPTION COMMENTS

1568 Very Low Noise, High Frequency, Active RC,

Filter Building Block Up to 10MHz Filters, SNR = 92dB, THD = –84dBc at 2MHz

LT1993-2/LT1993-4/

LT1993-10 800MHz/900MHz/700MHz Low Distortion, Low Noise

Differential Ampliﬁ er/ADC Driver AV = 2V/V / AV = 4V/V / AV = 10V/V, NF = 12.3dB/14.5dB/12.7dB,

OIP3 = 38dBm/40dBm/40dBm at 70MHz

LT1994 Low Noise, Low Distortion Fully differential Input/Output

Ampliﬁ er/Driver Low Distortion, 2VP-P, 1MHz: –94dBc, 13mA, Low Noise: 3nV/√Hz

LT6402-6/LT6402-12/

LT6402-20 300MHz Low Distortion, Low Noise Differential Ampliﬁ er/

ADC Driver AV = 6dB/AV = 12dB/AV = 20dB, NF = 18.6dB/15dB/12.4dB,

OIP3 = 49dBm/43dBm/51dBm at 20MHz

LTC6404-1 Fully Differential Ampliﬁ er, GBW = 500MHz Very Low Distortion, (2VP-P, 10MHz): –91dBc

LTC6404-2 Fully Differential Ampliﬁ er, GBW = 900MHz Very Low Distortion, (2VP-P, 10MHz): –96dBc

LTC6404-4 Fully Differential Ampliﬁ er, GBW = 1700MHz Very Low Distortion, (2VP-P, 10MHz): –101dBc

LT6600-2.5/LT6600-5/

LT6600-10/LT6600-20 Very Low Noise, Fully Differential Ampliﬁ er and Filter 2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply,

SO-8 Package

LTC6602 Dual, Matched Bandpass Filter Programmable Gain and Bandwidth for RFID Applications

(40kHz to 1MHz)

LTC6603 Dual, Matched Lowpass Filter Programmable Gain and Bandwidth (25kHz to 2.5MHz)

LTC6604-X Dual, Matched Lowpass Filter 2.5MHz, 5MHz, 10MHz and 15MHz

LTC6605-X Dual, Matched Lowpass Filter 7MHz, 10MHz and 14MHz

TYPICAL APPLICATION

4th Order, 10MHz, Lowpass Filter with 12dB Gain

Gain Magnitude vs Frequency

RELATED PARTS

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VIN

ZIN(DIFF) = 200 49.9 49.9

–

20 19 18 17 16

6 7 8 9 10

LTC6601-1

VOUT(DIFF)

–

66011 TA02a

FREQUENCY (Hz)

GAIN (dB)

66011 TA02b

–20

–40

–60

–80

–100

100k 100M10M1M