This is information on a product in full production.
July 2015 DocID022218 Rev 3 1/35
VIPER37
VIPerPlus family: fixed frequency offline converter
Datasheet
-
production data
Figure 1. Typical topology
Features
•800 V avalanche-rugged power MOSFET
allowing ultra wide range input V
ac
to b e
achieved
•PWM operation with adjustable limiting current
•30 mW standby power at 265 V
ac
•Operating frequency:
– 60 kHz (L type), 115 kHz (H type)
•Frequency jittering for low EMC
•Output overvoltage protection
•High primary current protection (2
nd
OCP)
•Input undervoltage setting (brownout)
•Onboard soft-start
•Safe auto-restart after a fault condition
•Hysteretic thermal shutdown
Applications
•SMPS for set-top boxes, DVD players and
recorders, white goods
•Auxiliary power supply for consumer and home
equipment
•ATX auxi li ar y powe r su ppl y
•Low / medium power AC-DC adapters
Description
This device is an offline converter with an 800 V
rugged power section, a PWM control, two levels
of overcurrent protection, overvoltage and
overload protection, hysteretic thermal protection,
soft-start, and safe auto-restart after the removal
of any fault condition. Burst mode operation and
very low device consumption help to meet the
standby energy saving regulations. Advance
frequency jittering reduces EMI filter costs.
Brownout function protects the switch mode
power supply when the rectified input voltage
level is below the normal minimum level specified
for the system. The high voltage startup circuit is
embedded in the device.
DC input high voltage
wide range
+
DC Output voltage
-
+
VIPER37
DRAINDRAIN DRAIN DRAIN DRAIN
BRVDD CONT FBGND
62QDUURZ
6',3
Table 1. Device summary
Order code Package Packing
VIPER37LE SDIP10
Tube
VIPER37HE
VIPER37HD
SO16 narrow
VIPER37LD
VIPER37HDTR Tape and reel
VIPER37LDTR
www.st.com
Contents VIPER37
2/35 DocID022218 Rev 3
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Elect rical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Efficiency performances for a typical flyback converter . . . . . . . . . . . 16
8 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.2 High voltage st artup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.3 Power-up and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.4 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5 Auto-restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.7 Current mode conversion with adj ustable current limit set point . . . . . . . 21
8.8 Overvol tage protection (O VP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.9 About the CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.10 Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 24
8.11 Burst mode operati on at no load or very light load . . . . . . . . . . . . . . . . . . 26
8.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.13 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 29
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID022218 Rev 3 3/35
VIPER37 Contents
35
9.1 SDIP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 SO16 narrow p a ckage informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block diagram VIPER37
4/35 DocID022218 Rev 3
1 Block diagram
Figure 2. Block diagram
2 Typical power
THERMAL
SHUTDOWN
6uA
LEB
&
OVP
LOGIC
SOFT
START OC P
BLOCK
Ref
TU R N -ON
LOGIC
DRAIN
SUPPLY
& UVLO
OTPOLP
BURST
Internal Supply bus
BR
BURST-MODE
LOGIC BURST
S
R1 R2
Q
+
-
UVLO
Vin_OK
+
-
OCP
Ref erence Voltages
OVP
15uA
Istart-up
OVP
Vcc
OSCI LLATOR
FB
VBRth
HV_ON
OTP
.
GND
+
-
Rsense
CONT
+
-
PWM
2nd OCP
LOGIC
VDD
Table 2. Typical power
Part number 230 V
AC
85-265 V
AC
Adapter
(1)
Open frame
(2)
Adapter
(1)
Open frame
(2)
VIP ER37 18 W 20 W 13 W 15 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50
°
C ambient.
2. Maximum practical continuous power in an open frame design at 50
°
C ambient, with adequate heatsinking.
DocID022218 Rev 3 5/35
VIPER37 Pin settings
35
3 Pin settings
Figure 3. Connection diagram (top view)
Note: The copper area for heat dissipation must be designed under the DRAIN pins.
Table 3. Pin description
Pin n. Name Function
SO16N
1...2 GND This pin represents the device ground and the source of the power section.
3 N.C. Not connected.
4N.A.
Not available for user.
This pin is mechanically connected to the controller die pad of the frame.
In order to impro ve the noise immunity, is highly recom mended con nect it to GND
(pin 1-2).
5VDD
Supply voltage of the control section. This pin also provides the charging current
of the external capacitor during start-up time.
6CONT
Control pin. The following functions can be selected:
1. current limit set poi nt a dju st me nt. The internal set default value of the cycle-by-
cycle current limit can be reduced by connecting to ground an external resistor.
2. out put volt age mon itoring. A volt age exc eeding V
OVP
threshold (see Table 8 on
page 8) shuts the IC down reducing the device consumption. This function is
strobed and digitally filtered for high noise immunity.
7FB
Control input for duty cycle control. Internal current generator provides bias
current for loop regulation. A voltage below the threshold V
FBbm
activates the
burst-mode operation. A level close to the threshold V
FBlin
means that we are
approaching the cycle-by-cycle over-current set point.
8BR
Brownout protection input with hysteresis. A voltage below the threshold V
BRth
shuts down (not latch) the device and lowers the power consumption. Device
operation re st art s as t he volt age excee ds the thresho ld V
BRth
+ V
BRhyst
. It ca n be
connected to ground when not used.
9...12 N.C. Not connected.
13...16 DRAIN High voltage drain pin. The built-in high voltage switched start-up bias current is
drawn from this pin too.
Pins connected to the metal frame to facilitate heat dissipation.
Electrical data VIPER37
6/35 DocID022218 Rev 3
4 Electrical data
4.1 Maximum ratings
4.2 Thermal data
Table 4. Absolute maxi mum ratings
Symbol Parameter Value Unit
Min. Max.
V
DRAIN
Drain-to-source (ground) voltage 800 V
E
AV
Repetitive avalanche energy
(limited by T
J
= 150 °C) 5mJ
I
AR
Repetitive avalanche current
(limited by T
J
= 150 °C) 1.5 A
I
DRAIN
Pulse drain current 3 A
V
CONT
Control input pin voltage -0.3 6 V
V
FB
Feedback voltage -0.3 5.5 V
V
BR
Brownout input pin voltage -0.3 5 V
V
DD
Supply voltage (I
DD
= 25 mA) -0.3 Self limited V
I
DD
Input current 25 mA
P
TOT
Pow er di ssipation a t T
A
< 60 °C 1.5 W
T
J
Operating junction temperature range -40 150 °C
T
STG
Storage temperature -55 150 °C
Table 5. Thermal data
Symbol Parameter Max. value Unit
SO16N SDIP10
R
thJP
Thermal resistance junction pin
(Dissipated power = 1 W) 35 35 °C/W
R
thJA
Thermal resistance junction ambient
(Dissipated power = 1 W) 110 100 °C/W
R
thJA
Thermal resistance junction ambient
(1)
(Dissipated power = 1 W)
1. When mounted on a standard single side FR4 board with 100 mm
2
(0.155 sq. in.) of Cu (35 µm thick).
80 85 °C/W
DocID022218 Rev 3 7/35
VIPER37 Electrical data
35
4.3 Electrical characteristics
(T
J
= -25 to 125 °C, V
DD
= 14 V
(a)
; unless otherwise specified).
a. Adjust V
DD
above V
DDon
startup threshold before setting to 14 V.
Table 6. Power section
Symbol Parameter Test condition Min. Typ. Max. Unit
V
BVDSS
Breakdow n vo ltage I
DRAIN
= 1 mA, V
FB
= GND
T
J
= 25 °C 800 V
I
OFF
OFF state drain current
V
DRAIN
= max. rating,
V
FB
= GND, T
J
= 25 °C 60 μA
R
DS(on)
Drain-s ou r ce on st a t e
resistance
I
DRAIN
= 0.4 A, V
FB
= 3 V,
V
BR
= GND, T
J
= 25 °C 4.5 Ω
I
DRAIN
= 0.4 A, V
FB
= 3 V,
V
BR
= GND, T
J
= 125 °C 9Ω
C
OSS
Effective (energy related)
output ca pacitance
V
DRAIN
= 0 to 640 V,
T
J
= 25 °C 17 pF
Table 7. Supply section
Symbol Parameter Test condition Min. Typ. Max. Unit
Voltage
V
DRAIN_START Drain-so urce start
voltage 60 80 100 V
IDDch Startup charging current
V
DRAIN
= 120 V
V
BR
= GND
V
FB
= GND
V
DD
= 4 V
-2 -3 -4 mA
V
DRAIN
= 120 V
V
BR
= GND
V
FB
= GND
V
DD
= 5 V after fault
-0.4 -0.6 -0.8 mA
V
DD
Operating voltage
range After turn-on 8.5 23.5 V
V
DDclamp
V
DD
clamp voltage I
DD
= 20 mA 23.5 V
V
DDon
V
DD
startup threshold
V
DRAIN
= 120 V
V
BR
= GND
V
FB
= GND
13 14 15 V
V
DDoff
V
DD
undervoltage
shutdown threshold 7.588.5V
V
DD(RESTART)
V
DD
restar t voltage
threshold 44.55 V
Electrical data VIPER37
8/35 DocID022218 Rev 3
Current
I
DD0
Operati ng su ppl y curre nt,
not switching V
FB
= GND, F
SW
= 0 kHz,
V
BR
= GND, V
DD
= 10 V 0.9 mA
I
DD1
Operati ng su ppl y curre nt,
switching
V
DRAIN
= 120 V,
F
SW
= 60 kHz 2.5 mA
V
DRAIN
= 120 V,
F
SW
= 115 kHz 3.5 mA
I
DD_FAULT
Operati ng su ppl y curre nt,
with protection tripping V
DD
= 10 V 400 μA
I
DD_OFF
Operati ng su pply current
with V
DD
< V
DD_OFF
V
DD
= 7 V 270 μA
Table 7. Supply section (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Table 8. Controller section
Symbol Parameter Test condition Min. Typ. Max. Unit
Feedback pin
V
FBolp
Overload shutdown threshold 4.5 4.8 5.2 V
V
FBlin
Linear dynamics upper limit 3.2 3.5 3.7 V
V
FBbm
Burst mode threshold Voltage falling 0.6 V
V
FBbmhys
Burst mode hysteresis Voltage rising 100 mV
I
FB
Feedback sourced current V
FB
= 0.3 V -150 -200 -280 μA
3.3 V < V
FB
< 4.8 V -3 μA
R
FB(DYN)
Dynamic resistance V
FB
< 3.3 V 14 21 kΩ
H
FB
∆V
FB
/ ∆I
D
0.5 2 V/A
CONT pin
V
CONT_l
Low level clamp voltage I
CONT
= -100 µA 0.5 V
V
CONT_h
High level clamp voltage I
CONT
= 1 mA 5 5.5 6 V
Current limitation
I
Dlim
Max. drain current limitation V
FB
= 4 V,
I
CONT
= -10 µA
T
J
= 25 °C 0.95 1 1.05 A
t
SS
Soft-start time 8 .5 ms
T
ON_MIN
Minimu m turn-on time 220 400 480 ns
td Propagation delay
(1)
100 ns
t
LEB
Leading edge blanking
(1)
300 ns
I
D_BM
Peak drain current during burst
mode V
FB
= 0.6 V 160 mA
DocID022218 Rev 3 9/35
VIPER37 Electrical data
35
Oscillator section
F
OSC
VIPER37L V
DD
= operating voltage
range,
V
FB
= 1 V
54 60 66 kHz
VIPER37H 103 115 127 kHz
FD Modulation depth VIPER37L ±4 kHz
VIPER37H ±8 kHz
FM Modulation frequency 250 Hz
D
MAX
Maximum duty cycl e 70 80 %
Overcurrent protec tion (2
nd
OCP)
I
DMAX
Second overcurrent threshold 1.7 A
Overvoltage protection
V
OVP
Overvoltage protection threshold 2.7 3 3.3 V
T
STROBE
Overvoltage protection strobe
time 2.2 us
Brownout protection
V
BRth
Brownout threshold Voltage falling 0.41 0.45 0.49 V
V
BRhyst
Voltage hysteresis above V
BRth
Voltage rising 50 mV
I
BRhyst
Current hyst er esi s 7 12 μA
V
BRclamp
Clamp voltage I
BR
= 250 µA 3 V
V
DIS
Brownout disable voltage 50 150 mV
Thermal shutdown
T
SD
Thermal shu t down temperature
(1)
150 160 °C
T
HYST
Thermal shu t down hystere si s
(1)
30 °C
1. Spec ification assured by design, characterization and statistical correlation.
Table 8. Controller section (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Electrical data VIPER37
10/35 DocID022218 Rev 3
Figure 4. Minimum turn-on time test circuit
Figure 5. Brownout threshold test circuits
Figure 6. OVP threshold test circuits
Note: Adjust V
DD
above V
DDon
startup threshold before setting to 14 V.
14 V
3.5 V
50 Ω
30 V
FB
BR
V(DRAIN)
I(DRAIN)
IDLIM
Time
Time
TONmin
90 %
10 %
GND
CONT
VDD
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
14 V
2 V
10 kΩ
30 V
FB
BR
GND
CONT
VDD
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
VBRth+VBRhyst
VBRth
V(BR)
I(BR)
VDIS
IBRhyst
I(DRAIN)
Time
Time
Time
IBRhyst
VOVP
V(CONT)
V(DRAIN)
Time
Time
14 V
2 V
10 kΩ
30 V
FB
BR
GND
CONT
VDD
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DocID022218 Rev 3 11/35
VIPER37 Typical electrical characteristics
35
5 Typical electrical characteristics
Figure 7. Current limit vs. T
J
Figure 8. Switching frequency vs. T
J
Figure 9. Drain start voltage vs. T
J
Figure 10. HFB vs. T
J
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Typical electrical characteristics VIPER37
12/35 DocID022218 Rev 3
Figure 11. Brownout threshold vs. T
J
Figure 12. Brownout hysteresis vs. T
J
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Figure 13. Brownout hysteresis current vs. T
J
Figure 14. Operating supply current
(not switching) vs. T
J
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DocID022218 Rev 3 13/35
VIPER37 Typical electrical characteristics
35
Figure 15. Operating supply current (switching)
vs. T
J
Figure 16. Current limit vs. R
LIM
Figure 17. Power MOSFET ON resistance vs. T
J
Figure 18. Pow er MOSF E T breakd ow n voltage
vs. T
J
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Typical electrical characteristics VIPER37
14/35 DocID022218 Rev 3
Figure 19. Thermal shutdown
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DocID022218 Rev 3 15/35
VIPER37 Typi cal circ u it
35
6 Typical circuit
Figure 20. Min-features flyback application
Figure 21. Full-features flyback application
OPTO
R5
C6
AC I N
R3
AC I N
VoutD3
R1
C5
U2
R4
BR
C4 R6
C3
C1
D1
GND
C2
R2 D2
BR
CONT
DRAIN
SOURCE
CONTROL
Vcc
FB
V
DD
GND
BR
CONT
DRAIN
SOURCE
CONTROL
Vcc
FB
C3
C2
BR
Vout
R2
Daux
C5
GND
Rl
R3
Rovp
Rh
Rlim
R6
D2
U2
AC I N
D3
R1
C6
OPTO
D1
C4
R5
AC I N
C1
R4
V
DD
GND
Efficiency performances for a typical flyback converter VIPER37
16/35 DocID022218 Rev 3
7 Efficiency performances for a typical flyback
converter
The efficiency of the converter has been measured in different load and line voltage
conditions. In accordance with the ENERGY STAR
®
average active mode testing efficiency
method, the efficiency measurements have been performed at 25%, 50% and 75% and
100% of the rated output power, at both 115 V
AC
and 230 V
AC
.
Figure 22. Power supply consumption at light output loads, V
OUT
=5 V
Table 9. Power supply efficiency, V
OUT
= 5 V, V
IN
= 115 V
AC
%Load Iout [A] Vout [V] Pout [W] Pin [W] Efficiency [%]
25% 0.75 5.04 3.78 4.83 78.26%
50% 1.5 5.04 7.56 9.72 77.78%
75% 2.25 5.04 11.34 14.84 76.42%
100% 3 5.04 15.12 20.04 75.45%
Average efficiency 76.97%
Table 10. Power supply efficiency, V
OUT
= 5 V, V
IN
= 230 V
AC
%Load Iout [A] Vout [V] Pout [W] Pin [W] Efficiency [%]
25% 0.75 5.04 3.78 5.01 75.45%
50% 1.5 5.04 7.56 9.76 77.46%
75% 2.25 5.04 11.34 14.67 77.30%
100% 3 5.03 15.09 19.59 77.03%
Average efficiency 76.81%
50 100 150 200 250 300
0
50
100
150
200
250
300
350
200mW
100mW
50mW
30mW
Input power [mW]
Input voltage [Vac]
DocID022218 Rev 3 17/35
VIPER37 Operation description
35
Figure 23. Power supply consumption at no output load, V
OUT
=5 V
8 Operation description
The device is a high-performance low-voltage PWM controller chip with an 800 V avalanche
rugged power section.
The controller includes: the oscillator with jittering feature, the startup circuits with soft-start
feature, the PWM logic, the current limit circuit with adjustable set point, the second
overcurrent circuit, the burst mode management, the brownout circuit, the UVLO circuit, the
auto-restart circuit, and the thermal protection circuit.
The current limit set-point is set by the CONT pin. The burst mode operation guarantees
high performance in standby mode and helps to accomplish the energy saving norm.
All the fault protections are built in auto-restart mode with very low repetition rate to prevent
the IC overheating.
8.1 Power section and gate driver
The power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The power section has a B
VDSS
of 800 V min. and a typical R
DS(on)
of 4.5 Ω
at 25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the power section cannot be turned on
accidentally.
50 100 150 200 250 300
10
15
20
25
30
35
40
45
50
55
60
65
No brownout
With brownout
Input power [mW]
Input voltage [Vac]
Operation description VIPER37
18/35 DocID022218 Rev 3
8.2 High voltage startup generator
The HV current generator is supplied through the DRAIN pin and is enabled only if the input
bulk capacitor voltage is higher than the V
DRAIN_START
threshold, 80 V
DC
(typ i c a l) . When
the HV current generator is ON, the I
DDch
current (3 mA typical value) is delivered to the
capacitor on the V
DD
pin. In the case of auto-restart mode after a fault event, the I
DDch
current is reduced to 0.6 mA, in order to have a slow duty cycle during the restart phase.
8.3 Power-up and soft-start
If the input voltage rises up to the device start threshold V
DRAIN_START
, the V
DD
voltage
begins to grow due to the I
DDch
current (see Table 7) coming from the internal high voltage
startup circuit. If the V
DD
voltage reaches the V
DDon
threshold (see Table 7), the Power
MOSFET starts switching and the HV current generator is turned off (see Figure 25).
The IC is powered by the energy stored in the capacitor on the V
DD
pin, C
VDD
, until the self-
supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
The C
VDD
capacitor must be sized correctly in order to avoid fast discharge and keep the
needed voltage value higher than the V
DDoff
threshold. In fact, a too low capacitance value
could terminate the switching operation before the controller receives any energy from the
auxiliary winding.
The following formula can be used for the V
DD
capacitor calculation:
Equation 1
The t
SSaux
is the time needed for the steady-state of the auxiliary voltage. This time is
estimated by the applicator according to the output stage configurations (transformer , output
capacitances, etc.).
During the converter startup time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of the startup converter or after a fault.
C
VDD
I
DDch
t
SSaux
×
V
DDon
V
DDoff
–
----------------------------------------=
DocID022218 Rev 3 19/35
VIPER37 Operation description
35
Figure 24. I
DD
current during startup and burst mode
Figure 25. Timing diagram: normal power-up and power-down sequences
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Operation description VIPER37
20/35 DocID022218 Rev 3
Figure 26. Timing diagram: soft-start
8.4 Power down operation
At converter power down, the system loses regulation as soon as the input voltage is so low
that the peak current limitation is reached. The V
DD
voltage drops and when it falls below
the V
DDoff
threshold (see Table 7) the Power MOSFET is switched OFF, the energy
transfers to the IC interrupted and consequently the V
DD
voltages decreas e, Figure 25.
Later, if the V
IN
is lower than V
DRAIN_START
(see Table 7), the startup sequence is inhibited
and the power down completed. This feature is useful to prevent the converter’s restart
attempts and ensures monotonic output voltage decay during the system power down.
8.5 Auto-restart operation
If, after a converter power down, the V
IN
is higher than V
DRAIN_START,
the startup sequence
is not inhibited and is activated only when the V
DD
voltage drops below the V
DD(RESTART)
threshold (see Table 7). This means that the HV startup current generator restarts the V
DD
capacitor charging only when the V
DD
voltage drops below V
DD(RESTART)
. The scenario
described above is, for instance, a power down because of a fault condition. After a fault
condition, the charging current I
DDch
is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal
startup converter phase. This feature, together with the low V
DD(RESTART)
threshold,
ensures that, after a fault, the restart attempts of the IC have a very long repetition rate and
the converter works safely with extremely low power throughput. Figure 27 shows the IC
behavior after a short-circuit event.
FBlin
V
V
FBolp
IDRAIN
VFB
tss
t
t
IDlim
DocID022218 Rev 3 21/35
VIPER37 Operation description
35
Figure 27. Timing diagram: behavior after short-circuit
8.6 Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both cases the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz
(115 kHz version) at a 250 Hz (typ.) rate, so that the resulting spread-spectrum action
distributes the energy of each harmonic of the switching frequency over a number of side-
band harmonics having the same energy on the whole but smaller amplitudes.
8.7 Current mode conversion with adjustable current limit set
point
This device is a current mode converter: the drain current is sensed and converted into
voltage that is applied to the non-inverting pin of the PWM comparator. This voltage is
compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle
basis.
The device has a default current limit value, I
Dlim
, that the user can adjust according to the
electrical specifications, through the R
LIM
resistor connected to the CONT pin (see
Figure 16).
The CONT pin has a minimum current sunk, needed to activate the I
Dlim
adjustment: without
R
LIM
or with high R
LIM
(i.e. 100 kΩ), the current limit is fixed to the default value (see I
Dlim
,
Table 8).
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Operation description VIPER37
22/35 DocID022218 Rev 3
8.8 Overvoltage protection (OVP)
The device can monitor the converter output voltage. This operation is done by the CONT
pin during Power MOSFET OFF-time, when the voltage generated by the auxiliary winding
tracks the converter's output voltage, through turn ratio (see Figure 28).
In order to perform the output voltage monitor , the CONT pin must be connected to the aux.
winding through a resistor divider made up of R
LIM
and R
OVP
(see Figure 21 or Figure 29). If
the voltage applied to the CONT pin exceeds the internal reference V
OVP
(see Table 8) for
four consecutive times, the controller recognizes an overvoltage condition. This special
feature uses an internal counter; that is to reduce sensitivity to noise and prevent the latch
from being erroneously activated (see Figure 28). The counter is reset every time the OVP
signal is not triggered in one oscillator cycle.
Referring to Figure 21, the re sistors’ divider rat io k
OVP
is given by:
Equation 2
Equation 3
where:
•V
OVP
is the OVP threshold (see Table 9)
•V
OUT OVP
is the converter output voltage value to activate the OVP set by the user
•N
AUX
is the auxiliary winding turns
•N
SEC
is the secondary winding turns
•V
DSEC
is the secondary diode forward voltage
•V
DAUX
is the auxiliary diode forward voltage
•R
OVP
together with R
LIM
make up the output voltage divider.
Then, once the R
LIM value is
fixed
,
according to the desired I
Dlim
, the R
OVP
can be calculated
by:
Equation 4
N
AUX
N
SEC
--------------
k
OVP
V
OVP
N
AUX
N
SEC
-------------- V
OUTOVP
V
DSEC
+()V
DAUX
–⋅
---------------------------------------------------------------------------------------------------=
k
OVP
R
LIM
R
LIM
R
OVP
+
----------------------------------=
R
OVP
R
LIM
1k
OVP
–
k
OVP
-----------------------×=
DocID022218 Rev 3 23/35
VIPER37 Operation description
35
The resistor values are such that the current sourced and sunk by the CONT pin are within
the rated capability of the internal clamp.
Figure 28. OVP timing diagram
8.9 About the CONT pin
Referring to Figure 29, the features below can be implemented through the CONT pin:
1. Current limit set point
2. Overvoltage protection on the converter output voltage
Table 11, referring to Figure 29, lists the external resistance combinations needed to
activate one or more of the CONT pin functions.
Figure 29. CONT pin configuration
t
V
DS
VA
U
X
t
t
t
STROBE
t
COUNTER
RESET
t
COUNTER
STATUS t
0
CONT
(pin 4)
sampling time
OVP
FAULT
0 0 0 0 →11 →22 →00 →11 →
22 →33 →
4
0
ERULIAF POOL KCABDEEFECNABRUTSID YRAROPMETNOITAREPO LAMRON t
V
DS
t
t
t
STROBE
t
COUNTER
RESET
t
COUNTER
STATUS t
0
(pin 4)
OVP
FAULT
0 0 0 0 →1 →2 →0 →1 →2 →3 →
0
ERULIAF POOL KCABDEEFECNABRUTSID YRAROPMETNOITAREPO LAMRON t
VOVP
TSTROBE
+
-
Current Limit Comparator
To OVP Protection
R
OVP
R
LIM
D
AUX
SOFT
START
CONT
From SenseFET
Auxiliary
winding
To PW M Logic
OVP DETECTION
LOGIC
Curr. Lim.
BLOCK
OCP
Operation description VIPER37
24/35 DocID022218 Rev 3
8.10 Feedback and overload protection (OLP)
The device
is a current mode converter: the feedback pin controls the PWM operation,
controls the burst mode, and actives the overload protection. Figure 30 and Figure 31 show
the internal current mode structure.
With the feedback pin voltage between
V
FBbm
and
V
FBlin
, (see Table 8) the drain current is
sensed and converted into voltage that is applied to the non-inverting pin of the PWM
comparator.
This voltage is compared with the one on the feedback pin through a voltage divider on a
cycle-by-cycle basis. When these two voltages are equal, the PWM logic orders the switch-
off of the Power MOSFET. The drain current is always limited to the I
Dlim
value .
In case of overload, the feedback pin increases in reaction to this event and when it goes
higher than
V
FBlin
, the PWM comparator is disabled and the drain current is limited to I
Dlim
by
the OCP comparator, see Figure 2.
When the feedback pin voltage reaches the threshold V
FBlin
,
an internal current generator
starts to charge the feedback capacitor (C
FB
) and when the feedback voltage reaches the
V
FBolp
threshold, the converter is turned off and the startup phase is activated with a reduced
value of I
DDch
to 0.6 mA, see Table 7.
During the first startup phase of the converter, after the soft-start time (t
SS
), the output
voltage may force the feedback pin voltage to rise up to the
V
FBolp
threshold that switches off
the converter itself.
To avoid this event, the appropriate feedback network must be selected according to the
outp ut load . Moreov er , the feedbac k networ k fixes the com pensati on loop s tabil ity. Figure 30
and Figure 31 show the two different feedback networks.
The time from the overload detection (VFB =
V
FBlin
) to the device shutdown
(VFB =
V
FBolp
) can be set by the C
FB
value (see Figure 30 and Figure 31), using the formula:
Equation 5
where I
FB
is the value, reported in Table 8, when the FB voltage is between V
FBlin
and
V
FBolp
.
In Figure 30, the capacitor connected to the FB pin (C
FB
) is part of the compensation circuit
as well as being necessary to activate the overload protection.
Table 11. CONT pin configurations
Function / component R
LIM (1)
1. R
LIM
must be fixed before R
OVP
.
R
OVP
D
AUX
I
Dlim
reduction See Figure 16 No No
OVP ≥ 80 kΩSee Equation 4 Yes
I
Dlim
reduction + OVP See Figure 16 See Equation 4 Yes
T
OLP delay–
C
FB
V
FBolp
V
FBlin
–
I
FB
----------------------------------------×=
DocID022218 Rev 3 25/35
VIPER37 Operation description
35
After the startup time, t
SS
, during which the feedback voltage is fixed at
V
FBlin
, the output
capacitor may not be at its nominal value and the controller interprets this situation as an
overload condition. In this case, the OLP delay helps to avoid an incorrect device shutdown
during the startup phase.
Owing to the above considerations, the OLP delay time must be long enough to bypass the
initial output voltage transient and check the overload condition only when the output
voltage is in steady-state. The output transient time depends on the value of the output
capacitor and on the load.
When the value of the C
FB
capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used, shown in
Figure 31.
Using this alternative compensation network, two poles (f
PFB
, f
PFB1
) and one zero (f
ZFB
) ar e
introduced by the capacitors C
FB
and C
FB1
and the resistor R
FB1
.
The capacitor C
FB
introduces a pole (f
PFB
) at a higher frequency than f
ZB
and f
PFB1
. This
pole is usually used to compensate the high frequency zero due to the ESR (equivalent
series resistor) of the output capacitance of the flyback converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 31, are reported by the equations below:
Equation 6
Equation 7
Equation 8
R
FB(DYN)
is the dynamic resistance seen by the FB pin.
The C
FB1
capacitor fixes the OLP delay and usually C
FB1
results much higher than C
FB
.
Equation 5 can still be used to calculate the OLP delay time but C
FB1
must be considered
instead of C
FB
. Using the alternative compensation network, the user can satisfy, in all
cases, the loop stability and the correct OLP delay time alike.
1FB1FB
ZFB
RC2 1
f⋅⋅π⋅
=
()
1FB)DYN(FBFB
1FB)DYN(FB
PFB
RRC2 RR
f⋅⋅⋅π⋅
+
=
()
)DYN(FB1FB1FB
1PFB
RRC2 1
f+⋅⋅π⋅
=
Operation description VIPER37
26/35 DocID022218 Rev 3
Figure 30. FB pin configuration 1
Figure 31. FB pin configuration 2
8.11 Burst mode operation at no load or very light load
When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If
it falls below the burst mode threshold, V
FBbm
, the Power MOSFET is no longer allowed to
be switched on. After the MOSFET stops, as a result of the feedback reaction to the energy
delivery stop, the feedback pin voltage increases and when it exceeds the level, V
FBbm
+
V
FBbmhys
, the power MOSFET starts switching again. The burst mode thresholds are
reported in Table 8 and Figure 32 shows this behavior. Depending on the output load, the
power alternates between periods of time in which the Power MOSFET is switching and is
enabled, with periods of time when the Power MOSFET is not switching; this working mode
is called burst mode. The power delivered to the output during switching periods exceeds
the load power demands; the excess of power is balanced from the non-switching period
where no power is processed. The advantage of burst mode operation is an average
switching frequency much lower then the normal operation working frequency, up to a few
hundred hertz, minimizing all frequency related losses. During burst mode the drain current
peak is clamped to the level, I
D_BM
, reported in Table 8.
From sense FET
4.8V
BURST
PWM
CONTROL
Cfb
To PWM Logic
BURST-MODE
REFERENCES
BURST-MODE
LOGIC
+
-
PWM
+
-
OLP comparator To disable logic
4.8V
From sense FET
PWM
CONTROL
+
-
PWM
BURST
To disable logic
+
-
OLP comparator
To PWM Logic
BURST-MODE
LOGIC
Cfb1
Rfb1 Cfb
BURST-MODE
REFERENCES
DocID022218 Rev 3 27/35
VIPER37 Operation description
35
Figure 32. Burst mode timing diagram, light load management
8.12 Brownout protection
Brownout protection is a not-latched shutdown function activated when a condition of mains
undervoltage is detected.
The brownout comparator is internally referenced to V
BRth
,Table 8, and disables the PWM if
the voltage applied at the BR pin is below this internal reference. Under this condition the
Power MOSFET is turned off. Until the brownout condition is present, the VDD voltage
continuously oscillates between the V
DDon
and the UVLO thresholds, as shown in the timing
diagram of Figure 33. A voltage hysteresis is present to improve the noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus
the previously mentioned voltage hysteresis, see Figure 5.
The brownout comparator is provided also with a current hysteresis, I
BRhyst
. The user must
set the rectified input voltage above which the Power MOSFET starts switching after
brownout event, V
INon
, and the rectified input voltage below which the Power MOSFET is
switched off, V
INoff
. Thanks to the I
BRhyst
, see Table 8, these two thresholds can be set
separately.
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Operation description VIPER37
28/35 DocID022218 Rev 3
When the V
INon
and the V
INoff
levels are fixe d, with refer enc e to Figure 33, the following
relationships can be established for the calculation of the resistors R
H
and R
L
:
Equation 9
Equation 10
For a proper operation of this function, V
IN on
must be less than the peak voltage at
minimum mains and V
IN off
less than the minimum voltage on the input bulk capacitor at
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, it is therefore prone
to pick up noise, which might alter the OFF threshold when the converter operates or
creates an undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent
any malfunctioning of this kind.
If the brownout function is not used, the BR pin must be connected to GND, ensuring that
the voltage is lower than the minimum V
DIS
threshold (50 mV), see Table 8.
Figure 33. Brownout protection: BR external setting and timing diagram
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BRthINoff
BRhystINoffINon
BRhyst
BRhyst
LIV
VV VVV
I
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−
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+−=
BRhyst
BRhyst
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BRhyst
BRhystINoffINon
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DocID022218 Rev 3 29/35
VIPER37 Operation description
35
In order to enable the brownout function, the BR pin voltage must be higher than the
maximum V
DIS
threshold (150 mV), see Table 8.
8.13 2
nd
level overcurrent protection and hiccup mode
The device is protected against short-circuit of the secondary rectifier, short-circuit on the
secondary winding, or a hard-saturation of the flyback transformer. Such an anomalous
condition is invoked when the drain current exceeds the threshold I
DMAX
(see Table 8).
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal trip. If, in the subsequent switching cycle, the
signal is not tripped, a temporary disturbance is assumed and the protection logic is reset in
its idle state; otherwise, if the I
DMAX
threshold is exceeded for two consecutive switching
cycles, a real malfunction is assumed and the Power MOSFET is turned off.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding; hence the voltage on the V
DD
capacitor
decays to the V
DD
undervoltage threshold (V
DDoff
), which clears the latch.
The startup HV current generator is still off, until the V
DD
voltage goes below its restart
voltage, V
DD(RESTART)
. After this condition the V
DD
capacitor is charged again by a 600 µA
current, and the converter switching restarts if the V
DDon
occurs. If the fault condition is not
removed the device enters auto-restart mode. This behavior results in a low-frequency
intermittent operation (hiccup-mode operation), with very low stress on the power circuit.
See the timing diagram of Figure 34.
Figure 34. Timing diagram: hiccup-mode OCP
VDRAIN
VDD
IDRAIN
V
DDon
time
V
DDof f
V
DD(RESTART)
time
time
Hiccup-mode
Secondary diode
short circuit
Normal operation
IDMAX
Package information VIPER37
30/35 DocID022218 Rev 3
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST tradema rk.
9.1 SDIP10 package information
Figure 35. SDIP10 package outline
DocID022218 Rev 3 31/35
VIPER37 Package information
35
Table 12. SDIP10 mechanical data
Dim. mm
Min. Typ. Max.
A 5.33
A1 0.38
A2 2.92 4.95
b 0.36 0.56
b2 0.51 1.15
c 0.2 0.36
D 9.02 10.16
E 7.62 8.26
E1 6.1 7.11
E2 7.62
E3 10.92
e 1.77
L 2.92 3.81
Package information VIPER37
32/35 DocID022218 Rev 3
9.2 SO16 narrow package information
Figure 36. SO16 narrow package outline
DocID022218 Rev 3 33/35
VIPER37 Package information
35
Table 13. SO16 narrow mechanical data
Dim. mm
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
Revision history VIPER37
34/35 DocID022218 Rev 3
10 Revision history
Table 14. Document revision histor y
Date Revision Changes
17-Feb-2 012 1 Initial rele as e
20-May-2015 2
Added SO16 narrow package.
Updated features in cover page.
Updated Table 1: Devi ce summ ar y, Table 2: Typical power,
Table 3: Pin description, Section 4.3: Electrical chara cte ristic s,
Figure 3: Connection diagram (top vie w).
Modified the HFB parameter in Table 8: Controller section.
Added Section 9.2: SO16 narrow package information.
Minor text changes.
01-Jul-2015 3 Minor text changes.
DocID022218 Rev 3 35/35
VIPER37
35
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