LC717A10PJ-AH - ON Semiconductor

53014HK No.A2214-1/14

Semiconductor Components Industries, LLC, 2014

May, 2014

http://onsemi.com

ORDERING INFORMATION

See detailed ordering and shipping information on page 14 of this data sheet.

LC717A10PJ

Overview

The LC717A10PJ is a high-performance and low-cost capacitance-digital-converter LSI for electrostatic

capacitive touch sensor, especially focused on usability.

It has 16 channels capacitance-sensor input. This makes it ideal for use in the products that need many switches.

Since the calibration function and the judgment of ON/OFF are automatically performed in LSI internal, it can

make development time more short. A detection result (ON/OFF) for each input can be read out by the serial

interface (I2C compatible bus or SPI).

Also, measurement value of each input can be read out as 8-bit digital data. Moreover, gain and other parameters

can be adjusted using serial interface.

Function

 Detection system: Differential capacitance detection (Mutual capacitance type)

 Input capacitance resolution: Can detect capacitance changes in the femto Farad order

 Measurement interval (16 differential inputs): 30ms (Typ) (at initial configuration),

6ms (Typ) (at minimum interval configuration)

 External components for measurement: Not required

 Interface: I2C * compatible bus or SPI selectable.

 Current consumption: 570A (Typ) (VDD = 2.8V), 1.3mA (Typ) (VDD = 5.5V)

 Supply voltage: 2.6V to 5.5V

 Detection operations: Switch

 Packages: SSOP30

Orderin

numbe

: EN*A2214

CMOS LSI

Capacitance-Digital-Converter LSI

for Electrostatic Capacitive Touch

Sensors

SSOP30(225mil)

Advance Information

This document contains information on a new product. Specifications and information

herein are subject to change without notice.

* I2C Bus is a trademark of Philips Corporation.

LC717A10PJ

No.A2214-2/14

Specifications

Absolute Maximum Ratings at Ta = +25C

Parameter Symbol Ratings (VSS = 0V) Unit Remarks

Supply voltage VDD -0.3 to +6.5 V

Input voltage VIN -0.3 to VDD+0.3 V *1

Output voltage VOUT -0.3 to VDD+0.3 V *2

Power dissipation Pd max 160 mW Ta = +105C,

Mounted on a substrate *3

Peak output current IOP ±8 mA Per a pin

Duty ratio 50% *2

Total output current IOA ±40 mA LSI outputs total value

Duty ratio 25% *2

*1) Apply to Cin0 to 15, Cref, CrefAdd, nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS

*2) Apply to Cdrv, SDA, SO, INTOUT

*3) Single-layer glass epoxy board (76.1114.31.6t mm)

Recommended Operating Conditions

Parameter Symbol Conditions min typ max Unit Remarks

Operating supply voltage VDD 2.6 5.5 V

Supply ripple + noise Vpp ±20 mV *1

Operating temperature Topr -40 25 105 C

*1) We recommend connecting large and small capacitance between VDD and VSS.

In this case, the small capacitance is equal to or more than 0.1F, and layout nearby LSI.

Electrical Characteristics at VSS = 0V, VDD = 2.6 to 5.5V, Ta  -40 to +105C

* Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143kHz.

* Not tested at low temperature before shipment.

Parameter Symbol Conditions min typ max Unit Remarks

Capacitance detection resolution N 8 bit

Output noise RMS NRMS minimum gain setting ±1.0 LSB *1 *3

Input offset capacitance

adjustment range

CoffRANGE ±8.0 pF *1 *3

Input offset capacitance

adjustment resolution

CoffRESO 8 bit

Cin offset drift CinDRIFT minimum gain setting ±8 LSB *1

Cin detection sensitivity CinSENSE minimum gain setting 0.052 0.108 LSB/fF *2

Cin pin leak current ICin Cin = Hi-Z ±25 ±500 nA

Cin allowable parasitic input

capacitance

CinSUB Cin against VSS 30 pF *1 *3

Cdrv drive frequency fCDRV 100 143 186 kHz

VDD = 5V ±3%, 54.8kHz

setting 50.4 59.45 68.5 kHz *1

nRST minimum pulse width tNRST 1 s

Power-on reset time tPOR 20 ms

Power-on reset operation

condition: Hold time

tPOROP 10 ms *1

Power-on reset operation

condition: Input voltage

VPOROP 0.1 V *1

Power-on reset operation

condition: Power supply rise rate

tVDD 0V to VDD 1 V/ms *1

Long interval time TIVAL 40 101 162 ms

Continued to the next page.

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,

damage may occur and reliability may be affected.

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended

Operating Ranges limits may affect device reliability.

LC717A10PJ

No.A2214-3/14

Continued from the previous page.

Parameter Symbol Conditions min typ max Unit Remarks

Pin input voltage VIH High input 0.8VDD

V *4

VIL Low input 0.2VDD

Pin output voltage VOH High output

(IOH = +3mA) 0.8VDD

V *5

VOL Low output

(IOL = -3mA) 0.2VDD

VOH V

DD = 5V ±3%, High output

(IOH = +3mA) 0.96VDD

V *1 *5

VOL V

DD = 5V ±3%, Low output

(IOL = -3mA) 0.02VDD

SDA pin output voltage VOL I2C SDA Low output

(IOL = -3mA) 0.4 V

Pin leak current ILEAK ±1 A *6

Current consumption IDD When initial setting and

non-touch

VDD = 2.8V

570 980 A *1

When initial setting and

non-touch

VDD = 5.5V

1.3 2.2 mA *1

Short interval mode ( short

interval time is set to 5ms)

VDD = 5.5V

4.2 6.5 mA

ISTBY During Sleep process 0.1 70 A

*1) Design guarantee values (not tested before shipment)

*2) Measurements conducted using the test mode in the LSI

*3) Ta = +25C

*4) Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS

*5) Apply to Cdrv, SO, INTOUT

*6) Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.

LC717A10PJ

No.A2214-4/14

I2C Compatible Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105C

*Not tested at low temperature before shipment

Parameter Symbol Pin Name Conditions min typ max Unit Remarks

SCL clock frequency fSCL SCL 400 kHz

START condition hold time tHD;STA SCL

SDA

0.6 s

SCL clock low period tLOW SCL 1.3 s

SCL clock high period tHIGH SCL 0.6 s

Repeated START condition

setup time

tSU;STA SCL

SDA

0.6 s *1

Data hold time tHD;DAT SCL

SDA

00.9 s

Data setup time tSU;DAT SCL

SDA

500 ns

100 ns *1

SDA, SCL rise/fall time tr / tf SCL

SDA

300 ns *1

STOP condition setup time tSU;STO SCL

SDA

0.6 s

STOP-to-START bus release

time

tBUF SCL

SDA

2.5 s

1.3 s *1

*1) Design guarantee values (not tested before shipment)

LC717A10PJ

No.A2214-5/14

SPI Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105C

*Not tested at low temperature before shipment

Parameter Symbol Pin Name Conditions min typ max Unit Remarks

SCK clock frequency fSCK SCK 5 MHz

SCK clock Low time tLOW SCK 100 ns

90 ns *1

SCK clock High time tHIGH SCK 100 ns

90 ns *1

Input signal rise/fall time tr / tf nCS

SCK

300 ns *1

nCS setup time tSU;NCS nCS

SCK

200 ns

90 ns *1

SCK clock setup time tSU;SCK nCS

SCK

100 ns

90 ns *1

Data setup time tSU;SI SCK

100 ns

20 ns *1

Data hold time tHD;SI SCK

100 ns

30 ns *1

nCS hold time tHD;NCS nCS

SCK

200 ns

90 ns *1

SCK clock hold time tHD;SCK nCS

SCK

700 ns

90 ns *1

nCS standby pulse width tCPH nCS 300 ns

90 ns *1

Output high impedance time

from nCS

tCHZ nCS

80 ns *1

Output data determination time tv SCK

100 ns

80 ns *1

Output data hold time tHD;SO SCK

100 ns

0 ns *1

Output low impedance time from

SCK clock

tCLZ SCK

100 ns

0 ns *1

*1) Design guarantee values (not tested before shipment)

LC717A10PJ

No.A2214-6/14

Dynamic offset calibration function to correct Cin offset drift

When measurement data at a certain channel are consecutively within the execution range of dynamic offset

calibration (4 to touch threshold, or -128 to -4) for the period of time corresponding to a value, dynamic offset

calibration is performed and the reference value at the channel is gradually corrected to 0.

The figure below shows the operation when the measured value began to drift in the positive

direction from the central value gradually.

The examples of setting to 8 times the dynamic offset calibration carried count.

CinX Threshold

Execution Range of

Dynamic Offset Calibration

(Positive range)

1234567800

= 0x01

Dynamic Offset Calibration

Execution Count Number

(Positive range)

Measurement Time + Long Interval Time [ms]

Dynamic OffCal

Count Plus Register

Measurement Timing

Dynamic Offset

Calibration

Judgment points (They means measurement points where the LC717A10

judges whether to perform dynamic offset calibration

All other measurement points other than the above

Judgment points within the execution range of dynamic offset calibration

LC717A10PJ

No.A2214-7/14

Power-on Reset (POR)

When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset

time, tPOR. Power-on Reset operation condition; Power supply rise rate tVDD must be at least 1V/ms.

Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset, it is possible to

verify the timing of release of power-on reset externally.

During power-on reset, Cin, Cref and CrefAdd are unknown.

fig.1

I2C Compatible Bus Data Timing

fig.2

I2C Compatible Bus Communication Formats

 Write format (data can be written into sequentially incremented addresses)

START Slave Address

Write=L

Data written to Register Address (N)

ACK

Data written to Register Address (N+1)

ACK STOP

Slave Slave Slave Slave

fig.3

 Read format (data can be read from sequentially incremented addresses)

START Slave Address

Write=L

Data read from Register Address (N)

ACK

RESTART

Slave Address

Read=H

ACK

Data read from Register Address (N+1)

ACK

Data read from Register Address (N+2)

NACK

STOP

Slave

Master Master

Master

fig.4

SDA

SCL

START

condition

tHD;STA

tLOW

tHIGH

repeated START

condition

STOP

condition

10%

90%

10% 10%

90% 90%

tHD;DTA tSU;DTA

10% 10%

10%

90%

tSU;STA

90% 90%

tHD;STA

90%

10%

90%

10%

90%

10%

tSU;STO

tBUF

START

condition

90%

POR

(LSI internal signal) RELEASE

tPOR

VDD

RESET

tVDD

INTOUT

VPOROP

Cin,

Cref,

CrefAdd UNKNOWN

VALID

tPOROP

UNKNOWN

UNKNOWN RESET RELEASE

tPOR

VALID

LC717A10PJ

No.A2214-8/14

I2C Compatible Bus Slave Address

Selection of two kinds of addresses is possible through the SA0 and SA1 terminals.

SA1 input SA0 input 7bit slave address Binary notation 8bit slave address

Low Low 0x16 00101100b (Write) 0x2C

00101101b (Read) 0x2D

Low High 0x17 00101110b (Write) 0x2E

00101111b (Read) 0x2F

High Low 0x18 00110000b (Write) 0x30

00110001b (Read) 0x31

High High 0x19 00110010b (Write) 0x32

00110011b (Read) 0x33

SPI Data Timing (SPI Mode 0 / Mode 3)

fig.5

SPI Communication Formats (Example of Mode 0)

 Write format (data can be written into sequentially incremented addresses with preserving nCS = L)

nCS

SCK

76543210

Hi-Z

Data written to Register Address(N) Data written to Register Address(N+1)

Write=L

7654321076543210

fig.6

 Read format (data can be read from sequentially incremented addresses with preserving nCS = L)

Data read from Register Address(N) Data read from Register Address(N+1)

Read=H

76543210

Hi-Z

nCS

SCK

SO 7654321076543210

fig.7

nCS

SCK

tSU;SI

VALID

Hi-Z

tHD;SI

tSU;SCK tSU;NCS tHIGH t

LOW tf

tCPH

tHD;NCS tHD;SCK

tCLZ tHD;SO tCHZ

VALID

LC717A10PJ

No.A2214-9/14

Package Dimensions [LC717A10PJ]

unit : mm

SSOP30 (225 mil)

CASE 565AZ

ISSUE A

SOLDERING FOOTPRINT*

NOTE: The measurements are not to guarantee but for reference only.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

(Unit: mm)

5.80

0.32

1.00

0.50

XXXXX = Specific Device Code

Y = Year

M = Month

DDD = Additional Traceability Data

GENERIC

MARKING DIAGRAM*

*This information is generic. Please refer to

device data sheet for actual part marking.

XXXXXXXXXX

YMDDD

LC717A10PJ

No.A2214-10/14

Pin Assignment

Pin No. Pin Name Pin No. Pin Name

1 VDD 16 Cref

2 VSS 17 CrefAdd

3 Non Connect *1 18 Cdrv

4 Cin4 19 INTOUT

5 Cin5 20 SA1

6 Cin6 21 SCL/SCK

7 Cin7 22 SDA/SI

8 Cin8 23 SA0/SO

9 Cin9 24 nCS

10 Cin10 25 nRST

11 Cin11 26 Non Connect *1

12 Cin12 27 Cin0

13 Cin13 28 Cin1

14 Cin14 29 Cin2

15 Cin15 30 Cin3

*1) connect to GND when mounted

Block Diagram

Cin0

VDD

VSS

INTOUT

Cin1

Cin2

Cin3

Cin4

Cin5

Cin6

Cin7

Cin8

Cin9

Cin10

Cin11

Cin12

Cin13

Cin14

Cin15

Cref

CrefAdd

Cdrv

nRST

nCS

SCL/SCK

SDA/SI

SA0/SO

SA1

MUX

1st

AMP

A/D

CONVERTER

2nd

AMP

CONTROL

LOGIC

C/SPI

POR OSCILLATOR

LC717A10PJ is capacitance-digital-converter LSI capable of detecting changes in capacitance in the order of femto

Farads. It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system

when the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects the changes in

the capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into

digital data, an I2C compatible bus or a SPI that enables serial communication with external devices and a control logic

that controls the entire chip.

LC717A10PJ

No.A2214-11/14

Pin Functions

Pin Name I/O Pin Functions Pin Type

Cin0 I/O Capacitance sensor input

AMP

VDD

VSS Buffer

Cin1 I/O Capacitance sensor input

Cin2 I/O Capacitance sensor input

Cin3 I/O Capacitance sensor input

Cin4 I/O Capacitance sensor input

Cin5 I/O Capacitance sensor input

Cin6 I/O Capacitance sensor input

Cin7 I/O Capacitance sensor input

Cin8 I/O Capacitance sensor input

Cin9 I/O Capacitance sensor input

Cin10 I/O Capacitance sensor input

Cin11 I/O Capacitance sensor input

Cin12 I/O Capacitance sensor input

Cin13 I/O Capacitance sensor input

Cin14 I/O Capacitance sensor input

Cin15 I/O Capacitance sensor input

Cref I/O Reference capacitance input

CrefAdd I/O Reference capacitance input for addition

Cdrv O Output for capacitance sensors drive

VDD

VSS

Buffer

INTOUT O Interrupt output

SCL/SCK I Clock input (I2C)

/ Clock input (SPI)

VDD

VSS

nCS I Interface selection

/ Chip select inverting input (SPI)

nRST I External reset signal inverting input

SA1 I Slave address selection (I2C)

SDA/SI I/O Data input and output (I2C)

/ Data input (SPI)

VDD

VSS

Continued to the next page.

LC717A10PJ

No.A2214-12/14

Continued from the previous page.

Pin Name I/O Pin Functions Pin Type

SA0/SO I/O Slave address selection (I2C)

/ Data output (SPI)

VDD

VSS

Buffer

VDD Power supply (2.6V to 5.5V) *1

VSS Ground (Earth) *1 *2

*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.

In this case, the small-valued capacitor should be at least 0.1F, and is mounted near the LSI.

*2) When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.

Details of Pin Functions

●Cin0 to Cin15

These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern.

Cin and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively

coupled. Therefore, LSI can detect capacitance change near each pattern as 8bit digital data.

However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able to

detect the capacitance change correctly.

In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude

values. Cin0 to Cin15 are connected to the inverting input of the 1st amplifier.

During measurement process, channels other than the one being measured are all in “Low” condition.

Leave the unused terminals open.

●Cref, CrefAdd

These are the reference-capacitance-input pins. These are used by connecting to the wire pattern like Cin pins or are

used by connecting any capacitance between this pin and Cdrv pin.

In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude

values. Cref is connected to the non-inverting input of the 1st amplifier.

Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one

generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin

accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change

accurately.

However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect

capacitance change of each Cin pin correctly.

CrefAdd can be used as additional terminal for Cref. Leave the CrefAdd open if not in used.

●Cdrv

It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at

Cin0 to Cin15.

Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.

●INTOUT

It is the interrupt-output pin.

It is used by connecting to a main microcomputer if necessary, and use as interrupt signal. (High Active)

Leave the terminal open if not in used.

●SCL/SCK

Clock input (I2C) / Clock input (SPI)

It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation.

LC717A10PJ

No.A2214-13/14

●nCS

Interface selection / Chip-select-inverting input (SPI)

Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is automatically

in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To switch to SPI mode

after LSI initialization, change the nCS input “High”  “Low”. The nCS pin is used as the chip-select-inverting input

pin of SPI, and SPI mode is kept until LSI is again initialized.

●nRST

It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in reset state.

Each pin (Cin0 to 15, Cref, CrefAdd) is “Hi-Z” during reset state.

●SDA/SI

Data input and output (I2C) / Data input (SPI)

It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of

operation.

●SA0/SO

Slave address selection (I2C) / Data output (SPI)

It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode of

operation.

●SA1

Slave address selection (I2C)

It is the slave address selection pin of the I2C compatible bus.

When SPI mode, connect to the SA1 pin to GND.

LC717A10PJ

PS No.A2214-14/14

ORDERING INFORMATION

Device Package Shipping (Qty / Packing)

LC717A10PJ-AH SSOP30(225mil)

(Pb-Free / Harogen Free) 1000 / Tape & Reel

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