CMOS Latched
8-/16-Channel Analog Multiplexers
ADG526A/ADG527A
Rev. C
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FEATURES
44 V supply maximum rating
VSS to VDD analog signal range
Single- or dual-supply specifications
Wide supply ranges (10.8 V to 16.5 V)
Microprocessor compatible (100 ns WR pulse)
Extended plastic temperature range (−40°C to +85°C)
Low leakage (20 pA typical)
Low power dissipation (28 mW maximum)
Available in PDIP, CERDIP, SOIC, and PLCC packages
Superior alternative to DG526 and DG527
APPLICATIONS
Data acquisition systems
Communication systems
Automatic test equipment
Microprocessor controlled systems
GENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 single channels and dual 8 channels,
respectively. On-chip latches facilitate microprocessor interfacing.
The ADG526A switches one of 16 inputs to a common output,
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs to
a common differential output, depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic-compatible digital inputs.
The ADG526A and ADG527A are designed on an enhanced
LC2MOS process that gives an increased signal capability of VSS
to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single- or dual-supply range. These multiplexers
also feature high switching speeds and low RON.
FUNCTIONAL BLOCK DIAGRAMS
A0 A1 A2 A3 EN RS
DECODER/
LATCHES
WR
D
S16
S1
ADG526A
01532-001
Figure 1. ADG526A
A0 A1 A2 EN RS
DECODER/
LATCHES
WR
DA
S
8
A
S
1
A
DB
S
8B
S
1B
ADG527A
01532-002
Figure 2. ADG527A
PRODUCT HIGHLIGHTS
1. Single- or Dual-Supply Specifications with a Wide
Tolerance. The devices are specified in the 10.8 V to
16.5 V range for both single and dual supplies.
2. Easily Interfaced. The ADG526A and ADG527A can be
easily interfaced with microprocessors. The WR signal
latches the state of the address control lines and the enable
line. The RS signal clears both the address and enable data
in the latches, resulting in no output (all switches off). RS
can be tied to the microprocessor reset pin.
3. Extended Signal Range. The enhanced LC2MOS
processing results in a high breakdown and an increased
analog signal range from VSS to VDD.
4. Break-Before-Make Switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
5. Low Leakage. Leakage currents in the range of 20 pA
make these multiplexers suitable for high precision circuits.
ADG526A/ADG527A
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 12
Timing .............................................................................................. 13
Test Circuits ..................................................................................... 14
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/08—Rev. B to Rev. C.
Updated Format .................................................................. Universal
ADG526A LCCC Package Removed ............................... Universal
Changes to Features .......................................................................... 1
Added Applications Section ............................................................ 1
Changes to Absolute Maximum Ratings ....................................... 7
Added Table 4, Renumbered Sequentially .................................... 8
Added Table 5 .................................................................................... 9
Changes to Figure 7 and Figure 8 ................................................. 11
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 19
2/02—Rev. A to Rev. B.
Edits to Specifications Table, Dual Supply ..................................... 2
Edits to Specifications Table, Single Supply ................................... 3
Edits to Ordering Guide ................................................................... 4
Removal of one Pin Configuration and Diagram ......................... 6
ADG526A/ADG527A
Rev. C | Page 3 of 20
SPECIFICATIONS
DUAL SUPPLY
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted.
Table 1.
Parameter
ADG526A/ADG527A ADG526A
Unit Comments
K Version B Version T Version
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
ANALOG SWITCH
Analog Signal Range VSS VSS VSS VSS VSS VSS V min
V
DD VDD VDD VDD VDD VDD V max
RON 280 280 280 Ω typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA;
see Figure 15
450 600 450 600 450 600 Ω max
300 400 300 400 Ω max VDD = +15 V (±10%),
VSS = −15 V (±10%)
300 400 Ω max VDD = +15 V (±5%),
VSS = −15 V (±5%)
RON Drift 0.6 0.6 0.6 %/°C typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA
RON Match 5 5 5 % typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA
IS (Off), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = 10 V;
see Figure 16
1 50 1 50 1 50 nA max
ID (Off), Off Output
Leakage
0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V;
see Figure 17
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
ID (On), On Channel
Leakage
0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V;
see Figure 18
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
IDIFF, Differential Off
Output Leakage
25 25 nA max V1 = ±10 V, V2 = 10 V;
see Figure 19
(ADG527A Only)
DIGITAL CONTROL
VINH, Input High Voltage 2.4 2.4 2.4 V min
VINL, Input Low Voltage 0.8 0.8 0.8 V max
IINL or IINH 1 1 1 μA max VIN = 0 to VDD
CIN, Digital Input
Capacitance
8 8 8 pF max
DYNAMIC
CHARACTERISTICS1
tTRANSITION 200 200 200 ns typ V1 = ±10 V, V2 = 10 V;
see Figure 20
300 400 300 400 300 400 ns max
tOPEN 50 50 50 ns typ See Figure 21
25 10 25 10 25 10 ns min
tON (EN, WR) 200 200 200 ns typ See Figure 22 and Figure 23
300 400 300 400 300 400 ns max
tOFF (EN, RS) 200 200 200 ns typ See Figure 22 and Figure 24
300 400 300 400 300 400 ns max
tW , Write Pulse Width 100 120 100 120 100 130 ns min See Figure 13
tS, Address Enable Setup
Time
100 100 100 ns min See Figure 13
tH, Address Enable Hold
Time
10 10 10 ns min See Figure 13
tRS, Reset Pulse Width 100 100 100 ns min See Figure 14
ADG526A/ADG527A
Rev. C | Page 4 of 20
Parameter
ADG526A/ADG527A ADG526A
Unit Comments
K Version B Version T Version
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
Off Isolation 68 68 68 dB typ VEN = 0.8 V, RL = 1 kΩ, CL =
15 pF,VS = 7 V rms, f = 100 kHz
50 50 50 dB min VS = 7 V rms, f = 100 kHz
CS (Off) 5 5 5 pF typ VEN = 0.8 V
CD (Off)
ADG526A 44 44 44 pF typ VEN = 0.8 V
ADG527A 22 22 pF typ
QINJ, Charge Injection 4 4 4 pC typ RS = 0 Ω, VS = 0 V;
see Figure 25
POWER SUPPLY
IDD 0.6 0.6 0.6 mA typ VIN = VINL or VINH
1.5 1.5 1.5 mA max
ISS 20 20 20 μA typ VIN = VINL or VINH
0.2 0.2 0.2 mA max
Power Dissipation 10 10 10 mW typ
28 28 28 mW max
1 Sample tested at 25°C to ensure compliance.
ADG526A/ADG527A
Rev. C | Page 5 of 20
SINGLE SUPPLY
VDD = 10.8 V to 16.5 V, VSS = GND to 0 V, unless otherwise noted.
Table 2.
Parameter
ADG526A/ADG527A ADG526A
Unit Comments
K Version B Version T Version
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
ANALOG SWITCH
Analog Signal Range VSS VSS VSS VSS VSS VSS V min
V
DD VDD VDD VDD VDD VDD V max
RON 500 500 500 Ω typ 0 V ≤ VS ≤ 10 V, IDS =
0.5 mA; see Figure 15
700 1000 700 1000 700 1000 Ω max
RON Drift 0.6 0.6 0.6 %/°C typ 0 V ≤ VS ≤ 10 V, IDS =
0.5 mA
RON Match 5 5 5 % typ 0 V ≤ VS ≤ 10 V, IDS =
0.5 mA
IS (Off), Off Input
Leakage
0.02 0.02 0.02 nA typ V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 16
1 50 1 50 1 50 nA max
ID (Off), Off Output
Leakage
0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 17
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
ID (On), On Channel
Leakage
0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 18
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
IDIFF, Differential Off
Output Leakage
(ADG527A Only)
25 25 nA max V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 19
DIGITAL CONTROL
VINH, Input High Voltage 2.4 2.4 2.4 V min
VINL, Input Low Voltage 0.8 0.8 0.8 V max
IINL or IINH 1 1 1 μA max VIN = 0 to VDD
CIN, Digital Input
Capacitance
8 8 8 pF max
DYNAMIC
CHARACTERISTICS1
tTRANSITION 300 300 300 ns typ V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 20
450 600 450 600 450 600 ns max
tOPEN 50 50 50 ns typ See Figure 21
25 10 25 10 25 10 ns min
tON (EN, WR) 250 250 250 ns typ See Figure 22 and Figure 23
450 600 450 600 450 600 ns max
tOFF (EN, RS) 250 250 250 ns typ See Figure 22 and Figure 24
450 600 450 600 450 600 ns max
tW Write Pulse Width 100 120 100 120 100 130 ns min See Figure 13
tS Address Enable
Setup Time
100 100 100 ns min See Figure 13
tH Address Enable Hold
Time
10 10 10 ns min See Figure 13
tRS Reset Pulse Width 100 100 100 ns min See Figure 14
Off Isolation 68 68 68 dB typ VEN = 0.8 V, RL = 1 kΩ, CL =
15 pF
50 50 50 dB min VS = 3.5 V rms, f = 100 kHz
ADG526A/ADG527A
Rev. C | Page 6 of 20
Parameter
ADG526A/ADG527A ADG526A
Unit Comments
K Version B Version T Version
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
CS (Off) 5 5 5 pF typ VEN = 0.8 V
CD (Off)
ADG526A 44 44 44 pF typ VEN = 0.8 V
ADG527A 22 22 pF typ
QINJ, Charge Injection 4 4 4 pC typ RS = 0 Ω, VS = 0 V; see
Figure 25
POWER SUPPLY
IDD 0.6 0.6 0.6 mA typ VIN = VINL or VINH
1.5 1.5 1.5 mA max
Power Dissipation 11 11 11 mW typ
25 25 25 mW max
1 Sample tested at 25°C to ensure compliance.
ADG526A/ADG527A
Rev. C | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 44 V
VDD to GND 25 V
VSS to GND −25 V
Analog Inputs1
Voltage at Sx or Dx Pins VSS − 2 V to VDD + 2 V
or 20 mA, whichever
occurs first
Continuous Current, Sx or Dx Pins 20 mA
Pulsed Current, Sx or Dx Pins
1 ms Duration, 10% Duty Cycle 40 mA
Digital Inputs1
Voltage at A, EN, WR, RS VSS − 4 V to VDD + 4 V
or 20 mA, whichever
occurs first
Power Dissipation (Any Package)
Up to 75°C 470 mW
Derates Above 75°C 6 mW/°C
Operating Temperature Range
Commercial (K Version) −40°C to +85°C
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
1 Overvoltage at A, EN, WR, RS, Sx, or Dx pins are clamped by diodes. Limit
current to the maximum rating in . Table 3
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG526A/ADG527A
Rev. C | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD 1
NC
2
RS
3
S16
4
D
28
V
SS
27
S8
26
S7
25
S15
5
S6
24
S14
6
S5
23
S13
7
S4
22
S12
8
S3
21
S11
9
S2
20
S10
10
S1
19
S9
11
EN
18
GND
12
A0
17
WR
13
A1
16
A3
14
A2
15
NC = NO CONNECT
ADG526A
TOP VIEW
(No t t o Scale)
0
1532-005
Figure 3. ADG526A PDIP, SOIC, and CERDIP Pin Configuration
1282726234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
S15
S14
S13
S12
S11
S10
S09
S7
S6
S5
S4
S3
S2
S1
S16
RS
NC
V
DD
D
V
SS
S8
GND
WR
A3
A2
A1
A0
EN
PIN 1
IDENTFIER
12 13 14 15 16 17 18
ADG526A
TOP VIEW
(No t to Scale )
0
1532-007
Figure 4. ADG526A PLCC Pin Configuration
Table 4. ADG526A Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 NC No Connect.
3 RS Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off).
4 S16 Source Terminal. This pin can be an input or output.
5 S15 Source Terminal. This pin can be an input or output.
6 S14 Source Terminal. This pin can be an input or output.
7 S13 Source Terminal. This pin can be an input or output.
8 S12 Source Terminal. This pin can be an input or output.
9 S11 Source Terminal. This pin can be an input or output.
10 S10 Source Terminal. This pin can be an input or output.
11 S9 Source Terminal. This pin can be an input or output.
12 GND Ground (0 V) Reference.
13 WR Write. The WR signal latches the state of the address control lines and the enable line.
14 A3 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
15 A2 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
16 A1 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
17 A0 Logic control inputs. Selects which source terminal is connected to the drain (D).
18 EN Enable. Active high logic control input.
19 S1 Source Terminal. This pin can be an input or output.
20 S2 Source Terminal. This pin can be an input or output.
21 S3 Source Terminal. This pin can be an input or output.
22 S4 Source Terminal. This pin can be an input or output.
23 S5 Source Terminal. This pin can be an input or output.
24 S6 Source Terminal. This pin can be an input or output.
25 S7 Source Terminal. This pin can be an input or output.
26 S8 Source Terminal. This pin can be an input or output.
27 VSS Most Negative Power Supply Potential.
28 D Drain Terminal. This pin can be an input or output.
ADG526A/ADG527A
Rev. C | Page 9 of 20
DA
V
SS
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
EN
A0
A1
A2
V
DD
DB
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
RS
WR
1
2
3
4
28
27
26
25
5
6
7
24
23
22
821
920
10 19
11 18
12 17
13 16
14 15
NC = NO CONNECT
ADG527A
TO P VIEW
(Not to Scale)
01532-006
Figure 5. ADG527A PDIP, SOIC Pin Configuration
1282726234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CO NNE CT
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S7A
S6A
S5A
S4A
S3A
S2A
S1A
S8B
RS
DB
V
DD
DA
V
SS
S8A
GND
WR
NC
A2
A1
A0
EN
PIN 1
IDENTFIER
12 13 14 15 16 17 18
ADG527A
TOP VIEW
(No t t o S cale)
01532-008
Figure 6. ADG527A PLCC Pin Configuration
Table 5. ADG527A Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 DB Drain Terminal. This pin can be an input or output.
3 RS Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off).
4 S8B Source Terminal. This pin can be an input or output.
5 S7B Source Terminal. This pin can be an input or output.
6 S6B Source Terminal. This pin can be an input or output.
7 S5B Source Terminal. This pin can be an input or output.
8 S4B Source Terminal. This pin can be an input or output.
9 S3B Source Terminal. This pin can be an input or output.
10 S2B Source Terminal. This pin can be an input or output.
11 S1B Source Terminal. This pin can be an input or output.
12 GND Ground (0 V) Reference.
13 WR Write. The WR signal latches the state of the address control lines and the enable line.
14 NC No Connect.
15 A2 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
16 A1 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
17 A0 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
18 EN Enable. Active high logic control input.
19 S1A Source Terminal. This pin can be an input or output.
20 S2A Source Terminal. This pin can be an input or output.
21 S3A Source Terminal. This pin can be an input or output.
22 S4A Source Terminal. This pin can be an input or output.
23 S5A Source Terminal. This pin can be an input or output.
24 S6A Source Terminal. This pin can be an input or output.
25 S7A Source Terminal. This pin can be an input or output.
26 S8A Source Terminal. This pin can be an input or output.
27 VSS Most Negative Power Supply Potential.
28 DA Drain Terminal. This pin can be an input or output.
ADG526A/ADG527A
Rev. C | Page 10 of 20
Table 6. ADG526A Truth Table1
A3 A2 A1 A0 EN WR RS ON SWITCH
X X X X X 1 Retains previous switch condition
X X X X X X 0 None (address and enable latches cleared)
X X X X 0 0 1 None
0 0 0 0 1 0 1 1
0 0 0 1 1 0 1 2
0 0 1 0 1 0 1 3
0 0 1 1 1 0 1 4
0 1 0 0 1 0 1 5
0 1 0 1 1 0 1 6
0 1 1 0 1 0 1 7
0 1 1 1 1 0 1 8
1 0 0 0 1 0 1 9
1 0 0 1 1 0 1 10
1 0 1 0 1 0 1 11
1 0 1 1 1 0 1 12
1 1 0 0 1 0 1 13
1 1 0 1 1 0 1 14
1 1 1 0 1 0 1 15
1 1 1 1 1 0 1 16
1 X = don’t care.
Table 7. ADG527A Truth Table1
A2 A1 A0 EN WR RS ON SWITCH PAIR
X X X X 1 Retains previous switch condition
X X X X X 0 None (address and enable latches cleared)
X X X 0 0 1 None
0 0 0 1 0 1 1
0 0 1 1 0 1 2
0 1 0 1 0 1 3
0 1 1 1 0 1 4
1 0 0 1 0 1 5
1 0 1 1 0 1 6
1 1 0 1 0 1 7
1 1 1 1 0 1 8
1 X = don’t care.
ADG526A/ADG527A
Rev. C | Page 11 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
700
0
100
200
300
400
500
600
–20 –15 –10 –5 0 5 10 15 20
R
ON
(Ω)
V
D
(V
S
) (V)
V
DD
= 10.8V
V
SS
= 0V
V
DD
= 15V
V
SS
= 0V
01532-009
Figure 7. RON as a Function of VD (VS): Single-Supply Voltage, TA = 25°C
700
0
100
200
300
400
500
600
–20 –15 –10 –5 0 5 10 15 20
R
ON
(Ω)
V
D
(V
S
) (V)
V
DD
= +5V
V
SS
= –5V
V
DD
= +10.8V
V
SS
= –10.8V
V
DD
= +15V
V
SS
= –15V
01532-010
Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C
100
10
1
0.1
0.01
25 35 45 55 65 75 85 95 105 115 125
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
ID (ON)
ID (OFF)
VDD = +16.5V
VSS = –16.5V
IS (OFF)
01532-011
Figure 9. Leakage Current as a Function of Temperature (Leakage Currents
Reduce as the Supply Voltages Reduce)
1.9
1.8
1.7
1.6
1.5
56789101112131415
TRIGGER LEVEL (V)
SUPPLY VOLTAGE (V)
01532-012
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply,
TA = 25°C
800
100
200
300
400
500
600
700
56789101112131415
t
TRANSITION
(ns)
SUPPLY VOLTAGE (V)
SINGLE
SUPPLY
DUAL
SUPPLY
01532-013
Figure 11. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25°C
(Note: For VDD and VSS <10 V; V1 = VDD/VSS, V2 = VSS/VDD; See Figure 20)
1.0
0.8
0.6
0.4
0.2
0
5678910111213 15 1714 16
IDD (mA)
SUPPLY VOLTAGE (V)
01532-014
Figure 12. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25°C
ADG526A/ADG527A
Rev. C | Page 12 of 20
TERMINOLOGY
RON
Ohmic resistance between Terminal D and Terminal S.
RON Match
Difference between the RON of any two channels.
RON Drift
Change in RON vs. temperature.
IS (Off)
Source terminal leakage current when the switch is off.
ID (Off)
Drain terminal leakage current when the switch is off.
ID (On)
Leakage current that flows from the closed switch into the body.
VS (VD)
Analog voltage on Terminal S or Terminal D.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 10% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and switch on condition when switching from one
address state to another.
tOPEN
Off time measured between 50% points of both switches when
switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
VDD
Most positive voltage supply.
VSS
Most negative voltage supply.
IDD
Positive supply current.
ISS
Negative supply current.
ADG526A/ADG527A
Rev. C | Page 13 of 20
TIMING
Figure 13 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
3
V
0V
3V
0V
WR
EN, A0, A1,
A2, (A3)
1.5V
2.0V
0.8V
t
W
t
S
t
H
01532-003
Figure 13. Timing Sequence
Figure 14 shows the reset pulse width, tRS, and reset turn-off
time, tOFF (RS).
Note that all digital input signal rise and fall times are measured
from 10% to 90% of 3 V, tR = tF = 20 ns.
t
RS
t
OFF
(RS)
3
V
0V
V
O
0V
RS
0.8V
1.5V
SWITCH
O
UTPUT
01532-004
Figure 14. Reset Pulse
ADG526A/ADG527A
Rev. C | Page 14 of 20
TEST CIRCUITS
SD
V
S
I
DS
V1
R
ON
= V1
I
DS
0
1532-015
Figure 15. RON
A
V2V1
IS (OFF) D
EN
GND
VDD VSS
VDD VSS
0.8V
01532-016
Figure 16. IS (Off)
V
DD
V
SS
V
DD
V
SS
D
A
EN
GND
0.8V
V2
V
1
I
D
(OFF)
01532-017
Figure 17. ID (Off)
V
DD
V
SS
VDD VSS
V1
D
A
EN
GND
2.4V
V2
ID (ON)
01532-018
Figure 18. ID (On)
IDIFF = IDA (OFF) – IDB (OFF)
V
DD
V
SS
VDD VSS
DA A
GND
V
1
EN
V2
ADG527A
DB A
0.8V
01532-019
Figure 19. IDIFF
ADG526A/ADG527A
Rev. C | Page 15 of 20
3
V
0
V
ADDRESS
DRIVE (V
IN
)
OUTPUT
90%
90%
50%
t
TRANSITION
t
TRANSITION
*SIMILAR CONNECTION FOR ADG527A.
50Ω
V1
OUTPUT
ADG526A*
A2
A1
A0
2.4V EN
GND
S1
S2 TO S15
S16
D
1MΩ35pF
A3
V2
WR
RS
V
IN
V
DD
V
SS
V
DD
V
SS
01532-020
Figure 20. Switching Time of Multiplexer, tTRANSITION
*SIMILAR CONNECTION FOR ADG527A.
50Ω
5V
OUTPUT
ADG526A*
A2
A1
A0
2.4V EN
GND
S1
S2 TO S15
S16
D
1kΩ35pF
A3
WR
RS
V
IN
V
DD
V
SS
V
DD
V
SS
3V
0V
ADDRESS
DRIVE (V
IN
)
OUTPUT
50%
t
OPEN
0
1532-021
Figure 21. Break-Before-Make Delay, tOPEN
*SIMILAR CONNECTION FOR ADG527A.
5V
OUTPUT
ADG526A*
A2
A1
A0
2.4V
EN
GND
S1
S2 TO S16
D
1kΩ35pF
A3
WR
50Ω
V
IN
V
DD
V
SS
V
DD
V
SS
RS
3
V
0
V
ENABLE
DRIVE (V
IN
)
OUTPUT
10%
90%
50%
t
ON
(EN)
t
OFF
(EN)
01532-022
Figure 22. Enable Delay, tON (EN) tOFF (EN)
ADG526A/ADG527A
Rev. C | Page 16 of 20
*SIMILAR CONNECTION FOR ADG527A.
5V
OUTPUT
ADG526A*
A2
A1
A0
2.4V
GND
S1
S2 TO S16
D
1kΩ35pF
A3
50Ω
V
IN
V
DD
V
SS
V
DD
V
SS
EN
WR
RS
OUTPUT
20%
50%
3V
0V
(WR)
DRIVE (V
IN
)
NOTE:
DEVICE MUST BE RESET PRIOR TO APPLYING WR PULSE.
t
ON
(WR)
01532-023
Figure 23. Write Turn-On Time, tON (WR)
*SIMILAR CONNECTION FOR ADG527A.
5V
OUTPUT
ADG526A*
A2
A1
A0
2.4V
GND
S1
S2 TO S16
D
1kΩ35pF
A3
50Ω
V
IN
V
DD
V
SS
V
DD
V
SS
EN
RS
WR
NOTE:
DEVICE WR MUST PULSE LOW PRIOR TO APPLYING RS PULSE.
80%
OUTPUT
50%
3V
0V
RS DRIVE (V
IN
)
t
OFF
(RS)
01532-024
Figure 24. Reset Turn-Off, tOFF (RS)
*SIMILAR CONNECTION FOR ADG527A.
2.4V
ADG526A*
A2
A1
A0
S1
GND
RS
D
A3
50Ω
V
IN
V
DD
V
SS
V
DD
V
SS
EN
WR
3V
V
IN
0V
V
O
Q
INJ
= C
L
× ΔV
O
ΔV
O
V
O
C
L
1nF
R
S
V
S
01532-025
Figure 25. Charge Injection
ADG526A/ADG527A
Rev. C | Page 17 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
28
114
15
0.610 (15.49)
0.500 (12.70)
0.005 (0.13)
MIN
0.100 (2.54)
MAX
0.620 (15.75)
0.590 (14.99)
0.018 (0.46)
0.008 (0.20)
SEATING
PLANE
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
MIN
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15°
0°
PIN 1
030106-A
Figure 26. 28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
COMPLIANT TO JEDEC STANDARDS MS-0 11
071006-A
0.100 (2.54)
BSC
1.565 (39.75)
1.380 (35.05)
0.580 (14.73)
0.485 (12.31)
0.022 (0.56)
0.014 (0.36)
0.200 (5.08)
0.115 (2.92)
0.070 (1.78)
0.050 (1.27)
0.250 (6.35)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
0.625 (15.88)
0.600 (15.24)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.125 (3.17)
28
114
15
Figure 27. 28-Lead Plastic Dual In-Line Package [PDIP]
(N-28)
Dimensions shown in inches and (millimeters)
ADG526A/ADG527A
Rev. C | Page 18 of 20
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
4
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
SQ
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.495 (12.57)
0.485 (12.32) SQ
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.120 (3.04)
0.090 (2.29)
0.056 (1.42)
0.042 (1.07) 0.020 (0.51)
MIN
0.180 (4.57)
0.165 (4.19)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
042508-A
Figure 28. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28A)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AE
18.10 (0.7126)
17.70 (0.6969)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
28 15
14
1
1.27 (0.0500)
BSC
060706-A
Figure 29. 28-Lead Standard Small Outline Package [SOIC] Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
ADG526A/ADG527A
Rev. C | Page 19 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG526AKN −40°C to +85°C 28-Lead PDIP N-28
ADG526AKNZ1−40°C to +85°C 28-Lead PDIP N-28
ADG526AKR −40°C to +85°C 28-Lead SOIC RW-28
ADG526AKR-REEL −40°C to +85°C 28-Lead SOIC RW-28
ADG526AKRZ1 −40°C to +85°C 28-Lead SOIC RW-28
ADG526AKRZ-REEL1
−40°C to +85°C 28-Lead SOIC RW-28
ADG526AKP −40°C to +85°C 28-Lead PLCC P-28A
ADG526AKP-REEL −40°C to +85°C 28-Lead PLCC P-28A
ADG526AKPZ1 −40°C to +85°C 28-Lead PLCC P-28A
ADG526AKPZ-REEL1 −40°C to +85°C 28-Lead PLCC P-28A
ADG526ATQ −55°C to +125°C 28-Lead CERDIP Q-28
ADG526ABQ −40°C to +85°C 28-Lead CERDIP Q-28
ADG526ATCHIPS DIE
ADG527AKN −40°C to +85°C 28-Lead PDIP N-28
ADG527AKNZ1
−40°C to +85°C 28-Lead PDIP N-28
ADG527AKR −40°C to +85°C 28-Lead SOIC RW-28
ADG527AKR-REEL −40°C to +85°C 28-Lead SOIC RW-28
ADG527AKRZ1
−40°C to +85°C 28-Lead SOIC RW-28
ADG527AKP −40°C to +85°C 28-Lead PLCC P-28A
ADG527AKPZ1
−40°C to +85°C 28-Lead PLCC P-28A
1 Z = RoHS Compliant Part, # denotes RoHS complaint product, may be top or bottom marked.
ADG526A/ADG527A
Rev. C | Page 20 of 20
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01532-0-6/08(C)
