MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by MC100EP221/D DATA SHEET Low-Voltage 1:20 Differential Low-Voltage 1:20 Differential ECL/PECL ClockClock Driver Driver ECL/PECL Freescale Semiconductor, Inc... The MC100EP221 is a low skew 1-to-20 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The input signals can be either differential or single-ended if the VBB output is used. The selected signal is fanned out to 20 identical differential outputs. * * * * * * * MC100EP221 MC100EP221 LOW-VOLTAGE 1:20 DIFFERENTIAL ECL/PECL CLOCK DRIVER 270ps max. Part-to-Part Skew 50ps max. Output-to-Output Skew Differential Design VBB Output Voltage and Temperature Compensated Outputs Supports 3.3V and 2.5V, ECL and PECL Operation Supports HSTL and PECL Clock Systems The EP221 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate- to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew TB SUFFIX device. 52-LEAD LQFP PACKAGE EXPOSED PAD To ensure that the tight skew specification is met it is necessary that CASE 1336 both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all ten differential pairs will be used and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The MC100EP221, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the EP221 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the EP221's performance to distribute low skew clocks across the backplane. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. 08/01 IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock For Driver More Information On This Product, REV 1 1 Motorola, Inc. 2001 Go by to:Integrated www.freescale.com Freescale Timing Solutions Organization has been acquired Device Technology, Inc 1 MC100EP221 MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. MC100EP221 NETCOM VCCO 40 Q5 VCCO Q11 Q11 Q10 Q10 Q9 Q9 Q8 Q8 Q7 Q7 Q6 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Q12 41 25 Q12 Q5 42 24 Q13 Q4 43 23 Q13 Q4 44 22 Q14 Q3 45 21 Q14 Q3 46 20 Q15 Q2 47 19 Q15 Q2 48 18 Q16 Q1 49 17 Q16 Q1 50 16 Q17 Q0 51 15 Q17 Q0 52 14 VCCO 7 8 CLK0 CLK0 VBB CLK1 CLK1 9 10 11 12 13 Q18 6 Q18 5 Q19 4 Q19 3 VEE 2 CLKSEL 1 VCC MC100EP211 VCCO Freescale Semiconductor, Inc... Q6 Pinout: 52-Lead LQFP (Top View) FUNCTION CLK_SEL Active Input 0 1 CLK0, CLK0 CLK1, CLK1 LOGIC SYMBOL CLK0 W 65 k VEE VCC 65 k W CLK0 0 W 65 k VEE CLK1 Q0 16 W 65 k CLK1 Q0 VEE VCC 65 k W Q1:18 1 W 65 k VEE CLK_SEL Q1:18 Q19 Q19 W 65 k VEE IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc MOTOROLA 2 Go to: www.freescale.com 2 MC100EP221 TIMING SOLUTIONS MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. NETCOM MC100EP221 Table 1: PIN CONFIGURATION Pin Type Function CLK0, CLK0 Input ECL/LVPECL Differential reference clock signal input CLK1, CLK1 Input ECL/LVPECL or HSTL Alternative differential reference clock signal input CLK_SEL Input LVPECL Output frequency divider select Q[0-19], Q[0-19] Output LVPECL Differential clock outputs VEEa Supply Negative power supply VCC, VCCO Supply Positive power supply. All VCC and VCCO pins must be connected to the positive power supply for correct DC and AC operation VBB Output DC bias output for single ended input operation a. Freescale Semiconductor, Inc... I/O In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referrenced to the most positive supply (VCC). Table 2: ABSOLUTE MAXIMUM RATINGSa Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 4.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V 20 mA 50 mA 125 C VOUT IIN IOUT TS DC Input Current DC Output Current Storage temperature -65 Condition a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3: GENERAL SPECIFICATIONS Symbol Characteristics VTT Output termination voltage Typ VCC - 2a Max Unit MM ESD Protection (Machine model) 75 V ESD Protection (Human body model) 1500 V CDM ESD Protection (Charged device model) 500 V Latch-up immunity 200 mA CIN JA 4.0 Thermal resistance junction to ambient Condition V HBM LU a. b. Min pF Inputs See application informationb JC Thermal resistance junction to case See application information Output termination voltage VTT = 0V for VCC=2.5V operation is supported but the power consumption of the device will increase. Proper thermal management is critical for reliable system operation. This especially true for high-fanout and high drive capability products. Thermal package information and exposed pad land pattern design recommendations are available in the applications section of this datasheet. In addition, the means of calculating die power consumption, the corresponding die temperature and the relationsship to long-term reliability is addressed in the Motorola application note AN1545. Thermal modeling is recommended for the MC100EP221. IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc TIMING SOLUTIONS 3 Go to: www.freescale.com 3 MC100EP221 MOTOROLA MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. NETCOM MC100EP221 Table 4: PECL and HSTL DC Characteristics (VCCO = VCC = 2.375V to 3.8V, VEE = GND) Symbol TA = -40C Min Max Characteristics TA = 25C Min Max TA = 85C Min Max Unit Condition Clock input pair CLK0, CLK0, CLK1, CLK1a (LVPECL differential signals) VPP VCMR Differential input voltageb VCC=3.3V VCC=2.5V 0.10 0.15 Differential cross point voltagec CLK0 CLK1 1.0 0.1 0.10 0.15 VCC-0.4 VCC-1.0 0.10 0.15 V V 1.0 0.1 VCC-0.4 VCC-1.0 1.0 0.1 VCC-0.4 VCC-1.0 V V Clock input pair CLK1, CLK1d (HSTL differential signals) Freescale Semiconductor, Inc... VDIF VX VIH VIL Differential input voltagee VCC=3.3V VCC=2.5V Differential cross point voltagef Input high voltage Input low voltage 0.4 0.4 1.0 1.0 0.4 0.4 1.0 1.0 0.4 0.4 1.0 1.0 V V 0.68 0.9 0.68 0.9 0.68 0.9 V VX+0.2 VX-0.5 VX+0.5 VX-0.2 VX+0.2 VX-0.5 VX+0.5 VX-0.2 VX+0.2 VX-0.5 VX+0.5 VX-0.2 V VCC-0.880 VCC-1.480 VCC-1.165 VCC-1.810 VCC-0.880 VCC-1.480 VCC-1.165 VCC-1.810 VCC-0.880 VCC-1.480 V 150 A VIN = VCC to VEE VCC-0.82 VCC-1.40 V IOH= -30mAg IOL= -5mAg V All inputs (LVPECL single ended signals) VIH VIL Input high voltage IIH Input Current Input low voltage VCC-1.165 VCC-1.810 150 150 V LVPECL clock outputs (Q0-19, Q0-19) VOH VOL Output High Voltage Output Low Voltage VCC-1.20 VCC-1.90 VCC-0.82 VCC-1.40 VCC-1.15 VCC-1.90 VCC-0.82 VCC-1.40 VCC-1.15 VCC-1.9 V Supply current and VBB IEE ICC VBB a. b. c. d. e. f. g. h. i. Max. Supply Current Max. Supply Currenth 190 190 190 mA 750 750 750 mA VEE pin VCC pins Output reference voltagei VCC=3.3V VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 V VCC=2.5V VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.22 VCC-1.35 VCC-1.22 V The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both HSTL and LVPECL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. Only applicable to CLK1, CLK1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Equivalent to an output termination of 50 to VTT. ICC includes current through the output resistors (all outputs terminated 50 to VTT). VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3 mA DC current. W IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc MOTOROLA 4 Go to: www.freescale.com 4 MC100EP221 TIMING SOLUTIONS MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. NETCOM MC100EP221 Table 5: ECL DC Characteristics (VCC = VCCO = GND, VEE = -3.8V to -2.375V) Symbol Characteristics TA = -40C Min Max TA = 25C Min Max Clock input pair CLK0, CLK0, CLK1, CLK1a for ECL differential signals VPP Differential input voltageb 0.10 0.10 VEE=-3.3V 0.15 0.15 VEE=-2.5V VCMR Differential cross point voltagec -0.4 VEE+1.0 CLK0 VEE+1.0 -1.0 VEE+0.1 CLK1 VEE+0.1 TA = 85C Min Max 0.10 0.15 Unit Condition V V -0.4 -1.0 VEE+1.0 VEE+0.1 -0.4 -1.0 V V V Freescale Semiconductor, Inc... All inputs ECL single ended signals VIH VIL Input high voltage -1.165 -0.880 -1.165 -0.880 -1.165 -0.880 Input low voltage -1.810 -1.480 -1.810 -1.480 -1.810 -1.480 V IIH Input Current 150 A VIN = VEE to VCC IOH= -30 mAd IOL= -5 mAd 150 150 LVPECL clock outputs (Q0-19, Q0-19) VOH VOL Output High Voltage -1.20 -0.82 -1.20 -0.82 -1.20 -0.82 V Output Low Voltage -1.90 -1.40 -1.90 -1.40 -1.90 -1.40 V Supply current and VBB IEE ICC VBB a. b. c. d. e. f. Max. Supply Current Max. Supply Currente 190 190 190 mA 750 750 750 mA VEE pin VCC Pins Output reference voltagef -1.35 -1.24 -1.35 -1.24 -1.35 -1.24 V VEE=-3.3V -1.35 -1.24 -1.35 -1.22 -1.35 -1.22 V VEE=-2.5V The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Equivalent to an output termination of 50 to VTT. ICC includes current through the output resistors (all outputs terminated 50 to VTT). VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3 mA DC current. W IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc TIMING SOLUTIONS 5 Go to: www.freescale.com 5 MC100EP221 MOTOROLA MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. NETCOM MC100EP221 Table 6: PECL/ECL/HSTL AC Characteristicsa (VCC = VCCO = 2.375V to 3.8V, VEE = GND) or (VEE = -3.8V to -2.375V, VCC = VCCO = GND) Symbol Characteristics Min TA = -40C Typ Max TA = 25C Typ Max Min TA = 85C Typ Max 1.0 0.5 1.0 1.0 0.3 VCC-0.4 VCC-1.3 1.0 1.0 0.3 1.0 0.5 1.0 0.5 1.0 V -0.4 -1.3 VEE+1.0 VEE+0.3 -0.4 -1.3 VEE+1.0 VEE+0.3 -0.4 -1.3 V V 1.0 GHz V Min Clock input pair CLK0, CLK0, CLK1, CLK1b for PECL differential signals VPP Differential input voltagec 0.5 1.0 0.5 (peak-to-peak) VCMR fCLK Differential cross point voltaged CLK0 CLK1 Input Frequency (PECL) 1.0 0.3 VCC-0.4 VCC-1.3 1.0 0 Unit Conditi tion V VCC-0.4 V VCC-1.3 V 1.0 GHz Clock input pair CLK0, CLK0, CLK1, CLK1 for ECL differential signals Freescale Semiconductor, Inc... VPP VCMR fCLK Differential input voltage (peak-to-peak) 0.5 Differential cross point voltage CLK0 VEE+1.0 CLK1 VEE+0.3 Input Frequency (ECL) 0 1.0 Clock input pair CLK1, CLK1 for HSTL differential signals VDIF Differential input voltagee 0.4 (peak-to-peak) CLK1 VX fCLK Differential cross point voltagef CLK1 Input Frequency (HSTL) 1.0 1.0 0.5 1.0 0.5 1.0 0.68 0.9 0.68 0.9 0.68 0.9 V 0 1.0 1.0 GHz 750 800 ps ps 1.0 PECL/ECL clock outputs (Q0-19, Q0-19) tPD VO(P-P) Propagation Delay CLK0 to Qx CLK1 to Qx Differential output voltage (peak-to-peak)fO < 50 MHz fO < 0.8 GHz fO < 1.0 GHz tsk(O) Output-to-output skew (within device) tsk(PP) Output-to-output skew (part-to-part) tJIT(CC) Output cycle-to-cycle jitter (RMS) a. b. c. d. e. f. 350 370 460 500 600 640 450 400 375 390 440 520 570 550 500 400 30 50 30 49.5 tr, tf Output Rise/Fall Time 100 50.0 630 680 50 30 TBD 50.5 49.5 500 100 50.0 50.5 49.5 500 100 Diff. Diff. mV mV mV 270 TBD Output duty cycle 480 530 550 500 400 270 DCO 660 710 50.0 50 ps Diff. 270 ps Diff. TBD ps 50.5 % DCfref= 50% 500 ps 20% to 80% AC characteristics apply for parallel output termination of 50 to VTT. The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP (AC) is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential input signal. AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay and part-to-part skew. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics. Only applicable to CLK1. VX (AC) is the crosspoint of the differential HSTL input signal. AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay and part-to-part skew. IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc MOTOROLA 6 Go to: www.freescale.com 6 MC100EP221 TIMING SOLUTIONS MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. ZO = 50 Differential Pulse Generator Z = 50 NETCOM MC100EP221 ZO = 50 W RT = 50 DUT MC100EP221 RT = 50 VTT VTT Freescale Semiconductor, Inc... Figure 1. MC100EP221 AC test reference CLKN VPP=0.8V VCMR=VCC-1.3V CLKN QX QX tPD (CLKN to QX) Figure 2. MC100EP221 AC reference measurement waveform IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc TIMING SOLUTIONS 7 Go to: www.freescale.com 7 MC100EP221 MOTOROLA MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. NETCOM MC100EP221 APPLICATIONS INFORMATION III III III III III IIII III IIII III III III III IIII IIIIII II IIIIIIII II IIIIII II IIIIIIII II IIIIII IIIIIIIII II II I II I II I II I I I I II IIII III III III III all units mm 7 Thermal via array (5x5), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 1. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 2. "Recommended solder mask openings" shows a recommend solder mask opening with respect to the recommended 5 x 5 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 2. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. I I I I II I II I II I I II II I I I I II I II I II I I II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II IIII II II II II II II II II I I I I II I II I II I II I IIIII II II I II I I all units mm 0.2 1.0 1.0 0.2 7 The MC100EP221 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the leadframe is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100EP221 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100EP221. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is the absolute minimum requirement for MC100EP221 applications on multi-layer boards. The recommended thermal land design comprises a 5 x 5 t h e r m a l v i a a r r a y a s s h o w n i n F i g u r e 1. "Recommended thermal land pattern", providing an efficient heat removal path. 7 Freescale Semiconductor, Inc... Using the thermally enhanced package of the MC100EP221 7 Thermal via array (5x5), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 2. Recommended solder mask openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 7: Thermal Resistancea ConvectionLFPM RTHJAb C/W RTHJAc C/W Natural 57.1 24.9 100 50.0 21.3 200 46.9 20.0 400 43.4 18.7 800 38.6 16.9 RTHJCd C/W RTHJBe C/W 15.8 9.7 a. Thermal data pattern with a 3 x 3 thermal via array on 2S2P boards (based on empirical results) b. Junction to ambient, single layer test board, per JESD51-6 c. Junction to ambient, four conductor layer test board (2S2P), per JES51-6 d. Junction to case, per MIL-SPEC 883E, method 1012.1 e. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100EP221 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc MOTOROLA 8 Go to: www.freescale.com 8 MC100EP221 TIMING SOLUTIONS MC100EP221 Freescale Low-Voltage 1:20 Differential ECL/PECL Clock Driver Semiconductor, Inc. NETCOM MC100EP221 OUTLINE DIMENSIONS TB SUFFIX PLASTIC LQFP PACKAGE CASE 1336-01 ISSUE O 4X 0.20 H A-B D AB 4X 13 TIPS X=A, B OR D X 0.20 C A-B D D AB 52 CL 40 1 39 Freescale Semiconductor, Inc... e 48X B VIEW Y VIEW Y E1 E b1 PLATING A E1/2 13 14 CCC EEEE EEEE CCC E/2 8 27 BASE METAL 8 c c1 26 8 b 8 D1/2 SECTION AB-AB ROTATED 90_ CLOCKWISE D/2 D1 D H 0.08 C J b C A-B D 52X C 52X Z2 4X A SEATING PLANE 0.08 M 4X J Z3 VIEW AA S Z1 R1 A2 Z R2 A1 G L L1 VIEW AA F EXPOSED PAD VIEW J-J NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 mm. 6. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 mm AND 0.25 mm FROM THE LEAD TIP. DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 R1 R2 S F G Z Z1 Z2 Z3 IDTTM Low-Voltage 1:20 Differential ECL/PECL Clock Driver For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc TIMING SOLUTIONS 9 Go to: www.freescale.com 9 MILLIMETERS MIN MAX --- 1.70 0.05 0.20 1.30 1.50 0.271 0.334 0.27 0.33 0.123 0.136 0.122 0.132 12.00 BSC 10.00 BSC 0.65 BSC 12.00 BSC 10.00 BSC 0.45 0.75 1.00 REF 0.08 --- 0.08 0.20 0.20 --- 6.50 7.50 6.50 7.50 0_ 7_ --- 0_ 11_ 13 _ 11_ 13 _ MC100EP221 MOTOROLA MC100EP221 MPC92459 PART NUMBERS 900 Low-Voltage MHzPRODUCT Low1:20 Voltage Differential LVDS Clock ECL/PECL Synthesizer Clock Driver INSERT NAME AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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