MOTOROLA
SEMICONDUCTOR TECHNICAL DATA Order this document
by MC100EP221/D
1REV 1
Motorola, Inc. 2001
08/01
Low-Voltage 1:20 Differential
ECL/PECL Clock Driver
The MC100EP221 is a low skew 1–to–20 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The input signals can be either differential or single–ended if
the VBB output is used. The selected signal is fanned out to 20 identical
differential outputs.
•270ps max. Part–to–Part Skew
•50ps max. Output–to–Output Skew
•Differential Design
•VBB Output
•Voltage and Temperature Compensated Outputs
•Supports 3.3V and 2.5V, ECL and PECL Operation
•Supports HSTL and PECL Clock Systems
The EP221 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate–
to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50Ω, even if only
one side is being used. In most applications, all ten differential pairs will
be used and therefore terminated. In the case where fewer than ten pairs
are used, it is necessary to terminate at least the output pairs on the same
package side as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used
which, while not being catastrophic to most designs, will mean a loss of
skew margin.
The MC100EP221, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the EP221 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the
EP221’s performance to distribute low skew clocks across the backplane. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies.
MC100EP221
LOW–VOLTAGE
1:20 DIFFERENTIAL
ECL/PECL CLOCK DRIVER
TB SUFFIX
52–LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336
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DATA SHEET
MC100EP221
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
1
Low-Voltage 1:20 Differential
ECL/PECL Clock Driver
MC100EP221
MOTOROLA TIMING SOLUTIONS2
LOGIC SYMBOL
Q0
Q0
0
1
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Pinout: 52–Lead LQFP
(Top View)
Q1:18
Q1:18
Q19
Q19
16
VCCO
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
VCCO
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
VCCO
VCC
VCCO
CLKSEL
CLK0
CLK0
VBB
CLK1
CLK1
VEE
Q19
Q19
Q18
Q18
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
12345678910111213
39 38 37 36 35 34 33 32 31 30 29 28 2726
MC100EP211
FUNCTION
Active Input
CLK0, CLK0
CLK1, CLK1
CLK_SEL
0
1
65 k
W
65 k
W
65 k
W
65 k
W
65 k
W
65 k
W
VCC
VCC
VEE
VEE
VEE
VEE
65 k
W
VEE
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MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
2
MC100EP221
TIMING SOLUTIONS 3 MOTOROLA
Table 1: PIN CONFIGURATION
Pin I/O Type Function
CLK0, CLK0 Input ECL/LVPECL Differential reference clock signal input
CLK1, CLK1 Input ECL/LVPECL or HSTL Alternative dif ferential reference clock signal input
CLK_SEL Input LVPECL Output frequency divider select
Q[0-19], Q[0-19] Output LVPECL Dif ferential clock outputs
VEEaSupply Negative power supply
VCC, VCCO Supply Positive power supply. All VCC and VCCO pins must be connected to
the positive power supply for correct DC and AC operation
VBB Output DC bias output for single ended input operation
a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V).
In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V.
In both modes, the input and output levels are referrenced to the most positive supply (VCC).
Table 2: ABSOLUTE MAXIMUM RATINGSa
Symbol Characteristics Min Max Unit Condition
VCC Supply Voltage -0.3 4.6 V
VIN DC Input Voltage -0.3 VCC+0.3 V
VOUT DC Output Voltage -0.3 VCC+0.3 V
IIN DC Input Current ±20 mA
IOUT DC Output Current ±50 mA
TSStorage temperature -65 125 °C
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur . Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability . Functional operation at absolute-maximum-rated conditions is not
implied.
Table 3: GENERAL SPECIFICATIONS
Symbol Characteristics Min Typ Max Unit Condition
VTT Output termination voltage VCC - 2aV
MM ESD Protection (Machine model) 75 V
HBM ESD Protection (Human body model) 1500 V
CDM ESD Protection (Charged device model) 500 V
LU Latch-up immunity 200 mA
CIN 4.0 pF Inputs
θJA Thermal resistance junction to ambient See application informationb
θJC Thermal resistance junction to case See application information
a. Output termination voltage VTT = 0V for VCC=2.5V operation is supported but the power consumption of the device will increase.
b. Proper thermal management is critical for reliable system operation. This especially true for high-fanout and high drive capability
products. Thermal package information and exposed pad land pattern design recommendations are available in the applications section
of this datasheet. In addition, the means of calculating die power consumption, the corresponding die temperature and the relationsship
to long-term reliability is addressed in the Motorola application note AN1545. Thermal modeling is recommended for the MC100EP221.
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MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
3
MC100EP221
MOTOROLA TIMING SOLUTIONS4
Table 4: PECL and HSTL DC Characteristics (VCCO = VCC = 2.375V to 3.8V, VEE = GND)
Symbol Characteristics TA = -40°C TA = 25°C TA = 85°CUnit Condition
Min Max Min Max Min Max
Clock input pair CLK0, CLK0, CLK1, CLK1a (LVPECL differential signals)
VPP Differential input
voltageb V
CC=3.3V
VCC=2.5V 0.10
0.15 0.10
0.15 0.10
0.15 V
V
VCMR Differential cross point
voltagecCLK0
CLK1 1.0
0.1 VCC-0.4
VCC-1.0 1.0
0.1 VCC-0.4
VCC-1.0 1.0
0.1 VCC-0.4
VCC-1.0 V
V
Clock input pair CLK1, CLK1d (HSTL differential signals)
VDIF Differential input
voltagee V
CC=3.3V
VCC=2.5V 0.4
0.4 1.0
1.0 0.4
0.4 1.0
1.0 0.4
0.4 1.0
1.0 V
V
VXDifferential cross point
voltagef0.68 0.9 0.68 0.9 0.68 0.9 V
VIH Input high voltage VX+0.2 VX+0.5 VX+0.2 VX+0.5 VX+0.2 VX+0.5 V
VIL Input low voltage VX-0.5 VX-0.2 VX-0.5 VX-0.2 VX-0.5 VX-0.2 V
All inputs (LVPECL single ended signals)
VIH Input high voltage VCC-1.165 VCC-0.880 VCC-1.165 VCC-0.880 VCC-1.165 VCC-0.880 V
VIL Input low voltage VCC-1.810 VCC-1.480 VCC-1.810 VCC-1.480 VCC-1.810 VCC-1.480 V
IIH Input Current 150 150 150 µA VIN = VCC to
VEE
LVPECL clock outputs (Q0-19, Q0-19)
VOH Output High Voltage VCC-1.20 VCC-0.82 VCC-1.15 VCC-0.82 VCC-1.15 VCC-0.82 V IOH= -30mAg
VOL Output Low Voltage VCC-1.90 VCC-1.40 VCC-1.90 VCC-1.40 VCC-1.9 VCC-1.40 V IOL= -5mAg
Supply current and VBB
IEE Max. Supply Current 190 190 190 mA VEE pin
ICC Max. Supply Currenth750 750 750 mA VCC pins
VBB Output reference
voltagei V
CC=3.3V
VCC=2.5V VCC-1.35
VCC-1.35 VCC-1.24
VCC-1.24 VCC-1.35
VCC-1.35 VCC-1.24
VCC-1.22 VCC-1.35
VCC-1.35 VCC-1.24
VCC-1.22 V
V
a. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets
both HSTL and LVPECL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold
voltage (VCMR).
b. VPP is the minimum differential input voltage swing required to maintain device functionality.
c. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR (DC)
range and the input swing lies within the VPP (DC) specification.
d. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1.
e. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. Only applicable to CLK1, CLK1.
f. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
g. Equivalent to an output termination of 50Ω to VTT.
h. ICC includes current through the output resistors (all outputs terminated 50
W
to VTT).
i. VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3
mA DC current.
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MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
4
MC100EP221
TIMING SOLUTIONS 5 MOTOROLA
Table 5: ECL DC Characteristics (VCC = VCCO = GND, VEE = -3.8V to -2.375V)
Symbol Characteristics TA = -40°C TA = 25°C TA = 85°CUnit Condition
Min Max Min Max Min Max
Clock input pair CLK0, CLK0, CLK1, CLK1a for ECL differential signals
VPP Differential input voltageb
VEE=-3.3V
VEE=-2.5V 0.10
0.15 0.10
0.15 0.10
0.15 V
V
VCMR Differential cross point voltagec
CLK0
CLK1 VEE+1.0
VEE+0.1 -0.4
–1.0 VEE+1.0
VEE+0.1 -0.4
–1.0 VEE+1.0
VEE+0.1 -0.4
–1.0 V
V
All inputs ECL single ended signals
VIH Input high voltage -1.165 -0.880 -1.165 -0.880 -1.165 -0.880 V
VIL Input low voltage -1.810 -1.480 -1.810 -1.480 -1.810 -1.480 V
IIH Input Current 150 150 150 µA VIN = VEE to
VCC
LVPECL clock outputs (Q0-19, Q0-19)
VOH Output High Voltage -1.20 -0.82 -1.20 -0.82 -1.20 -0.82 V IOH= -30 mAd
VOL Output Low Voltage -1.90 -1.40 -1.90 -1.40 -1.90 -1.40 V IOL= -5 mAd
Supply current and VBB
IEE Max. Supply Current 190 190 190 mA VEE pin
ICC Max. Supply Currente750 750 750 mA VCC Pins
VBB Output reference voltagef
VEE=-3.3V
VEE=-2.5V -1.35
-1.35 -1.24
-1.24 -1.35
-1.35 -1.24
-1.22 -1.35
-1.35 -1.24
-1.22 V
V
a. The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The dif ference between CLK0 and CLK1 is
the differential input threshold voltage (VCMR).
b. VPP is the minimum differential input voltage swing required to maintain device functionality.
c. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR (DC)
range and the input swing lies within the VPP (DC) specification.
d. Equivalent to an output termination of 50Ω to VTT.
e. ICC includes current through the output resistors (all outputs terminated 50
W
to VTT).
f. VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3
mA DC current.
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MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
5
MC100EP221
MOTOROLA TIMING SOLUTIONS6
Table 6: PECL/ECL/HSTL AC Characteristicsa (VCC = VCCO = 2.375V to 3.8V, VEE = GND) or (VEE = -3.8V to -2.375V,
VCC = VCCO = GND)
Symbol Characteristics TA = -40°C TA = 25°C TA = 85°CUnit Condi-
ti
Min Typ Max Min Typ Max Min Typ Max tion
Clock input pair CLK0, CLK0, CLK1, CLK1b for PECL differential signals
VPP Differential input voltagec
(peak-to-peak) 0.5 1.0 0.5 1.0 0.5 1.0 V
VCMR Differential cross point
voltagedCLK0
CLK1 1.0
0.3 VCC-0.4
VCC-1.3 1.0
0.3 VCC-0.4
VCC-1.3 1.0
0.3 VCC-0.4
VCC-1.3 V
V
fCLK Input Frequency (PECL) 0 1.0 1.0 1.0 GHz
Clock input pair CLK0, CLK0, CLK1, CLK1 for ECL differential signals
VPP Differential input voltage
(peak-to-peak) 0.5 1.0 0.5 1.0 0.5 1.0 V
VCMR Differential cross point
voltage CLK0
CLK1 VEE+1.0
VEE+0.3 -0.4
-1.3 VEE+1.0
VEE+0.3 -0.4
–1.3 VEE+1.0
VEE+0.3 -0.4
-1.3 V
V
fCLK Input Frequency (ECL) 0 1.0 1.0 1.0 GHz
Clock input pair CLK1, CLK1 for HSTL differential signals
VDIF Differential input voltagee
(peak-to-peak) CLK1 0.4 1.0 0.5 1.0 0.5 1.0 V
VXDifferential cross point
voltagefCLK1 0.68 0.9 0.68 0.9 0.68 0.9 V
fCLK Input Frequency (HSTL) 0 1.0 1.0 1.0 GHz
PECL/ECL clock outputs (Q0-19, Q0-19)
tPD Propagation Delay
CLK0 to Qx
CLK1 to Qx 350
370 460
500 600
640 390
440 520
570 660
710 480
530 630
680 750
800 ps
ps Diff.
Diff.
VO(P-P) Differential output voltage
(peak-to-peak)fO < 50 MHz
fO < 0.8 GHz
fO < 1.0 GHz
450
400
375
550
500
400
550
500
400
mV
mV
mV
tsk(O) Output-to-output skew
(within device) 30 50 30 50 30 50 ps Diff.
tsk(PP) Output-to-output skew
(part-to-part) 270 270 270 ps Diff.
tJIT(CC) Output cycle-to-cycle jitter
(RMS) TBD TBD TBD ps
DCOOutput duty cycle 49.5 50.0 50.5 49.5 50.0 50.5 49.5 50.0 50.5 % DCfref=
50%
tr, tfOutput Rise/Fall Time 100 500 100 500 100 500 ps 20% to
80%
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The dif ference between CLK0 and CLK1 is
the differential input threshold voltage (VCMR).
c. VPP (AC) is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-devic e skew.
d. VCMR (AC) is the crosspoint of the differential input signal. AC operation is obtained when the crosspoint is within the VCMR range and
the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay and
part-to-part skew.
e. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics. Only applicable to CLK1.
f. VX (AC) is the crosspoint of the differential HSTL input signal. AC operation is obtained when the crosspoint is within the VX (AC) range
and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay and
part-to-part skew.
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MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
6
MC100EP221
TIMING SOLUTIONS 7 MOTOROLA
Figure 1. MC100EP221 AC test reference
Differential
Pulse Generator
Z = 50
W
RT = 50Ω
ZO = 50Ω
DUT
MC100EP221
VTT
RT = 50Ω
ZO = 50Ω
VTT
tPD (CLKN to QX)
Figure 2. MC100EP221 AC reference measurement waveform
VCMR=VCC-1.3V
VPP=0.8V
CLKN
CLKN
QX
QX
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MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
7
MC100EP221
MOTOROLA TIMING SOLUTIONS8
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100EP221
The MC100EP221 uses a thermally enhanced exposed
pad (EP) 52 lead LQFP package. The package is molded so
that the leadframe is exposed at the surface of the package
bottom side. The exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the MC100EP221 high-speed bipolar integrated circuit and
eases the power management task for the system design. A
thermal land pattern on the printed circuit board and thermal
vias are recommended in order to take advantage of the
enhanced thermal capabilities of the MC100EP221. Direct
soldering of the exposed pad to the thermal land will provide
an efficient thermal path. In multilayer board designs, thermal
vias thermally connect the exposed pad to internal copper
planes. Number of vias, spacing, via diameters and land
pattern design depend on the application and the amount of
heat to be removed from the package. A nine thermal via
array, arranged in a 3 x 3 array and using a 1.2 mm pitch in
the center of the thermal land is the absolute minimum
requirement for MC100EP221 applications on multi-layer
boards. The recommended thermal land design comprises a
5 x 5 thermal via array as shown in Figure 1.
“Recommended thermal land pattern”, providing an efficient
heat removal path.
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Figure 1. Recommended thermal land pattern
Thermal via array (5x5),
1.2 mm pitch,
0.3 mm diameter
Exposed pad
land pattern
all
units
mm
7
The via diameter is should be approx. 0.3 mm with 1 oz.
copper via barrel plating. Solder wicking inside the via
resulting in voids during the solder process must be avoided.
If the copper plating does not plug the vias, stencil print
solder paste onto the printed circuit pad. This will supply
enough solder paste to fill those vias and not starve the
solder joints. The attachment process for exposed pad
package is equivalent to standard surface mount packages.
Figure 2. “Recommended solder mask openings” shows a
recommend solder mask opening with respect to the
recommended 5 x 5 thermal via array . Because a large solder
mask opening may result in a poor release, the opening
should be subdivided as shown in Figure 2. For the nominal
package standoff 0.1 mm, a stencil thickness of 5 to 8 mils
should be considered.
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Figure 2. Recommended solder mask openings
Thermal via array (5x5),
1.2 mm pitch,
0.3 mm diameter
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1.0
0.2
all
units
mm
7
1.0
0.2
For thermal system analysis and junction temperature
calculation the thermal resistance parameters of the package
is provided. For thermal system analysis and junction
temperature calculation the thermal resistance parameters of
the package is provided:
Table 7: Thermal Resistancea
Convection-
LFPM RTHJAb
°C/W RTHJAc
°C/W RTHJCd
°C/W RTHJBe
°C/W
Natural 57.1 24.9
100 50.0 21.3
200 46.9 20.0 15.8 9.7
400 43.4 18.7
800 38.6 16.9
a. Thermal data pattern with a 3 x 3 thermal via array on
2S2P boards (based on empirical results)
b. Junction to ambient, single layer test board, per
JESD51-6
c. Junction to ambient, four conductor layer test board
(2S2P), per JES51-6
d. Junction to case, per MIL-SPEC 883E, method 1012.1
e. Junction to board, four conductor layer test board (2S2P)
per JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100EP221 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals. The thermal land should be connected to GND
through connection of internal board layers.
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nc...
MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
8
MC100EP221
TIMING SOLUTIONS 9 MOTOROLA
OUTLINE DIMENSIONS
TB SUFFIX
PLASTIC LQFP PACKAGE
CASE 1336–01
ISSUE O
b1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM
PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN 0.08
mm. DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 mm.
6. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.1 mm AND 0.25 mm FROM
THE LEAD TIP.
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇ
ÇÇÇ
VIEW AA
AB
AB
VIEW Y
SECTION AB–AB
ROTATED 90
_
CLOCKWISE
DIM
D
MIN MAX
12.00 BSC
MILLIMETERS
D1 10.00 BSC
e0.65 BSC
E12.00 BSC
A––– 1.70
A1 0.05 0.20
A2 1.30 1.50
b0.271 0.334
b1 0.27
c0.123 0.136
E1 10.00 BSC
0.33
c1 0.122 0.132
L1 1.00 REF
L0.45 0.75
R1
R2
S0.20 –––
F
G
Z
C
L
X=A, B OR D
1
13
14 26
27
39
4052
4X 13 TIPS
4X D0.20 H A–B D0.20 C A–B
SEATING
PLANE
A0.08 C
A2
A1
S
L
L1
PLATING BASE METAL
b
cc1
E1 E
E1/2
D1
D
E/2
D1/2
D/2
e
07
__
0
_
–––
VIEW Y
VIEW AA
R1
0.08 –––
0.08 0.20
6.50 7.50
6.50 7.50
Z1
Z2
Z3 11 13
__
11 13
__
B
D
A
CA–B
M
0.08 DC
52X b
VIEW J–J
EXPOSED PAD
G
F
H52X
4X Z2
4X Z3
Z1
Z
R2
X
48X
8
8
8
8
J J
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage 1:20 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP221
9
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
PART NUMBERS
INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM
MPC92459
900 MHz Low Voltage LVDS Clock Synthesizer NETCOM
MC100EP221
Low-Voltage 1:20 Differential ECL/PECL Clock Driver NETCOM
