PN7150B0UK/C11002Z - NXP SEMICONDUCTORS

PN7150

High performance NFC controller with integrated firmware,

supporting all NFC Forum modes

Rev. 4.0 — 25 June 2020 Product data sheet

317440 COMPANY PUBLIC

1 Introduction

This document describes the functionality and electrical specification of the NFC

Controller PN7150.

Additional documents describing the product functionality further are available for design-

in support. Refer to the references listed in this document to get access to the full

documentation provided by NXP.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 2 / 66

2 General description

Plug´n play and high-performance full NFC solution PN7150 is a full NFC controller

solution with integrated firmware and NCI interface designed for contactless

communication at 13.56 MHz. It is compatible with NFC forum requirements.

PN7150 is designed based on learnings from previous NXP NFC device generation. It

is the ideal solution for rapidly integrating NFC technology in any application, especially

those running O/S environment like Linux and Android, reducing Bill of Material (BOM)

size and cost, thanks to:

•Full NFC forum compliancy (see [1]) with small form factor antenna

•Embedded NFC firmware providing all NFC protocols as pre-integrated feature

•Direct connection to the main host or microcontroller, by I2C-bus physical and NCI

protocol

•Ultra-low power consumption in polling loop mode

•Highly efficient integrated power management unit (PMU) allowing direct supply from a

battery

PN7150 embeds a new generation RF contactless front-end supporting various

transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC

15693, MIFARE Classic IC-based card and FeliCa card specifications. It embeds an Arm

Cortex-M0 microcontroller core loaded with the integrated firmware supporting the NCI

1.0 host communication. It also allows to provide a higher output power by supplying the

transmitter output stage from 3.0 V to 4.75 V.

The contactless front-end design brings a major performance step-up with on one hand

a higher sensitivity and on the other hand the capability to work in active load modulation

communication enabling the support of small antenna form factor.

Supported transmission modes are listed in Figure 1. For contactless card functionality,

the PN7150 can act autonomously if previously configured by the host in such a manner.

PN7150 integrated firmware provides an easy integration and validation cycle as all the

NFC real-time constraints, protocols and device discovery (polling loop) are being taken

care internally. In few NCI commands, host SW can configure the PN7150 to notify for

card or peer detection and start communicating with them.

aaa-023871

CARD

(PICC)

T4T - ISO/IEC 14443 A

T4T - ISO/IEC 14443 B

READER

(PCD - VCD)

ISO/IEC 14443 A

ISO/IEC 14443 B

ISO/IEC 15693

MIFARE Classic 1K/4K

MIFARE DESFire

Sony FeliCa(1)

NFC FORUM

NFC-IP MODES

P2P ACTIVE

106 TO 424 kbps

INITIATOR AND TARGET

P2P PASSIVE

106 TO 424 kbps

INITIATOR AND TARGET

NFC FORUM T3T

READER FOR NFC FORUM

Tag Types 1 TO 5

Figure 1. PN7150 transmission modes

1. According to ISO/IEC 18092 (Ecma 340) standard.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 3 / 66

3 Features and benefits

•Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property

licensing rights

•Arm Cortex-M0 microcontroller core

•Highly integrated demodulator and decoder

•Buffered output drivers to connect an antenna with minimum number of external

components

•Integrated RF level detector

•Integrated Polling Loop for automatic device discovery

•RF protocols supported

–NFCIP-1, NFCIP-2 protocol (see [8] and [11])

–ISO/IEC 14443A, ISO/IEC 14443B PICC, NFC Forum T4T modes via host interface

(see [3])

–NFC Forum T3T via host interface

–ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital

protocol T4T platform and ISO-DEP (see [1])

–FeliCa PCD mode

–MIFARE Classic PCD encryption mechanism (MIFARE Classic 1K/4K)

–NFC Forum tag 1 to 5 (MIFARE Ultralight, Jewel, Open FeliCa tag, MIFARE

DESFire) (see [1])

–ISO/IEC 15693/ICODE VCD mode (see [9])

•Supported host interfaces

–NCI protocol interface according to NFC Forum standardization (see [2])

–I2C-bus High-speed mode (see [4])

•Integrated power management unit

–Direct connection to a battery (2.3 V to 5.5 V voltage supply range)

–Support different Hard Power-Down/Standby states activated by firmware

–Autonomous mode when host is shut down

•Automatic wake-up via RF field, internal timer and I2C-bus interface

•Integrated non-volatile memory to store data and executable code for customization

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 4 / 66

4 Applications

•All devices requiring NFC functionality especially those running in an Android or Linux

environment

•TVs, set-top boxes, blu-ray decoders, audio devices

•Home automation, gateways, wireless routers

•Home appliances

•Wearables, remote controls, healthcare, fitness

•Printers, IP phones, gaming consoles, accessories

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 5 / 66

5 Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Card Emulation and Passive

Target; VSS = 0 V

[1]

[2]

2.3 - 5.5 VVBAT battery supply voltage

Reader, Active Initiator and

Active Target; VSS = 0 V

[1]

[2]

2.7 - 5.5 V

VDD supply voltage internal supply voltage 1.65 1.8 1.95 V

supply voltage for host

interface

•1.8 V host supply;VSS = 0 V [1] 1.65 1.8 1.95 V

VDD(PAD) VDD(PAD) supply voltage

•3 V host supply; VSS = 0 V [1] 3.0 - 3.6 V

in Hard Power Down state;VBAT = 3.6 V; T

= 25 °C

[3] - 10 14 μA

in Standby state;VBAT = 3.6 V; T = 25 °C - 20 - μA

in Monitor state;VBAT = 2.75 V; T = 25 °C - - 14 μA

in low-power polling loop;VBAT = 3.6 V; T =

25 °C;loop time = 500 ms

[4] - 150 - μA

IBAT battery supply current

PCD mode at typical 3 V [2] - - 190 mA

IO(VDDPAD) output current on pin

VDD(PAD)

total current which can be

pulled on VDD(PAD) referenced

outputs

- - 15 mA

Ith(Ilim) current limit threshold

current

current limiter on VDD(TX) pin;VDD(TX) = 3.3

[2] - 180 - mA

Ptot total power dissipation Reader; IVDD(TX) = 100 mA;VBAT = 5.5 V - - 420 mW

Tamb ambient temperature JEDEC PCB-0.5 -30 - +85 °C

[1] VSS represents VSS(PAD) and VSS(TX).

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when

coupling with another device must be taken into account).

[3] External clock on NFC_CLK_XTAL1 must be LOW.

[4] See [10] for computing the power consumption as it depends on several parameters.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 6 / 66

6 Versions

6.1 Version C11006

PN7150B0HN/C11006 contains a firmware update compared to the previous version.

The firmware version is 10.01.AE and contains the following new features and fixes:

•Anti tearing mechanism: An Anti tearing mechanism has been added. For details,

please refer to the User Manual UM10936.

•A fix has been added that addresses a collision resolution problem for ISO 15693 tags

in case there are multiple tags in the field.

6.2 Version C11004

PN7150B0HN/C11004 has been withdrawn.

6.3 Version C11002

PN7150B0HN/C11002 and PN7150B0UK/C11002 is the initial released version.

The firmware version is 10.01.A0

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 7 / 66

7 Ordering information

Table 2. Ordering information

PackageType number

Name Description Version

PN7150B0HN/C110xx[1] HVQFN40 plastic thermal enhanced very thin quad

flat package; no leads; 40 terminals;

body; 6 mm × 6 mm × 0.85 mm

SOT618-1

PN7150B0UK/C110xx[1] WLCSP42 wafer level chip-scale package; 42

bumps; 2.88 mm × 2.80 mm × 0.54 mm

(Backside coating included)

Do not use for new designs. Planned

for discontinuation.

SOT1459-1

[1] xx = firmware code variant

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 8 / 66

8 Marking HVQFN40

0 5

Terminal 1 index area

A : 7

B1 : 6

aaa-007965

B2 : 6

C : 7

Figure 2. PN7150 package marking

HVQFN40 (top view) 4 lines

aaa-038147

A : 7

Terminal 1 index area

B1 : 6

C : 7

Figure 3. PN7150 package marking

HVQFN40 (top view) 3 lines

Table 3. Marking codes

Type number Marking code

Line A 7 characters used: basic type number:PN7150x

where x is the FW variant

Line B1 6 characters used: diffusion batch sequence

number

Line B2 (optional) 6 characters used: assembly ID number

Line C 7 characters used: manufacturing code

including:

•diffusion center code:

–Z: SSMC

–S: Powerchip (PTCT)

•assembly center code:

–S: ATKH

•RoHS compliancy indicator:

–D: Dark Green; fully compliant RoHS

and no halogen and antimony

•manufacturing year and week, 3 digits:

–Y: year

–WW: week code

•product life cycle status code:

–X: means not qualified product

–nothing means released product

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 9 / 66

9 Marking WLCSP42

aaa-028702

Figure 4. WLCSP42

Table 4. WLCSP package marking (top view)

Line number Marking code

Line 1 Product identification

•Product name: 7150x; where x is the variant.

Line 2 Diffusion batch sequence number

•Diffusion fabrication code: NNNNN

•Wafer ID: DD

Line 3 Manufacturing code including:

•Diffusion center code:

–Z: SSMC

–s: Global Foundry

–S: Power chip (PTCT)

•Assembly center code:

–Q: ASE-CL

•RoHS compliancy indicator:

–D: Dark Green; fully compliant RoHS and no halogen

and antimony

•Manufacturing year and week; 4 digits:

–YY: year

–WW: week code

•Mask layout version

•Product life cycle status code:

–X: not qualified product

–Nothing means released product

Line 4 NXP logo

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 10 / 66

10 Block diagram

aaa-016737

RF DETECTRF DETECT

CLESS

INTERFACE UNIT

SENSOR

DEMOD ADC

DRIVER TxCtrl

PLL BG

VMID

MISCELLANEOUS

TIMERS

CRC

COPROCESSOR

RANDOM

NUMBER

GENERATOR

CLOCK MANAGEMENT UNIT

OSCILLATOR

380 kHz

FRACN

PLL

OSCILLATOR

40 MHz

QUARTZ

OSCILLATOR

CLESS UART

AHB to APB

RX CODEC SIGNAL

PROCESSING

TX CODEC

DATA

MEMORY

SRAM

EEPROM

CODE

MEMORY

ROM

EEPROM

HOST INTERFACE

ARM

CORTEX M0

MEMORY

CONTROL

I2C-bus

POWER

MANAGEMENT UNIT

BATTERY

MONITOR

4.5 V

TX-LDO

1.8 V

DSLDO

Fig 3. PN7150 block diagram

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 11 / 66

11 Pinning information

11.1 Pinning HVQFN40

aaa-016738

PN7150

VSS

Transparent top view

terminal 1

index area

I2CADR0

i.c.

I2CADR1

VSS(PAD)

I2CSDA

VDD(PAD)

I2CSCL

IRQ

VSS

VEN

VDDD

VDD

VDDA

VSS

VBAT

i.c.

VDD(TX_IN)

TX1

n.c.

VSS(TX)

TX2

VDD(MID)

RXP

RXN

VDD(TX)

BAT1

BAT2

i.c.

NFC

CLK

Fig 4. Pinning

Table 5. Pin description

Symbol Pin Type[1] Refer Description

I2CADR0 1 I VDD(PAD) I2C-bus address 0

i.c. 2 - - internally connected; must be connected to GND

I2CADR1 3 I VDD(PAD) I2C-bus address 1

VSS(PAD) 4 G n/a pad ground

I2CSDA 5 I/O VDD(PAD) I2C-bus data line

VDD(PAD) 6 P n/a pad supply voltage

I2CSCL 7 I VDD(PAD) I2C-bus clock line

IRQ 8 O VDD(PAD) interrupt request output

VSS 9 G n/a ground

VEN 10 I VBAT reset pin. Set the device in Hard Power Down

i.c. 11 - - internally connected; leave open

VBAT2 12 P n/a battery supply voltage; must be connected to VBAT

VBAT1 13 P n/a TXLDO input supply voltage

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 12 / 66

Symbol Pin Type[1] Refer Description

VDD(TX) 14 P n/a transmitter supply voltage

RXN 15 I VDD negative receiver input

RXP 16 I VDD positive receiver input

VDD(MID) 17 P n/a receiver reference input supply voltage

TX2 18 O VDD(TX) antenna driver output

VSS(TX) 19 G n/a contactless transmitter ground

n.c. 20 - - not connected

TX1 21 O VDD(TX) antenna driver output

VDD(TX_IN) 22 P n/a transmitter input supply voltage; must be connected to VDD(TX)

i.c. 23 - - internally connected; leave open

i.c. 24 - - internally connected; leave open

i.c. 25 - - internally connected; leave open

VBAT 26 P n/a battery supply voltage

VSS 27 G n/a ground

VDDA 28 P n/a analog supply voltage; must be connected to VDD

VDD 29 P n/a supply voltage

VDDD 30 P n/a digital supply voltage; must be connected to VDD

n.c. 31 - - not connected

n.c. 32 - - not connected

n.c. 33 - - not connected

n.c. 34 - - not connected

n.c. 35 - - not connected

NFC_CLK_XTAL1 36 I VDD oscillator input/PLL input

NFC_CLK_XTAL2 37 O VDD oscillator output

i.c. 38 - - internally connected; leave open

i.c. 39 - - internally connected; leave open

CLK_REQ 40 O VDD(PAD) clock request pin

[1] P = power supply

G = ground

I = input

O = output

I/O = input/output

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 13 / 66

11.2 Pinning WLCSP42

aaa-007576

42 61 3 5 7

ball A1

index area

Figure 5. WLCSP42 pinning (bottom view)

Table 6. WLCSP package marking (top view)

Symbol Pin Type[1] Refer Description

VBAT2 A1 P n/a battery supply voltage; to be connected to VBAT

i.c. A2 - - internally connected; leave open

VBAT1 A3 P n/a TXLDO input supply voltage

RXN A4 I VDD negative receiver input

VDD(MID) A5 P n/a receiver reference input supply voltage

TX2 A6 O VDD(TX) antenna driver output

TX1 A7 O VDD(TX) antenna driver output

VSS B1 G n/a ground

VSS B2 G n/a ground

VDD(TX) B3 P n/a transmitter supply voltage

RXP B4 I VDD positive receiver input

VSS B5 G n/a ground

VSS(TX) B6 G n/a contactless transmitter ground

VDD(TX_IN) B7 P n/a transmitter input supply voltage; must be connected to VDD(TX)

IRQ C1 O VDD(PAD) interrupt request output

VDD(PAD) C2 P n/a pad supply voltage

VEN C3 I VBAT reset pin. Set the device in Hard Power Down

VSS C4 G n/a power ball. Shall be connected to ground for dissipation

VSS C5 G n/a power ball. Shall be connected to ground for dissipation

i.c. C6 - - internally connected; leave open

i.c. C7 - - internally connected; leave open

I2CSCL D1 I VDD(PAD) I2C-bus clock line

I2CSDA D2 I/O VDD(PAD) I2C-bus data line

CLK_REQ D3 O VDD(PAD) clock request pin

i.c. D4 - - internally connected; leave open

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 14 / 66

Symbol Pin Type[1] Refer Description

i.c. D5 - - internally connected; leave open

VDDD D6 P n/a digital supply voltage; must be connected to VDD

VBAT D7 P n/a battery supply voltage

VSS(PAD) E1 G n/a pad ground

I2CADR1 E2 I VDD(PAD) I2C-bus address 1

i.c. E3 - - internally connected; leave open

NFC_CLK_XTAL1 E4 I VDD oscillator input/PLL input

i.c. E5 - - internally connected; leave open

i.c. E6 - - internally connected; leave open

VDD E7 P n/a LDO output supply voltage

I2CADR0 F1 I VDD(PAD) I2C-bus address 0

i.c. F2 - - internally connected; must be connected to GND

NFC_CLK_XTAL2 F3 O VDD oscillator output

i.c. F4 - - internally connected; leave open

i.c. F5 - - internally connected; must be connected to GND

i.c. F6 - - internally connected; leave open

i.c. F7 - - internally connected; leave open

[1] P = power supply

G = ground

I = input

O = output

I/O = input/output

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 15 / 66

12 Functional description

PN7150 can be connected on a host controller through I2C-bus. The logical interface

towards the host baseband is NCI-compliant [2] with additional command set for NXP-

specific product features. This IC is fully user controllable by the firmware interface

described in [5].

Moreover, PN7150 provides flexible and integrated power management unit in order to

preserve energy supporting Power Off mode.

In the following chapters you will find also more details about PN7150 with references to

very useful application note such as:

•PN7150 User Manual ([5]):

User Manual describes the software interfaces (API) based on the NFC forum NCI

standard. It does give full description of all the NXP NCI extensions coming in addition

to NCI standard ([2]).

•PN7150 Hardware Design Guide ([6]):

Hardware Design Guide provides an overview on the different hardware design options

offered by the IC and provides guidelines on how to select the most appropriate ones

for a given implementation. In particular, this document highlights the different chip

power states and how to operate them in order to minimize the average NFC-related

power consumption so to enhance the battery lifetime.

•PN7150 Antenna and Tuning Design Guide ([7]):

Antenna and Tuning Design Guide provides some guidelines regarding the way to

design an NFC antenna for the PN7150 chip.

It also explains how to determine the tuning/matching network to place between this

antenna and the PN7150.

Standalone antenna performances evaluation and final RF system validation (PN7150

+ tuning/matching network + NFC antenna within its final environment) are also

covered by this document.

•PN7150 Low-Power Mode Configuration ([10]):

Low-Power Mode Configuration documentation provides guidance on how PN7150

can be configured in order to reduce current consumption by using Low-power polling

mode.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 16 / 66

aaa-016739

NFCC

host interface

control

HOST

CONTROLLER

BATTERY/PMU

ANTENNA

MATCHING

Fig 5. PN7150 connection

Important: To avoid data corruption inside the EEPROM memory, make sure to follow

these rules:

•Prevent re-applying RF settings configuration when not required (different possibilities

of implementation exist depending on the integration environment, please contact NXP

support for more details).

•Insure RF settings configuration is not interrupted (no interruption between related

CORE_SET_CONFIG_CMD and CORE_SET_CONFIG_RSP).

•Split the RF settings configuration into several CORE_SET_CONFIG_CMD to limit

the time for the FW to treat this command. Only one transferred RF parameter via

the CORE_SET_CONFIG_CMD takes approximately 2.7ms. 5.4ms in the specific

case where the RF parameter resides in two separated Flash memory blocks, which

increase the probability for an interruption between CORE_SET_CONFIG_CMD and

CORE_SET_CONFIG_RSP.

•It must be ensured that the RF settings configuration will not be interrupted due to a

power off or hardware reset. Once the memory is corrupted, the IC cannot recover from

this stage and cannot be used anymore.

12.1 System modes

12.1.1 System power modes

PN7150 is designed in order to enable the different power modes from the system.

2 power modes are specified: Full power mode and Power Off mode.

Table 7. System power modes description

System power mode Description

Full power mode the main supply (VBAT) as well as the host interface supply (VDD(PAD)) is

available, all use cases can be executed

Power Off mode the system is kept Hard Power Down (HPD)

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 17 / 66

aaa-015871

[VEN = Off]

[VBAT = On && VDD(PAD) = On

VEN = On]

[VBAT = Off || VEN = Off]

Full power mode

Power Off mode

Fig 6. System power mode diagram

Table 6 summarizes the system power mode of the PN7150 depending on the status of

the external supplies available in the system:

Table 8. System power modes configuration

VBAT VEN Power mode

Off X Power Off mode

On Off Power Off mode

On On Full power mode

Depending on power modes, some application states are limited:

Table 9. System power modes description

System power mode Allowed communication modes

Power Off mode no communication mode available

Full power mode Reader/Writer, Card Emulation, P2P modes

12.1.2 PN7150 power states

Next to system power modes defined by the status of the power supplies, the power

states include the logical status of the system thus extend the power modes.

4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active.

Table 10. PN7150 power states

Power state name Description

Monitor The PN7150 is supplied by VBAT which voltage is below its programmable

critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The

system power mode is Power Off mode.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 18 / 66

Power state name Description

Hard Power Down The PN7150 is supplied by VBAT which voltage is above its programmable

critical level when Monitor state is enabled and PN7150 is kept in Hard

Power Down (VEN voltage is kept low by host or SW programming) to have

the minimum power consumption. The system power mode is in Power Off.

Standby The PN7150 is supplied by VBAT which voltage is above its programmable

critical level when the Monitor state is enabled, VEN voltage is high (by host

or SW programming) and minimum part of PN7150 is kept supplied to

enable

configured wake-up sources which allow to switch to Active state; RF

field,Host interface. The system power mode is Full power mode.

Active The PN7150 is supplied by VBAT which voltage is above its programmable

critical level when Monitor state is enabled, VEN voltage is high (by host or

SW programming) and the PN7150 internal blocks are supplied. 3 functional

modes are defined: Idle, Target and Initiator. The system power mode is Full

power mode.

At application level, the PN7150 will continuously switch between different states to

optimize the current consumption (polling loop mode). Refer to Table 1 for targeted

current consumption in here described states.

The PN7150 is designed to allow the host controller to have full control over its functional

states, thus of the power consumption of the PN7150 based NFC solution and possibility

to restrict parts of the PN7150 functionality.

12.1.2.1 Monitor state

In Monitor state, the PN7150 will exit it only if the battery voltage recovers over the critical

level. Battery voltage monitor thresholds show hysteresis behavior as defined in Table

27.

12.1.2.2 Hard Power Down (HPD) state

The Hard Power Down state is entered when VDD(PAD) and VBAT are high by setting VEN

voltage < 0.4 V. As these signals are under host control, the PN7150 has no influence on

entering or exiting this state.

12.1.2.3 Standby state

Active state is PN7150’s default state after boot sequence in order to allow a quick

configuration of PN7150. It is recommended to change the default state to Standby state

after first boot in order to save power. PN7150 can switch to Standby state autonomously

(if configured by host).

In this state, PN7150 most blocks including CPU are no more supplied. Number of wake-

up sources exist to put PN7150 into Active state:

•I2C-bus interface wake-up event

•Antenna RF level detector

•Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled)

If wake-up event occurs, PN7150 will switch to Active state. Any further operation

depends on software configuration and/or wake-up source.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 19 / 66

12.1.2.4 Active state

Within the Active state, the system is acting as an NFC device. The device can be in 3

different functional modes: Idle, Poller and Target.

Table 11. Functional modes in active state

Functional modes Description

Idle the PN7150 is active and allows host interface communication. The RF

interface is not activated.

Listener the PN7150 is active and is configured for listening to external device.

Poller the PN7150 is active and is configured in Poller mode. It polls external

device

Poller mode In this mode, PN7150 is acting as Reader/Writer or NFC

Initiator, searching for or communicating with passive

tags or NFC target. Once RF communication has ended,

PN7150 will switch to active battery mode (that is, switch

off RF transmitter) to save energy. Poller mode shall

be used with 2.7 V < VBAT < 5.5 V and VEN voltage >

1.1 V. Poller mode shall not be used with VBAT < 2.7 V.

VDD(PAD) is within its operational range (see Table 1).

Listener mode In this mode, PN7150 is acting as a card or as an NFC

Target. Listener mode shall be used with 2.3 V < VBAT <

5.5 V and VEN voltage > 1.1 V.

12.1.2.5 Polling loop

The polling loop will sequentially set PN7150 in different power states (Active or

Standby). All RF technologies supported by PN7150 can be independently enabled

within this polling loop.

There are 2 main phases in the polling loop:

•Listening phase. The PN7150 can be in Standby power state or Listener mode

•Polling phase. The PN7150 is in Poller mode

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 20 / 66

aaa-016741

Emulation

Pause

Type A

Type B

Type F

@424

Type F

@212

ISO15693

Listening phase

Polling phase

Fig 7. Polling loop: all phases enabled

Listening phase uses Standby power state (when no RF field) and PN7150 goes to

Listener mode when RF field is detected. When in Polling phase, PN7150 goes to Poller

mode.

To further decrease the power consumption when running the polling loop, PN7150

features a low-power RF polling. When PN7150 is in Polling phase instead of sending

regularly RF command, PN7150 senses with a short RF field duration if there is any NFC

Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms

(configurable duration, see [5]) listening phase duration, the average power consumption

is around 150 μA.

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aaa-016743

Listening phase

Emulation

Pause

Polling phase

Fig 8. Polling loop: low-power RF polling

Detailed description of polling loop configuration options is given in [5].

12.2 Microcontroller

PN7150 is controlled via an embedded ARM Cortex-M0 microcontroller core.

PN7150 features integrated in firmware are referenced in [5].

12.3 Host interface

PN7150 provides the support of an I2C-bus Slave Interface, up to 3.4 MBaud.

The host interface is waken-up on I2C-bus address.

To enable and ensure data flow control between PN7150 and host controller, additionally

a dedicated interrupt line IRQ is provided which Active state is programmable. See [5] for

more information.

12.3.1 I2C-bus interface

The I2C-bus interface implements a slave I2C-bus interface with integrated shift register,

shift timing generation and slave address recognition.

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I2C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode

(3.4 MHz SCL) are supported.

The mains hardware characteristics of the I2C-bus module are:

•Support slave I2C-bus

•Standard, Fast and High-speed modes supported

•Wake-up of PN7150 on its address only

•Serial clock synchronization can be used by PN7150 as a handshake mechanism to

suspend and resume serial transfer (clock stretching)

The I2C-bus interface module meets the I2C-bus specification [4] except General call, 10-

bit addressing and Fast mode Plus (Fm+).

12.3.1.1 I2C-bus configuration

The I2C-bus interface shares four pins with I2C-bus interface also supported by PN7150.

When I2C-bus is configured in EEPROM settings, functionality of interface pins changes

to one described in Table 10.

Table 12. Functionality for I2C-bus interface

Pin name Functionality

I2CADR0 I2C-bus address 0

I2CADR1 I2C-bus address 1

I2CSCL[1] I2C-bus clock line

I2CSDA[1] I2C-bus data line

[1] I2CSCL and I2CSDA are not fail-safe and VDD(pad) shall always be available when

using the SCL and SDA lines connected to these pins.

PN7150 supports 7-bit addressing mode. Selection of the I2C-bus address is done by 2-

pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, I2CADR1, I2CADR0, R/W.

Table 13. I2C-bus interface addressing

I2CADR1 I2CADR0 I2C-bus address

(R/W = 0, write)

I2C-bus address

(R/W = 1, read)

0 0 0x50 0x51

0 1 0x52 0x53

1 0 0x54 0x55

1 1 0x56 0x57

12.4 PN7150 clock concept

There are 4 different clock sources in PN7150:

•27.12 MHz clock coming either/or from:

–Internal oscillator for 27.12 MHz crystal connection

–Integrated PLL unit which includes a 1 GHz VCO, taking is reference clock on pin

NFC_CLK_XTAL1

•13.56 MHz RF clock recovered from RF field

•Low-power oscillator 40 MHz

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•Low-power oscillator 380 kHz

12.4.1 27.12 MHz quartz oscillator

When enabled, the 27.12 MHz quartz oscillator applied to PN7150 is the time reference

for the RF front end when PN7150 is behaving in Reader mode or NFCIP-1 initiator.

Therefore stability of the clock frequency is an important factor for reliable operation. It is

recommended to adopt the circuit shown in Figure 9.

aaa-016745

PN7150

NFC_CLK_XTAL1 NFC_CLK_XTAL2

crystal

27.12 MHz cc

Fig 9. 27.12 MHz crystal oscillator connection

Table 12 describes the levels of accuracy and stability required on the crystal.

Table 14. Crystal requirements

Symbol Parameter Conditions Min Typ Max Unit

fxtal crystal frequency ISO/IEC and FCC

compliancy

- 27.12 - MHz

full operating range [1] -100 - +100 ppm

all VBAT range;T = 20

°C

[1] -50 - +50 ppm

Δfxtal crystal frequency accuracy

all temperature

range;VBAT = 3.6 V

[1] -50 - +50 ppm

ESR equivalent series resistance - 50 100 Ω

CLload capacitance - 10 - pF

Pxtal crystal power dissipation - - 100 μW

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC

14443 and ISO/IEC 18092, then ± 14 kHz apply.

12.4.2 Integrated PLL to make use of external clock

When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock

13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.

The 27.12 MHz of the PLL is used as the time reference for the RF front end when

PN7150 is behaving in Reader mode or ISO/IEC 18092 Initiator as well as in Target

when configured in Active Communication mode.

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The input clock on NFC_CLK_XTAL1 shall comply with the.following phase noise

requirements for the following input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz,

38.4 MHz and 52 MHz:

aaa-007232

Input reference

noise floor

-140 dBc/Hz

dBc/Hz

-20dBc/Hz

Input reference noise corner

50 kHz

Fig 10. Input reference phase noise characteristics

This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For

configuration of input frequency, refer to [9]. There are 6 pre-programmed and validated

frequencies for the PLL: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.

Table 15. PLL input requirements

Coupling: single-ended, AC coupling;

Symbol Parameter Conditions Min Typ Max Unit

- 13 - MHz

- 19.2 - MHz

- 24 - MHz

- 26 - MHz

- 38.4 - MHz

fclk clock frequency ISO/IEC and FCC

compliancy

- 52 - MHz

full operating range;frequencies

typical values:13 MHz, 26 MHz and

52 MHz

[1] -25 - +25 ppmfi(ref)acc reference input

frequency accuracy

full operating range;frequencies

typical values:19.2 MHz, 24 MHz

and

38.4 MHz

[1] -50 - +50 ppm

φnphase noise input noise floor at 50 kHz -140 - - dB/

Sinusoidal shape

Vi(p-p) peak-to-peak input

voltage

0.2 - 1.8 V

Vi(clk) clock input voltage 0 - 1.8 V

Square shape

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Symbol Parameter Conditions Min Typ Max Unit

Vi(clk) clock input voltage 0 - 1.8 ± 10 % V

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC

14443 and ISO/IEC 18092, then ± 400 ppm limits apply.

For detailed description of clock request mechanisms, refer to [5] and [6].

12.4.3 Low-power 40 MHz ± 2.5 % oscillator

Low-power OSC generates a 40 MHz internal clock. This frequency is divided by two to

make the system clock.

12.4.4 Low-power 380 kHz oscillator

A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-

up PN7150 from Standby state. This allows implementation of low-power reader polling

loop at application level. Moreover, this 380 kHz is used as the reference clock for write

access to EEPROM memory.

12.5 Power concept

12.5.1 PMU functional description

The Power Management Unit of PN7150 generates internal supplies required by PN7150

out of VBAT input supply voltage:

•VDD: internal supply voltage

•VDD(TX): output supply voltage for the RF transmitter

The Figure 11 describes the main blocks available in PMU:

aaa-016748

VBAT VDD

NFCC

BANDGAP

DSLDO

TXLDO

VBAT1 and VBAT2

VDD(TX)

Fig 11. PMU functional diagram

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12.5.2 DSLDO: Dual Supply LDO

The input pin of the DSLDO is VBAT.

The Low drop-out regulator provides VDD required in PN7150.

12.5.3 TXLDO

Transmitter voltage can be generated by internal LDO (VDD(TX)) or come from an external

supply source VDD(TX).

The regulator has been designed to work in 2 configurations:

12.5.3.1 Configuration 1: supply connection in case the battery is used to generate RF field

The Low drop Out Regulator has been designed to generate a 3.0 V, 3.3 V or 3.6 V

supply voltage to a transmitter with a current load up to 180 mA.

The output is called VDD(TX). The input supply voltage of this regulator is a battery voltage

connected to VBAT1 pin.

aaa-017002

VBAT1

NFCC

VDD(TX)

VDD(TX_IN)

VBAT2

BATTERY

Fig 12. VBAT1 = VBAT2 (between 2.3 V and 5.5 V)

VDD(TX) value shall be chosen according to the minimum targeted VBAT value for which

reader mode shall work.

•If VBAT is above 3.0 V plus the regulator voltage dropout, then VDD(TX) = 3.0 V shall be

chosen:

•If VBAT is above 3.3 V plus the regulator voltage dropout, then VDD(TX) = 3.3 V shall be

chosen:

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•If VBAT is above 3.6 V plus the regulator voltage dropout, then VDD(TX) = 3.6 V shall be

chosen:

aaa-014174

5.0 V

2.8 V

3.6 V

3.3 V

3.0 V

4.5 V 3.6 V 3.3 V 3.0 V 2.8 V

Drop = 1 Ω * load

Fig 13. VDD(TX) offset behavior

Figure 13 shows VDD(TX) offset disabled behavior for both cases of VDD(TX) programmed

for 3.0 V, 3.3 V or 3.6 V.

In Standby state, whenever VDD(TX) is configured for 3.0 V, 3.3 V or 3.6 V, VDD(TX) is

regulated at 2.5 V.

aaa-009463

VBAT

2.5 V

Fig 14. VDD(TX) behavior when PN7150 is in Standby state

Figure 14 shows the case where the PN7150 is in standby state.

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12.5.3.2 Configuration 2: supply connection in case a 5 V supply is used to generate RF

field with the use of TXLDO

TXLDO has also the possibility to generate 4.75 V or 4.5 V supply in case the supply of

this regulator is an external 5 V supply.

aaa-017003

NFCC

EXTERNAL 5 V VBAT1

VBAT2

BATTERY

VDD(TX)

VDD(TX_IN)

Fig 15. VBAT1 = 5 V, VBAT2 between 2.3 V and 5.5 V

aaa-017004

VBAT1

Drop = 1 * load

4.75 V

5.5 V

4.5 V VDD(TX)

Fig 16. VDD(TX) behavior when PN7150 is supply using external supply on VBAT1

Figure 16 shows the behavior of VDD(TX) depending on VBAT1 value.

12.5.3.3 TXLDO limiter

The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in

reader or initiator modes.

The current limiter block compares an image of the TXLDO output current to a reference.

Once the reference is reached, the output current gets limited which is equivalent to a

typical output current of 220 mA whatever VBAT or VBAT1 value in the range of 2.3 V to

5.5 V.

12.5.4 Battery voltage monitor

The PN7150 features low-power VBAT voltage monitor which protects mobile device

battery from being discharged below critical levels. When VBAT voltage goes below

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VBATcritical threshold, then the PN7150 goes in Monitor state. Refer to Figure 17 for

principle schematic of the battery monitor.

The battery voltage monitor is enabled via an EEPROM setting.

At the first start-up, VBAT voltage monitor functionality is OFF and then enabled if properly

configured in EEPROM. The PN7150 monitors battery voltage continuously.

aaa-013868

SYSTEM

MANAGEMENT

low power

DVDD_CPU

VDDD

VDD

power off

VBAT

MONITOR

REGISTERS

enable

threshold

selection

POWER SWITCHES

POWER

MANAGEMENT

DIGITAL

(memories, cpu,

etc,...)

VBAT

EEPROM

Fig 17. Battery voltage monitor principle

The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM

setting. This value has a typical hysteresis around 150 mV.

12.6 Reset concept

12.6.1 Resetting PN7150

To enter reset, there are 2 ways:

•Pulling VEN voltage low (Hard Power Down state)

•if VBAT monitor is enabled: lowering VBAT below the monitor threshold (Monitor state, if

VEN voltage is kept above 1.1 V)

Reset means resetting the embedded FW execution and the registers values to their

default values. Part of these default values is defined from EEPROM data loaded values,

others are hardware defined. See [5] to know which ones are accessible to tune PN7150

to the application environment.

To get out of reset:

•Pulling VEN voltage high with VBAT above VBAT monitor threshold if enabled

Figure 18 shows reset done via VEN pin.

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aaa-015878

host

communication

possible

tboot

tw(VEN)

VEN

VDD(PAD)

VBAT

Fig 18. Resetting PN7150 via VEN pin

See Section 16.2.2 for the timings values.

12.6.2 Power-up sequences

There are 2 different supplies for PN7150. PN7150 allows these supplies to be set up

independently, therefore different power-up sequences have to be considered.

12.6.2.1 VBAT is set up before VDD(PAD)

This is at least the case when VBAT pin is directly connected to the battery and when

PN7150 VBAT is always supplied as soon the system is supplied.

As VEN pin is referred to VBAT pin, VEN voltage shall go high after VBAT has been set.

aaa-015879

host

communication

possible

tboot

tt(VDD(PAD)-VEN)

VEN

VDD(PAD)

VBAT

Fig 19. VBAT is set up before VDD(PAD)

See Section 16.2.3 for the timings values.

12.6.2.2 VDD(PAD) and VBAT are set up in the same time

It is at least the case when VBAT pin is connected to a PMU/regulator which also supply

VDD(PAD).

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aaa-015881

host

communication

possible

tboot

tt(VBAT-VEN)

VEN

VDD(PAD)

VBAT

Fig 20. VDD(PAD) and VBAT are set up in the same time

See Section 16.2.3 for the timings values.

12.6.2.3 PN7150 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut

off

This can be the case when VBAT pin is directly connected to the battery and when

VDD(PAD) is generated from a PMU. When the battery voltage is too low, then the PMU

might no more be able to generate VDD(PAD). When the device gets charged again, then

VDD(PAD) is set up again.

As the pins to select the interface are biased from VDD(PAD), when VDD(PAD) disappears

the pins might not be correctly biased internally and the information might be lost.

Therefore it is required to make the IC boot after VDD(PAD) is set up again.

tboot

tW(VEN)

VEN

VDD(PAD)

VBAT

tt(VDD(PAD)-VEN)

aaa-015884

host

communication

possible

Fig 21. VDD(PAD) is set up or cut-off after PN7150 has been enabled

See Section 16.2.3 for the timings values.

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12.6.3 Power-down sequence

aaa-015886

tVBAT(L)

t > 0 mst > 0 ms

(nice to have)

VBAT

VEN

VDD(PAD)

PN7150Fig 22. power-down sequence

12.7 Contactless Interface Unit

PN7150 supports various communication modes at different transfer speeds and

modulation schemes. The following chapters give more detailed overview of selected

communication modes.

Remark: all indicated modulation index and modes in this chapter are system

parameters. This means that beside the IC settings a suitable antenna tuning is required

to achieve the optimum performance.

12.7.1 Reader/Writer communication modes

Generally 5 Reader/Writer communication modes are supported:

•PCD Reader/Writer for ISO/IEC 14443 type A and for MIFARE Classic

•PCD Reader/Writer for Jewel/Topaz

•PCD Reader/Writer for FeliCa

•PCD Reader/Writer for ISO/IEC 14443B

•VCD Reader/Writer for ISO/IEC 15693/ICODE

12.7.1.1 Communication mode for ISO/IEC 14443 type A, MIFARE Classic and Jewel/Topaz

PCD

The ISO/IEC 14443A and MIFARE Classic PCD communication mode is the general

reader to card communication scheme according to the ISO/IEC 14443A specification.

This modulation scheme is as well used for communications with Jewel/Topaz cards.

Figure 23 describes the communication on a physical level, the communication table

describes the physical parameters (the numbers take the antenna effect on modulation

depth for higher data rates).

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aaa-016749

NFCC

ISO/IEC 14443A -

MIFARE Classic

PCD mode

PICC (Card)

ISO/IEC 14443A -

MIFARE Classic

PCD to PICC

100 % ASK at 106 kbit/s

> 25 % ASK at 212, 424 or 848 kbit/s

Modified Miller coded

PICC to PCD,

subcarrier load modulation

Manchester coded at 106 kbit/s

BPSK coded at 212, 424 or 848 kbit/s

Fig 23. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic

Table 16. Communication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic

ISO/IEC 14443A/

MIFARE

Classic/

Jewel/ Topaz

ISO/IEC 14443A higher transfer speeds

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s

Communication

direction

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs (16/13.56) μs

PN7150 → PICC

modulation on

PN7150 side

100 % ASK > 25 % ASK > 25 % ASK > 25 % ASK(data sent by PN7150 to a

card)

bit coding Modified Miller Modified Miller Modified Miller Modified Miller

PICC → PN7150

modulation on

PICC side

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier

frequency

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

(data received by PN7150

from a card)

bit coding Manchester BPSK BPSK BPSK

The contactless coprocessor and the on-chip CPU of PN7150 handle the complete ISO/

IEC 14443A and MIFARE Classic RF-protocol, nevertheless a dedicated external host

has to handle the application layer communication.

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12.7.1.2 FeliCa PCD communication mode

The FeliCa communication mode is the general Reader/Writer to card communication

scheme according to the FeliCa specification. Figure 24 describes the communication on

a physical level, the communication overview describes the physical parameters.

aaa-016750

NFCC

ISO/IEC 18092 - FeliCa

PCD mode

PICC (Card)

FeliCa card

PCD to PICC,

8 - 12 % ASK at 212 or 424 kbits/s

Manchester coded

PICC to PCD,

load modulation

Manchester coded at 212 or 424 kbits/s

Fig 24. FeliCa Reader/Writer communication mode diagram

Table 17. Overview for FeliCa Reader/Writercommunication mode

FeliCa FeliCa higher transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

Communication direction

Bit length (64/13.56) μs (32/13.56) μs

PN7150 → PICC

modulation on

PN7150 side

8 % - 12 % ASK 8 % - 12 % ASK(data sent by PN7150 to a card)

bit coding Manchester Manchester

PICC → PN7150

modulation on PICC

side

load modulation load modulation

subcarrier frequency no subcarrier no subcarrier

(data received by PN7150 from a card)

bit coding Manchester Manchester

The contactless coprocessor of PN7150 and the on-chip CPU handle the FeliCa

protocol. Nevertheless a dedicated external host has to handle the application layer

communication.

12.7.1.3 ISO/IEC 14443B PCD communication mode

The ISO/IEC 14443B PCD communication mode is the general reader to card

communication scheme according to the ISO/IEC 14443B specification. Figure 25

describes the communication on a physical level, the communication table describes the

physical parameters.

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aaa-016751

NFCC

ISO/IEC 14443 Type B

PCD mode

PICC (Card)

ISO/IEC 14443 Type B

PCD to PICC,

8 - 14 % ASK at 106, 212, 424 or 848 kbit/s

NRZ coded

PICC to PCD,

subcarrier load modulation

BPSK coded at 106, 212, 424 or 848 kbit/s

Fig 25. ISO/IEC 14443B Reader/Writer communication mode diagram

Table 18. Overview for ISO/IEC 14443B Reader/Writer communication mode

ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s

Communication

direction

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs (16/13.56) μs

PN7150 → PICC

modulation on

PN7150 side

8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK(data sent by PN7150 to a

card)

bit coding NRZ NRZ NRZ NRZ

PICC → PN7150

modulation on

PICC side

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier

frequency

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

(data received by PN7150

from a card)

bit coding BPSK BPSK BPSK BPSK

The contactless coprocessor and the on-chip CPU of PN7150 handles the complete

ISO/IEC 14443B RF-protocol, nevertheless a dedicated external host has to handle the

application layer communication.

12.7.1.4 R/W mode for NFC forum Type 5 Tag

The R/W mode for NFC forum Type 5 Tag (T5T) is the general reader to card

communication scheme according to the ISO/IEC 15693 specification. PN7150 will

communicate with VICC (Type 5 Tag) using only the 26.48 kbit/s with single subcarrier

data rate of the VICC.

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aaa-016752

NFCC

ISO/IEC 15693

VCD mode

Card

(VICC/TAG)

ISO/IEC 15693

VCD to VICC,

100 % ASK at 26.48 kbit/s

pulse position coded

VICC to VCD,

subcarrier load modulation

Manchester coded at 26.48 kbit/s

Fig 26. R/W mode for NFC forum T5T communication diagram

Figure 26 and Table 17 show the communication schemes used.

Table 19. Communication overview for NFC forum T5T R/W mode

Communication direction

PN7150 → VICC

transfer speed 26.48 kbit/s

bit length (512/13.56) μs

modulation on PN7150 side 100 % ASK

(data sent by PN7150 to a tag)

bit coding pulse position modulation 1 out of 4 mode

VICC → PN7150

transfer speed 26.48 kbit/s

bit length (512/13.56) μs

modulation on VICC side subcarrier load modulation

subcarrier frequency single subcarrier

(data received by PN7150 from a tag)

bit coding Manchester

12.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes

An NFCIP-1 communication takes place between 2 devices:

•NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.

•NFC Target: responds to NFC Initiator command either in a load modulation scheme in

Passive communication mode or using a self-generated and self-modulated RF field for

Active communication mode.

The NFCIP-1 communication differentiates between Active and Passive communication

modes.

•Active communication mode means both the NFC Initiator and the NFC Target are

using their own RF field to transmit data

•Passive communication mode means that the NFC Target answers to an NFC

Initiator command in a load modulation scheme. The NFC Initiator is active in terms of

generating the RF field.

PN7150 supports the Active Target, Active Initiator, Passive Target and Passive Initiator

communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as

defined in the NFCIP-1 standard.

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aaa-016755

NFCC

BATTERY

NFC Target: Passive or Active Communication modesNFC Initiator: Passive or Active Communication modes

HOST

NFCC

BATTERY

HOST

Fig 27. NFCIP-1 communication mode

Nevertheless a dedicated external host has to handle the application layer

communication.

12.7.2.1 ACTIVE communication mode

Active communication mode means both the NFC Initiator and the NFC Target are using

their own RF field to transmit data.

aaa-016756

1. NFC Initiator starts the communication at selected transfer speed

2. NFC Target answers at the same transfer speed

NFCC

NFC Target

host

power

for digital

processing

NFCC

NFC Target

host

power

for digital

processing

NFC Initiator

host

power

to generate

the field

NFC Initiator

host

power

to generate

the field

Fig 28. Active communication mode

The following table gives an overview of the Active communication modes:

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Table 20. Overview for Active communication mode

ISO/IEC 18092, Ecma 340, NFCIP-1

Baud rate 106 kbit/s 212 kbit/s 424 kbit/s

Communication direction

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

NFC Initiator → NFC Target

modulation 100 % ASK 8 % - 30 % ASK[1] 8 % - 30 % ASK[1]

bit coding Modified Miller Manchester Manchester

NFC Target → NFC Initiator

modulation 100 % ASK 8 % - 30 % ASK[1] 8 % - 30 % ASK[1]

bit coding Miller Manchester Manchester

[1] This modulation index range is according to NFCIP-1 standard. It might be that some

NFC forum type 3 cards does not withstand the full range as based on FeliCa range

which is narrow (8 % to 14 % ASK).

12.7.2.2 Passive communication mode

Passive communication mode means that the NFC Target answers to an NFC Initiator

command in a load modulation scheme.

aaa-016757

1. NFC Initiator starts the communication at selected transfer speed

2. NFC Target answers using load modulation at the same transfer speed

host

power

for digital

processing

NFCC

NFC Target

host

power

for digital

processing

NFC Initiator

host

power

to generate

the field

NFC Initiator

host

power

to generate

the field

NFCC

NFC Target

Fig 29. Passive communication mode

Table 19 gives an overview of the Passive communication modes:

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Table 21. Overview for Passive communication mode

ISO/IEC 18092, Ecma 340, NFCIP-1

Baud rate 106 kbit/s 212 kbit/s 424 kbit/s

Communication direction

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

NFC Initiator → NFC Target

modulation 100 % ASK 8 % - 30 % ASK[1] 8 % - 30 % ASK[1]

bit coding Modified Miller Manchester Manchester

NFC Target → NFC Initiator

modulation subcarrier load

modulation

load modulation load modulation

subcarrier frequency 13.56 MHz/16 no subcarrier no subcarrier

bit coding Manchester Manchester Manchester

[1] This modulation index range is according to NFCIP-1 standard. It might be that some

NFC forum type 3 cards does not withstand the full range as based on FeliCa range

which is narrow (8 % to 14 % ASK). To adjust the index, see [7].

12.7.2.3 NFCIP-1 framing and coding

The NFCIP-1 framing and coding in Active and Passive communication modes are

defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340.

12.7.2.4 NFCIP-1 protocol support

The NFCIP-1 protocol is not completely described in this document. For detailed

explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard.

However the datalink layer is according to the following policy:

•Transaction includes initialization, anticollision methods and data transfer. This

sequence must not be interrupted by another transaction

•PSL shall be used to change the speed between the target selection and the data

transfer, but the speed should not be changed during a data transfer

12.7.3 Card communication modes

PN7150 can be addressed as NFC forum T3T and T4T tags. This means that PN7150

can generate an answer in a load modulation scheme according to the ISO/IEC 14443A,

ISO/IEC 14443B and the Sony FeliCa interface description.

Remark: PN7150 does not support a complete card protocol. This has to be handled by

the host controller.

Table 20, Table 21 and Table 22 describe the physical parameters.

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12.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode

Table 22. Overview for NFC forum T4T, ISO/IEC 14443A card mode

ISO/IEC 14443A ISO/IEC 14443A higher transfer speeds

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s

Communication

direction

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

PCD → PN7150

modulation on PCD

side

100 % ASK > 25 % ASK > 25 % ASK(data received by PN7150

from a card)

bit coding Modified Miller Modified Miller Modified Miller

PN7150 → PCD

modulation on

PN7150 side

subcarrier load modulation subcarrier load

modulation

subcarrier load

modulation

subcarrier

frequency

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

(data sent by PN7150 to a

card)

bit coding Manchester BPSK BPSK

12.7.3.2 NFC forum T4T, ISO/IEC 14443B card mode

Table 23. Overview for NFC forum T4T, ISO/IEC 14443B card mode

ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds

Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s

Communication

direction

Bit length (128/13.56) μs (64/13.56) μs (32/13.56) μs

PCD → PN7150

modulation on PCD

side

8 % - 14 % ASK 8 % - 14 % ASK 8 % - 14 % ASK(data received by PN7150

from a Reader)

bit coding NRZ NRZ NRZ

PN7150 → PCD

modulation on

PN7150 side

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier

frequency

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

(data sent by PN7150 to a

Reader)

bit coding BPSK BPSK BPSK

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12.7.3.3 NFC forum T3T, Sony FeliCa card mode

Table 24. Overview for NFC forum T3T, Sony FeliCa card mode

FeliCa FeliCa higher transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

Communication direction

Bit length (64/13.56) μs (32/13.56) μs

PCD → PN7150

modulation on

PN7150 side

8 % - 12 % ASK 8 % - 12 % ASK(data received by PN7150 from a Reader)

bit coding Manchester Manchester

PN7150 → PCD

modulation on PICC

side

load modulation load modulation

subcarrier frequency no subcarrier no subcarrier

(data sent by PN7150 to a Reader)

bit coding Manchester Manchester

12.7.4 Frequency interoperability

When in communication, PN7150 is generating some RF frequencies. PN7150 is also

sensitive to some RF signals as it is looking from data in the field.

In order to avoid interference with others RF communication, it is required to tune the

antenna and design the board according to [6].

Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of 13.56

MHz ± 7 kHz, FCC regulation does not allow this wide spread and limits the dispersion to

± 50 ppm, which is in line with PN7150 capability.

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13 Limiting values

Table 25. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD(PAD) VDD(PAD) supply voltage supply voltage for host

interface

- 4.35 V

VBAT battery supply voltage - 6 V

human body model

(HBM)[1] ; 1500 Ω, 100 pF

- 1.5 kVVESD electrostatic discharge voltage

charge device model

(CDM)[2] - 500 V

Tstg storage temperature -55 +150 °C

Ptot total power dissipation all modes [3] - 600 mW

VRXN(i) RXN input voltage 0 2.5 V

VRXP(i) RXP input voltage 0 2.5 V

[1] According to ANSI/ESDA/JEDEC JS-001.

[2] According to ANSI/ESDA/JEDEC JS-002

[3] The design of the solution shall be done so that for the different use cases targeted the power to be dissipated from the

field or generated by PN7150 does not exceed this value.

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14 Recommended operating conditions

Table 26. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

Tamb ambient temperature JEDEC PCB-0.5 -30 +25 +85 °C

battery monitor enabled;VSS =

0 V

[1] 2.3 - 5.5 V

Card Emulation and

Passive Target;VSS = 0 V

[1]

[2]

2.3 - 5.5 V

VBAT battery supply voltage

Reader, Active Initiator

and Active Target;VSS = 0 V

[1]

[2]

2.7 - 5.5 V

supply voltage for host

interface

•1.8 V host supply;VSS = 0 V [1] 1.65 1.8 1.95 V

VDD(PAD) VDD(PAD) supply voltage

•3 V host supply;VSS = 0 V [1] 3.0 - 3.6 V

Ptot total power dissipation Reader;IVDD(TX) = 100 mA;VBAT

= 5.5 V

- - 420 mW

in Hard Power Down

state; VBAT = 3.6 V;T = 25 °C

[3] - 10 14 μA

in Standby state;VBAT = 3.6 V;

T = 25 °C

- 20 - μA

in Monitor state;VBAT = 2.75 V;

T = 25 °C

- - 14 μA

in low-power polling

loop; VBAT = 3.6 V; T =

25 °C;loop time = 500 ms

[4] - 150 - μA

IBAT battery supply current

PCD mode at typical 3 V [5] - - 190 mA

Ith(Ilim) current limit threshold

current

current limiter on VDD(TX)

pin; VDD(TX) = 3.3 V

[5] - 180 - mA

[1] VSS represents VSS(PAD) and VSS(TX).

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when

coupling with another device must be taken into account).

[3] External clock on NFC_CLK_XTAL1 must be LOW.

[4] See [10] for computing the power consumption as it depends on several parameters.

[5] The antenna shall be tuned not to exceed the maximum of IBAT.

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15 Thermal characteristics

15.1 Thermal characteristics HVQFN40

Table 27. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance from

junction to ambient

in free air with exposed pad soldered on a

4 layer JEDEC PCB

- 40 - K/W

15.2 Thermal characteristics WLCSP42

Table 28. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance from

junction to ambient

in free air with exposed pad soldered on a

4 layer JEDEC PCB

- 42 - K/W

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16 Characteristics

16.1 Current consumption characteristics

Table 29. Current consumption characteristics for operating ambient temperature range

Symbol Parameter Conditions Min Typ Max Unit

in Hard Power Down

state; VBAT = 3.6 V; VEN

voltage = 0 V

- 10 20 μA

in Standby state;VBAT = 3.6 V; [1] - 20 35 μA

in Idle and Listener

modes; VBAT = 3.6 V

- 4.55 - mA

in Poller mode;VBAT = 3.6 V - 150 - mA

IBAT battery supply current

in Monitor state;VBAT = 2.75 V [2] - 10 20 μA

[1] Refer to Section 10.1.2 for the description of the power modes.

[2] This is the same value for VBAT = 2.3 V when the monitor threshold is set to 2.3 V.

16.2 Functional block electrical characteristics

16.2.1 Battery voltage monitor characteristics

Table 30. Battery voltage monitor characteristics

Symbol Parameter Conditions Min Typ Max Unit

set to 2.3 V 2.15 2.3 2.45 VVth threshold voltage

set to 2.75 V 2.6 2.75 2.9 V

Vhys hysteresis voltage 100 150 200 mV

16.2.2 Reset via VEN

Table 31. Reset timing

Symbol Parameter Conditions Min Typ Max Unit

tW(VEN) VEN pulse width to reset 10 - - μs

tboot boot time - - 2.5 ms

16.2.3 Power-up timings

Table 32. Power-up timings

Symbol Parameter Conditions Min Typ Max Unit

tt(VBAT-VEN) transition time from pin VBAT

to pin VEN

VBAT, VEN

voltage = HIGH

0 0.5 - ms

tt(VDDPAD-VEN) transition time from pin

VDD(PAD) to pin VEN

VDD(PAD), VEN

voltage = HIGH

0 0.5 - ms

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Symbol Parameter Conditions Min Typ Max Unit

tt(VBAT-VDDPAD) transition time from pin VBAT

to pin VDD(PAD)

VBAT,VDD(PAD) =

HIGH

0 0.5 - ms

16.2.4 Power-down timings

Table 33. Power-down timings

Symbol Parameter Conditions Min Typ Max Unit

tVBAT(L) time VBAT LOW 20 - - ms

16.2.5 I2C-bus timings

Here below are timings and frequency specifications.

aaa-017006

I2CSDA

I2CSCL

tr(I2CSDA) tHD;DAT

tSU;DAT

tLOW

tHIGH

tHD;STA

tSU;STA

tf(I2CSDA)

Fig 30. I2C-bus timings

Table 34. High-speed mode I2C-bus timings specification

Symbol Parameter Conditions Min Max Unit

fclk(I2CSCL) clock frequency on pin

I2CSCL

I2C-bus SCL;Cb < 100

0 3.4 MHz

tSU;STA set-up time for a repeated

START condition

Cb < 100 pF 160 - ns

tHD;STA hold time (repeated) START

condition

Cb < 100 pF 160 - ns

tLOW LOW period of the SCL clock Cb < 100 pF 160 - ns

tHIGH HIGH period of the SCL clock Cb < 100 pF 60 - ns

tSU;DAT data set-up time Cb < 100 pF 10 - ns

tHD;DAT data hold time Cb < 100 pF 0 - ns

tr(I2CSDA) rise time on pin I2CSDA I2C-bus SDA;Cb < 100

10 80 ns

tf(I2CSDA) fall time on pin I2CSDA I2C-bus SDA;Cb < 100

10 80 ns

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Symbol Parameter Conditions Min Max Unit

Vhys hysteresis voltage Schmitt trigger

inputs;Cb < 100 pF

0.1VDD(PAD) - V

Table 35. Fast mode I2C-bus timings specification

Symbol Parameter Conditions Min Max Unit

fclk(I2CSCL) clock frequency on pin I2CSCL I2C-bus SCL;Cb < 400

0 400 kHz

tSU;STA set-up time for a repeated

START condition

Cb < 400 pF 600 - ns

tHD;STA hold time (repeated) START

condition

Cb < 400 pF 600 - ns

tLOW LOW period of the SCL clock Cb < 400 pF 1.3 - μs

tHIGH HIGH period of the SCL clock Cb < 400 pF 600 - ns

tSU;DAT data set-up time Cb < 400 pF 100 - ns

tHD;DAT data hold time Cb < 400 pF 0 900 ns

Vhys hysteresis voltage Schmitt trigger

inputs;Cb < 400 pF

0.1VDD(PAD) - V

16.3 Pin characteristics

16.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins characteristics

Table 36. Input clock characteristics on NFC_CLK_XTAL1 when using PLL

Symbol Parameter Conditions Min Typ Max Unit

Vi(p-p) peak-to-peak input voltage 0.2 - 1.8 V

δ duty cycle 35 - 65 %

Table 37. Pin characteristics for NFC_CLK_XTAL1 when PLL input

Symbol Parameter Conditions Min Typ Max Unit

IIH HIGH-level input current VI = VDD -1 - +1 μA

IIL LOW-level input current VI = 0 V -1 - +1 μA

Viinput voltage - - VDD V

Vi(clk)(p-p) peak-to-peak clock input

voltage

200 - - mV

Ciinput capacitance all power modes - 2 - pF

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Table 38. Pin characteristics for 27.12 MHz crystal oscillator

Symbol Parameter Conditions Min Typ Max Unit

Ci(NFC_CLK_XTAL1) NFC_CLK_XTAL1 input

capacitance

VDD = 1.8 V - 2 - pF

Ci(NFC_CLK_XTAL2) NFC_CLK_XTAL2 input

capacitance

- 2 - pF

Table 39. PLL accuracy

Symbol Parameter Conditions Min Typ Max Unit

fo(acc) output frequency

accuracy

deviation added to

NFC_CLK_XTAL1

frequency on RF frequency

generated;worst case whatever

input frequency

-50 - +50 ppm

16.3.2 VEN input pin characteristics

Table 40. VEN input pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 1.1 - VBAT V

VIL LOW-level input voltage 0 - 0.4 V

IIH HIGH-level input current VEN voltage = VBAT -1 - +1 μA

IIL LOW-level input current VEN voltage = 0 V -1 - +1 μA

Ciinput capacitance - 5 - pF

16.3.3 Pin characteristics for IRQ and CLK_REQ

Table 41. pin characteristics for IRQ and CLK_REQ

Symbol Parameter Conditions Min Typ Max Unit

VOH HIGH-level output

voltage

IOH < 3 mA VDD(PAD) - 0.4 - VDD(PAD) V

VOL LOW-level output

voltage

IOL < 3 mA 0 - 0.4 V

CLload capacitance - - 20 pF

CL = 12 pF max

•high speed 1 - 3.5 ns

tffall time

•slow speed 2 - 10 ns

CL = 12 pF max

•high speed 1 - 3.5 ns

trrise time

•slow speed 2 - 10 ns

Rpd pull-down resistance [1] 0.35 - 0.85 MΩ

[1] Activated in HPD and Monitor states.

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16.3.4 Input pin characteristics for RXN and RXP

Table 42. Input pin characteristics for RXN and RXP

Symbol Parameter Conditions Min Typ Max Unit

VRXN(i) RXN input voltage 0 - VDD V

VRXP(i) RXP input voltage 0 - VDD V

Ci(RXN) RXN input capacitance - 12 - pF

Ci(RXP) RXP input capacitance - 12 - pF

Zi(RXN-

VDDMID)

input impedance between

RXN and VDD(MID)

Reader, Card and

P2P modes

0 - 15 kΩ

Zi(RXP-

VDDMID)

input impedance between

RXP and VDD(MID)

Reader, Card and

P2P modes

0 - 15 kΩ

Miller coded

•106 kbit/s - 150 200 mV(p-p)

Vi(dyn)(RXN) RXN dynamic input voltage

•212 kbit/s to

424 kbit/s

- 150 200 mV(p-p)

Miller coded

•106 kbit/s - 150 200 mV(p-p)

Vi(dyn)(RXP) RXP dynamic input voltage

•212 kbit/s to

424 kbit/s

- 150 200 mV(p-p)

Vi(dyn)(RXN) RXN dynamic input voltage Manchester, NRZ

or BPSK

coded;106

kbit/s to 848 kbit/s

- 150 200 mV(p-p)

Vi(dyn)(RXP) RXP dynamic input voltage Manchester, NRZ

or BPSK

coded;106

kbit/s to 848 kbit/s

- 150 200 mV(p-p)

Vi(dyn)(RXN) RXN dynamic input voltage All data coding;106

kbit/s to

848 kbit/s

VDD - - V(p-p)

Vi(dyn)(RXP) RXP dynamic input voltage All data coding;106

kbit/s to

848 kbit/s

VDD - - V(p-p)

Vi(RF) RF input voltage RF input voltage

detected; Initiator

modes

100 - mV(p-p)

16.3.5 Output pin characteristics for TX1 and TX2

Table 43. Output pin characteristics for TX1 and TX2

Symbol Parameter Conditions Min Typ Max Unit

VOH HIGH-level output

voltage

VDD(TX) = 3.3 V and

IOH = 30 mA;PMOS

driver fully on

VDD(TX) - 150 - - mV

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Symbol Parameter Conditions Min Typ Max Unit

VOL LOW-level output

voltage

VDD(TX) = 3.3 V and

IOL = 30 mA;NMOS

driver fully on

- - 200 mV

Table 44. Output resistance for TX1 and TX2

Symbol Parameter Conditions Min Typ Max Unit

ROL LOW-level output

resistance

VDD(TX) - 100

mV;CWGsN = 01h

- - 85 Ω

ROL LOW-level output

resistance

VDD(TX) - 100

mV;CWGsN = 0Fh

- - 5 Ω

ROH HIGH-level

output

resistance

VDD(TX) - 100 mV - - 4 Ω

16.3.6 Input pin characteristics for I2CADR0 and I2CADR1

Table 45. Input pin characteristics for I2CADR0 and I2CADR1

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input

voltage

0.65VDD(PAD) - VDD(PAD) V

VIL LOW-level input

voltage

0 - 0.35VDD(PAD) V

IIH HIGH-level input

current

VI = VDD(PAD) -1 - +1 μA

IIL LOW-level input

current

VI = 0 V -1 - +1 μA

Ciinput capacitance - 5 - pF

16.3.7 Pin characteristics for I2CSDA and I2CSCL

Table 46. Pin characteristics for I2CSDA and I2CSCL

Symbol Parameter Conditions Min Typ Max Unit

VOL LOW-level output

voltage

IOL < 3 mA [1] 0 - 0.4 V

CLload capacitance - - 10 pF

tffall time CL = 100 pF;Rpull-up = 2

kΩ;Standard and Fast mode

[1] 30 - 250 ns

tffall time CL = 100 pF;Rpull-up = 1

kΩ;High-speed mode

[1] 80 - 110 ns

trrise time CL = 100 pF;Rpull-up = 2

kΩ;Standard and Fast mode

[1] 30 - 250 ns

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Symbol Parameter Conditions Min Typ Max Unit

CL = 100 pF;

Rpull-up = 1 kΩ;

High-speed mode

[1] 10 - 100 ns

VIH HIGH-level input

voltage

0.7VDD(PAD) - VDD(PAD) V

VIL LOW-level input

voltage

0 - 0.3VDD(PAD) V

IIH HIGH-level input

current

VI = VDD(PAD);high impedance -1 - +1 μA

IIL LOW-level input

current

VI = 0 V;high impedance -1 - +1 μA

Ciinput capacitance - 5 - pF

[1] Only for pin I2CSDA as I2CSCL is only used as input.

16.3.8 VDD pin characteristic

Table 47. Electrical characteristic of VDD

Symbol Parameter Conditions Min Typ Max Unit

VDD VDD supply voltage VSS = 0 V 1.65 1.8 1.95 V

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17 Package outline

17.1 Package outline HVQFN40

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT618-1 MO-220

sot618-1_po

02-10-22

13-11-05

Unit

max

nom

min

1.00 0.05 0.2 6.1 4.25 6.1

0.4

A(1)

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;

40 terminals; body 6 x 6 x 0.85 mm SOT618-1

A1b

0.30

c D(1) DhE(1) Eh

4.10

e e1e2L v w

0.05

0.1

0.85 0.02 6.0 4.10 6.00.21

0.33.950.80 0.00 5.9 3.95 5.90.18

0.5 4.5 0.54.25 4.5 0.1

1/2 e

terminal 1

index area

AA1

11 20

40 31

terminal 1

index area

0 2.5 5 mm

scale

detail X

B A

Figure 6. Package outline, HVQFN40, SOT618-1, MSL3

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17.2 Package outline WLCSP42

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT1459-1 - - - - - -

sot1459-1_po

16-09-01

16-09-02

Unit

max

nom

min

0.29 2.90 2.82

2.0 0.15 0.05

Dimensions (mm are the original dimensions)

WLCSP42: wafer level chip-scale package; 42 bumps; 2.88 x 2.80 x 0.54 mm (Backside coating included) SOT1459-1

A1A2

0.37

0.31

0.26 2.88 2.80 0.4

b D E e e1

2.4

e2v w

0.05

0.23 2.86 2.78

0.34

0.23

0.17

0.20

0.58

0.50

0.54

scale

3 mm

detail X

ball A1

index area

7654321

bAC BØ v

CØ w

ball A1

index area

1/2 e

Note: Backside coating 40 µm

Figure 7. Package outline, WLCSP42, SOT1459-1

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18 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 "Surface mount reflow

soldering description".

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached

to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides

both the mechanical and the electrical connection. There is no single soldering method

that is ideal for all IC packages. Wave soldering is often preferred when through-hole

and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is

not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming

from a standing wave of liquid solder. The wave soldering process is suitable for the

following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

NXP Semiconductors PN7150

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Product data sheet Rev. 4.0 — 25 June 2020

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•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads

to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board

is heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder

paste characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with Table

45 and 46

Table 48. SnPb eutectic process (from J-STD-020D)

Package reflow temperature (°C)

Volume (mm3)

Package thickness (mm)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 49. Lead-free process (from J-STD-020D)

Package reflow temperature (°C)

Volume (mm3)

Package thickness (mm)

< 350 350 to 2 000 > 2 000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 32.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

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001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

MSL: Moisture Sensitivity Level

Fig 32. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

"Surface mount reflow soldering description".

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 57 / 66

19 Abbreviations

Table 50. Abbreviations

Acronym Description

API Application Programming Interface

ASK Amplitude Shift keying

ASK modulation

index

The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/

(Vmax + Vmin) × 100%

Automatic device

discovery

Detect and recognize any NFC peer devices (initiator or target) like: NFC

initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Classic

and MIFARE Ultralight PICC, ISO/IEC 15693 VICC

BPSK Bit Phase Shift Keying

Card Emulation The IC is capable of handling a PICC emulation on the RF interface including

part of the protocol management. The application handling is done by the

host controller

DEP Data Exchange Protocol

DSLDO Dual Supplied LDO

FW FirmWare

HPD Hard Power Down

LDO Low Drop Out

LFO Low Frequency Oscillator

MOSFET Metal Oxide Semiconductor Field Effect Transistor

MSL Moisture Sensitivity Level

NCI NFC Controller Interface

NFC Near Field Communication

NFCC NFC Controller, PN7150 in this data sheet

NFC Initiator Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication

NFCIP NFC Interface and Protocol

NFC Target Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication

NRZ Non-Return to Zero

P2P Peer to Peer

PCD Proximity Coupling Device. Definition for a Card reader/writer device

according to the ISO/IEC 14443 specification or MIFARE Classic

PCD -> PICC Communication flow between a PCD and a PICC according to the

ISO/IEC 14443 specification or MIFARE Classic

PICC Proximity Interface Coupling Card. Definition for a contactless Smart Card

according to the ISO/IEC 14443 specification or MIFARE Classic

PICC-> PCD Communication flow between a PICC and a PCD according to the

ISO/IEC 14443 specification or MIFARE Classic

PMOS P-channel MOSFET

PMU Power Management Unit

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 58 / 66

Acronym Description

PSL Parameter SeLection

TXLDO Transmitter LDO

UM User Manual

VCD Vicinity Coupling Device. Definition for a reader/writer device according to the

ISO/IEC 15693 specification

VCO Voltage Controlled Oscillator

VICC Vicinity Integrated Circuit Card

WUC Wake-Up Counter

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 59 / 66

20 References

[1] NFC Forum Device Requirements V1.3

[2] NFC Controller Interface (NCI) Technical Specification V1.0

[3] ISO/IEC 14443 parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1 2006

(01/09/2006) and part 4: 2nd edition 2008 (15/07/2008)

[4] I2C Specification, UM10204 rev4 (13/02/2012), https://www.nxp.com/docs/en/user-

guide/UM10204.pdf

[5] UM10936 PN7150 User Manual, https://www.nxp.com/docs/en/user-guide/

UM10936.pdf

[6] AN11756 PN7150 Hardware Design Guide, https://www.nxp.com/docs/en/

application-note/AN11756.pdf

[7] AN11755 PN7150 Antenna design and matching guide, https://www.nxp.com/docs/

en/application-note/AN11755.pdf

[8] ISO/IEC 18092 (NFCIP-1) edition, 15/032013. This is similar to Ecma 340.

[9] ISO/IEC 15693 part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001)

[10] AN11757 PN7150 Low-Power Mode Configuration, https://www.nxp.com/docs/en/

application-note/AN11757.pdf

[11] ISO/IEC 21481 (NFCIP-2) edition, 01/07/2012. This is similar to Ecma 352.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 60 / 66

21 Revision history

Table 51. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PN7150 v4.0 20200625 Product data sheet - PN7150 v3.9

Modifications: •Included new product type PN7150B0HN/C11006

•Marked PN7150B0UK/C11002 to be come discontinued

•Added information about withdrawal of PN7150B0HN/C11004

PN7150 v3.9 20190828 Product data sheet - PN7150 v3.8

Modifications: •Added a version history of the different firmware versions, see Section 6

PN7150 v3.8 20181030 Product data sheet - PN7150 v3.7

Modifications: •Added an important note regarding EEPROM memory to chapter "Functional description".

PN7150 v3.7 20180424 Product data sheet - PN7150 v3.6

Modifications: •Fixed some cross references in chapter 11.6

PN7150 v3.6 20171127 Product data sheet - PN7150 v3.5

Modifications: •Minor typos corrected.

•Included new product type PN7150B0UK/C11002

PN7150 v3.5 20171018 Product data sheet - PN7150 v3.4

Modifications: •Table 19 (Communication overview for NFC Forum T5T R/W mode) updated.

PN7150 v3.4 20171004 Product data sheet - PN7150 v3.3

Modifications: •Descriptive title updated

•Section 2: Figure 1 updated

•MIFARE branding upated

PN7150 v3.3 20160704 Product data sheet - PN7150 v3.2

Modifications: •Figure 1: updated.

•Section 10.7.1.4: updated.

•Section 10.7.3: updated.

PN7150 v3.2 201600525 Product data sheet - PN7150 v3.1

PN7150 v3.1 20160511 Product data sheet - PN7150 v3.0

PN7150 v3.0 20151209 Product data sheet - PN7150 v2.1

PN7150 v2.1 20151127 Preliminary data sheet - PN7150 v2.0

PN7150 v2.0 20150701 Preliminary data sheet - PN7150 v1.2

PN7150 v1.2 20150625 Objective data sheet - PN7150 v1.1

PN7150 v1.1 20150212 Objective data sheet - PN7150 v1.0

PN7150 v1.0 20150129 Objective data sheet - -

Modifications: •Initial version

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

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22 Legal information

22.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

22.2 Definitions

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 62 / 66

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Security — While NXP Semiconductors has implemented advanced

security features, all products may be subject to unidentified vulnerabilities.

Customers are responsible for the design and operation of their applications

and products to reduce the effect of these vulnerabilities on customer’s

applications and products, and NXP Semiconductors accepts no liability for

any vulnerability that is discovered. Customers should implement appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

22.4 Licenses

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

RATP/Innovatron

Technology

This NXP Semiconductors IC is ISO/IEC

14443 Type B software enabled and is

licensed under Innovatron’s Contactless

Card patents license for ISO/IEC 14443 B.

The license includes the right to use the IC

in systems and/or end-user equipment.

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of the

Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/

IEC 21481 does not convey an implied license under any patent right

infringed by implementation of any of those standards. Purchase of NXP

Semiconductors IC does not include a license to any NXP patent (or other

IP right) covering combinations of those products with other products,

whether hardware or software.

22.5 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

MIFARE — is a trademark of NXP B.V.

DESFire — is a trademark of NXP B.V.

ICODE and I-CODE — are trademarks of NXP B.V.

MIFARE Ultralight — is a trademark of NXP B.V.

MIFARE Classic — is a trademark of NXP B.V.

NXP — wordmark and logo are trademarks of NXP B.V.

AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE,

Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle,

Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,

Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS,

ULINKpro, µVision, Versatile — are trademarks or registered trademarks

of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related

technology may be protected by any or all of patents, copyrights, designs

FeliCa — is a trademark of Sony Corporation.

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 63 / 66

Tables

Tab. 1. Quick reference data .........................................5

Tab. 2. Ordering information ..........................................7

Tab. 3. Marking codes ...................................................8

Tab. 4. WLCSP package marking (top view) .................9

Tab. 5. Pin description .................................................11

Tab. 6. WLCSP package marking (top view) ...............13

Tab. 7. System power modes description ................... 16

Tab. 8. System power modes configuration ................ 17

Tab. 9. System power modes description ................... 17

Tab. 10. PN7150 power states ......................................17

Tab. 11. Functional modes in active state .....................19

Tab. 12. Functionality for I2C-bus interface ...................22

Tab. 13. I2C-bus interface addressing .......................... 22

Tab. 14. Crystal requirements ....................................... 23

Tab. 15. PLL input requirements ...................................24

Tab. 16. Communication overview for ISO/IEC 14443

type A and read/write mode for MIFARE

Classic ............................................................. 33

Tab. 17. Overview for FeliCa Reader/

Writercommunication mode .............................34

Tab. 18. Overview for ISO/IEC 14443B Reader/

Writer communication mode ............................35

Tab. 19. Communication overview for NFC forum

T5T R/W mode ................................................36

Tab. 20. Overview for Active communication mode .......38

Tab. 21. Overview for Passive communication mode ....39

Tab. 22. Overview for NFC forum T4T, ISO/IEC

14443A card mode ..........................................40

Tab. 23. Overview for NFC forum T4T, ISO/IEC

14443B card mode ..........................................40

Tab. 24. Overview for NFC forum T3T, Sony FeliCa

card mode ....................................................... 41

Tab. 25. Limiting values ................................................ 42

Tab. 26. Operating conditions ....................................... 43

Tab. 27. Thermal characteristics ................................... 44

Tab. 28. Thermal characteristics ................................... 44

Tab. 29. Current consumption characteristics for

operating ambient temperature range ............. 45

Tab. 30. Battery voltage monitor characteristics ............45

Tab. 31. Reset timing .................................................... 45

Tab. 32. Power-up timings ............................................ 45

Tab. 33. Power-down timings ........................................ 46

Tab. 34. High-speed mode I2C-bus timings

specification .....................................................46

Tab. 35. Fast mode I2C-bus timings specification .........47

Tab. 36. Input clock characteristics on NFC_CLK_

XTAL1 when using PLL .................................. 47

Tab. 37. Pin characteristics for NFC_CLK_XTAL1

when PLL input ............................................... 47

Tab. 38. Pin characteristics for 27.12 MHz crystal

oscillator .......................................................... 48

Tab. 39. PLL accuracy .................................................. 48

Tab. 40. VEN input pin characteristics .......................... 48

Tab. 41. pin characteristics for IRQ and CLK_REQ .......48

Tab. 42. Input pin characteristics for RXN and RXP ......49

Tab. 43. Output pin characteristics for TX1 and TX2 .....49

Tab. 44. Output resistance for TX1 and TX2 .................50

Tab. 45. Input pin characteristics for I2CADR0 and

I2CADR1 ......................................................... 50

Tab. 46. Pin characteristics for I2CSDA and I2CSCL .... 50

Tab. 47. Electrical characteristic of VDD .......................51

Tab. 48. SnPb eutectic process (from J-STD-020D) ..... 55

Tab. 49. Lead-free process (from J-STD-020D) ............ 55

Tab. 50. Abbreviations ...................................................57

Tab. 51. Revision history ...............................................60

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 64 / 66

Figures

Fig. 1. PN7150 transmission modes ............................ 2

Fig. 2. PN7150 package marking HVQFN40 (top

view) 4 lines ...................................................... 8

Fig. 3. PN7150 package marking HVQFN40 (top

view) 3 lines ...................................................... 8

Fig. 4. WLCSP42 ..........................................................9

Fig. 5. WLCSP42 pinning (bottom view) .................... 13

Fig. 6. Package outline, HVQFN40, SOT618-1,

MSL3 ............................................................... 52

Fig. 7. Package outline, WLCSP42, SOT1459-1 ........53

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Product data sheet Rev. 4.0 — 25 June 2020

COMPANY PUBLIC 317440 65 / 66

Contents

1 Introduction ......................................................... 1

2 General description ............................................ 2

3 Features and benefits .........................................3

4 Applications .........................................................4

5 Quick reference data .......................................... 5

6 Versions ............................................................... 6

6.1 Version C11006 ................................................. 6

6.2 Version C11004 ................................................. 6

6.3 Version C11002 ................................................. 6

7 Ordering information .......................................... 7

8 Marking HVQFN40 ...............................................8

9 Marking WLCSP42 .............................................. 9

10 Block diagram ................................................... 10

11 Pinning information .......................................... 11

11.1 Pinning HVQFN40 ........................................... 11

11.2 Pinning WLCSP42 ........................................... 13

12 Functional description ......................................15

12.1 System modes .................................................16

12.1.1 System power modes ......................................16

12.1.2 PN7150 power states ...................................... 17

12.1.2.1 Monitor state ....................................................18

12.1.2.2 Hard Power Down (HPD) state ........................18

12.1.2.3 Standby state ...................................................18

12.1.2.4 Active state ...................................................... 19

12.1.2.5 Polling loop ...................................................... 19

12.2 Microcontroller ................................................. 21

12.3 Host interface .................................................. 21

12.3.1 I2C-bus interface ............................................. 21

12.3.1.1 I2C-bus configuration .......................................22

12.4 PN7150 clock concept .....................................22

12.4.1 27.12 MHz quartz oscillator .............................23

12.4.2 Integrated PLL to make use of external clock ...23

12.4.3 Low-power 40 MHz ± 2.5 % oscillator ............. 25

12.4.4 Low-power 380 kHz oscillator ..........................25

12.5 Power concept .................................................25

12.5.1 PMU functional description .............................. 25

12.5.2 DSLDO: Dual Supply LDO .............................. 26

12.5.3 TXLDO ............................................................. 26

12.5.3.1 Configuration 1: supply connection in case

the battery is used to generate RF field ...........26

12.5.3.2 Configuration 2: supply connection in case a

5 V supply is used to generate RF field with

the use of TXLDO ........................................... 28

12.5.3.3 TXLDO limiter .................................................. 28

12.5.4 Battery voltage monitor ....................................28

12.6 Reset concept ..................................................29

12.6.1 Resetting PN7150 ............................................29

12.6.2 Power-up sequences ....................................... 30

12.6.2.1 VBAT is set up before VDD(PAD) ................... 30

12.6.2.2 VDD(PAD) and VBAT are set up in the same

time .................................................................. 30

12.6.2.3 PN7150 has been enabled before

VDD(PAD) is set up or before VDD(PAD)

has been cut off .............................................. 31

12.6.3 Power-down sequence .................................... 32

12.7 Contactless Interface Unit ............................... 32

12.7.1 Reader/Writer communication modes ..............32

12.7.1.1 Communication mode for ISO/IEC 14443

type A, MIFARE Classic and Jewel/Topaz

PCD ................................................................. 32

12.7.1.2 FeliCa PCD communication mode ...................34

12.7.1.3 ISO/IEC 14443B PCD communication mode ... 34

12.7.1.4 R/W mode for NFC forum Type 5 Tag .............35

12.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1

communication modes .....................................36

12.7.2.1 ACTIVE communication mode .........................37

12.7.2.2 Passive communication mode ......................... 38

12.7.2.3 NFCIP-1 framing and coding ........................... 39

12.7.2.4 NFCIP-1 protocol support ................................39

12.7.3 Card communication modes ............................ 39

12.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode ... 40

12.7.3.2 NFC forum T4T, ISO/IEC 14443B card mode ...40

12.7.3.3 NFC forum T3T, Sony FeliCa card mode ........ 41

12.7.4 Frequency interoperability ............................... 41

13 Limiting values .................................................. 42

14 Recommended operating conditions .............. 43

15 Thermal characteristics ....................................44

15.1 Thermal characteristics HVQFN40 .................. 44

15.2 Thermal characteristics WLCSP42 .................. 44

16 Characteristics .................................................. 45

16.1 Current consumption characteristics ................45

16.2 Functional block electrical characteristics ........ 45

16.2.1 Battery voltage monitor characteristics ............ 45

16.2.2 Reset via VEN .................................................45

16.2.3 Power-up timings ............................................. 45

16.2.4 Power-down timings ........................................ 46

16.2.5 I2C-bus timings ................................................46

16.3 Pin characteristics ............................................47

16.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2

pins characteristics .......................................... 47

16.3.2 VEN input pin characteristics ...........................48

16.3.3 Pin characteristics for IRQ and CLK_REQ .......48

16.3.4 Input pin characteristics for RXN and RXP ...... 49

16.3.5 Output pin characteristics for TX1 and TX2 ..... 49

16.3.6 Input pin characteristics for I2CADR0 and

I2CADR1 ..........................................................50

16.3.7 Pin characteristics for I2CSDA and I2CSCL .... 50

16.3.8 VDD pin characteristic ..................................... 51

17 Package outline .................................................52

17.1 Package outline HVQFN40 ..............................52

17.2 Package outline WLCSP42 ............................. 53

18 Soldering of SMD packages .............................54

18.1 Introduction to soldering .................................. 54

18.2 Wave and reflow soldering .............................. 54

18.3 Wave soldering ................................................54

18.4 Reflow soldering .............................................. 54

19 Abbreviations .................................................... 57

20 References ......................................................... 59

21 Revision history ................................................ 60

22 Legal information .............................................. 61

NXP Semiconductors PN7150

High performance NFC controller with integrated firmware, supporting all NFC Forum modes

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 June 2020

Document number: 317440