ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
- 1 -
GENERA L DESCRI P TIO N
T he AK43 40 offe rs the idea l features for consumer systems tha t require a 2Vrms audio output . Using
AKM's multi bit architecture for its modulator the AK4340 delivers a wide dynamic range while preserving
lineari ty for im proved THD+N performance. The AK4340 integrates the Swi tched Capacitor Filter (SCF)
increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz
sampling rate make this part ideal for a wide range of applications including Set-top-box, DVD-Audio. The
AK 4340 is offere d in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ra nging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched Capacitor Filter wit h High Tolerance to Clock Jitter
On chip Buffer with 2 Vrms Single -ended output
Digita l De-emphasis F ilter: 32kHz , 44 . 1kHz o r 48kHz
Soft Mute Function
Digital A tte n ua tor (L ine ar 25 6 Ste p)
Audio interfac e format: 24Bit MSB justified, 24/20 /16 LSB jus tified or
I2S co mpat ibl e
Maste r cl oc k: 256fs, 384fs, 51 2fs, 768fs or 11 52fs (Normal Speed Mode)
128fs, 192fs, 256fs or 512fs (Double Speed Mode)
128fs or 192fs (Quad Spee d Mode)
THD+N: -90dB
Dynamic Range: 106dB
Po wer su p pl y: +4. 5 V to +5 .5 V (DAC), - 4.5V to - 13.2V (Output Buffer)
Ta = - 20 to 85 °C
Package: 16pin T SSO P (6.4 mm x 5. 0mm)
192kHz 24-Bit Stereo ∆Σ DAC wi t h 2 V rms O ut put
AK4340
LRC
K
BICK
SDTI
Audio
Data
Interface
MCLK
PDN
∆Σ
Modulator
A
OUTL
8X
Interpolator SCF
LPF
AOUTR
V
DD
V
SS
De-emphasis
Control
P/S
µP
In terface
Clock
Divider
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
∆Σ
Modulator
8X
Interpolator
HVEE
SCF
LPF
ATT
ATT
GAIN
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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Ordering Gui de
AK4340ET -20
∼ +85°C 16pin TSSO P (0. 65mm pitch)
AKD4340 Evaluation board for AK4340
Pin Layo ut
1
MCLK
LRCK
BICK
SMUTE/CSN
A
CKS/CCLK
DIF0/CDTI
Top
View
2
3
4
5
6
7
8
GAIN
NC
VSS
VDD
HVEE
AOUTL
AOUTR
P/S
16
15
14
13
12
11
10
9
PDN
SDTI
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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PIN / FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be i nput on this pin.
2 BICK I Audi o Ser i a l Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 L RCK I L/R Clock Pin
5 PDN I Power - D own M ode Pin
When at “L”, th e AK4340 is in the power -down mode and is held in reset.
The AK4340 must be reset once upon power -up.
SMUTE I
Soft Mute Pin in parallel control mode
“H”: En a ble, “L”: Di sa ble
6 CSN I Chip Sel ect Pin in ser ial control mode
ACKS I
Auto Set tin g Mode Pin in parallel contr ol mode
“L”: Manual Settin g Mode, “H” : Auto Settin g Mod e
7 CCLK I Control Dat a Clock Pin in serial control mode
DI F0 I Au di o Data In terface For m at Pi n in paral l el con trol m ode
8 CDTI I Contr ol Dat a Input Pin in seria l con trol mode
9 AOUTR O Rch Analog Ou tput Pin
10 AOUTL O Lch Analog Output Pin
11 HVEE - Output Buffer Negative Power Supply Pin
No rmally conne cte d to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap .
12 VSS - Ground Pin
13 VDD - DAC Power Supply Pin
14 P/S I Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel contr ol mode
15 NC - No connect
No in ternal banding (Note)
16 GAIN I Output Gain Select Pin
“L”: 0dB, “H”: +1.94dB
Note: Do not all ow digital in put pins except pull-u p pin to float.
Note: Pi n No.1 5 (NC) h as n o int er n al bonding an d ca n be left Op en , conn ect ed GND or VDD.
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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ABSOLUTE MAXIMU M R ATINGS
(VSS= 0 V; Not e 1 )
Parameter Symbol min max Units
Power Su p p l y D AC
O u tpu t Bu ffe r VDD
HVEE -0.3
-14.0 +6.0
0.3 V
V
Input Curr ent (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 VDD+0.3 V
Ambi ent Operating Temperature Ta -2 0 85 °C
Storage Temperature Tstg -65 150 °C
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Norma l operation is not guaranteed at these extremes.
RECOMMENDED OPERAT I NG CONDITIONS
(VSS= 0 V; Not e 1 )
Parameter Symbol min typ max Units
Power Su p p l y DAC
Output Bu ffer VDD
HVEE +4.5
-13.2 +5.0
-5.0 +5.5
-4.5 V
V
Note 1. All voltages with respect to ground.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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ANAL O G CHARA CTERISTICS
(Ta=25°C; VDD=+5.0VV; HVEE=-5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measu rement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; u n less other wise specifi ed)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characterist i cs (Not e 2)
fs=44.1kHz
BW=20kHz 0dBFS
-60dBFS -90
-42 -84
- dB
dB
fs=96kHz
BW=40kHz 0dBFS
-60dBFS -90
-39 -
- dB
dB
THD+N
fs=192kHz
BW=40kHz 0dBFS
-60dBFS -90
-39 -
- dB
dB
Dynamic Range (-60dBFS with A-weighted) (Note 3) 100 106 dB
S/N (A-weighted) (Note 4) 100 106 dB
Interchannel Isolation (1kHz) 90 100 dB
Interchannel Gain M is match 0.2 0.5 dB
DC Accuracy
Gain Drift 100 - ppm/°C
GAIN pin = “L” 1.85 2 2.15 Vrms Output Voltage (Note 5) GAIN pin = “H” 2.35 2.5 2.65 Vrms
Load Capacitance (Note 6) 25 pF
Load Resist a n ce 5 kΩ
Power Suppl ies
Power Supply Curren t: (Note 7)
Nor mal Operation (PDN pin = “H”, fs≤96kHz)
VDD
HVEE
Normal Operation (PDN pin = “H”, fs=192kHz)
VDD
HVEE
Power-Down Mode (PDN pin = “L”) ( N ote 8)
VDD
HVEE
22
6
25
6
10
10
30
9
33
9
100
100
mA
mA
mA
mA
µA
µA
No te 2 . Me asured b y Audi o Pre cis ion (S y ste m Two ). GAIN p in = “L ”. R efe r to the e valuatio n b oard manual re gard ing the
measurement results.
Note 3. 98dB at 16bit data
Note 4. S/N r a t i on does n ot dep end on t h e i n pu t da ta l ength
Note 5. Full-scale voltage (0dB). Output voltage is proportional to VDD voltage.
AOUT (typ.@ 0dB, GAIN = 0dB) = 2Vrms × VDD/5.
Note 6. When the output pin d rives a capacitive load, a resistor should be added in series between output pin and
capacitive load.
Note 7. These valu es ar e sup pl ied to VDD pin or HVEE pi n.
No t e 8. P/S pin is tie d to VDD and the o ther all digital inputs i nclud ing c lo c k pins (MCLK, BICK and LR CK) are tied to
VDD or VSS .
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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FILTER CHARACTERISTICS
(Ta = 25°C; VDD = +4.5 ∼ +5.5V, HVEE = -13.2 ∼ -4.5V; fs = 44.1kHz, DEM = OFF)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 9)
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 9) SB 24.1 kHz
Passband Ripple PR ± 0. 0 2 dB
Stopband Attenuat ion SA 54 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
Digital Filter + LPF
Frequency Response 20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.05
± 0.05
± 0.05
-
-
-
dB
dB
dB
Note 9. The passband and stopban d fr equen cies scale with fs (system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 10. Delay time caused by digit al filtering. This t ime is fr om set ting the 16/24bit data of both channels to input
register to the output of an alog signal.
DC CHARACTE RI STI CS
(Ta=25°C; VDD = +4.5 ∼ +5.5 V, HV EE = -13. 2 ∼ -4.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
Input Leakage Current ( Note 11) Iin - - ± 10 µA
Note 11. P/S pin is pulled-up internally. (typ. 100kΩ)
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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SWI T CHING CHARACTE RIS T ICS
(Ta=25°C; VDD = +4.5 ∼ +5.5 V, HV EE = -13. 2 ∼ -4.5V)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle fCLK
dCLK 2.048
40 11.2896 36.864
60 MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
Audi o Interf ace T iming
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK Edge (Note 12)
LRCK Edge to BICK rising (Note 12)
SDTI Hol d Time
SDTI Setup Ti me
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interf ace Ti mi ng
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup T ime
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 13)
tPD
150
ns
Note 12. BICK rising edge must not occur at the same time as LRCK edge.
Note 13. The AK4340 can be reset by bringing PDN pin = “L”.
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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Timi ng D iagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Figure 1. Clock Tim ing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Fi gure 2. Serial Int erface Timing
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
Figure 3. WRITE Command Input Timi ng
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
Figure 4. WRITE Data Input Timing
tPD
VIL
PDN
Figure 5. Power-down Timing
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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OPERA TION OVERVIEW
Syste m Clock
The AK4340 requires M CL K , B IC K and LRCK e xt ernal c locks. The ma ster c lo c k (M CL K ) sho ul d be synchronized with
LRCK but the phase is not critical. The MCLK is used to opera te the digita l interpolation filter and the delta-sigma
modulator. Th ere are two methods to set MCLK frequen cy. In Manual Sett in g Mode (ACKS = “0”: Reg ister 00H), the
sampling speed is set by DFS0/1 (Table 1). The fr equency of MC LK at each sampling speed is set a utomatically. (Table
2) After exiting reset (PDN pin = “↑”), the AK4340 is in Auto Setting Mode. In Auto Sett ing Mode (ACKS = “1”:
Default), as MCLK frequency is detected automatic ally (Table 3), and the internal master clock becomes the appropriate
frequency (Table 4), it is not necessary to set DFS0/1.
In parallel contro l mo de, the sampling spe ed c an be set b y only ACKS p in. The inte rnal DFS0 and DFS1 b its are f ixe d to
“0”. Therefore, when ACKS pin is “L”, the AK4340 operates in Nor m al Speed Mode. The AK4340 operates in Auto
Settin g Mode at ACKS pin = “H”. In parallel control mode, the AK4340 does not support 128fs and 192fs of Double
Speed Mode.
All exte rnal c lo c ks (M CL K, BI CK and L RC K) s ho uld alw ay s b e p re se nt w henev er the AK4340 is i n the normal op eration
mode (PDN pin = “H”). If these clocks are not provided, the AK4340 may dra w excess current and may fall into
unpredictable operation . This i s because the device utili zes dyn a mic refreshed logi c in ternally. The AK4340 should be
reset by PDN pin = “L” after threse clocks ar e provided. If the exter nal clocks are n ot presen t, the AK4340 should be in
the power-down mode (PDN pin = “L”). After exitin g reset at power-up etc., the AK4340 is in t h e power-down mode
until MCLK and LRCK are in put.
DFS1 DFS0 Sampling Rate (fs)
0 0 Normal Speed Mode 8kHz~48kHz
Default
0 1 Double Speed Mode 60kHz~96kHz
1 0 Quad Speed Mode 120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
(kHz) MCLK (MHz) BICK
(MHz)
DFS1 DFS0 Sampling
Speed fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs
0 0 32.0 - - 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480
0 0 44.1 - - 11.2896 16.9344 22.5792 33.8688 - 2.8224
0 0
Normal 48.0 - - 12.2880 18.4320 24.5760 36.8640 - 3.0720
0 1 88.2 11.2896 16.9344 22.5792 33.8688 - - - 5.6448
0 1
Double 96.0 12.2880 18.4320 24.5760 36.8640 - - - 6.1440
1 0 176.4 22.5792 33.8688 - - - - - 11.2896
1 0
Quad 192.0 24.5760 36.8640 - - - - - 12.2880
T abl e 2. System Cl ock E x a m pl e (M a n ual Set ti n g M ode)
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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MCLK Sampling Speed
1152fs Normal (fs=32kHz Only)
512fs 768fs Normal
256fs 384fs Double
128fs 192fs Quad
Table 3. Sam pling Speed (Auto Setting Mode: Default at Serial control mode)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - - Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - -
Quad
Table 4. System Clock Example (Auto Setting Mode)
Audio Serial Interfa ce Forma t
Data is shifted in via th e SDTI pin using BICK an d LRCK inputs. In serial control mode, five serial data mode can be
select ed by DIF2-0 bit s . (See Tabl e 5). In parall el control mode, two serial data mode can be selected by DIF0 pin. (See
Table 6) In all modes the serial data is MSB-f irst, 2’s compliment format and is latched on the rising edge of BICK. Mode
2 can be used for 16/20 MSB justified formats by zeroing t he unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format BICK Figure
0 0 0 0 16bit LSB Justified ≥32fs Figur e 6
1 0 0 1 20bit LSB Justified ≥40fs Figur e 7
2 0 1 0 24bit MSB Justified
≥48fs Figur e 8 Default
3 0 1 1 24bit I2S Compatible ≥48f s Figure 9
4 1 0 0 24bit LSB Justified ≥48fs Figur e 7
Table 5. Audio Data Format i n Serial control mode
Mode DIF0 SDTI Format BICK Figure
2 0 24bit MSB Justifi ed ≥48fs Figure 8
3 1 24bit I2S Compat ible ≥48fs Figure 9
Table 6. Audio Data Format in Parallel control mode
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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SDTI
BICK
LRCK
SDTI 15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3 2 1 0 15 14
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mo de 0 D o n’t care Don’t car e
15:MSB, 0:LSB
M ode 0 1514 6543210
Lch Data Rch Data
Figure 6. Mode 0 Timing
SDTI
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
M ode 1 Don’t care Don’t care
19:MSB, 0:LSB
SDTI
Mode 4 23:MSB, 0:LSB
20 19 0 20 19 0Don’t car e Don’t c are22 21 22 21
Lch D ata Rch Data
8
23 23
8
Figure 7. Mode 1,4 Timing
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0 Don’t care23 2223
Figure 8. Mode 2 Timing
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care23
Lch Data Rch Data
23 25 322423 25
22 1 0 Don’t care23 23
Figure 9. Mode 3 Timing
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 an d DEM1. In case of d oubl e speed and quad speed mode, the digi tal de-emph a sis filter is al ways OFF.
DEM1 DEM0 Mo de
0 0 44.1kHz
0 1 OFF
Default
1 0 48kHz
1 1 32kHz
Table 7. De-emphasis Filter Control (Normal Speed Mode)
Output Volume
The AK 43 40 in clu des c ha nn e l indep endent dig ital o utp ut vol umes (ATT) with 256 l evels a t linea r step includi ng MUT E .
These volumes are in front of the DAC and can attenuate the i nput data from 0dB to –48dB and mut e. When changing
levels, transitions are ex ecuted via soft changes; thus no switching noise occurs during these transitions. The transition time
of 1 level and all 256 levels is shown in Table 8.
Tra n sit ion Time
Samplin g Speed 1 Level 255 to 0
Normal Speed Mode 4LRCK 1020LRC K
Double Speed Mode 8LRCK 2040LRCK
Quad Speed Mode 16LRCK 4080LRC K
Table 8. ATT Tr a n siti on Time
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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Output Gain Setting
Outputs level of AOUTL/AOUTR pin can be selected by GAI N pin.
GAIN pin GAIN Output Level (VDD=5V)
L 0dB 2Vrms (typ)
H +1.94dB 2.5Vrms (typ)
Fi gu r e 10 . Ou t p ut Level Sett ing
S oft Mute O pe r ation
Soft mute operation is perfor med in digita l domain . When th e SMUTE bit (SMUTE p in) goes to “1”(“H”), the out put
signal is at ten uated by -∞ du ri ng ATT_DAT A×ATT tr an sit ion time (Table 8) fr om t he cur rent A TT level. When t he
SM UTE b it (S MUTE pin) is returne d to “ 0” (“ L”), the mute is c anc elle d and the o utput atte nuatio n gradually changes to
the ATT level durin g ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after
starting the operation, the attenuation is discontinued and r eturned to ATT level by the same cycle. The soft mute is
effective for ch anging the signal sou rce without stopping t he si gnal transmission.
SMUTE bit or
SMUTE pin
Attenuation
ATT Level
-∞
AOUT
GD GD
(1)
(2)
(3)
(1)
Notes:
(1) ATT_DATA×A TT trans ition t ime (Tab le 8). Fo r ex ample , in Normal Sp ee d M o de , this time is 1020L R C K cycles
(1020/fs) at ATT_DATA=255.
(2) Th e analog output correspondin g to the digital input has a group delay, GD.
(3) If the s of t mute is cancelle d bef ore atte nuating to -∞ af ter starting the op eration, the attenu ation is d is co ntinued and
return ed to ATT level by t h e sam e cycl e.
Figure 11. Soft Mute function
System Reset
The AK4340 should be reset once by bringing PDN pin = “L” upon power-up. The AK4340 is powered up and the
inte rnal timing starts clo c king b y LR CK “↑” after exiting reset and power down stat e by MCLK. The AK4340 is in the
power-down mode until MCLK and LRCK are input.
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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P ower- down
The AK4340 is placed in t he power-down mode by br inging PDN pin “L” and the analog outputs ar e GND. Fig ur e 6
shows an example of th e system timing at the power-down and power-up.
N or ma l Op er ati o n
Internal
State
PDN
Power-do wn No rmal Operatio n
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
M CLK , LR CK, BI CK
(1) (3)
(6)
DZFL/DZFR
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output correspondin g to digital i nput has the group delay (GD).
(2) Analog outputs ar e floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” d ata is input.
(4) The externa l clocks (MCLK, BICK and LRCK) can be stopped in th e power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system a pplication.
The timing example is shown in this figur e.
Figure 12. Power-down/up Sequence Example
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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Res e t Func ti on
When RSTN=0, DAC is powered down but the inter nal register values are not initi alized. The analog outputs go to
VCOM voltage and DZF pin goes to “H”. Figure 7 sh ows the example of reset by RSTN bit.
Internal
State
RSTN bit
Digital Block Power-down Normal Operati on
GD GD
“0” data
D/A O ut
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
External
MUTE
(3) (1)
(2)
Normal Operation
Internal
RSTN bit
2~3/fs (6)3~4/fs (6)
Don’t care
(4)
Mute ON
Notes:
(1) The analog output correspondin g to digital i nput has the group delay (GD).
(2) Analog outputs go to VCOM voltage ( VDD/2) .
(3) Click noise o ccurs at the edges(“↑ ↓”) of the inte rnal timing o f R S TN b it. This noise is output ev en if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5 ) DZF pins go to “H” when the RST N bit becomes “0”, and g o to “L” at 2/fs after RSTN bit becomes “1”.
(6) T her e is a delay, 3~4/fs fr om RSTN bit “0” to t h e inter nal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Fi gure 13. Reset Sequence Example
ASAHI KASEI [AK4 340 ]
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Mode Control Interface
Some function of the AK4340 can be con tr olled by pins (par allel con tr ol mode) sh own in Table 11. Th e ser ial cont r ol
interface is enabled by the P/S pin = “L”. Internal re gisters may b e written to 3-wire µP interface pins, CSN, CCLK and
CDTI. The data on this interface consists of Chip Address (2bit s, C 1/0; fixed to “01”), Read/Write (1bit; fixed to “1”,
Write o nly ), Reg is ter Address (MS B f irst, 5bits ) and Co ntrol Da ta (MSB first, 8bits). The AK4340 latches the data o n the
rising edge of CC LK, s o data should clocked in on the fallin g edge. The writing of data becomes valid by CSN “↑”. The
clock speed of CCLK is 5MHz (max).
Function Parallel control mode Serial control mode
Double sampling mode at 128/192fs X O
De-emphasis X O
SMUTE O O
16/20/ 24bit LSB justified format X O
Table 11. Fun ction list (O: avail able, X: not available)
PDN pin = “L ” resets the registers to t heir defa ult values. When the state of P/S pin is chang ed, the AK4340 should be
reset by PDN pin = “L”. The inter nal timin g cir cuit is reset by RSTN bit, but the registers are not initial ized.
CDTI
CCLK
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7
A
1
A
2
A3
A
4R/WC0
A
0D0D1D2D3
CSN
C1-C0: Chip Address (Fi xed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 14. Control I/F Timing
*The AK4340 does not support the read comman d and chip address. C1/0 a n d R/W ar e fixed to “011”
*Wh en the AK4340 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing in to the contr ol
register is inhibited.
Regi ster Ma p
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
01H Control 2 0 0 0 DFS1 DFS0 DEM1 DEM0 SMUTE
02H Control 3 0 0 0 INVL INVR 0 0 0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Notes:
For a ddresses from 05H to 1FH, data must not be wri tten.
When PDN pin goes “L”, the registers ar e initia lized to their default va lues.
When RSTN bi t g oes “0”, the only in ternal timing is reset an d the registers are n ot initialized to their default
values. All data can be written to t he register even if PW or RSTN bit is “0”.
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
default 1 0 0 0 1 0 1 1
RST N: Internal timing reset control
0: Reset. All registers are not initia lized.
1: Normal Operation
When M C LK frequency or DFS changes, th e click noise can be reduced by RSTN bit .
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data inter face formats (see Table 5)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Ena ble
0: Disable, Manual Setting Mode
1: E nable, Auto Setting Mode
Master cloc k freq uenc y is de tected automatically at ACKS b it “1”. In this c ase, the se ttings o f DF S1-0
are ignored. When thi s bit is “0”, DFS1-0 set the sampling speed mode.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 0 0 DFS1 DFS0 DEM1 DEM0 SMUTE
default 0 0 0 0 0 0 1 0
SMUTE: Soft Mute Ena bl e
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 7 )
Initial: “01” , OFF
DFS 1-0: Sampling sp eed contr ol
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
When chang ing between Normal/Double Sp eed Mode and Quad Speed Mode, some click noise
occurs .
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 0 0 0 INVL INVR 0 0 0
default 0 0 0 0 0 0 0 0
INVR: In vert in g Lch Output Polarit y
0: Normal Output
1: Inverted Output
INVL: In ver tin g Rch Output Polarit y
0: Normal Output
1: Inverted Output
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
default 1 1 1 1 1 1 1 1
ATT = 20 log
10 (ATT _DATA / 255) [dB]
00H: Mute
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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SYSTEM DESIGN
Fi gu r e 15 a nd Figu r e 16 show t h e s yst em connect ion dia g ra m . An eval ua ti on boa r d (A KD4 3 40 ) i s avail a bl e i n or der t o
allow a n easy study on the layout of a surr ound circuit.
MCLK 1
BICK 2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI 8
GAIN 16
P/S
15
VDD
14
VSS
13
HVEE
12
AOUTL
11
AOUTR
10
NC
9
Master C lock
µP
AK4340
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Rch Out
Lch Out
Analog Ground Digital Ground
+5 V Analog Supply
+
10u
0.1u Ne ga ti ve A na l og Supp ly
Figure 15. Typical Conn ection Diagram (Serial Control Mode, GAIN=0dB)
MCLK 1
BICK 2
SDTI
3
LRCK
4
PDN
5
SMUTE
6
ACKS
7
DIF0 8
GAIN 16
P/S
15
VDD
14
VSS
13
HVEE
12
AOUTL
11
AOUTR
10
NC
9
Master C lock
Mode
Setting
AK4340
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Rch Out
Lch Out
Analog Ground Digital Ground
+5 V Analog Supply
+
10u
0.1u Ne ga ti ve A na l og Supp ly
Figure 16. Typical Connection Diagram (Paral lel Control Mode, GAIN=0dB)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except for pull-up pin must not be left floating.
ASAHI KASEI [AK4 340 ]
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1. Grounding and Power Supply Decoupl ing
VDD, HVEE and VSS are supplied from analog supply and should be separated from sy stem digital supply. Decoup ling
capacitor, especially 0.1µF c e ramic capac itor f o r hi gh f reque nc y should b e plac ed as near t o V DD and H V EE as po ss ible .
The differential Voltage between VDD and VSS pin s set the anal og out put ran ge.
Power-up sequenc e between VDD and HVEE is not critic al .
2. Analog Out puts
The analo g ou tputs are single -e nded and centered around the grou nd (VSS) . The o ut pu t signal range is typically 2V rms
(@VDD=5V & GAIN pin = “L”). The phase of the analog outputs can be inverted channel independently by INVL/INVR
bits. The inter nal switched capacitor filter (SCF) an d continuous time filter (CTF) attenuate the noise gen erated by the
delt a-s igma mo dulato r beyond the audio pass b a nd. If the noise ge ne rated b y the delt a-s igma mo dulato r b eyond the audio
band would be the problem, the 1st order filter is required. (See Figure 17)
The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The
ideal output is 0V(VSS) for 000000H (@24bit).
470
2.2n
AOUT Analog
Out
Figure 17. External 1st order LPF Ci rcuit E xa m p le
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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PACKAGE
0-10°
Detail A
Seating Plane 0.10
0.17
±
0.050.22±0.1 0.65
*5.0±0.1 1.05±0.05
A
18
916
16
p
in TSSO P
(
Unit: mm
)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK4 340 ]
MS0501-E-00 2006/04
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MARKING
AKM
4340ET
XXYYY
1) Pin #1 indication
2) Da t e Code : XXYYY (5 dig its )
XX: Lot#
YYY: Date Code
3) Mar ketin g Code : 4340ET
4) Asahi Kasei Logo
Date (YY/MM/DD) Revision Reason Page Conten ts
06/04/24 00 First Edition
IMPO RTANT NOTICE
• Th ese pro du cts and t h ei r spe ci fi ca ti o ns a r e subj ec t t o ch an ge wi tho ut n oti c e. B efo re co nsi d eri n g
any use or a ppli cat i on, consult the Asahi Ka sei Mi cr osystem s Co., Lt d. (AKM ) sal es of f i ce o r
authorized distributor concerning their current status.
• AKM assum es no l iab i l it y for i nfr ing em en t o f a ny p at ent , i n t ell ec t ual pr o pe rt y, or ot h er ri gh t in t h e
appl i cat i on or use o f any i nf orm at ion con tai ned h ere in .
• A ny export o f these pr o du cts , or de v ices or s y ste ms c on taining th em, ma y req uir e a n export licen s e
or oth er of f i ci al appr oval unde r th e l aw a nd r egulat ion s of t he coun tr y of export pert ai ni ng t o
c ust oms an d tar i ff s, curr enc y exchan ge, or st rate gi c materi al s.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or syst em, and AKM assumes no responsibil ity relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A h azar d re l at e d device o r system is on e d esi g ne d or int e nd ed f o r l i f e sup po rt o r m ai nt e na nc e
of safety or for applications in medicine, aerospace, nuclear energy, or other fields , in which its
failure to function or perform may reasonably be expected to result in los s of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be ex pected to
result, whether directly or i ndirectl y, in the loss of the saf ety or eff ectiveness of t he devi ce or
system con tai ni ng i t, an d wh ic h mu st the ref or e me et ver y hi gh st anda rds of pe rf orm anc e and
reli abili ty.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the prod uct with a third party to not ify that p arty in advance of the above content
and conditions , and the buyer or dis tributor agrees to assume any and all responsibility and liability
for and hold AKM harml ess from any and al l claims arising from the use of said product in the
absence of such notif ication.
