1
FEATURES
Implemented on a 0.25mCMOS technology
Flexible static design allows up to 66MHz clock rate
89 DMIPS throughput via 66MHz base clock frequency
Internally configured clock network
On-board programmable timers and interrupt controllers
High-performance fully pipelined IEEE-754 FPU
Power saving 2.5V core power supply
3.3V I/O compatibility
Hardened-by-design flip-flops and memory cells
Separate instruction and data cache architecture
10/100 Base-T Ethernet port for VxWorks development
Integrated PCI 2.2 compatible core
Four integrated multi-protocol SpaceWire nodes with two
supporting the RMAP protocol
Two CAN-compliant 2.0 bus interfaces
Multifunctional memory controller
-40oC to +105oC temperature range
Operational environment:
- Intrinsic total-dose: 100 krad(Si) and 300 krad(Si)
- SEL Immune >108 MeV-cm2/mg
Packaging options:
- 352-pin Ceramic Quad Flatpack, weight 31.5 grams
- 484-pin Ceramic Land Grid, Column Grid and Ball
Grid Array packages
Standard Microcircuit Drawing 5962-08228
- QML Q and Q+
- QML V pending
Applications
- Nuclear power plant controls
- Critical transportation systems
- High-altitude avionics
- Medical electronics
- X-Ray cargo scanning
INTRODUCTION
The UT699 is a pipelined monolithic, high-performance, fault-
tolerant SPARCTM V8/LEON 3FT Processor. The UT699
provides a 32-bit master/target PCI interface, including a 16 bit
user I/O interface for off-chip peripherals. A compliant 2.0
AMBA bus interface integrates the on-chip LEON 3FT,
SpaceWire, Ethernet, memory controller, cPCI, CAN bus, and
programmable interrupt peripherals.
The UT699 is SPARC V8 compliant; compilers and kernels for
SPARC V8 can therefore be used industry standard
development tools. A full software development suite is
available including a C/C++ cross-compiler system based on
GCC and the Newlib embedded C-library.
BCC includes a small run-time kernel with interrupt support
and Pthreads library. For multi-threaded applications, a
SPARCTM compliant port of the eCos real-time kernel, RTEMS
4.6.5, and VxWorks 6.x is supported.
Standard Products
UT699 32-bit Fault-Tolerant
SPARCTM V8/LEON 3FT Processor
Data Sheet
March 28, 2011
2
1.0 Introduction
The UT699 LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates the
SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA
(Advanced Microcontroller Bus Architecture) backplane. This bus is comprised of the AHB (Advanced High-speed Bus) which is
used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.
Figure 1. UT699 Functional Block Diagram
The LEON 3FT architecture includes the following peripheral blocks:
• LEON3 SPARC V8 integer unit with 8kB instruction cache and 8kB of data cache
• IEEE-754 floating point unit
• Debug support unit
• UART and JTAG debug links
• 8/16/32-bit memory controller with EDAC for external PROM and SRAM
• 32-bit SDRAM controller with EDAC for external SDRAM
• Timer unit with three 32-bit timers and watchdog
• Interrupt controller for 15 interrupts in two priority levels
• 16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources
• AMBA AHB status register
• Up to four SpaceWire links with RMAP on channels 3and 4
• Up to two CAN controllers
• Ethernet with support for MII
• cPCI interface with 8-channel arbiter
AMBA AHB
Timers IrqCtrl
AMBA APB
8/32-bits memory bus
Debug
Support Unit
AHB interface
LEON 3FT
Memory
Controller
AHB/APB
Bridge
I/O portUART
IEEE754
FPU
MUL/DIV
MMU
PCI CAN-2.0
AHB Ctrl
Serial/JTAG
Debug Link 4x SpW Bridge
Ethernet
MAC
D-cache
2x4K
I-cache
512 MB
PROM
512 MB
I/O
Up t o1GB
SRAM
2x4K
D-cache
Up to 1GB
SDRAM
3
2.0 Pin Identification and Description
Pin Function Description
I CMOS input
IS CMOS input Schmitt
O CMOS output
I/O CMOS bi-direct
OD CMOS open drain
PCI-I PCI input
PCI-O PCI output
PCI-I/O PCI bi-direct
PCI-3 PCI three-state
2.1. System Signals
Notes:
1. This pin is actively driven low and must be tied to VDD through a pull-up resistor.
2.2 Address Bus
Pin Name Function
Pin Number Reset
Value Description
352 CQFP 484 CLGA
SYSCLK I 88 Y20 -- Main system clock
RESET IS 136 L19 -- System reset
ERROR1OD 142 K19 -- Processor error mode indicator. This is an
active low output.
WDOG1OD 145 J19 -- Watchdog indicator. This is an active low
output.
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
ADDR[0] O 1 W5 low Bit 0 of the address bus
ADDR[1] O 2 Y5 low Bit 1 of the address bus
ADDR[2] O 4 W6 low Bit 2 of the address bus
ADDR[3] O 5 AA5 low Bit 3 of the address bus
ADDR[4] O 6 Y6 low Bit 4 of the address bus
ADDR[5] O 7 AB5 low Bit 5 of the address bus
ADDR[6] O 9 W7 low Bit 6 of the address bus
ADDR[7] O 10 AA6 low Bit 7 of the address bus
ADDR[8] O 11 Y7 low Bit 8 of the address bus
ADDR[9] O 12 AA7 low Bit 9 of the address bus
4
2.3 Data Bus
ADDR[10] O 16 AB6 low Bit 10 of the address bus
ADDR[11] O 17 W8 low Bit 11 of the address bus
ADDR[12] O 18 AB7 low Bit 12 of the address bus
ADDR[13] O 19 Y8 low Bit 13 of the address bus
ADDR[14] O 21 AA8 low Bit 14 of the address bus
ADDR[15] O 22 W9 low Bit 15 of the address bus
ADDR[16] O 23 AB8 low Bit 16 of the address bus
ADDR[17] O 24 Y9 low Bit 17 of the address bus
ADDR[18] O 26 W10 low Bit 18 of the address bus
ADDR[19] O 27 AB9 low Bit 19 of the address bus
ADDR[20] O 28 Y10 low Bit 20 of the address bus
ADDR[21] O 29 AA9 low Bit 21 of the address bus
ADDR[22] O 31 W11 low Bit 22 of the address bus
ADDR[23] O 32 AA10 low Bit 23 of the address bus
ADDR[24] O 33 Y11 low Bit 24 of the address bus
ADDR[25] O 34 AB10 low Bit 25 of the address bus
ADDR[26] O 38 AB11 low Bit 26 of the address bus
ADDR[27] O 39 AA11 low Bit 27 of the address bus
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
DATA[0] I/O 43 W12 high-z Bit 0 of the data bus
DATA[1] I/O 45 W13 high-z Bit 1 of the data bus
DATA[2] I/O 46 Y12 high-z Bit 2 of the data bus
DATA[3] I/O 47 AA13 high-z Bit 3 of the data bus
DATA[4] I/O 48 AA12 high-z Bit 4 of the data bus
DATA[5] I/O 50 AB13 high-z Bit 5 of the data bus
DATA[6] I/O 51 W14 high-z Bit 6 of the data bus
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
5
DATA[7] I/O 52 AA14 high-z Bit 7 of the data bus
DATA[8] I/O 53 Y13 high-z Bit 8 of the data bus
DATA[9] I/O 57 W15 high-z Bit 9 of the data bus
DATA[10] I/O 58 AB15 high-z Bit 10 of the data bus
DATA[11] I/O 59 Y14 high-z Bit 11 of the data bus
DATA[12] I/O 60 AB14 high-z Bit 12 of the data bus
DATA[13] I/O 62 W16 high-z Bit 13 of the data bus
DATA[14] I/O 63 AA18 high-z Bit 14 of the data bus
DATA[15] I/O 64 Y15 high-z Bit 15 of the data bus
DATA[16] I/O 66 AB16 high-z Bit 16 of the data bus
DATA[17] I/O 67 AA15 high-z Bit 17 of the data bus
DATA[18] I/O 68 AB17 high-z Bit 18 of the data bus
DATA[19] I/O 69 AA16 high-z Bit 19 of the data bus
DATA[20] I/O 71 AA19 high-z Bit 20 of the data bus
DATA[21] I/O 72 W17 high-z Bit 21 of the data bus
DATA[22] I/O 73 AB18 high-z Bit 22 of the data bus
DATA[23] I/O 74 Y16 high-z Bit 23 of the data bus
DATA[24] I/O 78 Y17 high-z Bit 24 of the data bus
DATA[25] I/O 79 AA17 high-z Bit 25 of the data bus
DATA[26] I/O 80 W18 high-z Bit 26 of the data bus
DATA[27] I/O 81 AB19 high-z Bit 27 of the data bus
DATA[28] I/O 83 Y19 high-z Bit 28 of the data bus
DATA[29] I/O 84 AB20 high-z Bit 29 of the data bus
DATA[30] I/O 85 Y18 high-z Bit 30 of the data bus
DATA[31] I/O 86 AA20 high-z Bit 31 of the data bus
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
6
2.4 Check Bits
2.5 Memory Control Signals
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
CB[0] I/O 89 V19 high-z Bit 0 of EDAC checkbits
CB[1] I/O 90 AA21 high-z Bit 1 of EDAC checkbits
CB[2] I/O 91 Y21 high-z Bit 2 of EDAC checkbits
CB[3] I/O 92 W19 high-z Bit 3 of EDAC checkbits
CB[4] I/O 93 Y22 high-z Bit 4 of EDAC checkbits
CB[5] I/O 94 W20 high-z Bit 5 of EDAC checkbits
CB[6] I/O 96 W22 high-z Bit 6 of EDAC checkbits
CB[7] I/O 97 W21 high-z Bit 7 of EDAC checkbits
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
WRITE O 98 V21 high PROM and I/O write enable strobe
OE O 99 U19 high PROM and I/O output enable
IOS O 102 T20 high I/O area chip select
ROMS[0] O 103 V22 high PROM chip select
ROMS[1] O 104 U20 high PROM chip select
RWE[0] O 105 U22 high SRAM write enable strobe
RWE[1] O 108 T19 high SRAM write enable strobe
RWE[2] O 109 T22 high SRAM write enable strobe
RWE[3] O 110 T21 high SRAM write enable strobe
RAMOE[0] O 111 V20 high SRAM output enable
RAMOE[1] O 112 R21 high SRAM output enable
RAMOE[2] O 113 R20 high SRAM output enable
RAMOE[3] O 114 R22 high SRAM output enable
RAMOE[4] O 115 R19 high SRAM output enable
RAMS[0] O 117 P22 high SRAM chip select
RAMS[1] O 118 P20 high SRAM chip select
7
2.6 SDRAM
2.7 CAN 2.0 Interface
RAMS[2] O 119 P21 high SRAM chip select
RAMS[3] O 120 P19 high SRAM chip select
RAMS[4] O 123 N19 high SRAM chip select
READ O 139 K20 high SRAM, PROM, and I/O read indicator
BEXC I 140 K22 -- Bus exception
BRDY I 141 K21 -- Bus ready
Pin Name
Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
SDCLK O 41 AB12 high SDRAM clock
SDRAS O 124 N22 high SDRAM row address strobe
SDCAS O 125 N20 high SDRAM column address strobe
SDWE O 126 N21 high SDRAM write enable
SDCS[0] O 128 M21 high SDRAM chip select
SDCS[1] O 129 M22 high SDRAM chip select
SDDQM[0] O 131 L21 high SDRAM data mask
SDDQM[1] O 132 M20 high SDRAM data mask
SDDQM[2] O 133 L20 high SDRAM data mask
SDDQM[3] O 134 L22 high SDRAM data mask
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
CAN_RXD[0] I 146 J20 -- CAN receive data
CAN_TXD[0] O 147 J22 high CAN transmit data
CAN_RXD[1] I 148 J21 -- CAN receive data
CAN_TXD[1] O 150 H22 high CAN transmit data
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
8
2.8 Debug Support Unit (DSU)
2.9 JTAG Interface
2.10 Ethernet Interface
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
DSUACT O 151 H19 low DSUmode indicator
DSUBRE I 152 H20 -- DSU break
DSUEN I 153 G19 -- DSU enable
DSURX I 154 G20 -- DSU UART receive data
DSUTX O 155 G21 high DSU UART transmit data
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
TRST I156F20--JTAG reset
TMS I 157 F21 -- JTAG test mode select
TCK I 160 G22 -- JTAG clock
TDI I 161 F22 -- JTAG test data input
TDO O 162 F19 undef JTAG test data output
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
EMDC O 163 E22 low Ethernet media interface clock
ERX_CLK I 166 D22 -- Ethernet RX clock
EMDIO I/O 167 D20 high-z Ethernet media interface data
ERX_COL I 168 E21 -- Ethernet collision error
ERX_CRS I 169 E20 -- Ethernet carrier sense detect
ERX_DV I 171 D21 -- Ethernet receiver data valid
ERX_ER I 172 C21 -- Ethernet reception error
ERXD[0] I 173 C22 -- Ethernet receive data
ERXD[1] I 174 B21 -- Ethernet receive data
ERXD[2] I 175 C20 -- Ethernet receive data
9
2.11 General Purpose I/O
ERXD[3] I 176 B20 -- Ethernet receive data
ETXD[0] O 177 C19 low Ethernet transmit data
ETXD[1] O 178 C18 high Ethernet transmit data
ETXD[2] O 179 B18 low Ethernet transmit data
ETXD[3] O 180 B19 high Ethernet transmit data
ETX_CLK I 182 A19 -- Ethernet TX clock
ETX_EN O 184 A18 low Ethernet transmit enable
ETX_ER O 185 A20 low Ethernet transmit error. Always driven low.
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
GPIO[0] I/O 191 B17 high-z Bit 0 of general purpose I/O
GPIO[1] I/O 192 C17 high-z Bit 1 of general purpose I/O
GPIO[2] I/O 193 A17 high-z Bit 2 of general purpose I/O
GPIO[3] I/O 194 D17 high-z Bit 3 of general purpose I/O
GPIO[4] I/O 196 C16 high-z Bit 4 of general purpose I/O
GPIO[5] I/O 197 D16 high-z Bit 5 of general purpose I/O
GPIO[6] I/O 198 C15 high-z Bit 6 of general purpose I/O
GPIO[7] I/O 199 D15 high-z Bit 7 of general purpose I/O
GPIO[8] I/O 254 C7 high-z Bit 8 of general purpose I/O
GPIO[9] I/O 255 B5 high-z Bit 9 of general purpose I/O
GPIO[10] I/O 256 D7 high-z Bit 10 of general purpose I/O
GPIO[11] I/O 257 A5 high-z Bit 11 of general purpose I/O
GPIO[12] I/O 259 D6 high-z Bit 12 of general purpose I/O
GPIO[13] I/O 260 C5 high-z Bit 13 of general purpose I/O
GPIO[14] I/O 261 C6 high-z Bit 14 of general purpose I/O
GPIO[15] I/O 262 D5 high-z Bit 15 of general purpose I/O
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
10
2.12 SpaceWire Interface
2.13 UART Interface
2.14 PCI Address and Data Bus
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
SPW_CLK I 221 A11 -- SpaceWire clock
SPW_RXS[0] I 205 A16 -- SpaceWire receive strobe
SPW_RXD[0] I 206 A15 -- SpaceWire receive data
SPW_TXS[0] O 207 B16 low SpaceWire transmit strobe
SPW_TXD[0] O 208 B15 low SpaceWire transmit data
SPW_RXS[1] I 212 A14 -- SpaceWire receive strobe
SPW_RXD[1] I 213 A13 -- SpaceWire receive data
SPW_TXS[1] O 214 B14 low SpaceWire transmit strobe
SPW_TXD[1] O 215 B13 low SpaceWire transmit data
SPW_RXS[2] I 234 A9 -- SpaceWire receive strobe
SPW_RXD[2] I 235 A8 -- SpaceWire receive data
SPW_TXS[2] O 236 B9 low SpaceWire transmit strobe
SPW_TXD[2] O 237 B8 low SpaceWire transmit data
SPW_RXS[3] I 242 A7 -- SpaceWire receive strobe
SPW_RXD[3] I 243 A6 -- SpaceWire receive data
SPW_TXS[3] O 244 B7 low SpaceWire transmit strobe
SPW_TXD[3] O 245 B6 low SpaceWire transmit data
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
RXD I 223 C12 -- UART receive data
TXD O 224 C11 high UART transmit data
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
PCI_AD[0] PCI-I/O 266 AA2 high-z Bit 0 of PCI address and data bus
11
PCI_AD[1] PCI-I/O 267 AA3 high-z Bit 1 of PCI address and data bus
PCI_AD[2] PCI-I/O 268 Y1 high-z Bit 2 of PCI address and data bus
PCI_AD[3] PCI-I/O 269 Y2 high-z Bit 3 of PCI address and data bus
PCI_AD[4] PCI-I/O 270 Y3 high-z Bit 4 of PCI address and data bus
PCI_AD[5] PCI-I/O 272 W1 high-z Bit 5 of PCI address and data bus
PCI_AD[6] PCI-I/O 273 W2 high-z Bit 6 of PCI address and data bus
PCI_AD[7] PCI-I/O 274 W3 high-z Bit 7 of PCI address and data bus
PCI_AD[8] PCI-I/O 279 V2 high-z Bit 8 of PCI address and data bus
PCI_AD[9] PCI-I/O 280 V3 high-z Bit 9 of PCI address and data bus
PCI_AD[10] PCI-I/O 281 U1 high-z Bit 10 of PCI address and data bus
PCI_AD[11] PCI-I/O 284 U2 high-z Bit 11 of PCI address and data bus
PCI_AD[12] PCI-I/O 285 U3 high-z Bit 12 of PCI address and data bus
PCI_AD[13] PCI-I/O 286 T1 high-z Bit 13 of PCI address and data bus
PCI_AD[14] PCI-I/O 287 R2 high-z Bit 14 of PCI address and data bus
PCI_AD[15] PCI-I/O 288 R1 high-z Bit 15 of PCI address and data bus
PCI_AD[16] PCI-I/O 305 J1 high-z Bit 16 of PCI address and data bus
PCI_AD[17] PCI-I/O 306 K2 high-z Bit 17 of PCI address and data bus
PCI_AD[18] PCI-I/O 307 K1 high-z Bit 18 of PCI address and data bus
PCI_AD[19] PCI-I/O 308 G1 high-z Bit 19 of PCI address and data bus
PCI_AD[20] PCI-I/O 309 H3 high-z Bit 20 of PCI address and data bus
PCI_AD[21] PCI-I/O 310 H2 high-z Bit 21 of PCI address and data bus
PCI_AD[22] PCI-I/O 312 F1 high-z Bit 22 of PCI address and data bus
PCI_AD[23] PCI-I/O 313 F2 high-z Bit 23 of PCI address and data bus
PCI_AD[24] PCI-I/O 317 E1 high-z Bit 24 of PCI address and data bus
PCI_AD[25] PCI-I/O 318 E2 high-z Bit 25 of PCI address and data bus
PCI_AD[26] PCI-I/O 321 F3 high-z Bit 26 of PCI address and data bus
PCI_AD[27] PCI-I/O 322 D1 high-z Bit 27 of PCI address and data bus
PCI_AD[28] PCI-I/O 323 D2 high-z Bit 28 of PCI address and data bus
PCI_AD[29] PCI-I/O 324 E3 high-z Bit 29 of PCI address and data bus
PCI_AD[30] PCI-I/O 326 D3 high-z Bit 30 of PCI address and data bus
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
12
2.15 PCI Control Signals
Notes:
1. This pin must be tied to VDD through a pull-up resistor as specified in the PCI Local Bus Specification Revision 2.1 Section 4.3.3.
PCI_AD[31] PCI-I/O 327 C1 high-z Bit 31 of PCI address and data bus
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
PCI_RST PCI-I 265 C3 -- PCI reset input
PCI_CLK PCI-I 293 C2 -- PCI clock input
PCI_C/BE[0] PCI-I/O 275 V1 high-z PCI bus command and byte enable
PCI_C/BE[1] PCI-I/O 289 P2 high-z PCI bus command and byte enable
PCI_C/BE[2] PCI-I/O 302 H1 high-z PCI bus command and byte enable
PCI_C/BE[3] PCI-I/O 316 G2 high-z PCI bus command and byte enable
PCI_PAR PCI-I/O 290 P1 high-z PCI parity checkbit
PCI_FRAME1PCI-3 301 L1 high-z PCI cycle frame indicator
PCI_IRDY1PCI-3 300 L2 high-z PCI initiator ready indicator
PCI_TRDY1PCI-3 299 M1 high-z PCI target ready indicator
PCI_STOP1PCI-3 295 N1 high-z PCI target stop request
PCI_DEVSEL1PCI-3 296 M2 high-z PCI device select
PCI_IDSEL PCI-I 315 G3 -- PCI initialization device select
PCI_REQ PCI-O 329 A4 high-z PCI request to arbiter in point to point con-
figuration
PCI_GNT PCI-I 328 B2 -- PCI bus access indicator in point to point
configuration
PCI_HOST PCI-I 330 AB3 -- PCI host enable input (Connect to SYSEN in
PCI bus)
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
13
2.16 PCI Arbiter
2.17 Power and Ground Pins (352 CQFP)
Pin Name Direction
Pin Number Reset
Value Description
352 CQFP 484 CLGA
PCI_ARB_REQ[0] PCI-I 331 B4 -- PCI arbiter bus request
PCI_ARB_REQ[1] PCI-I 332 AB4 -- PCI arbiter bus request
PCI_ARB_REQ[2] PCI-I 337 Y4 -- PCI arbiter bus request
PCI_ARB_REQ[3] PCI-I 339 T3 -- PCI arbiter bus request
PCI_ARB_REQ[4] PCI-I 343 P3 -- PCI arbiter bus request
PCI_ARB_REQ[5] PCI-I 344 M3 -- PCI arbiter bus request
PCI_ARB_REQ[6] PCI-I 348 K3 -- PCI arbiter bus request
PCI_ARB_REQ[7] PCI-I 350 C4 -- PCI arbiter bus request
PCI_ARB_GNT[0] PCI-O 333 B3 high-z PCI arbiter bus grant
PCI_ARB_GNT[1] PCI-O 336 AA4 high-z PCI arbiter bus grant
PCI_ARB_GNT[2] PCI-O 338 W4 high-z PCI arbiter bus grant
PCI_ARB_GNT[3] PCI-O 342 R3 high-z PCI arbiter bus grant
PCI_ARB_GNT[4] PCI-O 345 N3 high-z PCI arbiter bus grant
PCI_ARB_GNT[5] PCI-O 347 L3 high-z PCI arbiter bus grant
PCI_ARB_GNT[6] PCI-O 349 J3 high-z PCI arbiter bus grant
PCI_ARB_GNT[7] PCI-O 351 A3 high-z PCI arbiter bus grant
Pin Name
Pin Number
Description
352 CQFP 484 CLGA
VDD 3, 15, 25, 35, 40, 44, 54, 65,
75, 87, 95, 106, 116, 127,
135, 137, 149, 158, 170,
181, 190, 200, 203, 211,
217, 222, 226, 229, 233,
241, 247, 251, 263, 271,
283, 292, 294, 304, 314,
325, 335, 346
B1, B10, B12, B22, E7, E9,
E14, E16, F6, F10, F13,
F17, G5, G9, G14, H6, H8,
H10, H13, H15, J7, J16,
J18, K5, K8, K15, K17, L6,
M6, N5, N8, N15, N17, P7,
P16, P18, R6, R8, R10,
R13, R15, T5, T9, T14, U6,
U9, U11, U12, U14, U17,
V10, V13, AA1, AA22
I/O supply voltage
14
VSS 8, 20, 30, 42, 49, 61, 70, 82,
107, 130, 138, 159, 183,
187, 195, 204, 216, 219,
225, 230, 238, 246, 250,
258, 264, 278, 282, 303,
311, 334, 352
A1, A12, A22, B11, C8,
C10, C13, D4, D9, D14,
D18, D19, E4, E6, E10,
E13, E17, E19, F4, G4, G8,
G11, G12, G15, G17, H4,
H7, H16, H18, J2, J4, J9,
J14, K4, K10, K13, L7,
L11, L12, L17, M7, M11,
M12, M17, N4, N10, N13,
P4, P9, P14, R4, R7, R16,
R18, T2, T4, T8, T15, T17,
U4, U10, U13, V4, V5, V8,
V11, V12, V15, V18, AB1,
AB22
I/O supply ground (pins 187/D19 and
264/D4 must be tied to VSS)
VDDC 14, 37, 56, 77, 101, 122,
144, 165, 186, 188, 201,
209, 220, 227, 232, 239,
249, 252, 276, 297, 319,
340
A2, A21, D10, D13, E5,
E11, E12, E18, F8, F15,
G7, G10, G13, G16, G18,
H5, H9, H11, H12, H14,
H17, J6, J8, J15, K7, K16,
L4, L8, L15, L18, M4, M8,
M15, M18, N7, N16, P6,
P8, P15, R5, R9, R11, R12,
R14, R17, T7, T10, T13,
T16, T18, U8, U15, V6,
V17, AB2, AB21
Core supply voltage
VSSC 13, 36, 55, 76, 100, 121,
143, 164, 189, 202, 210,
218, 228, 231, 240, 253,
277, 298, 320, 341
A10, C9, C14, D11, D12,
E8, E15, F5, F7, F9, F11,
F12, F14, F16, F18, G6,
H21, J5, J10, J11, J12, J13,
J17, K6, K9, K11, K12,
K14, K18, L5, L9, L10,
L13, L14, L16, M5, M9,
M10, M13, M14, M16,
M19, N6, N9, N11, N12,
N14, N18, P5, P10, P11,
P12, P13, P17, T6, T11,
T12, U5, U7, U16, U18,
U21, V7, V9, V14, V16
Core supply ground
N/C 248 D8 This pin must be left floating
Unused 291 N2 This pin must be tied to VDD through a
10k pull-up resistor
Pin Name
Pin Number
Description
352 CQFP 484 CLGA
15
3.0 AC and DC Electrical Specifications
3.1 Absolute Maximum Ratings1
Notes:
1. Stresses greater than those listed in the following table can result in permanent damage to the device. These parameters cannot be violated.
2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (TJ(max)-Tc(max))/JC
3. Maximum junction temperature may be increased to 175oC during burn-in and steady-static life testing.
Symbol Description Min Max Units
VDDC Core supply voltage -0.3 3.6 V
VDD I/O supply voltage -0.3 4.3 V
VIN Input voltage any pin VSS - 0.3 VDD + 0.3 V
PD2Maximum power dissipation permitted @
TC = 105oC
-- 9 W
TJ3Junction temperature -- 150 oC
JC Thermal resistance, junction to case 352 CQFP -- 5 oC/W
484 CLGA/CCGA/CBGA -- 5
TSTG Storage temperature -65 150 oC
ESDHBM ESD protection (human body model) Class 2 2000 -- V
16
3.2 Recommended Operating Conditions
VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Symbol Description Min Max Units
VDDC Core supply voltage 2.3 2.7 V
VDD I/O supply voltage 3.0 3.6 V
VIN Input voltage any pin 0 VDD V
TCCase operating temperature -40 105 oC
tRRise time, all CMOS and PCI inputs -- 20 ns
tFFall time, all CMOS and PCI inputs -- 20 ns
17
3.3 Power Supply Operating Characteristics (pre- and post-radiation)
VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. During this measurement the processor is executing the Dhrystone benchmark.
2. This measurement includes the contribution due to IDDCS.
3. This measurement includes the contribution due to IDDS.
4. Power-down mode is entered by performing a WRASR instruction wr %g0, %asr19.
Symbol Description Conditions Max Units
IDDC1,2 Active core power
supply current
VDDC = 2.7V, VDD= 3.6V
For 25MHz < fSYSCLK < 66MHz
All other clock inputs running at fSYSCLK
27 mA/MHz
IDD1,3 Active I/O power supply
current
VDDC = 2.7, VDD = 3.6V
For 25MHz < fSYSCLK < 66MHz
All other clock inputs running at fSYSCLK
0.75 mA/MHz
IDDCS Standby core power sup-
ply current
VDDC = 2.7V, VDD= 3.6V
fSYSCLK = 0MHz, fETH_CLK = 0MHz
fPCI_CLK = 0MHz, fSPW_CLK = 0MHz
TC = -40oC
and 25oC
2mA
TC = 105oC20
IDDS Standby I/O power sup-
ply quiescent current
VDDC = 2.7V, VDD = 3.6V
fSYSCLK = 0MHz, fETH_CLK = 0MHz,
fPCI_CLK = 0MHz, fSPW_CLK = 0MHz
0.75 mA
IPDC4Core power supply cur-
rent power-down mode
VDDC = 2.7V, VDD = 3.6V
fSYSCLK = 66MHz, fETH_CLK = 0MHz
fPCI_CLK = 0MHz, fSPW_CLK = 0MHz
2.75 mA/MHz
300k post rad 5
IPD4I/O power supply current
power-down mode
VDDC = 2.7V, VDD = 3.6V
fSYSCLK = 66MHz, fETH_CLK = 0MHz
fPCI_CLK = 0MHz, fSPW_CLK = 0MHz
0.75 mA/MHz
18
3.4 DC Characteristics for LVCMOS3 Inputs (pre- and post-radiation)
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.
Symbol Description Conditions Min Max Units
VIH High-level input voltage 0.7VDD -- V
VIL Low-level input voltage -- 0.3VDD V
VT+ Positive going threshold volt-
age for Schmitt inputs
-- 0.7VDD V
VT- Negative going threshold
voltage for Schmitt inputs
0.3VDD -- V
VHHysteresis voltage for
Schmitt inputs
0.4 -- V
IIN Input leakage current VIN = VDD -- 1 A
VIN = VSS -1 --
CIN1Input pin capacitance f = 1MHz; VDD = 0V,
VDDC = 0V
352 CQFP -- 19 pF
484 CLGA -- 16
19
3.5 DC Characteristics for LVCMOS3 Outputs (pre- and post-radiation)
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. Except open-drain output.
2. Supplied as a design limit. Neither guaranteed nor tested.
3. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.
Symbol Description Conditions Min Max Units
VOH1High-level output voltage IOH = -100AV
DD-0.25 --
V
IOH = -12mA 2.4 --
VOL Low-level output voltage IOL = 100A--0.25
V
IOL = 12mA -- 0.4
IOZ Three-state output current VO = VDD -10 10 A
VO = VSS -10 10
IOS2Short-circuit output current VO = VDD; VDD = 3.6V -- 130 mA
VO = VSS; VDD = 3.6V -65 --
COUT3Output pin capacitance f = 1MHz; VDD = 0V,
VDDC = 0V
352 CQFP -- 16 pF
484 CLGA -- 16
20
3.6 AC Electrical Characteristics for LVCMOS3 Inputs and Outputs (pre- and post-radiation)
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. Tested as shown in Figure 14.
2. Supplied as a design limit. Neither guaranteed nor tested.
Figure 2. System Clock and SDCLK Timing Diagram
Symbol Description Conditions Min Max Units
fCLK System clock frequency -- 66 MHz
tHIGH System clock high time 6.67 -- ns
tLOW System clock low time 6.67 -- ns
tDSD1System clock to SDRAM
clock propagation delay
25ns
tRSD2SDRAM clock rise time fCLK = 66MHz
VO transitioning between
VOH (min) and VOL
(max)
-- 2 ns
tFSD2SDRAM clock fall time fCLK = 66MHz
VO transitioning between
VOH (min) and VOL
(max)
-- 2 ns
tJCCSD2SDRAM clock cycle-cycle
jitter
fCLK = 66MHz -- 500 ps
tDSD
tDSD
1/fCLK
tLOW
ttHIGH
1/f
t
SYSCLK
SDCLK
21
3.7 DC Electrical Characteristics for PCI Inputs (pre- and post-radiation)
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.
3.8 DC Electrical Characteristics for PCI Outputs (pre- and post-radiation)
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. Supplied as a design guideline. Neither guaranteed nor tested.
2. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.
3.9 AC Electrical Characteristics for PCI Inputs (pre- and post-radiation)
Symbol Description Conditions Min Max Units
VIH High-level input voltage 0.5VDD -- V
VIL Low-level input voltage -- 0.3VDD V
IIN Input leakage current VIN = VDD -- 10 A
VIN = VSS -10 --
CIN1Input pin capacitance f = 1MHz; VDD = 0V, VDDC
= 0V
352 CQFP -- 19 pF
484 CLGA -- 22
Symbol Description Conditions Min Max Units
VOH High-level output voltage IOH = -500A0.9V
DD -- V
VOL Low-level output voltage IOL = 1500A--0.1V
DD V
IOZ Three-state output current VO = VDD -10 10 A
VO = VSS -10 10
IOS1Short-circuit output current VO = VDD; VDD = 3.6V -- 270 mA
VO = VSS; VDD = 3.6V -130 --
COUT2Output pin capacitance f = 1MHz; VDD = 0V, VDDC
= 0V
352 CQFP -- 19 pF
484 CLGA -- 22
22
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Figure 3. PCI Clock Timing Diagram
Symbol Description Conditions Min Max Units
fPCI_CLK PCI clock frequency -- 33 MHz
tHIGH PCI clock high time 11 -- ns
tLOW PCI clock low time 11 -- ns
1/fPCI_CLK
tLOW
ttHIGH
1/f
t
PCI_CLK
23
4.0 Timing Specifications
4.1 Power Sequencing and Reset
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. Guaranteed by design.
2. Guaranteed by design for control signals.
Symbol Description Conditions Min Max Units
tVCD1VDD valid to VDDC delay VDD > 3.0V; VDDC > 2.30V 0 -- ns
tVHBZ1VDD valid to control signals high-z
(WRITE, OE, IOS, ROMS[1:0],
RWE[3:0], RAMOE [4:0], READ
SDWE, and SDCS[1:0])
VDD valid to outputs high-z
([DATA[31:0], CB[7:0], and GPIO[15:0])
VDD > 1.5V; VDDC = 0V -- 4 tCLK
tCHBV1VDDC valid to control signals valid-inac-
tive
(WRITE, OE, IOS, ROMS[1:0],
RWE[3:0], RAMOE [4:0], READ
SDWE, and SDCS[1:0])
VDD > 3.0V; VDDC > 2.30V -- 4 tCLK
tRESET11VDDC valid to RESET deassert VDDC > 2.30V 4 -- tCLK
tRESET2 RESET deasserted to outputs valid-active
(ROMS[0] and OE)
-- 12 tCLK
tRESET32RESET asserted to control signals valid-
inactive
(WRITE, OE, IOS, ROMS[1:0],
RWE[3:0], RAMOE [4:0], READ
SDWE, and SDCS[1:0])
RESET asserted to outputs high-z
(DATA[31:0], CB[7:0], and GPIO[15:0])
-- 4 tCLK
24
Figure 4. Power Sequencing and Reset Timing Diagram
4.1.1. Power Sequencing
Proper power sequencing of the UT699 is achieved by bringing up VDD to its recommended minimum operating voltage of 3.0V,
and then delaying tVCD clock cycles before bringing up the VDDC supply. If power is applied to the VDDC supply pins while VDD
is less than 3.0V, excessive current or damage to the device could occur.
4.1.2 Bus Control and Bi-Direct Fail-Safe Circuitry
In order to prevent bus contention on the external memory interface while VDDC is ramping up, the UT699 has functionality to
ensure that the bi-direct and memory bus control signals described in Section 4.1 will be in a high-z state tVHBZ clock cycles after
VDD reaches 1.5V. The core logic will then put these signals into their valid-inactive states tCHBV clock cycles after VDDC reaches
2.3V.
It is recommended that users place pull-up resistors on the indicated output enable, write enable, and chip select pins, and a pull-
down resistor on the READ pin, if there will be a significant delay between when VDD and VDDC reach their recommended operat-
ing voltages. This will prevent bus capacitance or transients from inadvertently placing these pins in an active state, which could
result in external memory devices driving the address and data buses.
4.1.3 Reset Circuitry
The reset circuitry is controlled by the core logic; therefore, the circuitry is functional only after VDDC reaches its minimum operat-
ing voltage of 2.3V. After VDDC is stable, the system must continue to assert RESET for a minimum of tRESET1 clock cycles before
it can be de-asserted. Asserting RESET for less time could result in the RESET signal not being recognized.
VALID-INACTIVE VALID-ACTIVE VALID-INACTIVE
VALID-ACTIVE
tRESET3tVHBZ
tRESET3tRESET2
tCHBV
tVHBZ
tRESET1
tVCD
SYSCLK
VDD 3.3V
VDDC 2.5V
RESET
Memory Bus
Tri-State Outputs
Control Signals
OV
OV
25
The UT699 will begin fetching code from external memory no more than tRESET2 clock cycles after RESET is de-asserted. Control
signals ROMS[0] and OE will be driven to their valid-active states in order for the UT699 to begin fetching code from PROM.
During normal operation, the indicated bus control signals will go to a valid-inactive state, and the bi-directs will go to a high-z
state, within tRESET3 clock cycles after the assertion of RESET.
4.1.4 Programming Pins GPIO[2:0]
Data on pins GPIO[2:0] are latched on the rising edge of reset. The states of these pins determine the data width of the PROM area,
and enable EDAC for the PROM area. Chapter 3 of the User’s Manual describes the value of these inputs to achieve the required
operation.
In order for the state of GPIO[2:0] to be properly latched, it is recommended to place pull-up or pull-down resistors on these pins to
ensure that the setup and hold timing is met. The states of these pins should be statically set prior to the rising edge of RESET.
4.2 Output Timing Characteristics for Memory Interface, ERROR, and WDOG
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. All outputs are measured using the load conditions shown in Figure 14.
2. High-Z defined as +/-300mV change from steady state.
Symbol Description Min Max Units
t11SDCLK to output valid
(ADDR[27:0], WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE
[4:0], RAMS[4:0], READ, SDRAS, SDCAS, SDWE, SDCS[1:0], and
SDDQM[3:0])
28ns
t21SDCLK to output valid
(DATA[31:0] and CB[7:0])
28ns
t31,2 SDCLK to output high-Z
(DATA[31:0] and CB[7:0])
28ns
t41SDCLK to signal low
(ERROR and WDOG)
29ns
t81,2 WRITEor RWE[3:0]to output high-z
(DATA [31:0] and CB[7:0])
2.5 - ns
t91Skew from first memory output signal transition to last memory output
signal transition
-2ns
26
Figure 5. Memory Interface, ERROR, and WDOG Output Timing Diagram
4.3 Input Timing Characteristics for Memory Interface
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. CB[7] is not used for EDAC and is not tested
2. Guaranteed by design.
.
Figure 6. Memory Interface Input Timing Diagram
Symbol Description Min Max Units
t51Setup time to SDCLK
(DATA[31:0], CB[6:0], BEXC, and synchronous BRDY)
0-ns
t61Hold time from SDCLK
(DATA[31:0], CB[6:0], BEXC, and synchronous BRDY)
1-ns
t72Asynchronous BRDY pulse width 1.5 - tCLK
t4
t8
t3t2
t1
t9t9
SDCLK
All Outputs
DATA[31:0] and CB[7:0]
ERROR and WDOG
(Except Bi-Directs
and Open-Drains)
WRITE and RWE[3:0]
(Bi-Direct Outputs)
(Open-Drain Outputs)
t6t5
t7t7
SDCLK
All Inputs
Asynchronous BRDY
(Except Async BRDY)
27
4.4 Timing Characteristics for General Purpose Input / Output (GPIO)
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. All outputs are measured using the load conditions shown in Figure 14.
Figure 7. General Purpose I/O Timing Diagram
Symbol Description Min Max Units
t101SDCLK to GPIO output valid
(GPIO[15:0])
28ns
28
4.5 Timing Characteristics SpaceWire Interface
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. The SPW_CLK frequency must be less than 4x the SYS_CLK frequency. For example, if SPW_CLK is running at 200MHz, the SYS_CLK frequency must be
greater than 50MHz.
2. All outputs are measured using the load conditions shown in Figure 14.
3. Applies to both high pulse and low pulse.
4. A unit interval (UI) is defined as the nominal, or ideal, bit width.
Figure 8. SpaceWire Transmit Timing Diagram
Figure 9. SpaceWire Receive Timing Diagram
Symbol Description Min Max Units
t111SPW_CLK period 5 -- ns
t122SPW_CLK to data delay
(SPW_TXD[3:0])
37ns
t132SPW_CLK to strobe delay
(SPW_TXS[3:0])
37ns
t143Transmit data and strobe bit width variation
(SPW_TXD[3:0] and SPW_TXS[3:0])
UI-6004UI+600 ps
t153Receive data and strobe bit width
(SPW_RXD[3:0] and SPW_RXS[3:0])
2.5 -- ns
t16 Receive data and strobe edge separation
(SPW_RXD[3:0] and SPW_RXS[3:0])
2.5 -- ns
t13t13t14t14
t12t12t14t14
t11t11
SPW_CLK
SPW_TXD
SPW_TXS
t15t
t16t16
t15t
SPW_RXD
SPW_RXS
29
4.6 Timing Characteristics for PCI Interface
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. All outputs are measured using the load conditions shown in Figure 14.
2. High-Z defined as +/-300mV change from steady state.
3. Guaranteed by design.
Symbol Description Min Max Units
t171PCI_CLK to output valid
(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,
PCI_FRAME, PCI_IRDY, PCI_TDRY,
PCI_STOP, PCI_DEVSEL, PCI_REQ, and
PCI_ARB_GNT[7:0])
213ns
t181,2 PCI_CLK to output valid from high-z
(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,
PCI_FRAME, PCI_IRDY, PCI_TDRY,
PCI_STOP, and PCI_DEVSEL
213ns
t191,2 PCI_CLK to output high-Z
(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,
PCI_FRAME, PCI_IRDY, PCI_TDRY,
PCI_STOP, and PCI_DEVSEL
-- 14 ns
t20 Setup time to PCI_CLK
(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,
PCI_FRAME, PCI_IRDY, PCI_TDRY,
PCI_STOP, PCI_DEVSEL, PCI_IDSEL,
PCI_GNT, and PCI_ARB_REQ[7:0])
3--ns
t21 Hold time from PCI_CLK
(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,
PCI_FRAME, PCI_IRDY, PCI_TDRY,
PCI_STOP, PCI_DEVSEL, and
PCI_IDSEL)
1--ns
t223PCI_RST active time after power stable 1 -- ms
t233PCI_RST active time after PCI_CLK stable 100 -- us
t243PCI_RST active to output float delay -- 40 ns
30
Figure 10. PCI Timing Diagram
Figure 11. PCI Reset Timing Diagram
t21
t20
t19t18
t17
PCI_CLK
All Outputs
Bi-Direct and
All Inputs
Tri-State Outputs
t24
t23
t22
PCI_CLK
PCI_RST
Tri-State Outputs
3.3V
0V
VDD
31
4.7 Timing Characteristics for Ethernet Interface
(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC)
Notes:
1. All outputs are measured using the load conditions shown in Figure 14.
2. ERX_COL and ERX_CRS are asynchronous inputs and are not tested.
3. fEMDC = fSYSCLK / 202.
4. Guaranteed by design.
Figure 12. Ethernet Transmit and Receive Timing
Symbol Description Conditions Min Max Units
t251ETX_CLK to output valid
(ETXD[3:0], and ETX_EN)
28ns
t262Setup time to ERX_CLK
(ERX_DV4ERX_ER, and ERXD[3:0])
1--ns
t272Hold time from ERX_CLK
(ERX_DV4ERX_ER, and ERXD[3:0])
1--ns
t281EMDCto output valid (EMDIO) fEMDC= 123KHz3; fSYSCLK = 25MHz 211ns
t294Setup time to EMDC(EMDIO) 10 -- ns
t304Hold time from EMDC(EMDIO) 5 -- ns
t27t26
t25
ETX_CLK
All Outputs
ERX_CLK
All Inputs
32
Figure 13. Ethernet MDIO Interface Timing
4.8 Test Conditions for Timing Specifications
Figure 14. Equivalent Load Circuit for Timing Characteristics Tests
CL = 50 pF for ATE test load
CL =15 pF for benchtop test load
t30t29
t28
EMDC
EMDIO (Output)
EMDIO (Input)
VDD VDD
CL


33
5.0 Operational Environment
The UT699 processor includes the following SEU mitigation features:
* Register file SEU error-correction of up to 1 error per 32-bit word
* Cache memory error-detection of up to 4 errors per tag or 32-bit word
* Autonomous and software transparent error handling
* No timing impact due to error detection or correction.
Notes:
1. The UT699 is latchup immune to particle LETs >108 MeV-cm2/mg.
2. Worst case temperature and voltage of TC = +105oC, VDD = 3.6V, VDDC = 2.7V.
3. Contact factory for error rate information.
Table 1. Operational Environment
Parameter Limit Units
Total Ionizing Dose (TID) 3E5 rads(Si)
Single Event Latchup (SEL) 1, 2 >108 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
34
6.0 Packaging
Figure 15. 352-lead Ceramic Quad Flatpack with Top-Brazed Leads
35
Figure 16. 484-lead Ceramic Land Grid Array
36
Figure 17. 484-lead Ceramic Column Grid Array
37
Figure 18. 484-lead Ceramic Ball Grid Array
38
7.0 Ordering Information
UT699 LEON 3FT
Package Option Associated Lead Finish
(X) 352-CQFP (C) Gold
(Z) 484-CLGA (C) Gold
(S) 484-CCGA (A) Hot Solder Dipped
(C) 484-CBGA (A) Hot Solder Dipped
Lead Finish: (NOTE 1)
(C) = Gold
(A) = Hot Solder Dipped or Tinned
Screening Level: (NOTE 2 & 3)
(P) = Prototype (Temperature Range: 25oC only)
(E) = HiRel (Temperature Range: -40oC to +105oC)
Case Outline:
(X) = 352-Ceramic Quad Flat Package, Top Brazed
(Z) = 484-Ceramic Land Grid Array
(S) = 484-Ceramic Column Grid Array
(C) = 484-Ceramic Ball Grid Array
UT699 32-bit LEON 3FT
UT699 - * * *
Notes:
1. Lead finish (A or C) must be specified.
2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Radiation is neither tested nor guaranteed.
3. HiRel Flow per Aeroflex Manufacturing Flows Document. Radiation is neither tested nor guaranteed.
39
UT699 LEON 3FT: SMD
Lead Finish: (NOTE 1)
(C) = Gold
Case Outline: (NOTE 2)
(X) = 352-Ceramic Quad Flat Package, Top Brazed
(Y) = 484-Ceramic Land Grid Array Package
Screening Level:
(Q) = QML Class Q
(V) = QML Class V
Device Type: (NOTE 3)
(01) = UT699 (Temperature range: -40oC to +105oC)
(02) = UT699 Assembled to Aeroflex’s Q+ Flow (Temp range: -40oC to +105oC)
Drawing Number:
08228
Total Dose:
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
Federal Stock Class Number: No Options
5962 * 08228 ** * * *
Notes:
1. Lead finish is “C” (gold) only.
2. Aeroflex offers Column Attachment as an additional service for the Ceramic Land Grid Array (Case outline "Y"). If needed, please ask for
COLUMN ATTACHMENT when submitting your request for quotation.
3.Aeroflex’s Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QML-Q product through the SMD that is manufactured with Aero-
flex’s standard QML-V flow, and has completed QML-V qualification per MIL-PRF-38535.
40
41
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www.aeroflex.com info-ams@aeroflex.com
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
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trademark rights, or any other of the intellectual rights of
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel