2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG3241 FUNCTIONAL BLOCK DIAGRAM FEATURES 225 ps propagation delay through the switch 4.5 switch connection between ports Data rate 1.5 Gbps 2.5 V/3.3 V supply operation Selectable level shifting/translation Level translation 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V Small signal bandwidth 770 MHz Tiny 6-lead SC70 package and 6-lead SOT-66 package B 04221-001 A BE Figure 1. APPLICATIONS 3.3 V to 1.8 V voltage translation 3.3 V to 2.5 V voltage translation 2.5 V to 1.8 V voltage translation Bus switching Bus isolation Hot swap Hot plug Analog switch applications GENERAL DESCRIPTION The ADG3241 is a 2.5 V or 3.3 V single digital switch. It is designed on a low voltage CMOS process that provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. translating select pin (SEL) is included. When SEL is low, VCC is reduced internally, allowing for level translation between 3.3 V inputs and 1.8 V outputs. This makes the device suited to applications requiring level translation between different supplies, such as converter to DSP/microcontroller interfacing. The switch is enabled by means of the bus enable (BE) input signal. This digital switch allows a bidirectional signal to be switched when on. In the off condition, signal levels up to the supplies are blocked. 1. 3.3 V or 2.5 V supply operation. 2. Extremely low propagation delay through switch. 3. 4.5 switches connect inputs to outputs. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device translates the outputs to 1.8 V. In addition to this, a level 4. Level and voltage translation. 5. Tiny, SC70 package and SOT-66 package. PRODUCT HIGHLIGHTS Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADG3241 TABLE OF CONTENTS Features .............................................................................................. 1 Timing Measurement Information .............................................. 11 Applications....................................................................................... 1 Bus Switch Applications ................................................................ 12 Functional Block Diagram .............................................................. 1 Mixed Voltage Operation, Level Translation.......................... 12 General Description ......................................................................... 1 3.3 V to 2.5 V Translation ......................................................... 12 Product Highlights ........................................................................... 1 2.5 V to 1.8 V Translation ......................................................... 12 Revision History ............................................................................... 2 3.3 V to 1.8 V Translation ......................................................... 12 Specifications..................................................................................... 3 Bus Isolation................................................................................ 13 Absolute Maximum Ratings............................................................ 4 Hot Plug and Hot Swap Isolation............................................. 13 ESD Caution.................................................................................. 4 Analog Switching ....................................................................... 13 Pin Configuration and Function Descriptions............................. 5 High Impedance During Power-Up/Power-Down................ 13 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 14 Terminology .................................................................................... 10 Ordering Guide .......................................................................... 14 REVISION HISTORY 5/06 -- Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 4............................................................................ 5 Changes to Ordering Guide ......................................................... 14 Changes to Absolute Maximum Ratings........................................3 Changes to Pin Configurations .......................................................4 Changes to Ordering Guide .............................................................4 Updated Outline Dimensions....................................................... 11 10/04 -- Rev. 0 to Rev. A. Changes to Features.......................................................................... 1 Changes to Specifications ................................................................ 2 7/03--Revision 0: Initial Version Rev. B | Page 2 of 16 ADG3241 SPECIFICATIONS VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current Off State Leakage Current On State Leakage Current Maximum Pass Voltage Symbol Conditions Min VINH VINH VINL VINL II IOZ VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 2.0 1.7 VP 0 A, B VCC 0 A, B VCC VA/VB = VCC = SEL = 3.3 V, IO = -5 A VA/VB = VCC = SEL = 2.5 V, IO = -5 A VA/VB = VCC = 3.3 V, SEL = 0 V, IO = -5 A CA OFF CB OFF CA, CB ON CIN f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ CL = 50 pF, VCC = SEL = 3 V VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 2.3 V to 2.7 V; SEL = VCC VCC = 2.3 V to 2.7 V; SEL = VCC VCC = SEL = 3.3 V; VA/VB = 2 V VCC = SEL = 3.3 V; VA/VB = 2 V DIGITAL SWITCH On Resistance RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA POWER REQUIREMENTS VCC Quiescent Power Supply Current ICC Digital Inputs = 0 V or VCC; SEL = VCC Digital Inputs = 0 V or VCC; SEL = 0 V VCC = 3.6 V, BE = 3.0 V; SEL = VCC CAPACITANCE 3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD 4 Bus Enable Time BE to A or B 5 Bus Disable Time BE to A or B5 Bus Enable Time BE to A or B5 Bus Disable Time BE to A or B5 Bus Enable Time BE to A or B5 Bus Disable Time BE to A or B5 Maximum Data Rate Channel Jitter Increase in ICC per Input 6 2.2 1.5 1.5 B Version Typ 2 Max 0.01 0.01 0.01 2.5 1.8 1.8 3.5 3.5 7 4 1 1 1 1 1 1 3.2 3 3 2.5 3 2.5 1.5 45 4.5 12 5 9 5 12 2.3 ICC 1 0.8 0.7 1 1 1 2.7 2.1 2.1 0.01 0.1 0.15 Unit V V V V A A A V V V pF pF pF pF 0.225 4.6 4 4 3.8 4 3.4 ns ns ns ns ns ns ns Gbps ps p-p 8 28 9 18 8 3.6 1 0.2 8 V A mA A Temperature range is as follows: B Version: -40C to +85C. Typical values are at 25C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 See Timing Measurement Information section. 6 This current applies to the Control Pin BE only. The A and B ports contribute no significant ac or dc currents as they transition. 2 Rev. B | Page 3 of 16 ADG3241 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Parameter VCC to GND Digital Inputs to GND DC Input Voltage DC Output Current Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature SC70 Package JA Thermal Impedance SOT-66 Package JA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating -0.5 V to +4.6 V -0.5 V to +4.6 V -0.5 V to +4.6 V 25 mA per channel Only one absolute maximum rating can be applied at any one time. -40C to +85C -65C to +150C 150C 332C/W 191C/W (4-layer board) 300C 235C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 4 of 16 ADG3241 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 6 SEL VCC 1 ADG3241 5 VCC TOP VIEW (Not to Scale) A 3 4 B 6 ADG3241 2 Table 3. Pin Function Descriptions SC70 1 2 3 4 5 6 Mnemonic BE GND A B VCC SEL 6 4 3 5 1 2 Description Bus Enable (Active Low) Ground Reference Port A, Input or Output Port B, Input or Output Positive Power Supply Voltage Level Translation Select Table 4. Truth Table BE SEL 1 Function L L H L H X A = B, 3.3 V to 1.8 V level shifting A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V level shifting Disconnect 1 5 Figure 3. 6-Lead SOT-66 Figure 2. 6-Lead SC70 Pin No. SOT-66 BE B TOP VIEW A 3 (Not to Scale) 4 GND SEL 04221-002 GND 2 SEL = 0 V only when VDD = 3.3 V 10%. Rev. B | Page 5 of 16 04221-003 BE 1 ADG3241 TYPICAL PERFORMANCE CHARACTERISTICS 20 40 VCC = 3.3V SEL = VCC TA = 25C SEL = VCC 35 15 30 VCC = 3V VCC = 3.3V RON () RON () 25 20 VCC = 3.6V 10 +85C 15 +25C 5 10 5 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 3.0 3.5 0 0 1.0 0.5 2.0 1.5 VA/VB (V) Figure 4. On Resistance vs. Input Voltage 04221-007 0 04221-004 0 -40C Figure 7. On Resistance vs. Input Voltage for Different Temperatures 40 15 TA = 25C VCC = 2.5V SEL = VCC SEL = VCC 35 30 10 +85C RON () RON () 25 20 VCC = 2.3V 15 -40C 5 VCC = 2.5V 10 +25C VCC = 2.7V 0 0.5 1.0 1.5 VA/VB (V) 2.0 2.5 3.0 0 04221-005 0 0 1.2 VA/VB (V) Figure 5. On Resistance vs. Input Voltage Figure 8. On Resistance vs. Input Voltage for Different Temperatures 40 3.0 TA = 25C SEL = 0V 35 1.0 0.5 04221-008 5 VCC = 3.6V TA = 25C SEL = VCC IO = -5A 2.5 30 VCC = 3V 2.0 VOUT (V) VCC = 3.3V 20 VCC = 3.6V 15 VCC = 3.3V VCC = 3V 1.5 1.0 10 0 0 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 3.0 3.5 0 Figure 6. On Resistance vs. Input Voltage 0 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 Figure 9. Pass Voltage vs. VCC Rev. B | Page 6 of 16 3.0 3.5 04221-009 0.5 5 04221-006 RON () 25 ADG3241 3.0 2.5 TA = 25C SEL = VCC IO = -5A 2.0 VCC = 2.7V TA = 25C VA = 0V BE = 0 2.5 VOUT (V) VOUT (V) 2.0 1.5 VCC = 2.5V VCC = 2.3V VCC = 3.3V; SEL = 0V 1.5 VCC = SEL = 3.3V 1.0 1.0 0.5 0.5 0 0.5 1.0 1.5 VA/VB (V) 2.0 2.5 3.0 0 04221-010 0 0 0.02 0.06 0.08 0.10 IO (A) Figure 10. Pass Voltage vs. VCC Figure 13. Output Low Characteristic 2.5 3.0 TA = 25C VCC = 3.6V SEL = 0V IO = -5A 2.0 TA = 25C VA = VCC 2.5 BE = 0 2.0 1.5 VOUT (V) VOUT (V) 0.04 04221-013 VCC = SEL = 2.5V VCC = 3.3V VCC = 3V 1.0 VCC = SEL = 3.3V 1.5 1.0 VCC = SEL = 2.5V 0.5 0.5 1.0 1.5 2.0 3.0 2.5 3.5 VA/VB (V) VCC = 3.3V; SEL = 0V 0 -0.10 -0.08 -0.06 -0.02 0 Figure 14. Output High Characteristic Figure 11. Pass Voltage vs. VCC 0 500 TA = 25C 450 TA = 25C SEL = VCC ONOFF CL = 1nF -0.2 400 350 VCC = 2.5V -0.4 250 QINJ (pC) VCC = SEL = 3.3V 300 VCC = 3.3V; SEL = 0V -0.6 VCC = 3.3V 200 -0.8 150 100 -1.0 0 -1.2 0 5 10 15 20 25 30 35 ENABLE FREQUENCY (MHz) 40 45 50 0 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 Figure 15. Charge Injection vs. Source Voltage Figure 12. ICC vs. Enable Frequency Rev. B | Page 7 of 16 3.0 04221-015 VCC = SEL = 2.5V 50 04221-012 ICC (A) -0.04 IO (A) 04221-014 0 04221-011 0 0.5 ADG3241 2 4.0 1 3.5 0 ENABLE 3.0 VCC = SEL = 2.5V 2.5 TIME (ns) -2 -3 TA = 25C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER: RL = RS = 50 -6 -7 -8 0.03 0.1 1.5 1.0 0.5 1 10 100 1000 FREQUENCY (MHz) 0 -40 40 60 80 100 TA = 25C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER: RL = RS = 50 -30 80 70 -40 -50 -60 60 50 40 -70 30 -80 20 -90 10 1 10 FREQUENCY (MHz) 100 0 04221-017 0.1 1000 0.5 0.9 1.1 1.3 1.5 DATA RATE (Gbps) 1.7 1.9 Figure 20. Jitter vs. Data Rate; PRBS 31 Figure 17. Off Isolation vs. Frequency 100 4.0 3.5 0.7 04221-020 -20 VCC = SEL = 3.3V VIN = 1.5V p-p 20dB ATTENUATION 90 JITTER (ps p-p) -10 ATTENUATION (dB) 20 Figure 19. Enable/Disable Time vs. Temperature 0 VCC = SEL = 3.3V DISABLE ENABLE 95 VCC = SEL = 3.3V VIN = 1.5V p-p 20dB ATTENUATION 90 3.0 EYE WIDTH (%) 85 2.5 ENABLE DISABLE 2.0 VCC = 3.3V, SEL = 0V 1.5 80 75 70 65 1.0 60 0.5 0 -40 % EYE WIDTH = ((CLOCK PERIOD - JITTER p-p)/CLOCK PERIOD) x 100% 55 -20 0 20 40 TEMPERATURE (C) 60 80 50 04221-018 TIME (ns) 0 TEMPERATURE (C) Figure 16. Bandwidth vs. Frequency -100 -20 04221-019 -5 04221-016 -4 DISABLE 2.0 Figure 18. Enable/Disable Time vs. Temperature 0.5 0.7 0.9 1.1 1.3 1.5 DATA RATE (Gbps) 1.7 Figure 21. Eye Width vs. Data Rate; PRBS 31 Rev. B | Page 8 of 16 1.9 04221-021 ATTENUATION (dB) -1 VCC = 3.3V SEL = 3.3V VIN = 1.5V p-p 20dB ATTENUATION TA = 25C 20mV/DIV 200ps/DIV 04221-022 50mV/DIV 200ps/DIV Figure 22. Eye Pattern; 1.5 Gbps, VCC = 3.3 V, PRBS 31 VCC = 2.5V SEL = 2.5V VIN = 1.5V p-p 20dB ATTENUATION TA = 25C Figure 23. Eye Pattern; 1.244 Gbps, VCC = 2.5 V, PRBS 31 Rev. B | Page 9 of 16 04221-023 ADG3241 ADG3241 TERMINOLOGY VCC Positive power supply voltage. CIN Control input capacitance. This consists of BE and SEL. GND Ground (0 V) reference. ICC Quiescent power supply current. This current represents the leakage current between the VCC and ground pins. It is measured when all control inputs are at a logic high or low level and the switches are off. VINH Minimum input voltage for Logic 1. VINL Maximum input voltage for Logic 0. ICC Extra power supply current component for the BE control input when the input is not driven at the supplies. II Input leakage current at the control inputs. IOZ Off state leakage current. It is the maximum leakage current at the switch pin in the off state. IOL On state leakage current. It is the maximum leakage current at the switch pin in the on state. VP Maximum pass voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. RON Ohmic resistance offered by a switch in the on state. It is measured at a given voltage by forcing a specified amount of current through the switch. CX OFF Off switch capacitance. CX ON On switch capacitance. tPLH, tPHL Data propagation delay through the switch in the on state. Propagation delay is related to the RC time constant RON x CL, where CL is the load capacitance. tPZH, tPZL Bus enable times. These are the times taken to cross the VT voltage at the switch output when the switch turns on in response to the control signal, BE. tPHZ, tPLZ Bus disable times. These are the times taken to place the switch in the high impedance off state in response to the control signal. It is measured as the time taken for the output voltage to change by V from the original quiescent level, with reference to the logic level transition at the control input. Refer to Figure 26 for enable and disable times. Max Data Rate Maximum rate at which data can be passed through the switch. Channel Jitter Peak-to-peak value of the sum of the deterministic and random jitter of the switch channel. Rev. B | Page 10 of 16 ADG3241 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms, the notation that is used is VIN and VOUT where 0V tPZL 2 x VCC SW1 VOUT VIN = 0V VIN = VCC CL VCC VT VL + V tPHZ tPZH DUT RT VCC VOUT SW1 @ 2VCC GND RL tPLZ VL VH VOUT SW1 @ GND VH - V VT 0V 0V RL Figure 26. Enable and Disable Times Figure 24. Load Circuit Table 5. Switch Position 04221-024 NOTES 1. PULSE GENERATOR FOR ALL PULSES: tR 2.5ns, tF 2.5ns, FREQUENCY 10MHz. 2. CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES. 3. RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT OF THE PULSE GENERATOR. Test tPLZ, tPZL tPHZ, tPZH S1 2 x VCC GND VIH CONTROL INPUT BE VT tPLH VOUT 0V VH VT VL 04221-025 tPLH Figure 25. Propagation Delay Table 6. Test Conditions Symbol VCC = 3.3 V 0.3 V (SEL = VCC) VCC = 2.5 V 0.2 V (SEL = VCC) VCC = 3.3 V 0.3 V (SEL = 0 V) Unit RL V CL VT 500 300 50 1.5 500 150 30 0.9 500 150 30 0.9 mV pF V Rev. B | Page 11 of 16 04221-026 VIN PULSE GENERATOR VINH VT CONTROL INPUT BE VIN = VA and VOUT = VB or VIN = VB and VOUT = VA VCC DISABLE ENABLE ADG3241 BUS SWITCH APPLICATIONS MIXED VOLTAGE OPERATION, LEVEL TRANSLATION 2.5 V TO 1.8 V TRANSLATION Bus switches can provide an ideal solution for interfacing between mixed voltage systems. The ADG3241 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V. When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is 0 V to VCC, the maximum output signal is, as before, clamped to within a voltage threshold below the VCC supply. In this case, the output is limited to approximately 1.8 V, as shown in Figure 31. 2.5V 3.3V 3.3V 2.5V 3.3V ADC ADG3241 Figure 27 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3241 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 2.5V MICROPROCESSOR 04221-030 VOUT SWITCH INPUT 2.5V VIN 04221-031 SWITCH OUTPUT 04221-027 0V Figure 31. 2.5 V to 1.8 V Voltage Translation, SEL = VCC When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is 0 V to VCC, the maximum output signal will be clamped to within a voltage threshold below the VCC supply. 3.3V 3.3V 2.5V 3.3 V TO 1.8 V TRANSLATION The ADG3241 offers the option of interfacing between a 3.3 V device and a 1.8 V device. This is possible through the use of the SEL pin. The SEL pin is an active low control pin. SEL activates internal circuitry in the ADG3241 that allows voltage translation between 3.3 V devices and 1.8 V devices. 3.3V 2.5V 2.5V 04221-028 ADG3241 Figure 28. 3.3 V to 2.5 V Voltage Translation, SEL = VCC 3.3V Figure 32. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V 04221-029 SWITCH OUTPUT 2.5V VIN 1.8V When VCC is 3.3 V and the input signal range is 0 V to VCC, the maximum output signal is clamped to 1.8 V, as shown in Figure 32. To do this, the SEL pin must be tied to Logic 0. If SEL is unused, it should be tied directly to VCC. 3.3V SUPPLY SEL = 3.3V 3.3V ADG3241 04221-032 In this case, the output is limited to 2.5 V, as shown in Figure 29. This device can be used for translation from 2.5 V to 3.3 V devices and also between two 3.3 V devices. SWITCH INPUT 2.5V SUPPLY SEL = 2.5V 1.8V 3.3 V TO 2.5 V TRANSLATION 0V 1.8V Figure 30. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC Figure 27. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor VOUT ADG3241 2.5V Figure 29. 3.3 V to 2.5 V Voltage Translation, SEL = VCC Rev. B | Page 12 of 16 3.3V SUPPLY SEL = 0V 1.8V SWITCH OUTPUT CPU SWITCH INPUT 3.3V VIN 04221-033 0V RAM Figure 33. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V CARD I/O PLUG-IN CARD (2) CARD I/O BUS Figure 35. ADG3241 in a Hot Plug Application BUS ISOLATION A common requirement of bus architectures is low capacitance loading of the bus. Such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. Because the ADG3241 is designed specifically for applications that do not need drive yet require simple logic functions, it solves this requirement. The device isolates access to the bus, thus minimizing capacitance loading. LOAD A LOAD C BUS/ BACKPLANE LOAD B LOAD D There are many systems, such as docking stations, PCI boards for servers, and line cards for telecommunications switches, that require the ability to handle hot swapping. If the bus can be isolated prior to insertion or removal, there is more control over the hot swap event. This isolation can be achieved using bus switches. The bus switches are positioned on the hot swap card between the connector and the devices. During hot swap, the ground pin of the hot swap card must connect to the ground pin of the backplane before any other signal or power pins. ANALOG SWITCHING Bus switches can be used in many analog switching applications, such as video graphics. Bus switches can have lower on resistance, smaller on and off channel capacitance, and thus improved frequency performance over their analog counterparts. 04221-034 BUS SWITCH LOCATION PLUG-IN CARD (1) 04221-035 VOUT ADG3241 ADG3241 ADG3241 Figure 34. Location of Bus Switched in a Bus Isolation Application HOT PLUG AND HOT SWAP ISOLATION The ADG3241 is suitable for hot swap and hot plug applications. The output signal of the ADG3241 is limited to a voltage that is below the VCC supply, as shown in Figure 29, Figure 31, and Figure 33. Therefore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from damage. In hot plug applications, the system cannot be shut down when new hardware is being added. To overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. The bus switch is turned off during hot plug. Figure 35 shows a typical example of this type of application. The bus switch channel itself, consisting solely of an NMOS switch, limits the operating voltage (see Figure 4 for a typical plot), but in many cases this does not present an issue. HIGH IMPEDANCE DURING POWER-UP/POWERDOWN To ensure the high impedance state during power-up or powerdown, BE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. Rev. B | Page 13 of 16 ADG3241 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 6 5 4 1 2 3 2.40 2.10 1.80 PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 0.40 0.10 1.10 0.80 0.30 0.15 0.10 MAX SEATING PLANE 0.46 0.36 0.26 0.22 0.08 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 36. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.70 1.66 1.50 6 1.30 1.20 1.10 5 4 TOP VIEW 1 2 3 0.20 MIN 0.26 0.19 0.11 1.70 1.65 1.50 BOTTOM VIEW 0.10 NOM 0.05 MIN PIN 1 12 MAX 0.60 0.57 0.53 0.18 0.17 0.13 0.34 MAX 0.27 NOM 0.50 BSC 0.30 0.23 0.10 0.25 MAX 0.17 MIN SEATING PLANE Figure 37. 6-Lead Small Outline Transistor Package [SOT-66] (RY-6-1) Dimensions shown in millimeters ORDERING GUIDE Model ADG3241BKS-REEL7 ADG3241BKS-500RL7 ADG3241BKSZ-500RL7 1 ADG3241BKSZ-REEL71 ADG3241BKSZ-REEL1 ADG3241BRYZ-REEL71 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Thin Shrink Small Outline Transistor Package (SC70) 6-Lead Small Outline Transistor Package (SOT-66) Z = Pb-free part. Rev. B | Page 14 of 16 Package Option KS-6 KS-6 KS-6 KS-6 KS-6 RY-6-1 Branding SKA SKA S19 S19 S19 00 ADG3241 NOTES Rev. B | Page 15 of 16 ADG3241 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04221-0-4/06(B) Rev. B | Page 16 of 16