2.5 V/3.3 V, 1-Bit, 2-Port
Level Translator Bus Switch in SOT-66
ADG3241
Rev. B
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FUNCTIONAL BLOCK DIAGRAM
FEATURES
225 ps propagation delay through the switch
BE
A
B
04221-001
4.5 Ω switch connection between ports
Data rate 1.5 Gbps
2.5 V/3.3 V supply operation
Selectable level shifting/translation
Level translation Figure 1.
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small signal bandwidth 770 MHz
Tiny 6-lead SC70 package and 6-lead SOT-66 package
APPLICATIONS
3.3 V to 1.8 V voltage translation
3.3 V to 2.5 V voltage translation
2.5 V to 1.8 V voltage translation
Bus switching
Bus isolation
Hot swap
Hot plug
Analog switch applications
GENERAL DESCRIPTION
The ADG3241 is a 2.5 V or 3.3 V single digital switch. It is
designed on a low voltage CMOS process that provides low
power dissipation yet gives high switching speed and very low
on resistance. This allows the input to be connected to the
output without additional propagation delay or generating
additional ground bounce noise.
The switch is enabled by means of the bus enable (BE) input
signal. This digital switch allows a bidirectional signal to be
switched when on. In the off condition, signal levels up to the
supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device translates the outputs to 1.8 V. In addition to this, a level
translating select pin (SEL SEL
) is included. When is low, VCC is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different
supplies, such as converter to DSP/microcontroller interfacing.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Level and voltage translation.
5. Tiny, SC70 package and SOT-66 package.
ADG3241
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Terminology .................................................................................... 10
Timing Measurement Information.............................................. 11
Bus Switch Applications ................................................................ 12
Mixed Voltage Operation, Level Translation.......................... 12
3.3 V to 2.5 V Translation ......................................................... 12
2.5 V to 1.8 V Translation ......................................................... 12
3.3 V to 1.8 V Translation ......................................................... 12
Bus Isolation................................................................................ 13
Hot Plug and Hot Swap Isolation............................................. 13
Analog Switching ....................................................................... 13
High Impedance During Power-Up/Power-Down................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
5/06 — Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 4............................................................................ 5
Changes to Ordering Guide ......................................................... 14
10/04 — Rev. 0 to Rev. A.
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 2
Changes to Absolute Maximum Ratings........................................3
Changes to Pin Configurations .......................................................4
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 11
7/03—Revision 0: Initial Version
ADG3241
Rev. B | Page 3 of 16
SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 1.
B Version
Parameter Symbol Conditions Min Typ2Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage VINH VCC = 2.7 V to 3.6 V 2.0 V
V
INH VCC = 2.3 V to 2.7 V 1.7 V
Input Low Voltage VINL VCC = 2.7 V to 3.6 V 0.8 V
V
INL V
CC = 2.3 V to 2.7 V 0.7 V
Input Leakage Current II ±0.01 ±1 μA
Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
On State Leakage Current 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
Maximum Pass Voltage VP VA/VB = VCC = SEL = 3.3 V, IO = −5 μA 2.2 2.5 2.7 V
VA/VB = VCC = SEL = 2.5 V, IO = −5 μA 1.5 1.8 2.1 V
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = −5 μA 1.5 1.8 2.1 V
CAPACITANCE3
A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF
B Port Off Capacitance CB OFF f = 1 MHz 3.5 pF
A, B Port On Capacitance CA, CB ON f = 1 MHz 7 pF
Control Input Capacitance CIN f = 1 MHz 4 pF
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD4tPHL, tPLH CL = 50 pF, VCC = SEL = 3 V 0.225 ns
Bus Enable Time BE to A or B5tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = VCC 1 3.2 4.6 ns
Bus Disable Time BE to A or B5tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = VCC 1 3 4 ns
Bus Enable Time BE to A or B5tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = 0 V 1 3 4 ns
Bus Disable Time BE to A or B5tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = 0 V 1 2.5 3.8 ns
Bus Enable Time BE to A or B5tPZH, tPZL VCC = 2.3 V to 2.7 V; SEL = VCC 1 3 4 ns
Bus Disable Time BE to A or B5tPHZ, tPLZ VCC = 2.3 V to 2.7 V; SEL = VCC 1 2.5 3.4 ns
Maximum Data Rate VCC = SEL = 3.3 V; VA/VB = 2 V 1.5 Gbps
Channel Jitter VCC = SEL = 3.3 V; VA/VB = 2 V 45 ps p-p
DIGITAL SWITCH
On Resistance RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 Ω
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 12 28 Ω
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 Ω
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 9 18 Ω
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA 5 8 Ω
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 12 Ω
POWER REQUIREMENTS
VCC 2.3 3.6 V
Quiescent Power Supply Current ICC Digital Inputs = 0 V or VCC; SEL = VCC 0.01 1 μA
Digital Inputs = 0 V or VCC; SEL = 0 V 0.1 0.2 mA
Increase in ICC per Input6∆ICC VCC = 3.6 V, BE = 3.0 V; SEL = VCC 0.15 8 μA
1 Temperature range is as follows: B Version: −40°C to +85°C.
2 Typical values are at 25°C, unless otherwise stated.
3 Guaranteed by design, not subject to production test.
4 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5 See Timing Measurement Information section.
6 This current applies to the Control Pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
ADG3241
Rev. B | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VCC to GND −0.5 V to +4.6 V
Digital Inputs to GND −0.5 V to +4.6 V
DC Input Voltage −0.5 V to +4.6 V
DC Output Current 25 mA per channel
Operating Temperature Range Only one absolute maximum rating can be applied at any one
time.
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SC70 Package
θJA Thermal Impedance 332°C/W
SOT-66 Package
θJA Thermal Impedance 191°C/W (4-layer board)
Lead Temperature, Soldering (10 sec) 300°C
235°C
IR Reflow, Peak Temperature
(<20 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADG3241
Rev. B | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
CC
BE SEL
04221-002
1
G
ND
2
A
3
6
5
B
4
ADG3241
TOP VIEW
(Not to Scale)
1
SEL
A
B
GND
BE
ADG3241
TOP VIEW
(Not to Scale)
2
3
6
5
4
V
CC
04221-003
Figure 3. 6-Lead SOT-66
Figure 2. 6-Lead SC70
Table 3. Pin Function Descriptions
Pin No.
SC70 SOT-66 Mnemonic Description
BE
1 6 Bus Enable (Active Low)
2 4 GND Ground Reference
3 3 A Port A, Input or Output
4 5 B Port B, Input or Output
5 1 VCC Positive Power Supply Voltage
SEL
6 2 Level Translation Select
Table 4. Truth Table
BE SEL Function
1
L L A = B, 3.3 V to 1.8 V level shifting
L H A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V level shifting
H X Disconnect
1 SEL = 0 V only when VDD = 3.3 V ± 10%.
ADG3241
Rev. B | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0
00.5
5
10
15
20
1.5 2.01.0
+85°C
+25°C
–40°C
V
CC
= 3.3V
SEL = V
CC
R
ON
(Ω)
V
A
/V
B
(V)
04221-007
0
00.5
5
10
15
20
25
30
35
40
3.01.0
R
ON
(Ω)
T
A
= 25°C
SEL = V
CC
1.5 2.0 2.5 3.5
V
A
/V
B
(V)
V
CC
= 3V
V
CC
= 3.3V
V
CC
= 3.6V
04221-004
Figure 4. On Resistance vs. Input Voltage Figure 7. On Resistance vs. Input Voltage for Different Temperatures
0
5
10
15
00.5
1.0
+85°C
0
00.5
5
10
15
20
25
30
35
40
3.01.0
R
ON
(Ω)
T
A
= 25°C
SEL = V
CC
1.5 2.0 2.5
V
A
/V
B
(V)
V
CC
= 2.3V
V
CC
= 2.5V
V
CC
= 2.7V
04221-005
1.2
+25°C
–40°C
V
CC
= 2.5V
SEL = V
CC
R
ON
(Ω)
V
A
/V
B
(V)
4221-008
0
Figure 5. On Resistance vs. Input Voltage Figure 8. On Resistance vs. Input Voltage for Different Temperatures
0
00.5
5
10
15
20
25
30
35
40
3.01.0
R
ON
(Ω)
T
A
= 25°C
SEL = 0V
1.5 2.0 2.5 3.5
V
A
/V
B
(V)
V
CC
= 3V
V
CC
= 3.3V
V
CC
= 3.6V
04221-006
0
0.5
1.5
2.5
3.0
2.0
1.0
V
OUT
(V)
00.5 3.01.0 1.5 2.0 2.5 3.5
V
A
/V
B
(V)
T
A
= 25°C
SEL = V
CC
I
O
= –5µA
V
CC
= 3.6V
V
CC
= 3.3V
V
CC
= 3V
04221-009
Figure 9. Pass Voltage vs. VCC
Figure 6. On Resistance vs. Input Voltage
ADG3241
Rev. B | Page 7 of 16
0
0
0.5
1.5
2.5
3.0
2.0
1.0
V
OUT
(V)
I
O
(A)
0.02 0.04 0.06 0.08 0.10
T
A
= 25°C
V
A
= 0V
BE = 0
V
CC
= SEL = 3.3V
V
CC
= SEL = 2.5V
V
CC
= 3.3V; SEL = 0V
04221-013
0
0.5
1.5
2.5
2.0
1.0
TA = 25°C
SEL = VCC
IO = –5µA
00.5 3.01.0 1.5 2.0 2.5
V
A
/V
B
(V)
V
CC
= 2.3V
V
CC
= 2.5V
V
CC
= 2.7V
VOUT (V)
04221-010
Figure 10. Pass Voltage vs. VCC Figure 13. Output Low Characteristic
0
0.5
1.5
2.5
2.0
1.0
T
A
= 25°C
SEL = 0V
I
O
= –5µA
V
CC
= 3V
V
CC
= 3.3V
V
CC
= 3.6V
V
OUT
(V)
00.5 3.01.0 1.5 2.0 2.5 3.5
V
A
/V
B
(V)
04221-011
0
0.5
1.5
2.5
3.0
2.0
1.0
VOUT (V)
I
O
(A)
TA = 25°C
VA = VCC
BE = 0
–0.10 –0.08 –0.06 –0.04 –0.02 0
VCC = SEL = 3.3V
VCC = SEL = 2.5V
VCC = 3.3V; SEL = 0V
0
4221-014
Figure 14. Output High Characteristic
Figure 11. Pass Voltage vs. VCC
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
00.5 3.01.0 1.5 2.0 2.5
V
A
/V
B
(V)
QINJ (pC)
T
A
= 25°C
SEL = V
CC
ON→OFF
C
L
= 1nF
V
CC
= 3.3V
V
CC
= 2.5V
04221-015
500
ENABLE FREQUENCY (MHz)
50
100
150
200
250
300
350
400
450
0
I
CC
(µA)
0 5 10 15 20 25 30 35 40 45 50
T
A
= 25°C
V
CC
= SEL = 3.3V
V
CC
= SEL = 2.5V
V
CC
= 3.3V; SEL = 0V
04221-012
Figure 15. Charge Injection vs. Source Voltage
Figure 12. ICC vs. Enable Frequency
ADG3241
Rev. B | Page 8 of 16
4.0
3.5
3.0
TEMPERATURE (°C)
TIME (ns)
2.5
2.0
1.5
1.0
0.5
0
–40 –20 0 20 40 60 80
ENABLE
DISABLE
V
CC
= SEL = 2.5V
04221-019
2
0
1
–2
–1
–4
–3
FREQUENCY (MHz)
ATTENUATION (dB)
–6
–7
–5
–8
0.03 0.1 1 10 100 1000
T
A
= 25°C
V
CC
= 3.3V/2.5V
SEL = V
CC
V
IN
= 0dBm
N/W ANALYZER:
R
L
= R
S
= 50Ω
04221-016
Figure 19. Enable/Disable Time vs. Temperature
Figure 16. Bandwidth vs. Frequency
DATA RATE (Gbps)
JITTER (ps p-p)
60
70
80
90
100
50
40
30
20
10
0
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
V
CC
= SEL = 3.3V
V
IN
= 1.5V p-p
20dB ATTENUATION
04221-020
ATTENU
A
TION (dB)
–90
0
–100
–80
–70
–60
–50
–40
–30
–20
–10
FREQUENCY (MHz)
0.1 1 10 100 1000
T
A
= 25°C
V
CC
= 3.3V/2.5V
SEL = V
CC
V
IN
= 0dBm
N/W ANALYZER:
R
L
= R
S
= 50Ω
04221-017
Figure 20. Jitter vs. Data Rate; PRBS 31
Figure 17. Off Isolation vs. Frequency
EYE WIDTH (%)
60
70
80
85
90
95
100
75
65
55
50
DATA RATE (Gbps)
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
V
CC
= SEL = 3.3V
V
IN
= 1.5V p-p
20dB ATTENUATION
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) × 100%
04221-021
4.0
3.5
3.0
TEMPERATURE (°C)
TIME (ns)
2.5
2.0
1.5
1.0
0.5
0
–40–200 2040 6080
V
CC
= SEL = 3.3V
V
CC
= 3.3V, SEL = 0V
ENABLE
DISABLE
ENABLE
DISABLE
04221-018
Figure 18. Enable/Disable Time vs. Temperature Figure 21. Eye Width vs. Data Rate; PRBS 31
ADG3241
Rev. B | Page 9 of 16
50mV/DIV
200ps/DIV
20dB
ATTENUATION
T
A
= 25°C
V
CC
= 3.3V
SEL = 3.3V
V
IN
= 1.5V p-p
04221-022
20mV/DIV
200ps/DIV
20dB
ATTENUATION
T
A
= 25°C
V
CC
= 2.5V
SEL = 2.5V
V
IN
= 1.5V p-p
0
4221-023
Figure 22. Eye Pattern; 1.5 Gbps, VCC = 3.3 V, PRBS 31 Figure 23. Eye Pattern; 1.244 Gbps, VCC = 2.5 V, PRBS 31
ADG3241
Rev. B | Page 10 of 16
TERMINOLOGY
VCC
Positive power supply voltage.
GND
Ground (0 V) reference.
VINH
Minimum input voltage for Logic 1.
VINL
Maximum input voltage for Logic 0.
II
Input leakage current at the control inputs.
IOZ
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
IOL
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
VP
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the
switch input voltage is equal to the supply voltage.
RON
Ohmic resistance offered by a switch in the on state. It is
measured at a given voltage by forcing a specified amount of
current through the switch.
CX OFF
Off switch capacitance.
CX ON
On switch capacitance.
CIN
Control input capacitance. This consists of BE and SEL.
ICC
Quiescent power supply current. This current represents the
leakage current between the VCC and ground pins. It is
measured when all control inputs are at a logic high or low level
and the switches are off.
ΔICC
Extra power supply current component for the BE control input
when the input is not driven at the supplies.
tPLH, tPHL
Data propagation delay through the switch in the on state.
Propagation delay is related to the RC time constant RON × CL,
where CL is the load capacitance.
tPZH, tPZL
Bus enable times. These are the times taken to cross the VT
voltage at the switch output when the switch turns on in
response to the control signal, BE.
tPHZ, tPLZ
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
It is measured as the time taken for the output voltage to change
by VΔ from the original quiescent level, with reference to the
logic level transition at the control input. Refer to Figure 26 for
enable and disable times.
Max Data Rate
Maximum rate at which data can be passed through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
ADG3241
Rev. B | Page 11 of 16
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that
is used is VIN and VOUT where
ENABLE DISABLE
0V
0V
0V
V
IN
= 0V
V
IN
= V
CC
V
OUT
SW1 @ GND
V
OUT
SW1 @ 2V
CC
t
PZL
t
PZH
CONTROL INPUT BE
t
PHZ
t
PLZ
V
T
V
T
V
CC
V
INH
V
T
V
CC
V
L
+ V
Δ
V
L
V
H
V
H
– V
Δ
04221-026
VIN = VA and VOUT = VB or VIN = VB and VOUT = VA
SW1
GND
DUT
PULSE
GENERATOR
VIN
RT
V
CC
VOUT
CL
RL
RL
2 × VCC
NOTES
1. PULSE GENERATOR FOR ALL PULSES:
t
R ≤2.5ns,
t
F ≤2.5ns,
FREQUENCY ≤10MHz.
2. CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
3. RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT
OF THE PULSE GENERATOR.
04221-024
Figure 26. Enable and Disable Times
Table 5. Switch Position
Test S1
tPLZ, tPZL 2 × VCC
Figure 24. Load Circuit tPHZ, tPZH GND
0V
V
IH
VT
VH
VT
VL
t
PLH
t
PLH
CONTROL
INPUT BE
VOUT
0
4221-025
Figure 25. Propagation Delay
Table 6. Test Conditions
Symbol VCC = 3.3 V ± 0.3 V (SEL = VCC) VCC = 2.5 V ± 0.2 V (SEL = VCC) VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit
RL 500 500 500 Ω
VΔ 300 150 150 mV
CL 50 30 30 pF
VT 1.5 0.9 0.9 V
ADG3241
Rev. B | Page 12 of 16
BUS SWITCH APPLICATIONS
MIXED VOLTAGE OPERATION, LEVEL
TRANSLATION
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3241 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from
3.3 V directly to 2.5 V.
Figure 27 shows a block diagram of a typical application in
which a user needs to interface between a 3.3 V ADC and a
2.5 V microprocessor. The microprocessor may not have 3.3 V
tolerant inputs, therefore placing the ADG3241 between the
two devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
3.3V ADC
2.5
V
3.3
V
ADG3241
3.3
V
2.5V
MICROPROCESSOR
04221-027
Figure 27. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
3.3 V TO 2.5 V TRANSLATION
When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to VCC, the maximum output signal will be clamped to
within a voltage threshold below the VCC supply.
ADG3241
2.5V
2.5V
3.3V
2.5V
3.3
V
04221-028
Figure 28. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
In this case, the output is limited to 2.5 V, as shown in Figure 29.
This device can be used for translation from 2.5 V to 3.3 V
devices and also between two 3.3 V devices.
2
.5
V
0V 3.3V
V
OUT
SWITCH
OUTPUT
SWITCH
INPUT
V
IN
3.3V S U P P LY
SEL = 3.3V
04221-029
Figure 29. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
2.5 V TO 1.8 V TRANSLATION
When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to VCC, the maximum output signal is, as before, clamped to
within a voltage threshold below the VCC supply. In this case, the
output is limited to approximately 1.8 V, as shown in Figure 31.
ADG3241
1.8V
2.5V
2.5
V
04221-030
Figure 30. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC
1.8V
0V 2.5V
V
OUT
SWITCH
OUTPUT
SWITCH
INPUT
V
IN
2.5V S U P P LY
SEL = 2.5V
04221-031
Figure 31. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V TO 1.8 V TRANSLATION
The ADG3241 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through the use of
the SEL pin. The SEL pin is an active low control pin. SEL
activates internal circuitry in the ADG3241 that allows voltage
translation between 3.3 V devices and 1.8 V devices.
ADG3241
1.8V
3
.3
V
3.3
V
04221-032
Figure 32. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
When VCC is 3.3 V and the input signal range is 0 V to VCC,
the maximum output signal is clamped to 1.8 V, as shown in
Figure 32. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to VCC.
ADG3241
Rev. B | Page 13 of 16
CARD I/O
CARD I/O
RAM
CPU
ADG3241 ADG3241
PLUG-IN
CARD (1)
PLUG-IN
CARD (2)
BUS
04221-035
1.8V
0V 3.3V
OUT
SWITCH
OUTPUT
SWITCH
INPUT
V
IN
3.3V SUPPLY
SEL = 0V
04221-033
SEL
Figure 33. 3.3 V to 1.8 V Voltage Translation, = 0 V
Figure 35. ADG3241 in a Hot Plug Application
BUS ISOLATION
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3241 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus
switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground
pin of the backplane before any other signal or power pins.
BUS SWITCH
LOCATION
BUS/
BACKPLANE
LOAD A LOAD C
LOAD B LOAD D
04221-034
ANALOG SWITCHING
Bus switches can be used in many analog switching
applications, such as video graphics. Bus switches can have
lower on resistance, smaller on and off channel capacitance, and
thus improved frequency performance over their analog
counterparts.
Figure 34. Location of Bus Switched in a Bus Isolation Application
HOT PLUG AND HOT SWAP ISOLATION
The ADG3241 is suitable for hot swap and hot plug
applications. The output signal of the ADG3241 is limited to a
voltage that is below the VCC supply, as shown in
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see Figure 4 for a typical
plot), but in many cases this does not present an issue.
Figure 29,
Figure 31, and Figure 33. Therefore the switch acts like a buffer
to take the impact from hot insertion, protecting vital and
expensive chipsets from damage.
HIGH IMPEDANCE DURING POWER-UP/POWER-
DOWN
To ensure the high impedance state during power-up or power-
down,
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch
can be positioned on the backplane between the bus devices
and the hot plug connectors. The bus switch is turned off
during hot plug.
BE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
Figure 35 shows a typical example of this type
of application.
ADG3241
Rev. B | Page 14 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AB
0.22
0.08
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
4 5 6
3 2 1
PIN 1
0.65 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
0.40
0.10
1.10
0.80
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
0.46
0.36
0.26
Figure 36. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
SEATING
PLANE
0.60
0.57
0.53
12° MAX
TOP VIEW
0.34 MAX
0.27 NOM
0.18
0.17
0.13
BOTTOM
VIEW
1.70
1.66
1.50
1.30
1.20
1.10
1.70
1.65
1.50
1
3
5
6
2
4
0.10 NOM
0.05 MIN
0.20 MIN
0.50
BSC
0.25 MAX
0.17 MIN
0.30
0.23
0.10
0.26
0.19
0.11
PIN 1
Figure 37. 6-Lead Small Outline Transistor Package [SOT-66]
(RY-6-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model Package Description Branding
ADG3241BKS-REEL7 −40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BKS-500RL7 −40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 SKA
ADG3241BKSZ-500RL7 −40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 S19
1
ADG3241BKSZ-REEL7 −40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 S19
1
ADG3241BKSZ-REEL −40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 S19
1
ADG3241BRYZ-REEL7 −40°C to +85°C 6-Lead Small Outline Transistor Package (SOT-66) RY-6-1 00
1
1 Z = Pb-free part.
ADG3241
Rev. B | Page 15 of 16
NOTES
ADG3241
Rev. B | Page 16 of 16
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04221-0-4/06(B)